TPS2540, TPS2540A

TPS2541, TPS2541A
www.ti.com SLVSAG2C – OCTOBER 2010 – REVISED OCTOBER 2011

USB Charging Port Power Switch and Controller

Check for Samples: TPS2540, TPS2540A, TPS2541, TPS2541A

1FEATURES DESCRIPTION
2• Meets Battery Charging Specification BC1.2 The TPS2540/40A and TPS2541/41A are a
for DCP and CDP combination of current-limited USB port power switch
with a USB 2.0 high-speed data line (D+/D-) switch
• Meets Chinese Telecommunications Industry and a USB charging port identification circuit.
Standard YD/T 1591-2009 Applications include notebook PCs and other
• Supports Sleep-Mode Charging for Most intelligent USB host devices. The wide bandwidth (2.6
Available Apple® Devices and/or BC1.2 GHz) data-line switch also features low capacitance
Compliant Devices and low on resistance, allowing signals to pass with
minimum edge and phase distortion. The
• Compatible With USB 2.0 and 3.0 Power TPS2540/40A/41/41A monitors D+ and D-, providing
Switch Requirements the correct hand-shaking protocol with compliant
• 2.6-GHz Bandwidth USB 2.0 Data Switch client devices.
• 73-mΩ (typ.) High-Side MOSFET The TPS2540/40A/41/41A supports the following
• Adjustable Current Limit up to 2.8 A (typical) charging logic schemes:
• OUT Discharge Through CTLx=000 • USB 2.0 BC1.2
(TPS2540/40A) or DSC (TPS2541/41A) Input • Chinese Telecom Standard YD/T 1591-2009
• Longer Detach Detection Time (TPS2540A/41A) • Divider Mode, compliant with Apple devices such
Supporting Additional Legacy Devices as iPod® and iPhone®
• Available in 16-Pin QFN Package CTL1-CTL3 logic inputs are used to select one of the
various charge modes provided by the TPS2540/40A
APPLICATIONS and TPS2541/41A. These charge modes allow the
host device to actively select between Dedicated
• USB Ports/Hubs Charging Port (DCP) (wall-adapter emulation),
• Notebook PCs Charging Downstream Port (CDP) (active USB 2.0
• Universal Wall Charging Adapter data communications with 1.5-A support), or
Standard Downstream Port (SDP) USB 2.0 Mode
(active USB 2.0 data communications with 500-mA
support). The TPS2540/40A/41/41A also integrates
an auto-detect feature that supports both DCP
schemes for Battery Charging Specification (BC1.2)
and the Divider Mode without the need for outside
user interaction.

TPS2540/40A/41/41A RTE Package and Typical Application Diagram

To System Bus To Peripheral
TPS2540/40A/41/41A
RTE Package TPS2540/40A/41/41A
(Top View) 4.5 V to 5.5 V 1 IN OUT 12
FAULT

CUSB VBUS
ILIM0

ILIM1

GND

0.1 mF D-
ILIM0 16
RFAULT D+
10 kW GND
16 15 14 13 ILIM1 15 2x
RILIM
FAULT Signal 13 FAULT
IN 1 12 OUT
GND 14
DM_OUT 2 11 DM_IN ILIM Select 4 ILIM_SEL
Exposed
Thermal Die Power Switch EN 5 EN/DSC DM_IN 11
DP_OUT 3 10 DP_IN

ILIM_SEL 4 9 N/C Mode Select I/O 6 CTL1 DP_IN 10

Mode Select I/O 7 CTL2 DM_OUT 2

5 6 7 8
To Host Controller
Mode Select I/O 8 CTL3 DP_OUT 3
CTL3
CTL1
EN/DSC

CTL2

UDG-10116

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Apple, iPod, iPhone are registered trademarks of Apple Inc.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2540, TPS2540A
TPS2541, TPS2541A
SLVSAG2C – OCTOBER 2010 – REVISED OCTOBER 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONT.)
The TPS2540A/41A auto detect mode also has a longer detach detection time, so that it can support certain
unique non-compliant devices. The TPS2540/40A/41/41A power-distribution switch is intended for applications
where heavy capacitive loads and short-circuits are likely to be encountered, incorporating a 73-mΩ, N-channel
MOSFET in a single package. Constant-current mode is used when the output load exceeds the current-limit
threshold. ILIM_SEL logic input selects one of two current-limit thresholds, each one being individually adjustable
via an external resistor. Additional USB switch features include a de-glitched output fault reporting (FAULT), and
a logic-level enable EN (TPS2540/40A) or OUT discharge control DSC (TPS2541/41A). With the TPS2540/40A,
the mode “000” is used to force an output discharge.

PRODUCT INFORMATION (1)

(2)
TA FUNCTION TDCPLOW PACKAGE MARKING
Enable 2540
≤0.9 s
Output Discharge 2541
-40°C to 85°C QFN16
Enable 2540A
≤9 s
Output Discharge 2541A

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Low DP_IN period in DCP mode, see Figure 31.

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ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range, voltages are referenced to GND (unless otherwise noted)
PARAMETER MIN MAX UNIT
Supply voltage range IN -0.3 7
Input voltage range EN (TPS2540/40A), DSC (TPS2541/41A), ILIM0, ILIM1,
-0.3 7
ILIM_SEL, CTL1, CTL2, CTL3
(2)
Voltage range OUT, FAULT -0.3 7 V
Voltage range IN to OUT -7 7
Voltage range DP_IN, DM_IN, DP_OUT, DM_OUT (IN + 0.3)
-0.3
or 5.7
Input clamp current DP_IN, DM_IN, DP_OUT, DM_OUT ±20
Continuous current in SDP or CDP DP_IN to DP_OUT or DM_IN to DM_OUT
±100
mode mA
Continuous current in BC1.2 DCP DP_IN to DM_IN
±35
mode
Continuous output current IOUT Internally limited
Continuous output sink current FAULT 25
mA
Continuous output source current ILIM0, ILIM1 1
Continuous total power dissipation Internally limited
ESD rating, Human Body Model IN, ILIM_SEL, EN, DSC, CTL1, CTL2, CTL3, N/C, OUT,
2
(HBM) FAULT, GND, ILIM1, ILIM0 kV
DP_IN, DM_IN, DP_OUT, DM_OUT 8
ESD rating, Charged Device Model
500 V
(CDM)
Operating Junction temperature TJ Internally limited
Storage temperature range Tstg -65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Do not apply external voltage sources directly.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VIN Input voltage, IN 4.5 5.5
Input voltage, logic-level inputs,
(CTL1, CTL2, CTL3, EN (TPS2540/40A), DSC (TPS2541/41A), 0 5.5 V
ILIM_SEL)
Input voltage, data line inputs, (DP_IN, DM_IN, DP_OUT, DM_OUT) 5.5
Continuous current, data line inputs,
±30
(SDP or CDP mode, DP_IN to DP_OUT or DM_IN to DM_OUT )
mA
Continuous current, data line inputs, (BC1.2 DCP mode, DP_IN to
±10
DM_IN)
IOUT Continuous output current, OUT 0 2.5 A
RILIMx Current-limit set resistors, (ILIM0 to GND, ILIM1 to GND) 16.9 750 kΩ
TJ Operating virtual junction temperature -40 125 °C

THERMAL INFORMATION
TPS2540
TPS2540A
TPS2541
THERMAL METRIC (1) TPS2541A UNITS
RTE
16 PINS
θJA Junction-to-ambient thermal resistance (2) 53.4
(3)
θJCtop Junction-to-case (top) thermal resistance 51.4
θJB Junction-to-board thermal resistance (4) 17.2
°C/W
ψJT Junction-to-top characterization parameter (5) 3.7
ψJB Junction-to-board characterization parameter (6) 20.7
(7)
θJCbot Junction-to-case (bottom) thermal resistance 3.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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ELECTRICAL CHARACTERISTICS
Conditions are -40 ≤ TJ ≤ 125°C unless otherwise noted. VEN (if TPS2540 or TPS2540A) = VDSC (if TPS2541 or TPS2541A) =
VIN = 5 V, RFAULT = 10 kΩ, RILIM0 = 210 kΩ, RILIM1 = 20 kΩ, ILIM_SEL = 0 V, CTL1 = CTL2 = GND, CTL3 = VIN (TPS2540/40A) or
CTL3 = GND (TPS2541/41A), unless otherwise noted. Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Switch
IOUT = 2 A, VILIM_SEL = Logic HI 73 120
Static drain-source IOUT = 100 mA, VILIM_SEL = Logic LO 73 120
RDS(on) mΩ
on-state resistance -40°C ≤ TA = TJ ≤ 85°C, IOUT = 2 A, VILIM_SEL = Logic HI 73 105
TA = TJ = 25°C, IOUT = 2 A, VILIM_SEL = Logic HI 73 84
tr Rise time, output CL = 1 µF, RL = 100 Ω, (see Figure 27, Figure 28) 1 1.5
ms
tf Fall time, output CL = 1 µF, RL = 100 Ω, (see Figure 27, Figure 28) 0.2 0.5
OUT discharge
RDIS 400 500 630 Ω
resistance
IREV Reverse leakage current VOUT = 5.5 V, VIN = VEN = 0 V , TJ = 25°C 0 1 µA
Enable Input EN (TPS2540/40A), Output Discharge Input DSC (TPS2541/41A)
Enable pin turn on/off
VEN 0.9 1.1 1.65 V
threshold, falling
VEN_HYS EN Hysteresis 200 mV
IEN Input current VEN = 0 V or 5.5 V -0.5 0.5 µA
DSC pin turn on/off
VDSC 0.9 1.1 1.65 V
threshold, falling
VDSC_HYS DSC Hysteresis 200 mV
IDSC Input current VDSC = 0 V or 5.5 V -0.5 0.5 µA
tON Turn-on time CL = 1 µF, RL = 100 Ω(see Figure 27, Figure 29) 3.4 5
ms
tOFF Turn-off time CL = 1 µF, RL = 100 Ω(see Figure 27, Figure 29) 1.7 3
Current Limit
ILIM_SEL turn on/off
VILIM_SEL 0.9 1.1 1.65 V
threshold, falling
VILIM_HYS ILIM_SEL Hysteresis 200 mV
ILIM_SEL input current VILIM_SEL = 0 V or 5.5 V -0.5 0.5 µA
RILIM0 = 210 kΩ 185 230 265
VILIM_SEL = Logic LO
RILIM0 = 100 kΩ 420 480 530
Maximum DC output RILIM1 = 20 kΩ 2150 2430 2650
ISHORT VILIM_SEL = Logic HI mA
current from IN to OUT RILIM1 = 16.9 kΩ 2550 2840 3100
RILIM0 = 698 kΩ
VILIM_SEL = Logic LO 25 55 85
-40 ≤ TJ ≤ 85°C
Response time to
tIOS VIN = 5.0 V (see Figure 30) 1.5 µs
short-circuit
Supply Current
Supply current, switch
ICCL VEN = VDSC = 0 V, OUT grounded, -40 ≤ TJ ≤ 85°C 0.1 2
disabled
VILIM_SEL = Logic
150 185 µA
HI
ICCH Supply current, operating VEN = VDSC = VIN,
VILIM_SEL = Logic
130 170
LOW

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ELECTRICAL CHARACTERISTICS (continued)

Conditions are -40 ≤ TJ ≤ 125°C unless otherwise noted. VEN (if TPS2540 or TPS2540A) = VDSC (if TPS2541 or TPS2541A) =
VIN = 5 V, RFAULT = 10 kΩ, RILIM0 = 210 kΩ, RILIM1 = 20 kΩ, ILIM_SEL = 0 V, CTL1 = CTL2 = GND, CTL3 = VIN (TPS2540/40A) or
CTL3 = GND (TPS2541/41A), unless otherwise noted. Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Undervoltage Lockout
Low-level input voltage,
VUVLO VIN rising 3.9 4.1 4.3 V
IN
Hysteresis, IN 100 mV
FAULT
Output low voltage,
IFAULT = 1 mA 100 mV
FAULT
Off-state leakage VFAULT = 5.5 V 1 µA
FAULT deglitch FAULT assertion or de-assertion due to over-current condition 5 8.5 12 ms
CTLx Inputs
CTLx pins turn on/off
VCTL 0.9 1.1 1.65 V
threshold, falling
VCTL_HYS CTLx hysteresis 200 mV
Input current VCTL = 0 V or 5.5 V -0.5 0.5 µA
Thermal Shutdown
Thermal shutdown
155
threshold
Thermal shutdown °C
135
threshold in current-limit
Hysteresis 10
High-Bandwidth Analog Switch
On resistance DP/DM VDP/DM_OUT = 0 V, IDP/DM_IN = + 30 mA 2 4
RHS_ON
high-speed switch VDP/DM_OUT = 2.4 V, IDP/DM_IN = - 15 mA 3 6
Ω
On resistance match VDP/DM_OUT = 0 V, IDP/DM_IN = + 30 mA 0.05 0.15
ΔRHS_ON between channels
DP/DM switch VDP/DM_OUT = 2.4 V, IDP/DM_IN = - 15 mA 0.05 0.15
DP/DM off state
CIO_OFF f = 1 MHz, switch off 3 3.6
capacitance (1)
pF
DP/DM on state
CIO_ON f = 1 MHz, switch on 5.4 6.2
capacitance (2)
OIRR Off state isolation RL = 50 Ω, f = 250 MHz, -40 ≤ TJ ≤ 125°C 33
On-state cross channel dB
XTALK RL = 50 Ω, f = 250 MHz, -40 ≤ TJ ≤ 125°C 52
isolation
IOFF Off state leakage VDM_IN = VDP_IN = 3.6 V, VDM_OUT = VDP_OUT = 0 V 0.1 1.5 µA
BW Bandwidth (-3 dB) RL = 50 Ω 2.6 GHz
tpd Propagation delay 0.25
Skew between opposite ns
tSK transitions of the same 0.1 0.2
port (tPHL –tPLH)

(1) The resistance in series with this parasitic capacitance to GND is typically 250 Ω.
(2) The resistance in series with this parasitic capacitance to GND is typically 150 Ω.

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ELECTRICAL CHARACTERISTICS (continued)

Conditions are -40 ≤ TJ ≤ 125°C unless otherwise noted. VEN (if TPS2540 or TPS2540A) = VDSC (if TPS2541 or TPS2541A) =
VIN = 5 V, RFAULT = 10 kΩ, RILIM0 = 210 kΩ, RILIM1 = 20 kΩ, ILIM_SEL = 0 V, CTL1 = CTL2 = GND, CTL3 = VIN (TPS2540/40A) or
CTL3 = GND (TPS2541/41A), unless otherwise noted. Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DCP Shorted Mode Charger Interface
DP_IN/DM_IN shorting
RDPM_short CTLx configured for DCP BC1.2 125 200 Ω
resistance
Discharge resistance
RDCHG_PW DM_IN and DP_IN to CTLx configured for DCP BC1.2 2 3.2 6 MΩ
GND
Divider Mode Charger Interface
VDP_AM DP_IN output voltage 1.9 2 2.1
V
VDM_AM DM_IN output voltage 2.57 2.7 2.84
CTLx configured for divider mode
ZOUT_DP DP_IN output impedance 8 10 12.5
kΩ
ZOUT_DM DM_IN output impedance 8 10 12.5
CDP Interface
Voltage source on
VDM_SRC VDP_IN = 0.6 V, CTLx configured for CDP 0.5 0.6 0.7
DM_IN for CDP detect
DP_IN rising voltage V
VDAT_REF threshold to activate 0.25 0.4
VDM_SRC
VDAT_REF hysteresis 50 mV
IDM_IN = - 250 µA, CTLx configured for CDP
DP_IN rising voltage
VLGC_SRC threshold to deactivate 0.8 1 V
VDM_SRC
VLGC_SRC hysteresis 100 mV
IDP_SINK DP_IN sink current 0.4 V ≤VDP_IN ≤ 0.8 V, CTLx configured for CDP operation 50 150 µA
Timings
DM_IN voltage source From VDP_IN = 0 -> 0.6 V to VDM_IN = VDM_SRC , CTLx
tVDMSRC_EN 1 10
enable time, CDP mode configured for CDP
DM_IN voltage source From VDP_IN = 0.6 V -> 0 V to VDM_IN = 0 V, CTLx configured
tVDMSRC_DIS 10
disable time, CDP mode for CDP
ms
Time for OUT to be
reapplied after VOUT falls Any transition to and from CDP, or to and from SDP. Also
tVBUS_REAPP 200 500
below 0.7 V during during Auto-detect to shorted mode.
discharge
Timing Requirements
Session valid (IN high) to
tSLVD_CON_P TPS2540/TPS2541 1
VDP_SRC in DCP mode
s
Low DP_IN period in When VBUS is high, (TPS2540, TPS2541) 0.9
tDCPLOW
DCP mode When VBUS is high, (TPS2540A, TPS2541A) 9

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DEVICE INFORMATION

TPS2540, TPS2540A, TPS2541 and TPS2541A

TPS2540/TPS2540A TPS2541/TPS2541A
RTE Package RTE Package
(Top View) (Top View)

FAULT

FAULT
ILIM0

ILIM1

ILIM0

ILIM1
GND

GND
16 15 14 13 16 15 14 13

IN 1 12 OUT IN 1 12 OUT

DM_OUT 2 11 DM_IN DM_OUT 2 11 DM_IN

Exposed Exposed
Thermal Die Thermal Die
DP_OUT 3 10 DP_IN DP_OUT 3 10 DP_IN

ILIM_SEL 4 9 N/C ILIM_SEL 4 9 N/C

5 6 7 8 5 6 7 8
CTL3
CTL1
EN

CTL2

CTL3
CTL1
DSC

CTL2
Detection Block Diagram

To Host DM_OUT
2 VBUS
Controller USB
CDP/SDP Conector
2.7 V
10 kW
DM_IN VBUS
11 D-
D+
Divider Mode DCP Auto GND
CDP
125 W Shorted Detect/
Detect
Mode CTL
2V DP_IN
10 kW 10

8 CTL3
To Host DP_OUT CDP/SDP
3
Controller 7 CTL2
6 UDG-10126

CTL1

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TPS2540/40A/41/41A Top-Level Functional Block Diagram

IN 1

EN/DSC 5 12 OUT

Power Switch
ILIM0 16
Control Circuitry
ILIM1 15 13 FAULT

ILIM_SEL 4

CTL1 6

Charge
CTL2 7
Logic
Auto
CTL3 8
Discharge

DM_OUT 2

DP_OUT 3
High 11 DM_IN
Charging Bandwidth
Host Switch
Downstream
Port Mode BC Sense
10 DP_IN

Divider
Mode

Shorted Dedicated 14 GND

Mode Sense

UDG-10125

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PIN DESCRIPTIONS

Pin Descriptions
NAME PIN I/O DESCRIPTION
Power Switch
Input voltage; connect a 0.1-µF or greater ceramic capacitor from IN to GND as close
IN 1 PWR
to the device as possible.
OUT 12 PWR Power-switch output.
GND 14 PWR Ground connection; should be connected externally to Power PAD.
Internally connected to GND; used to heat-sink the part to the circuit board traces.
POWERPAD N/A
Connect to GND plane.
Current-Limit Threholds and Indication
External resistor used to set current-limit threshold when ILIM_SEL is LO;
ILIM0 16 I
recommended 16.9 kΩ ≤ RILIM ≤ 750 kΩ;
External resistor used to set current-limit threshold when ILIM_SEL is HI;
ILIM1 15 I
recommended 16.9 kΩ ≤ RILIM ≤ 750 kΩ;
Logic-level input signal used to dynamically change power switch current-limit
ILIM_SEL 4 I
threshold; logic LO selects ILIM0, logic HI selects ILIM1.
Active-low open-drain output, asserted during over-temperature or current limit
FAULT 13 O
conditions.
Input Logic Control Signals
Logic-level control input for turning the power switch and the signal switches on/off.
TPS2540/40A: When EN is low, the device is disabled, the signal and power
EN, DSC 5 I switches are OFF.
TPS2541/41A: When DSC is low, the device is disabled, the signal and power
switches are OFF and the output (OUT) capacitor is discharged.
CTL1 6 I Logic-level control inputs for controlling the charging mode and the signal switches.
The TPS2540/40A and TPS2541/41A use different control line truth tables. With the
CTL2 7 I
TPS2540/40A, the “000” configuration is used to force a discharge of the output
CTL3 8 I (OUT) capacitor.
D+/D- Data Line Signals
D- data line to connector, input/output used for hand-shaking with portable
DM_IN 11 I/O
equipment.
D+ data line to connector, input/output used for hand-shaking with portable
DP_IN 10 I/O
equipment.
DM_OUT 2 I/O D- data line to USB host controller.
DP_OUT 3 I/O D+ data line to USB host controller.
N/C 9 No connect pin. Can be grounded or left floating.

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TYPICAL CHARACTERISTICS
IN UVLO RISING SUPPLY CURRENT - DISABLED
vs vs
TEMPERATURE TEMPERATURE
4.5 1

4.4 0.9

0.8
4.3
0.7

ICCL - IN Current - mA
4.2
VUVLO - IN UVLO - V

0.6
4.1
0.5
4
0.4
3.9
0.3
3.8 0.2

3.7 0.1

3.6 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 1. Figure 2.

SUPPLY CURRENT - SDP or DCP BC SUPPLY CURRENT - AUTO-DETECT

vs vs
TEMPERATURE TEMPERATURE
120 150

110
140
ICCH - IN Current - mA

ICCH - IN Current - mA

100
130

90

120
80

110
70

60 100
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT - CDP or DIVIDER MODE CURRENT LIMIT
vs vs
TEMPERATURE CURRENT LIMIT RESISTANCE
150 3000

TJ = 25°C
2500
140

ISHORT - Current Limit - mA

ICCH - IN Current - mA

2000
130

1500

120
1000

110
500

100 0
-40 -20 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 160 180 200 220 240
TJ - Junction Temperature - °C RILIM - Current Limit Resistance - kW
Figure 5. Figure 6.

CURRENT LIMIT POWER SWITCH ON-RESISTANCE

vs vs
TEMPERATURE TEMPERATURE
2500 100

95
RDS(on) - IN/OUT ON Resistance - mW

2000 RILIM = 20 kW 90
ISHORT - Current Limit - mA

85

1500 80

75
RILIM = 100 kW
1000 RILIM = 210 kW 70

65

500 60

55

0 50
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

TURN-ON TIME, TURN-OFF TIME DATA SWITCH ON-RESISTANCE
vs vs
TEMPERATURE TEMPERATURE
5 5

4.5

RHS(on) - Data Switch ON Resistance - W

4 4
TON/TOFF - Turn-ON/OFF Time - ms

VDP/DM_OUT = 2.4 V, IDP/DM_IN = -15 mA

Turn-On Time
3.5

3 3

2.5

2 2

1.5 VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA

Turn-Off Time
1 1

0.5

0 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 9. Figure 10.

FAULT OUTPUT VOLTAGE EN THRESHOLD FALLING

vs vs
SINK CURRENT TEMPERATURE
700 2

1.8
600 TJ = 125°C
1.6
VEN - EN Falling Threshold - V
FAULT Low Voltage - mV

500 1.4

1.2
400 TJ = 25°C
1
300
0.8

200 0.6

0.4
100
TJ = -40°C 0.2

0 0
0 1 2 3 4 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 140
IFAULT - FAULT Sink Current - mA TJ - Junction Temperature - °C

Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

CTL1-3 THRESHOLD FALLING DIVIDER MODE DP/DM VOLTAGE
vs vs
TEMPERATURE TEMPERATURE
2 3

1.8 2.8 DM_IN Voltage

DP_IN/DM_IN Apple Output Voltage - V

1.6 2.6
CTL1-3 Falling Threshold - V

1.4 2.4

1.2 2.2

1 2

0.8 1.8 DP_IN Voltage

0.6 1.6

0.4 1.4

0.2 1.2

0 1
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 13. Figure 14.

DATA TRANSMISSION CHARACTERISTICS OFF STATE DATA SWITCH ISOLATION

vs vs
FREQUENCY FREQUENCY
0 60

50
-5
OIRR - Off State Isolation - dB
Transmission Gain - dB

40
-10

30

-15
20

-20
10

-20 0
0.01 0.1 1 10 0.01 0.1 1 10
Frequency - GHz Frequency - GHz
Figure 15. Figure 16.

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TYPICAL CHARACTERISTICS (continued)

ON STATE CROSS-CHANNEL ISOLATION
vs
FREQUENCY
80

XTALK - ON State Cross-Channel Isolation - dB

70

60

50

40

30

20

10

0
0.01 0.1 1 10
Frequency - GHz
Figure 17.

EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN
(with no switch) (with data switch)

0.5 0.5
0.4 0.4

0.3 0.3
Differential Signal - V

Differential Signal - V

0.2 0.2

0.1 0.1
0 0

-0.1 -0.1

-0.2 -0.2
-0.3 -0.3

-0.4 -0.4
-0.5 -0.5

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
t - Time (x10-9) -s t - Time (x10-9) -s
Figure 18. Figure 19.

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TYPICAL CHARACTERISTICS (continued)

EYE DIAGRAM OF NEARLY IDEAL PULSE EYE DIAGRAM OF NEARLY IDEAL PULSE
(with no switch) (with data switch)
200 mV/div.

200 mV/div.
348ps/div. 348ps/div.
Figure 20. Figure 21.

TURN ON INTO A SHORT CIRCUIT TURN ON INTO A SHORT CIRCUIT

IN (2 V/div.) IN (2 V/div.)
OUT (2 V/div.)
I_IN (0.5 A/div.)

I_IN (0.5 A/div.) OUT (2 V/div.)

0.2 s/div 10 ms/div

Figure 22. Figure 23.

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TYPICAL CHARACTERISTICS (continued)

RESPONSE TO A SHORT-CIRCUIT RESPONSE TO A SHORT-CIRCUIT
(from no-load condition) (from no-load condition)

IN (2 V/div.)

OUT (2 V/div.)
IN (2 V/div.)

OUT (2 V/div.)
I_IN (2 A/div.)

I_IN (2 A/div.)

100 ms/div 1 ms/div

Figure 24. Figure 25.

RESPONSE TO A SHORT-CIRCUIT FROM NO LOAD CONDITION

(with TPS51117EVM source)

IN (1 V/div.)

OUT (1 V/div.)

I_IN (2 A/div.)

2 ms/div
Figure 26.

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PARAMETER MEASUREMENT INFORMATION

OUT

RL CL

Figure 27. Test Circuit

tr tf
90% 90%
VOUT 10% 10%
UDG-10140

Figure 28. Voltage Waveform

50% 50% tOFF

VEN
tON

90%
VOUT 10%
UDG-10117

Figure 29. Voltage Waveforms

IOS

IOUT
UDG-10118

tIOS

Figure 30. Response Time to Short-Circuit Waveform

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tSVLD_CON_P

OUT

VLGC_SRC
DP_IN
VDAT_REF
0V

VLGC_SRC
DM_IN VDAT_REF
0V
UDG-10119
tDCPLOW tDCPLOW

Figure 31. DCP BC1.2 Operation

CTL1-3 SDP or CDP

OUT

0.7 V UDG-10120

tVBUS_REAPP

Figure 32. OUT Discharge During CTLx Lines Change

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Divider Only Mode

5V

1
Network Analyzer IN
50 W DP_IN DP_OUT
10 3
Source Signal 50 W

DM_IN DM_OUT
50 W 11 2
50 W GND 50 W
14

UDG-10141

Figure 33. OFF State Isolation (OIRR)

5V

1
IN
DP_IN DP_OUT
10 3

Network Analyzer 50 W 50 W

50 W DM_IN DM_OUT
11 2
Source Signal 50 W GND
14
50 W

UDG-10121

Figure 34. OFF State Isolation (OIRR)

Network Analyzer Setup

• Source signal = 600-mV peak-to-peak at 50-Ω load
• DC bias = 300 mV

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SDP Mode
5V

1
IN
DP_IN DP_OUT
10 3

Network Analyzer 50 W

50 W DM_IN DM_OUT
11 2
Source Signal GND 50 W
14
50 W

UDG-10142

Figure 35. ON State Cross Channel Isolation (XTALK)

5V

1
Network Analyzer IN
50 W DP_IN DP_OUT
10 3
Source Signal 50 W

DM_IN DM_OUT
50 W 11 2
50 W GND
14

UDG-10122

Figure 36. ON State Cross Channel Isolation (XTALK)

Network Analyzer Setup

• Source signal = 600-mV peak-to-peak at 50-Ω load
• DC bias = 300 mV

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SDP Mode
5V

1
Network Analyzer IN
50 W DP_IN DP_OUT
10 3
Source Signal

DM_IN DM_OUT
50 W 11 2
GND 50 W
14

UDG-10143

Figure 37. Bandwidth (BW)

5V

1
IN
DP_IN DP_OUT
10 3

Network Analyzer 50 W

50 W DM_IN DM_OUT
11 2
Source Signal GND
14
50 W

UDG-10123

Figure 38. Bandwidth (BW)

Network Analyzer Setup

• Source signal = 600-mV peak-to-peak at 50-Ω load
• DC bias = 300 mV

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SDP Mode
5V

1
IN
DP_IN DP_OUT
10 3

+ DM_IN DM_OUT
11 2
IOUT
GND
14
UDG-10124

Figure 39. On Resistance DP/DM High-Speed Switch (RHS_ON)

VDP _ IN - VDP _ OUT

RHS _ ON =
IOUT (1)
VDM _ IN - VDM _ OUT
RHS _ ON =
IOUT (2)

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GENERAL INFORMATION

Overview
The following overview references various industry standards. It is always recommended to consult the most
up-to-date standard to ensure the most recent and accurate information.
Rechargeable portable equipment requires an external power source to charge its batteries. USB ports are a
convenient location for charging because of an available 5-V power source. Universally accepted standards are
required to make sure host and client-side devices operate together in a system to ensure power management
requirements are met. Traditionally, USB host ports following the USB 2.0 specification must provide at least 500
mA to downstream client-side devices. Because multiple USB devices can be attached to a single USB port
through a bus-powered hub, it is the responsibility of the client-side device to negotiate its power allotment from
the host to ensure the total current draw does not exceed 500 mA. In general, each USB device is granted 100
mA and may request more current in 100 mA unit steps up to 500 mA. The host may grant or deny based on the
available current.
Additionally, the success of USB has made the mini-USB connector a popular choice for wall adapter cables.
This allows a portable device to charge from both a wall adapter and USB port with only one connector.
One common difficulty has resulted from this. As USB charging has gained popularity, the 500 mA minimum
defined by USB 2.0 has become insufficient for many handset and personal media players which need a higher
charging rate. On the other hand, wall adapters can provide much more current than 500 mA. Several new
standards have been introduced defining protocol handshaking methods that allow host and client devices to
acknowledge and draw additional current beyond the 500 mA minimum defined by USB 2.0 while still using a
single micro-USB input connector.
The TPS2540, TPS2540A, TPS2541 and TPS2541A support three of the most common protocols:
• USB 2.0 Battery Charging Specification BC1.2
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider Mode
All three methods have similarities and differences, but the biggest commonality is that all three define three
types of charging ports that provide charging current to client-side devices. These charging ports are defined as:
• Standard Downstream Port (USB 2.0) (SDP)
• Charging Downstream Port (CDP)
• Dedicated Charging Port (DCP)
BC1.2 defines a Charging Port as a downstream facing USB port that provides power for charging portable
equipment.
The table below shows the differences between these ports according to BC1.2 .

Table 1. Operating Modes

MAXIMUM ALLOWABLE CURRENT DRAW
PORT TYPE SUPPORTS USB 2.0 COMMUNICATION
BY PORTABLE EQUIPMENT (A)
SDP (USB 2.0) Yes 0.5
CDP Yes 1.5
DCP No 1.5

BC1.2 defines the protocol necessary to allow portable equipment to determine what type of port it is connected
to so that it can allot its maximum allowable current draw. The hand-shaking process has two steps. During step
one, the primary detection, the portable equipment outputs a nominal 0.6-V output on its D+ line and reads the
voltage input on its D- line. The portable device concludes it is connected to an SDP if the voltage is less than
the nominal data detect voltage of 0.3 V. The portable device concludes that it is connected to a Charging Port if
the D- voltage is greater than the nominal data detect voltage of 0.3 V and less than 0.8 V. The second step, the
secondary detection, is necessary for portable equipment to determine between a CDP and a DCP. The portable
device outputs a nominal 0.6 V output on its D- line and reads the voltage input on its D+ line. The portable
device concludes it is connected to a CDP if the data line being read remains less than the nominal data detect
voltage of 0.3 V. The portable device concludes it is connected to a DCP if the data line being read is greater
than the nominal data detect voltage of 0.3V and less than 0.8 V.

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Standard Downstream Port (SDP) USB 2.0

An SDP is a traditional USB port that follows USB 2.0 and supplies a minimum of 500 mA per port. USB 2.0
communications is supported, and the host controller must be active to allow charging.

Charging Downstream Port (CDP)

A CDP is a USB port that follows USB 2.0 BC1.2 and supplies a minimum of 1.5 A per port. It provides power
and meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host
controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking
logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for
additional current draw by the client device.
The CDP hand-shaking process is two steps. During step one the portable equipment outputs a nominal 0.6 V
output on its D+ line and reads the voltage input on its D- line. The portable device concludes it is connected to
an SDP if the voltage is less than the nominal data detect voltage of 0.3 V. The portable device concludes that it
is connected to a Charging Port if the D- voltage is greater than the nominal data detect voltage of 0.3V and less
than 0.8 V.
The second step is necessary for portable equipment to determine between a CDP and a DCP. The portable
device outputs a nominal 0.6 V output on its D- line and reads the voltage input on its D+ line. The portable
device concludes it is connected to a CDP if the data line being read remains less than the nominal data detect
voltage of 0.3 V. The portable device concludes it is connected to a DCP if the data line being read is greater
than the nominal data detect voltage of 0.3V and less than 0.8 V.

Dedicated Charging Port (DCP)

A DCP is a special type of wall-adapter used in charging applications that uses a micro-B connector to connect
to portable devices. A DCP only provides power and cannot enumerate upstream facing portable equipment. It
does not support USB 2.0 communications, but it does provide specific impedances on the data lines reserved
for USB 2.0 so that it is identifiable as a dedicated charger.
The impedances presented on D+ and D- are different depending on the specific standard the dedicated charger
is designed to. BC1.2 and the Chinese Telecommunications Industry Standard YD/T 1591-2009 define that the
D+ and D- data lines should be shorted together with a maximum series impedance of 200 Ω.
On the other hand, with the divider mode, 2 V and 2.7 V are presented on D+ and on D-.
The TPS2540/40A/41/41A integrates an auto-detect feature that supports both DCP schemes. It starts in Divider
Mode. If a BC1.2 -compliant device is attached, the TPS2540/40A/41/41A responds by discharging OUT, turning
back ON the power switch and operating in BC1.2 DCP mode. It then stays in that mode until the device is
unattached, in which case it goes back to Divider Mode.

High-Bandwidth Data Line Switch

The TPS2540/40A/41/41A passes the D+ and D- data lines through the device to enable monitoring and
handshaking while supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass
through the device without corrupting signal integrity. The data line switches are turned on in any of CDP or SDP
operating modes. The EN (or DSC if TPS2541/41A) input also needs to be at logic High for the data line
switches to be enabled.

NOTE
1. While in CDP mode, the data switches are ON even while CDP handshaking is occurring.
2. The data line switches are OFF if EN (or DSC) is low, or if in DCP mode (BC1.2, Divider mode
or Auto-detect). They are not automatically turned off if the power switch (IN to OUT) is doing
current limiting. With TPS2540/40A, the data line switches are also off when in “000” mode.
3. The data switches are for USB 2.0 differential pair only. In the case of a USB 3.0 host, the
super speed differential pairs must be routed directly to the USB connector without passing
through the TPS2540/40A/41/41A.

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Logic Control Modes

Both the TPS2540/40A and TPS2541/41A support the listed standards above for the SDP, CDP and DCP modes
using the CTL1, CTL2, and CTL3 logic I/O control pins, although their truth tables are different as shown below.
The different CTLx settings correspond to the different types of charge modes. Also, using the Auto-Detect
Mode, the Divider Mode or BC1.2 / YD/T 1591-2009 can be automatically selected without external user
interaction.

NOTE
With the TPS2540/40A, if the “000” mode is selected, the power switch will be turned off
and an output discharge resistor will be connected, while the data line switches will be
turned off.

Table 2. TPS2540/40A Control Truth Table

CTL1 CTL2 CTL3 MODE
0 0 0 OUT discharge, power switch OFF.
0 X 1 Dedicated charging port, auto-detect.
X 1 0 Standard downstream port, USB 2.0 Mode.
1 0 0 Dedicated charging port, BC1.2 only.
1 0 1 Dedicated charging port, Divider Mode only.
1 1 1 Charging downstream port, BC1.2.

Table 3. TPS2541/41A Control Truth Table

CTL1 CTL2 CTL3 MODE
0 0 X Dedicated charging port, auto-detect.
0 1 X Dedicated charging port, BC1.2.
1 0 X Dedicated charging port, Divider Mode only.
1 1 0 Standard downstream port, USB 2.0 Mode.
1 1 1 Charging downstream port, BC1.2.

Output Discharge
To allow a charging port to renegotiate current with a portable device, TPS2540/40A/41/41A uses the VBUS
discharge function. It proceeds by turning off the power switch while discharging OUT, then turning back ON the
power switch to reassert the OUT voltage.
This discharge function is automatically applied when a change at the CTLx lines results in any of the following
mode transitions.
• Any transition to and from CDP
• Any transition to and from SDP
In addition to this, a direct discharge control, DSC, is available with the TPS2541/41A, while with the
TPS2540/40A, a discharge can be achieved using the mode “000”.

Overcurrent Protection
When an over-current condition is detected, the device maintains a constant output current and reduces the
output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output has
been shorted before the device is enabled or before VIN has been applied.
The TPS2540/40A/41/41A senses the short and immediately switches into a constant-current output. In the
second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs,
high currents may flow for nominally one to two microseconds before the current-limit circuit can react. The
device operates in constant-current mode after the current-limit circuit has responded. Complete shutdown
occurs only if the fault is present long enough to activate thermal limiting. The device will remain off until the
junction temperature cools approximately 10°C and will then re-start. The device will continue to cycle on/off until
the over-current condition is removed.
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Current-Limit Thresholds
The TPS2540/40A/41/41A has two independent current-limit thresholds that are each programmed externally
with a resistor. The following equation programs the typical current-limit threshold:
48000
ISHORT =
RILIMx (3)
where ISHORT is in mA and RILIMx is in kΩ. RILIMx corresponds to RILIM0 when ILIM_SEL is logic LO and to
RILIM1 when ILIM_SEL is logic HI. The ILIM_SEL pin allows the system to digitally select between two
current-limit thresholds, which is useful in end equipment that may require a lower setting when powered from
batteries vs. wall adapters.

FAULT Response
The FAULT open-drain output is asserted (active low) during an over-temperature or current limit condition. The
output remains asserted until the fault condition is removed. The TPS2540/40A/41/41A is designed to eliminate
false FAULT reporting by using an internal deglitch circuit for current limit conditions without the need for external
circuitry. This ensures that FAULT is not accidentally asserted due to normal operation such as starting into a
heavy capacitive load. Over-temperature conditions are not deglitched and assert the FAULT signal immediately.

Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from
large current surges.

Thermal Sense
The TPS2540/40A/41/41A protects itself with two independent thermal sensing circuits that monitor the operating
temperature of the power distribution switch and disables operation if the temperature exceeds recommended
operating conditions. The device operates in constant-current mode during an over-current condition, which
increases the voltage drop across power switch. The power dissipation in the package is proportional to the
voltage drop across the power switch, so the junction temperature rises during an over-current condition. The
first thermal sensor turns off the power switch when the die temperature exceeds 135°C and the part is in current
limit. The second thermal sensor turns off the power switch when the die temperature exceeds 155°C regardless
of whether the power switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns
on after the device has cooled by approximately 10°C. The switch continues to cycle off and on until the fault is
removed. The open-drain false reporting output FAULT is asserted (active low) during an over-temperature
shutdown condition.

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APPLICATION INFORMATION

Programming the Current Limit Threshold

There are two overcurrent thresholds, which are user programmable via RILIM0 and RILIM1. The
TPS2540/40A/41/41A uses an internal regulation loop to provide a regulated voltage on the ILIM0 and ILIM1
pins. The current-limit thresholds are proportional to the current sourced out of ILIM0 and ILIM1. The
recommended 1% resistor range for RILIM0 and RILIM1 are 16.9 kΩ ≤ RILIM ≤ 750 kΩ to ensure stability of the
internal regulation loop, although not exceeding 210 kΩ results in a better accuracy. Many applications require
that the minimum current limit is above a certain current level or that the maximum current limit is below a certain
current level, so it is important to consider the tolerance of the overcurrent threshold when selecting a value for
RILIMx. The following equations calculates the resulting overcurrent threshold for a given external resistor value
(RILIMx). The traces routing the RILIMx resistors to the TPS2540/40A/41/41A should be as short as possible to
reduce parasitic effects on the current-limit accuracy.
The equations and the graph below can be used to estimate the minimum and maximum variation of the current
limit threshold for a predefined resistor value. This variation is an approximation only and does not take into
account the resistor tolerance or the variation of ILIM. For exact variation of ILIM, refer to the current limit section
of the electrical specification table.
48000
ISHORT _ min =
RILIMx1.037 (4)
48000
ISHORT _ max =
RILIMx 0.962 (5)
Current Limit Threshold Current Limit Threshold
vs vs
Current Limit Resistance Current Limit Resistance
3250 3250
3000 3000
2750
2750
2500
ISHORT - Current Limit - mA
ISHORT - Current Limit - mA

2500
2250
2250
2000
1750 2000

1500 1750 ISHORT_max

1250 ISHORT_max 1500

1000
1250
750
ISHORT_min
1000
500
250 ISHORT_min 750

0 500
0 20 40 60 80 100 120 140 160 180 200 220 10 15 20 25 30 35 40 45 50 55 60
RILIM - Current Limit Resistance - kW RILIM - Current Limit Resistance - kW

Figure 40. Figure 41.

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Product Folder Link(s): TPS2540, TPS2540A TPS2541, TPS2541A

 TPS2540, TPS2540A
TPS2541, TPS2541A
www.ti.com SLVSAG2C – OCTOBER 2010 – REVISED OCTOBER 2011

Current Limit Threshold

vs
Current Limit Resistance
1000

900

800

ISHORT - Current Limit - mA

700

600 ISHORT_max

500

400

300
ISHORT_min
200

100

0
60 80 100 120 140 160 180 200 220
RILIM - Current Limit Resistance - kW
Figure 42.

Current Limit Setpoint Example

In the following example, choose the ILIM resistor to ensure that the TPS2540/40A/41/41A does not trip off under
worst case conditions of ILIM and resistor tolerance (assume 1% resistor tolerance). For this example, IOSMIN =
2500 mA.
48000
IOSMIN = = 2500mA
R1.037
ILIMx (6)
1 1
é 48000 ù 1.037 é 48000 ù 1.037
RILIMx = ê ú =ê ú = 17.28kΩ
ë IOSMIN û ë 2500mA û (7)
Including resistor tolerance, target maximum:
17.28kΩ
RILIMx = = 17.11kΩ
1.01 (8)
Choose:
RILIMx = 16.9kΩ (9)

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Link(s): TPS2540, TPS2540A TPS2541, TPS2541A
TPS2540, TPS2540A
TPS2541, TPS2541A
SLVSAG2C – OCTOBER 2010 – REVISED OCTOBER 2011 www.ti.com

CTL Pin Configuration for Notebook States

The CTL pins provide the user with mode flexibility. Specifically, within a notebook, states S0, S3, S4, and S5 are
important for controlling power consumption. For S0 the host controller is active, so either SDP or CDP should be
selected. The notebook is responsible for sourcing at least 500mA when SDP is selected and at least 1500 mA
when CDP is selected. Figure 43 illustrates the circuit connection for TPS2541/41A using one control signal
(STATE). When STATE = logic 0, auto detect is selected (S3/S4/S5, 1.5 A). When STATE = logic 1, CDP mode
is selected (S0, 1.5 A).
FAULT

R6
R8
10 kW
20 kW

16 15 14 13
ILIM0 ILIM1 GND FAULT
5 V_HOST 1 IN OUT 12 VBUS
TPS2541/41A

DM-HOST 2 DM_OUT DM_IN 11 DM-CONN

Power Pad
DP-HOST 3 DP_OUT DP_IN 10 DP-CONN
C6
0.1 mF
4 ILIM_SEL N/C 9
DSC CTL1 CTL2 CTL3 + C7
5 6 7 8 150 mF

EN
UDG-10133
STATE

Figure 43. TPS2541/41A Application Using Single STATE Control Signal

Figure 44 illustrates the circuit connection for TPS2540/40A with STATE and ADAPTER control signals. If the
adapter is present (ADAPTER = logic 1), the TPS2540/40A supports auto detect operation when STATE = logic
0 (S3/S4/S5, 1.5 A) and CDP operation when STATE = logic 1 (S0, 1.5 A). If the adapter is not present
(ADAPTER = logic 0), the TPS2540/40A disables sleep charge when STATE = logic 0 (S3/S4/S5, power switch
off) and SDP operation when STATE = logic 1 (S0, 0.5 A).
FAULT

R3
R8
10 kW
20 kW

16 15 14 13
ILIM0 ILIM1 GND FAULT
5 V_HOST 1 IN OUT 12 VBUS
TPS2540/40A

DM-HOST 2 DM_OUT DM_IN 11 DM-CONN

Power Pad
DP-HOST 3 DP_OUT DP_IN 10 DP-CONN
C4
0.1 mF
4 ILIM_SEL N/C 9
EN CTL1 CTL2 CTL3 + C5
5 6 7 8 150 mF

EN
UDG-10134
STATE

ADAPTER

Figure 44. TPS2540/40A Application Using STATE and ADAPTER Control Signals

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 TPS2540, TPS2540A
TPS2541, TPS2541A
www.ti.com SLVSAG2C – OCTOBER 2010 – REVISED OCTOBER 2011

Layout Guidelines
TPS2540/40A/41/41A Placement: Place the TPS2540/40A/41/41A near the USB output connector and 150-µF
OUT pin filter capacitor. Connect the exposed Power PAD to the GND pin and to the system ground plane using
a via array.
IN Pin Bypass Capacitance: Place the 0.1-µF bypass capacitor near the IN pin and make the connection using
a low inductance trace.
D+ and D- Traces: Route in and out traces as controlled impedance differential pairs per the USB specification
and the Intel guideline for USB-2.0. Minimize the use of vias in the high speed data lines.

ESD
The use of a common mode choke in the upstream datapath can provide additional ESD protection from client
side cable insertion transients. In addition, a low capacitance ESD protection array such as the TPD2E001
provides a robust solution. The TPS2540EVM-623 (SLVU401) provides a good example of routing and output
datapath protection.
Using a system board, applying same design rules and protection devices as the TPS2540EVM-623 , the
TPS2540 has been tested to EN61000-4-2. The levels used were 8-kV contact discharge and 15-kV air
discharge. Voltage transients were applied between D+ terminal and the earth ground, and between D- terminal
and the earth ground, V- being connected to earth ground. Tests were performed while both powered and
unpowered. No TPS2540 failures were observed and operation was continuous.

ILIM0 and ILIM1 Pin Connections

Current limit set point accuracy can be compromised by stray leakage from a higher voltage source to the ILIM0
or ILIM1 pins. Ensure that there is adequate spacing between IN pin copper/trace and ILIM0 pin trace to prevent
contaminant buildup during the PCB assembly process. If a low current limit set point is required (RILIMx > 200
kΩ), use ILIM1 for this case as it is further away from the IN pin.

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 31

Product Folder Link(s): TPS2540, TPS2540A TPS2541, TPS2541A
TPS2540, TPS2540A
TPS2541, TPS2541A
SLVSAG2C – OCTOBER 2010 – REVISED OCTOBER 2011 www.ti.com

REVISION HISTORY

Changes from Original (October 2010) to Revision A Page

• Added TPS2540A device to the datasheet. .......................................................................................................................... 1

• Deleted All (Draft) notations for BC1.2. ................................................................................................................................ 1
• Added Longer Detach Detection Time (TPS2540A) bullet. .................................................................................................. 1
• Changed Typical Application Diagram. ................................................................................................................................. 1
• Added TPS2540A description information. ........................................................................................................................... 2
• Added Low DP_IN period in DCP mode information for the TPS2541A device .................................................................. 7
• Changed pinout drawing. ...................................................................................................................................................... 8
• Changed TPS2540/40A Control Signal drawing. ................................................................................................................ 30

Changes from Revision A (April 2011) to Revision B Page

• Added PRODUCT INFORMATION for device number TPS2540A. ..................................................................................... 2

Changes from Revision B (July 2011) to Revision C Page

• Added TPS2541A device to the datasheet. .......................................................................................................................... 1

• Added TDCPLOW column for A and non-A versions ................................................................................................................. 2
• Added PRODUCT INFORMATION for device number TPS2541A. ..................................................................................... 2
• Added Low DP_IN period in DCP mode, see Figure 32, note ............................................................................................. 2

32 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): TPS2540, TPS2540A TPS2541, TPS2541A

 PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS2540ARTER ACTIVE WQFN RTE 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2540A
& no Sb/Br)
TPS2540ARTET ACTIVE WQFN RTE 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2540A
& no Sb/Br)
TPS2540RTER ACTIVE WQFN RTE 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2540
& no Sb/Br)
TPS2540RTET ACTIVE WQFN RTE 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2540
& no Sb/Br)
TPS2541ARTER ACTIVE WQFN RTE 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2541A
& no Sb/Br)
TPS2541ARTET ACTIVE WQFN RTE 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2541A
& no Sb/Br)
TPS2541RTER ACTIVE WQFN RTE 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2541
& no Sb/Br)
TPS2541RTET ACTIVE WQFN RTE 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2541
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2014

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2540ARTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2540ARTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2540ARTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2540ARTET WQFN RTE 16 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2
TPS2540RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2540RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2540RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541ARTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541ARTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541ARTET WQFN RTE 16 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541ARTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541RTET WQFN RTE 16 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2
TPS2541RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2540ARTER WQFN RTE 16 3000 338.0 355.0 50.0
TPS2540ARTER WQFN RTE 16 3000 367.0 367.0 35.0
TPS2540ARTET WQFN RTE 16 250 210.0 185.0 35.0
TPS2540ARTET WQFN RTE 16 250 338.0 355.0 50.0
TPS2540RTER WQFN RTE 16 3000 367.0 367.0 35.0
TPS2540RTET WQFN RTE 16 250 210.0 185.0 35.0
TPS2540RTET WQFN RTE 16 250 210.0 185.0 35.0
TPS2541ARTER WQFN RTE 16 3000 338.0 355.0 50.0
TPS2541ARTER WQFN RTE 16 3000 367.0 367.0 35.0
TPS2541ARTET WQFN RTE 16 250 338.0 355.0 50.0
TPS2541ARTET WQFN RTE 16 250 210.0 185.0 35.0
TPS2541RTER WQFN RTE 16 3000 367.0 367.0 35.0
TPS2541RTER WQFN RTE 16 3000 338.0 355.0 50.0
TPS2541RTET WQFN RTE 16 250 338.0 355.0 50.0
TPS2541RTET WQFN RTE 16 250 210.0 185.0 35.0

Pack Materials-Page 2
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