Simatic S5100u

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SIEMENS
6EJ5921-1AA21
OTHER SYMBOLS:
6EJ59211AA21, 6EJ5921 1AA21, 6EJ5921-1AA21, 6EJ5 9211AA21, 6EJ5 921 1AA21, 6EJ5 921-1AA21
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SIMATIC S5
S5-100U
Programmable Controller
System Manual
CPU 100/102/103
EWA 4NEB 812 6120-02b
Edition 04

STEP ® SINEC ® and SIMATIC ® are registered trademarks of Siemens AG.
LINESTRA® is a registered trademark of the OSRAM Company.
Subject to change without prior notice.
The reproduction, transmission or use of this document or its contents is not

permitted without express written authority. Offenders will be liable for
damages. All rights, including rights created by patent grant or registration of a
utility model or design, are reserved.
Copyright© Siemens AG 1992
EWA 4NEB 812 6120-02b

Introduction
The SIMATIC S5 System Family 1

Technical Description 2
Installation Guidelines 3
Start-Up and Program Tests 4
Diagnostics and Troubleshooting 5
Addressing 6
Introduction to STEP 5 7
STEP 5 Operations 8
Integrated Blocks and Their Functions 9
Interrupt Processing 10
Analog Value Processing 11
The Integral Real-Time Clock, for CPU 103 and Higher 12
Connecting the S5-100U to SINEC L1 13
Module Spectrum 14
Function Modules 15
A/B/C
Appendices D/E/F
Index
EWA 4NEB 812 6120-02b

EWA 4NEB 812 6120-02b

S5-100U Contents
Contents
Page
How to Use This Manual ............................................. xv
1 The SIMATIC S5 System Family .................................. 1 - 1
2 Technical Description ......................................... 2 - 1
2.1 Programmable Controller Design ............................. 2 - 1
2.2 Principle of Operation for the Programmable Controller . . . . . . . . . . . . . . 2 - 3

2.2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
2.2.2 Mode of Operation for the External I/O Bus . . . . . . . . . . . . . . . . . . . . . . 2 - 6
3 Installation Guidelines ......................................... 3 - 1
3.1 Installing S5-100U Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1

3.1.1 Assembling a Tier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1
3.1.2 Multi-Tier Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5
3.1.3 Cabinet Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
3.1.4 Vertical Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3.2 Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
3.2.1 Connection Methods: Screw-Type Terminals and Crimp Snap-in ...... 3 - 9
3.2.2 Connecting the Power Supply to the S5-100U . . . . . . . . . . . . . . . . . . . . 3 - 12
3.2.3 Connecting Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 13
3.2.4 Connecting the Digital Input/Output Module . . . . . . . . . . . . . . . . . . . . . . 3 - 18
3.3 Electrical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20

3.3.1 Electrical Configuration for the S5-100U . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20
3.3.2 Electrical Configuration with External I/Os . . . . . . . . . . . . . . . . . . . . . . . 3 - 21
3.3.3 Non-Floating and Floating Configurations . . . . . . . . . . . . . . . . . . . . . . . . 3 - 25
3.4 Wiring Arrangement, Shielding, and Measures to

Guard against Electromagnetic Interference . . . . . . . . . . . . . . . . . . . . . . 3 - 29
3.4.1 Running Cables Inside and Outside a Cabinet . . . . . . . . . . . . . . . . . . . . 3 - 29
3.4.2 Running Cables Outside Buildings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 30
3.4.3 Equipotential Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 31
3.4.4 Shielding Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 32
3.4.5 Special Measures for Interference-Free Operation . . . . . . . . . . . . . . . . . 3 - 33
EWA 4NEB 812 6120-02b v

Contents S5-100U
Page
4 Start-Up and Program Tests ..................................... 4 - 1
4.1 Operating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

4.1.1 CPU Operator Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1
4.1.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1
4.1.3 Performing an Overall Reset on the Programmable Controller . . . . . . . . . 4 - 2
4.2 Starting Up a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3

4.2.1 Suggestions for Configuring and Installing the Product . . . . . . . . . . . . . . 4 - 3
4.2.2 Procedures for Starting Up the Programmable Controller . . . . . . . . . . . . 4 - 4
4.3 Loading the Program into the Programmable Controller . . . . . . . . . . . . . . 4 - 5
4.4 Backing Up the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 7

4.4.1 Backing Up the Program on a Memory Submodule ................ 4 - 7
4.4.2 Function of the Back-Up Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 8
4.5 Program-Dependent Signal Status Display “STATUS” .............. 4 - 8
4.6 Direct Signal Status Display “STATUS VAR” ..................... 4 - 9
4.7 Forcing Outputs, “FORCE”, for CPU 103 and Higher ............... 4 - 10
4.8 Forcing Variables, “FORCE VAR” ............................ 4 - 10
4.9 Search Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11
4.10 Program Check, for CPU 103 and Higher ....................... 4 - 11
5 Diagnostics and Troubleshooting ................................ 5 - 1
5.1 Indication of Errors by LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1
5.2 CPU Malfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.2.1 “ISTACK” Analysis Function ................................ 5 - 1
5.2.2 Interrupt Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4
5.2.3 Errors during Program Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
5.2.4 Explanation of the Mnemonics Used in “ISTACK” ................. 5 - 6
5.3 Program Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8

5.3.1 Locating the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8
5.3.2 Tracing the Program with the “BSTACK” Function . . . . . . . . . . . . . . . . . 5 - 11
5.4 I/O Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12
5.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12
5.6 The Last Resort ......................................... 5 - 13
vi EWA 4NEB 812 6120-02b

S5-100U Contents
Page
6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1
6.1 Slot Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1
6.2 Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4
6.3 Analog Modules ......................................... 6 - 5
6.4 Combined Input Modules and Output Modules . . . . . . . . . . . . . . . . . . . . 6 - 6

6.4.1 Output Modules with Error Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 6
6.4.2 Digital Input/Output Module, 16 Inputs, 16 Outputs, 24 V DC
for All CPUs Version 8MA02 and Higher and
for CPU 102, Version 8MA01, Revision 5 and Higher . . . . . . . . . . . . . . . 6 - 7
6.4.3 Function Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 7
6.5 The Structure of Process Image Input and Output Tables . . . . . . . . . . . . 6 - 8

6.5.1 Accessing the Process Image Input Table (PII) . . . . . . . . . . . . . . . . . . . 6 - 10
6.5.2 Accessing the Process Image Output Table (PIQ) . . . . . . . . . . . . . . . . . 6 - 11
6.6 Interrupt Process Images Tables and Time-Controlled Program

Processing in OB13 for CPU 103, Version 8MA02 and Higher . . . . . . . . . 6 - 12
6.6.1 Accessing the Interrupt PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 12
6.6.2 Accessing the Interrupt PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14
6.7 RAM Address Assignments ................................. 6 - 15
7 Introduction to STEP 5 ......................................... 7 - 1
7.1 Writing a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1

7.1.1 Methods of Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1
7.1.2 Operand Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.1.3 Circuit Diagram Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.2.1 Linear Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4
7.2.2 Structured Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5
7.3 Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.3.1 Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 9
7.3.2 Program Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.3 Sequence Blocks, for CPU 103 and Higher ..................... 7 - 11
7.3.4 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.5 Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 16
7.4 Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18

7.4.1 Program Processing with CPU 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 19
7.4.2 START-UP Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 24
7.4.3 Cyclic Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 26
7.4.4 Time-Controlled Program Processing, for CPU 103
Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 28
EWA 4NEB 812 6120-02b vii

Contents S5-100U
Page
7.4.5 Interrupt-Driven Program Processing, for CPU 103

Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 29
7.5 Processing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30

7.5.1 Changing Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.2 Changing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.3 Compressing the Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.6 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 31
8 STEP 5 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1
8.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1

8.1.1 Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8.1.2 Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8.1.3 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10
8.1.4 Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8.1.5 Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 25
8.1.6 Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30
8.1.7 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 31
8.1.8 Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 33
8.1.9 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 38
8.2 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 39

8.2.1 Load Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . . 8 - 40
8.2.2 Enable Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . 8 - 41
8.2.3 Bit Test Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . 8 - 42
8.2.4 Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 44
8.2.5 Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 48
8.2.6 Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 50
8.2.7 Decrement/Increment, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . 8 - 52
8.2.8 Disable/Enable Interrupt, for CPU 103 Version 8MA02 and Higher . . . . . . 8 - 53
8.2.9 “DO” Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . . 8 - 54
8.2.10 Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 56
8.2.11 Substitution Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . 8 - 58
8.3 System Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . 8 - 64

8.3.1 Set Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.2 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.3 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 67
8.3.4 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 68
8.4 Condition Code Generation ................................. 8 - 69
8.5 Sample Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71

8.5.1 Momentary-Contact Relay/Edge Evaluation . . . . . . . . . . . . . . . . . . . . . . 8 - 71
8.5.2 Binary Scaler/Binary Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71
8.5.3 Clock/Clock-Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 73
viii EWA 4NEB 812 6120-02b

S5-100U Contents
Page
9 Integrated Blocks and Their Functions ............................. 9 - 1
9.1 Assigning Internal Functions to DB1,

for CPU 103 Version 8MA03 and Higher . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1
9.1.1 Configuration and Default Settings for DB1 . . . . . . . . . . . . . . . . . . . . . . 9 - 1
9.1.2 Setting the Address for the Parameter Error Code in DB1 . . . . . . . . . . . . 9 - 2
9.1.3 Assigning Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.4 Rules for Setting Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.5 How to Recognize and Correct Parameter Errors . . . . . . . . . . . . . . . . . . 9 - 6
9.1.6 Transferring DB1 Parameters to the Programmable Controller . . . . . . . . . 9 - 9
9.1.7 Reference Guide for Setting Parameters in DB1 .................. 9 - 10
9.1.8 Defining System Characteristics in DB1 . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11
9.2 Integrated Function Blocks,

9.2.1 Code Converter : B4 - FB240 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 12
9.2.2 Code Converter : 16 - FB241 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 12
9.2.3 Multiplier : 16 - FB242 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 13
9.2.4 Divider : 16 - FB243 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 13
9.2.5 Analog Value Conditioning Modules FB250 and FB251 . . . . . . . . . . . . . . 9 - 14
9.3 Integrated Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14

9.3.1 Scan Time Triggering OB31, for CPU 103 and Higher .............. 9 - 14
9.3.2 Battery Failure OB34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14
9.3.3 OB251 PID Algorithm,
10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10.1 Interrupt Processing with OB2, for CPU 103

Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10.2 Calculating Interrupt Reaction Times . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5
11 Analog Value Processing ...................................... 11 - 1
11.1 Analog Input Modules .................................... 11 - 1
11.2 Connecting Current and Voltage Sensors to Analog

Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1
11.2.1 Voltage Measurement with Isolated or
Non-Isolated Thermocouples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11.2.2 Two-Wire Connection of Voltage Sensors . . . . . . . . . . . . . . . . . . . . . . 11 - 3
11.2.3 Two-Wire Connection of Current Sensors . . . . . . . . . . . . . . . . . . . . . . 11 - 4
11.2.4 Connection of Two-Wire and Four-Wire Transducers . . . . . . . . . . . . . . 11 - 4
11.2.5 Connection of Resistance Thermometers . . . . . . . . . . . . . . . . . . . . . . 11 - 6
11.3 Start-Up of Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7
11.4 Analog Value Representation of Analog Input Modules ............. 11 - 11
EWA 4NEB 812 6120-02b ix

Contents S5-100U
Page
11.5 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19

11.5.1 Connection of Loads to Analog Output Modules . . . . . . . . . . . . . . . . . . 11 - 19
11.5.2 Analog Value Representation of Analog Output Modules . . . . . . . . . . . . 11 - 20
11.6 Analog Value Conversion: Function Blocks FB250 and FB251 . . . . . . . . 11 - 22

11.6.1 Reading in and Scaling an Analog Value - FB250 - . . . . . . . . . . . . . . . . 11 - 22
11.6.2 Outputting of Analog Values - FB251 - . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
12 The Integral Real-Time Clock, for CPU 103 Version 8MA02 and Higher ... 12 - 1
12.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 1
12.2 Setting Parameters in DB1, for CPU 103 Version 8MA03

and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 2
12.2.1 Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 2
12.2.2 Reading the Current Clock Time and the Current Date . . . . . . . . . . . . . 12 - 3
12.2.3 DB1 Parameters Used for the Integral Real-Time Clock . . . . . . . . . . . . 12 - 4
12.3 Programming the Integral Real-Time Clock in DB1,

for CPU 103 Version 8MA03 and Higher . . . . . . . . . . . . . . . . . . . . . . . 12 - 5
12.3.1 Setting the Clock in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 5
12.3.2 Setting the Prompt Time in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6
12.3.3 Setting the Operating Hours Counter in DB1 . . . . . . . . . . . . . . . . . . . . 12 - 7
12.3.4 Entering the Clock Time Correction Factor in DB1 . . . . . . . . . . . . . . . . 12 - 7
12.4 Structure of the Clock Data Area ............................ 12 - 8
12.5 Structure of the Status Word and How to Scan It ................. 12 - 12
12.6 Setting Parameters for the Clock Data Area and the Status Word
in the System Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 15
12.7 Programming the Integral Real-Time Clock in the

User Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 21
12.7.1 Reading and Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 21
12.7.2 Programming the Prompt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 25
12.7.3 Programming the Operating Hours Counter . . . . . . . . . . . . . . . . . . . . . 12 - 30
12.7.4 Entering the Clock Time Correction Factor . . . . . . . . . . . . . . . . . . . . . 12 - 35
x EWA 4NEB 812 6120-02b

S5-100U Contents
Page
13 Connecting the S5-100U to SINEC L1, for CPU 102 and Higher ......... 13 - 1
13.1 Connecting the Programmable Controllers to the

L1 Bus Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 1
13.2 Setting Parameters in the Programmable Controller

for Exchanging Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 1
13.2.1 How to Program in a Function Block, for CPU 102 and Higher ....... 13 - 2
13.2.2 Setting Parameters in DB1, for CPU 103 and Higher . . . . . . . . . . . . . . 13 - 5
13.3 Coordinating Data Exchange in the Control Program . . . . . . . . . . . . . . . 13 - 7

13.3.1 Sending Data ......................................... 13 - 8
13.3.2 Receiving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 9
13.3.3 Programming the Messages in a Function Block . . . . . . . . . . . . . . . . . 13 - 11
14 Module Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 1
14.1 General Technical Specifications ............................ 14 - 3
14.2 Power Supply Modules ................................... 14 - 4
14.3 Central Processing Units ................................. 14 - 7
14.4 Bus Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 10
14.5 Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 14
14.6 Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 16

14.6.1 Digital Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 16
14.6.2 Digital Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 26
14.6.3 Digital Input/Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 36
14.7 Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 38

14.7.1 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 38
14.7.2 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 56
15 Function Modules ........................................... 15 - 1
15.1 Comparator Module 2×1 to 20 mA/0.5 to 10 V .................. 15 - 1
15.2 Timer Module 2×0.3 to 300 s .............................. 15 - 4
15.3 Simulator Module ....................................... 15 - 7
15.4 Diagnostic Module ...................................... 15 - 9
EWA 4NEB 812 6120-02b xi

Contents S5-100U
Page
15.5 Counter Module 2×0 to 500 Hz ............................. 15 - 12
15.6 Counter Module 25/500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 17

15.6.1 Installation Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 20
15.6.2 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 25
15.6.3 Functional Description of the Counter Mode . . . . . . . . . . . . . . . . . . . . 15 - 27
15.6.4 Functional Description of the Position Decoder . . . . . . . . . . . . . . . . . . 15 - 29
15.6.5 Entering New Setpoints for the Counter and
Position Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 38
15.6.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 39
15.7 Closed-Loop Control Module IP 262 . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 41
15.8 IP 263 Positioning Module ................................. 15 - 45
15.9 IP 264 Electronic Cam Controller Module ...................... 15 - 49
15.10 IP 265 High Speed Sub Control ............................. 15 - 52
15.11 Positioning Module IP 266 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 55
15.12 Stepper Motor Control Module IP 267 ........................ 15 - 59
15.13 Communications Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 62

15.13.1 Printer Communications Module CP 521 . . . . . . . . . . . . . . . . . . . . . . 15 - 62
15.13.2 Communications Module CP 521 BASIC . . . . . . . . . . . . . . . . . . . . . . 15 - 65
xii EWA 4NEB 812 6120-02b

S5-100U Contents
Appendices
A Operations List, Machine Code and List of Abbreviations .............. A - 1
A.1 Operations List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 1

A.1.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 1
A.1.2 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 8
A.1.3 System Operations, for CPU 102 and Higher . . . . . . . . . . . . . . . . . . . . . A - 13
A.1.4 Evaluation of CC 1 and CC 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 14
A.2 Machine Code Listing ..................................... A - 15
A.3 List of Abbreviations ...................................... A - 18
B Dimension Drawings .......................................... B - 1
C Active and Passive Faults in Automation Equipment .................. C - 1
D Information for Ordering Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D - 1
E Reference Materials ........................................... E - 1
F Siemens Addresses Worldwide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F - 1
Index
EWA 4NEB 812 6120-02b xiii

EWA 4NEB 812 6120-02b

S5-100U How to Use This System Manual
How to Use This System Manual

The S5-100U is a programmable controller for lower and intermediate performance ranges. It meets
all the requirements for a modern programmable controller. To use this controller optimally, you
need detailed information.
In this system manual we have attempted to present this information as completely and as well
organized as possible. Certain information is repeated in various chapters so that you do not have
to leaf through the manual to find what you need.
This How to Use This System Manual section gives you information that will make it easier for you
to find what you need. This section explains how the manual is organized.
Contents of This System Manual

• Hardware Description (Chapters 1, 2, and 3)
These chapters describe the controllers: how they fit into the SIMATIC® S5 family of
programmable controllers, how they function, and how you install them.
• Start-Up Information (Chapters 4, 5, and 6)
These chapters summarize the information you need to start up your programmable controller.
These chapters describe how the hardware and software influence each other.
• The Programming Language of the Programmable Controllers (Chapters 7, 8, and 9)
These chapters describe the structure, operations, and structuring aids of the STEP® 5 pro-
gramming language.
• Functions of the Programmable Controllers (Chapters 10, 11, 12, 13)
Each of these chapters contains a complete description of a particular function, from wiring to
programming. Subjects include analog value processing, counter and interrupt inputs, integral
clock, and the programmable controller as a SINEC® L1 slave.
• Module Spectrum (Chapters 14 and 15)
These chapters contain information about all the currently available S5-100U modules that you
can use to expand your controller. Chapter 15, Function Modules, includes the modules that
require an extensive description (i. e., more than just technical specifications).
• Overviews (Appendices)
In these chapters you will find not only a complete list of operations but also dimension
drawings, a description of errors that may occur during operation of the programmable controller,
maintenance and repair procedures, a list of accessories, and reference literature about
programmable controllers.
You will find correction pages at the end of the system manual. Use them to indicate any
corrections, additions, or suggestions for improvement you might have. Send these suggestions to
us. They will help us to improve the next edition of this system manual.
EWA 4NEB 812 6120-02b xv

How to Use This System Manual S5-100U
Conventions
This system manual is organized in menu form to make it easier for you to find information. This
means the following:
• Each chapter is marked with printed tabs.
• At the front of the system manual is an overview page that lists the title of each chapter.
Following this page, you will find a table of contents.
• At the beginning of each chapter is a table of contents for that chapter. Each chapter has three
level headings that are numbered. The fourth level heading is not numbered but appears in
boldface type.
• Pages, figures, and tables are numbered separately for each chapter. On the back of the table
of contents for each chapter you will find a list of the figures and tables that appear in that
chapter.
This system manual employs the following specific structuring devices:

• Specific terms have characteristic abbreviations (e. g., programmer is PG).
Appendix A contains a list of abbreviations.
• Footnotes are marked with a raised number (e. g., “1”) or a raised asterisk (“ * ”). You will find
the corresponding explanations in the lower margin of the page or under a figure or table if the
footnote appears in one of these.
• Lists are designated with bullets (• as in this particular listing) or with hyphens (-).
• Cross references are indicated as follows: (see section 7.3.2). There are no references to
specific page numbers.
• Dimensions in drawings are indicated in millimeters and inches.
• Value ranges are indicated as follows: 17 to 21 or 17-21.
• Especially important information appears in framed boxes such as the following:
Warning
You will find definitions for the terms “Warning,” “Danger,” “Caution,” and “Note” in the Safety-
Related Guidelines for the User at the end of the introduction.
xvi EWA 4NEB 812 6120-02b

S5-100U How to Use This System Manual
Changes Made to the Second Edition of the S5-100U System Manual

(Order Number: 6ES5 998-0UB22)
S5-100U System Manual (Order Number 6ES5 998-0UB23) has been completely revised:
• The format was adapted to the other system manuals in the SIMATIC S5 family.
• The contents were updated and reorganized.
Some of the functions of CPU 103 have been expanded:

• The default settings (default parameters) for DB1 have been integrated into CPU 103
version 8MA03. This feature makes it easier for you to use the internal CPU functions.
The following chapters were included or completely revised in the system manual:
- Chapter 9 “Integrated Blocks and Their Functions”
- Chapter 12 “Integral Real-Time Clock, for CPU 103 Version 8MA02 and Higher”
- Chapter 13 “Connecting the S5-100U to SINEC L1, for CPU 102 and Higher”
• The execution times of some operations have been reduced considerably, compared to the
“old” CPU 103. For the new execution times refer to the list of operations in Appendix A.
The S5-100U system has been expanded to include an additional module:

• The “Communications Module CP 521 BASIC” is described in section 15.10.2.
Changes Made to the Third Edition of the S5-100U System Manual

(Order Number: 6ES5 998-0UB23)
The contents were updated.
Training
Siemens offers a wide range of training courses for SIMATIC S5 users. Contact your Siemens
representative for more information.
EWA 4NEB 812 6120-02b xvii

How to Use This System Manual S5-100U
Safety-Related Guidelines for the User
This document provides the information required for the intended use of the particular product. The
documentation is written for technically qualified personnel.
Qualified personnel as referred to in the safety guidelines in this document as well as on the product
itself are defined as follows.
• System planning and design engineers who are familiar with the safety concepts of automation
equipment.
• Operating personnel who have been trained to work with automation equipment and are
conversant with the contents of the document in as far as it is connected with the actual
operation of the plant.
• Commissioning and service personnel who are trained to repair such automation equipment and
who are authorized to energize, de-energize, clear, ground, and tag circuits, equipment, and
systems in accordance with established safety practice.
Danger Notices
The notices and guidelines that follow are intended to ensure personal safety, as well as protect the
products and connected equipment against damage.
The safety notices and warnings for protection against loss of life (the users or service personnel) or
for protection against damage to property are highlighted in this document by the terms and
pictograms defined here. The terms used in this document and marked on the equipment itself have
the following significance.
Danger Warning
indicates that death, severe personal injury indicates that death, severe personal injury or
or substantial property damage will result if substantial property damage can result if
proper precautions are not taken. proper precautions are not taken.
Caution Note
indicates that minor personal injury or contains important information about the
property damage can result if proper product, its operation or a part of the doc-
precautions are not taken. ument to which special attention is drawn.
Proper Usage
Warning
• The equipment/system or the system components may only be used for the
applications described in the catalog or the technical description, and only in
combination with the equipment, components, and devices of other manu-
facturers as far as this is recommended or permitted by Siemens.
• The product will function correctly and safely only if it is transported, stored, set
up, and installed as intended, and operated and maintained with care.
xviii EWA 4NEB 812 6120-02b

1 The SIMATIC S5 System Family
EWA 4NEB 812 6120-02b

Figures
1-1 Members of the SIMATIC S5 System Family ...................... 1 - 1
EWA 4NEB 812 6120-02b

The SIMATIC S5 System Family S5-100U
The S5-100U has the following features:
• Modular Design
Depending on the CPU you use, the S5-100U allows you to have a maximum of 448 digital
inputs and outputs. It is suitable for machine control and for process automation and monitoring
on a medium scale. The S5-100U allows a broad expansion capability with various types of
modules to adapt optimally to a control task.
• Rugged, Lightweight Design

All of the modules you can use with the S5-100U are block-type modules that are small, rugged,
and easy to use. The modules operate without fans. None of these modules has electro-
magnetically sensitive electronics. The modules are plugged into bus units and screwed tightly
so that they are vibration-proof.
The bus units snap onto a standard mounting rail. You can configure the S5-100U in one or
more tiers and configure it vertically or horizontally. The S5-100U offers such a wide range of
configuration possibilities that you can use it in rough and difficult operating conditions.
• Simple Programming
The programming language is STEP 5 and its comprehensive operations set. It provides three
different methods of representation, - four, if you have a CPU 103 or higher.
You can use any of the U series programmers to program your S5-100U, or you can load
programs from memory submodules.
1-2 EWA 4NEB 812 6120-02b

2 Technical Description
2.1 Programmable Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1
2.2 Principle of Operation for the Programmable Controller . . . . . . . . . 2 - 3

2.2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
2.2.2 Mode of Operation for the External I/O Bus . . . . . . . . . . . . . . . . . 2 - 6
EWA 4NEB 812 6120-02b

Figures
2-1 The S5-100U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1

2-2 Functional Units of the S5-100U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
2-3 Example of an Arithmetic Logic Unit’s Mode of Operation ............ 2 - 5
2-4 Accumulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5
2-5 Structure of the External I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 6
2-6 Data Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 7
Tables
2-1 Retentive and Non-Retentive Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5

2-2 Number of Bits per Module in the Shift Register . . . . . . . . . . . . . . . . . . . . 2 - 8
EWA 4NEB 812 6120-02b

Technical Description S5-100U
Input/output modules
Input/output modules transfer information between the CPU and such process peripherals as
sensors, actuators, and transducers. You can use the following types of input/output modules
with your S5-100U:
• Digital input modules and digital output modules (4, 8, and 16/16 channel)
- Use these modules for simple control tasks involving signal states “0” and “1” only.
• Analog input modules and analog output modules
- Use these modules to record and generate such variable quantities as currents and
voltages.
• Timer module
- Use this module to set various times without having to change the program.
• Counter module
- Use this module to count pulses up to 500 Hz. You can input comparison values without
having to change the program.
• High-speed counter/position detection module
- Use the high-speed counter to record high-speed counter pulses of 25/500 kHz. You can
use this module for position detection in a positioning task.
• Comparator module
- This module makes it possible for you to monitor preset comparison values, such as for
current and voltage.
• Simulator module
- Use this module to generate digital input signals or to display digital output signals.
• Diagnostic module
- Use this module to check the function of the I/O bus.
• Communications module (CP)
- Use this module to output message texts with the date and clock time to a connected
printer. You can also use this module to connect to external systems.
• Intelligent I/O module (IP)
- Use these intelligent input/output modules for such special tasks as temperature control
and positioning tasks.
Bus units with terminal blocks (Crimp-snap-in or SIGUT, screw type)

Use bus units to connect the CPU to input/output modules. You can plug two input/output
modules into a single bus unit.
Interface modules (IM)

Use these modules to assemble your S5-100U in a multi-tier configuration.
Standard mounting rail

Mount your programmable controller on the standard mounting rail.
2-2 EWA 4NEB 812 6120-02b

S5-100U Technical Description
2.2 Principle of Operation for the Programmable Controller
The remainder of this chapter explains how your S5-100U processes your program.
2.2.1 Functional Units
CPU
Process Interrupt
Program Timers Counters Flags I/O image process System
memory tables I/O image data
tables*
RAM
ROM
Memory
(operating submodule
system)
Processor
ALU Serial
(ACCU 1 and 2,
port
bit-ACCU (RLO))
I/O bus
Digital Analog
modules: modules: Function
- input - input modules
- output - output
I/O modules
* Beginning with CPU 103, version 8MA02
Figure 2-2. Functional Units of the S5-100U
EWA 4NEB 812 6120-02b 2-3

Program Memory (EPROM/EEPROM)

In order to safely store the control program outside of your S5-100U, you must store it on an
EPROM or EEPROM memory submodule (see section 4.4).
Programs that are available on a memory submodule (EPROM or EEPROM) can be copied to the
internal program memory (see section 4.3). This internal program memory is a reserved area of the
CPU's internal RAM memory.
The internal RAM memory has the following characteristics:

• The memory contents can be changed quickly.
• Memory contents are lost when there is a supply voltage failure and there is no battery backup.
Operating System (ROM)

The operating system contains system programs that determine how the user program is executed,
how inputs and outputs are managed, how the memory is divided, and how data is managed.
The operating system is fixed and cannot be changed.
Process Image Tables (PII, PIQ)

Signal states of input and output modules are stored in the CPU in “process image tables”. Process
image tables are reserved areas in the RAM of the CPU.
Input and output modules have the following separate image tables:
• Process image input table (PII)
• Process image output table (PIQ)
Serial Interface
You can connect programmers, operator panels, and monitors to the serial port (cable connector).
You can use the serial port to connect your S5-100U as a slave to the SINEC L1 local area network.
Timers, Counters, Flags

The CPU has timers, counters, and flags available internally that the control program can use.
The program can set, delete, start, and stop the timers and counters. The time and count values are
stored in reserved areas of the RAM memory.
There is another area in the RAM memory where information such as intermediate results can be
stored as flags. You can address the flags by bits, bytes, or words.
If battery backup is available, then some of the flags and counters remain in the internal RAM
memory even if the supply voltage fails or your S5-100U is switched off. These flags and counters
are retentive.
2-4 EWA 4NEB 812 6120-02b

Table 2-1 gives information about the number and retentive characteristics (the internal memory
contents are retained/are not retained) of these timers, counters, and flags.
Table 2-1. Retentive and Non-Retentive Operands
Retentive Non-Retentive
Operand
CPU 100 to 103 CPU 100 CPU 102 CPU 103
Flags 0.0 to 63.7 64.0 to 127.7 64.0 to 127.7 64.0 to 255.7
Counters 0 to 7 8 to 15 8 to 31 8 to 127
Timers 0 to 15 0 to 31 0 to 127
Arithmetic Unit
The arithmetic unit (ALU) consists of two accumulators, ACCU 1 and 2. The accumulators can
process byte and word operations.
Load Process Transfer

information information information
from the PII. in ACCU 1 and ACCU 2. to the PIQ.
Figure 2-3. Example of an Arithmetic Logic Unit’s Mode of Operation
Accumulator Design
ACCU 2 ACCU 1
15 8 7 0 15 8 7 0
High byte Low byte High byte Low byte
Figure 2-4. Accumulator Design
Processor
According to the control program, the processor calls statements in the program memory in
sequence and executes them. It processes the information from the PII and takes into consideration
the values of internal timers and counters as well as the signal states of internal flags.
External I/O Bus

The I/O bus is the electrical connection for all signals that are exchanged between the CPU and the
S5-100U modules in a programmable controller.
EWA 4NEB 812 6120-02b 2-5

2.2.2 Mode of Operation for the External I/O Bus
The S5-100U has a serial bus for the transfer of data between the CPU and the I/O modules. This
serial bus has the following characteristics:
• The modular design permits optimal adaptation to the particular control task.
• No addresses have to be set on the I/O modules.
• A terminating resistor connector is not required.
• Direct access to individual modules is not possible.
A number of shift registers moves the data (Figure 2-5).
Four data bits and one check bit for bus monitoring are assigned to each slot in the bus unit. All
modules requiring more than four data bits have their own shift register and therefore do not have to
use the shift register of the particular slot.
Slot number Data ring bus
CPU
0 1 2 3
5 Bits
Shift register
of a slot
Shift register of an
8-channel digital module n x 5 Bits
or of an analog module n=2, 4, 6 to 16
Figure 2-5. Structure of the External I/O Bus
2-6 EWA 4NEB 812 6120-02b

Data Cycle
Prior to a program scan, the external I/O bus transfers current information from the input modules to
the process image input table (PII). At the same time, information contained in the process image
output table (PIQ) is transferred to the output modules.
Data cycle
aaaaaaaaaaaaaaaaaaaaaa
Shift Program scanning Shift
data data
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
Time axis
Transfer data from the shift register to
the output modules.
Load data from the input

modules into the shift register.
Figure 2-6. Data Cycle
Interrupt Data Cycle, for CPU 103 version 8MA02 and higher
There is an interrupt input data cycle prior to each time-controlled or interrupt-driven program scan.
Before a time-controlled program scan, current information about the input modules is read into the
interrupt PII. Before an interrupt-driven program scan, interrupt inputs on slots 0 and 1 only are read
into the interrupt PII.
Following a time-controlled program scan, there is not an interrupt output data cycle until data has
been moved into the interrupt PIQ via a transfer operation (see section 6.6.2).
Information is output from the interrupt PIQ to the output modules during an interrupt output data
cycle. The PIQ is updated.
EWA 4NEB 812 6120-02b 2-7

Length of the Shift Register

The total length of the shift register is obtained from the sum of the data bits of all plugged-in
modules and of the empty slots. The check bit is not counted.
You must know the length of the shift register to be able to determine the data cycle time. Data
cycle time is 25 µs x number of data bits.
Table 2-2. Number of Bits per Module in the Shift Register
Plugged-in Module Number of Data Bits
Diagnostic module or vacant slot 4
4-channel digital input and output modules 4
500 Hz comparator module, 500 Hz timer module, 4

500 Hz counter module
25 KHz counter module 32
8-channel digital input and output modules 8
Digital input and output module, 16 inputs/16 outputs 16
Simulator module 8
Analog modules for each activated channel 16*
CP 521, IP 262, IP 266, IP 267 64
Refer to the individual manuals for information on other modules.
* This does not apply to the 466-8MC11 analog input module (8 data bits).
The CPU specifies the maximum length of the shift register in a particular configuration.
• CPU 100: 256 data bits, 128 (max.) of these from analog modules
Note
If the maximum expansion allowed is exceeded, the S5-100U goes into the STOP mode.
The “PEU” bit (I/O not ready) is set in the ISTACK.
2-8 EWA 4NEB 812 6120-02b

Examples:
a) CPU 100: This CPU lets you operate six digital modules (8-channel) and two analog modules
(4-channel):
[6 x 8+2 x (4 x 16)]=48+128<256
b) CPU 100: This CPU does not let you use three digital modules (8-channel) with three analog
modules (4-channel) because the maximum permissible number of analog data bits
would be exceeded:
[3 x 8+3 x (4 x 16)]=24+192<256
c) CPU 102: This CPU lets you operate seven digital modules (8-channel) and four analog
modules (4-channel):
[7 x 8+4 x (4 x 16)]=56+256<480
d) CPU 102: This CPU does not let you use 20 digital modules (8-channel) with 5 analog
modules (4-channel) because the maximum permissible number of analog data bits
would be exceeded:
[20 x 8+5 x (4 x 16)]=160+320=480
e) CPU 103: This CPU lets you operate 24 digital modules (8-channel) and eight analog modules
(4-channel):
[24 x 8+8 x (4 x 16)]=192+512=704
f) CPU 103: This CPU does not let you use 31 digital modules (8-channel) with four analog
modules (2-channel) because the maximum permissible number of slots would be
exceeded:
[31 x 8+4 x (2 x 16)]=248+128<704
EWA 4NEB 812 6120-02b 2-9

EWA 4NEB 812 6120-02b

3 Installation Guidelines
3.1 Installing S5-100U Components . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1

3.1.1 Assembling a Tier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1
3.1.2 Multi-Tier Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5
3.1.3 Cabinet Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
3.1.4 Vertical Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3.2 Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
3.2.1 Connection Methods: Screw-Type Terminals and Crimp Snap-in . . 3 - 9
3.2.2 Connecting the Power Supply to the S5-100U . . . . . . . . . . . . . . . 3 - 12
3.2.3 Connecting Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 13
3.2.4 Connecting the Digital Input/Output Module . . . . . . . . . . . . . . . . . 3 - 18
3.3 Electrical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20

3.3.1 Electrical Configuration for the S5-100U . . . . . . . . . . . . . . . . . . . . 3 - 20
3.3.2 Electrical Configuration with External I/Os . . . . . . . . . . . . . . . . . . . 3 - 21
3.3.3 Non-Floating and Floating Configurations . . . . . . . . . . . . . . . . . . . 3 - 25
3.4 Wiring Arrangement, Shielding, and Measures to . . . . . . . . . . . . . 3 - 29

Guard against Electromagnetic Interference
3.4.1 Running Cables Inside and Outside a Cabinet . . . . . . . . . . . . . . . 3 - 29
3.4.2 Running Cables Outside Buildings . . . . . . . . . . . . . . . . . . . . . . . . 3 - 30
3.4.3 Equipotential Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 31
3.4.4 Shielding Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 32
3.4.5 Special Measures for Interference-Free Operation . . . . . . . . . . . . . 3 - 33
EWA 4NEB 812 6120-02b

Figures
3-1 Mounting the PS 930 Power Supply Module . . . . . . . . . . . . . . . . . . . . . . . 3 - 2

3-2 Removing Bus Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3
3-3 Coding System to Prevent an Inadvertent Interchange of Modules . . . . . . . . 3 - 4
3-4 Interconnecting Tiers with Interface Modules (6ES5 316-8MA12) ........ 3 - 5
3-5 Multi-Tier Configuration in a Cabinet with the
IM 316 Interface Module (6ES5 316-8MA12) . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
3-6 Cabinet Mounting with a Series of Devices . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3-7 Vertically Mounting a Programmable Controller . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3-8 SIGUT/Screw-Type Connection Method . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
3-9 Mounting the Crimp Snap-in Terminal ........................... 3 - 10
3-10 Disconnecting a Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 11
3-11 Connecting a Power Supply Module and a CPU . . . . . . . . . . . . . . . . . . . . . 3 - 12
3-12 Two-Wire Connection of a Sensor to Channel 2 . . . . . . . . . . . . . . . . . . . . . 3 - 14
3-13 Two-Wire Connection of a Lamp to Channel 3 . . . . . . . . . . . . . . . . . . . . . . 3 - 15
3-14 Connecting a Sensor to Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 16
3-15 Connecting a Lamp to Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 17
3-16 Front View of the Digital I/O Module with a Crimp Snap-In Connector
(simplified view and not true to scale) ........................... 3 - 18
3-17 Connecting a Sensor and a Load to Digital Input/Output Module 482 . . . . . . 3 - 19
3-18 Configuration Possibility: S5-100U with 115/230 V AC Power Supply
for Programmable Controller, Sensors, and Actuators . . . . . . . . . . . . . . . . . 3 - 22
3-19 Configuration Possibility: S5-100U with 24 V DC Power Supply (with Safe
Electrical Isolation According to DIN VDE 0160) for Programmable
Controller, Sensors, and Actuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 23
3-20 Non-Grounded Operation; 24 V DC Power Supply (with Safe Electrical Iso-
lation According to DIN VDE 0160) for Programmable Controller and I/Os . . . 3 - 24
3-21 Example: Non-Floating Connection of I/Os to the S5-100U . . . . . . . . . . . . . 3 - 25
3-22 Simplified Representation of a Non-Floating I/O Connection . . . . . . . . . . . . 3 - 26
3-23 Simplified Representation of a Galvanically Isolated Connection
of the I/Os to the S5-100U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 27
3-24 A Simplified Representation of a Floating I/O Connection . . . . . . . . . . . . . . 3 - 28
3-25 Laying Equipotential Bonding Conductor and Signal Label . . . . . . . . . . . . . . 3 - 31
3-26 Fixing Shielded Cables with Various Types of Cable Clamps . . . . . . . . . . . . 3 - 33
3-27 Wiring Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 33
3-28 Measures for Suppressing Interference from
Fluorescent Lamps in the Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 34
Tables
3-1 Installing, Removing, and Changing S5-100U Components . . . . . . . . . . . . 3 - 1

3-2 Connecting the Load Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 13
3-3 Rules for Common Running of Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 29
EWA 4NEB 812 6120-02b

S5-100U Installation Guidelines
3 Installation Guidelines
3.1 Installing S5-100U Components
Except for the I/O module, all of the S5-100U components are mounted on standard mounting rails
in accordance with DIN EN 50022-35x15. Mount the rails on a metal plate to obtain the same
reference potential.
Bus units with a SIGUT/screw-type, or crimp snap-in connection method have different heights.
If you install, remove, or change any parts of your S5-100U system, your system must be in the
state indicated in Table 3-1.
Table 3-1. Installing, Removing, and Changing S5-100U Components

Installing, Removing, and S5-100U S5-100U Load
Changing: Power Status Operating Mode Voltage
I/O modules X STOP OFF
Bus units Power OFF X X

Interface modules
Power supply X X
CPU power supply
voltage OFF
X=not relevant
3.1.1 Assembling a Tier

You need the following components to configure the S5-100U:
• Power supply module
• Central processing unit
• Bus units
• I/O modules
If you do not have a 24 V DC power supply, you must have a power supply module.
Mount the first module on the extreme left end of the standard mounting rail. Add other modules to
the right of the first module.
EWA 4NEB 812 6120-02b 3-1

Installation Guidelines S5-100U
Installing an Interface Module

1. Hook the interface module to the standard mounting rail.
2. Swing the interface module back until the slide on the bottom snaps into place on the rail.
3. Use the ribbon cable to connect the module to the last bus unit.
4. Use connecting cable 712-8 to join the two interface modules.
5. Connect the cable to the “out” socket on the programmable controller tier and to the “in” socket
on the expansion tier.
6. Securely screw the connecting cable plugs in place. Use two screws for each connecting cable
plug.
Removing an Interface Module

1. Only for the IM 316: Remove the hold-down screws from the plugs and remove the connecting
cable.
2. Remove the connecting ribbon cable from the adjacent bus unit.
3. Use a screwdriver to press down on the slide located on the bottom of the interface module.
4. Swing the module up and out of the standard mounting rail.
3-6 EWA 4NEB 812 6120-02b

3.1.3 Cabinet Mounting
Make sure that the S5-100U, the power supply, and all modules are well grounded. Mount the
S5-100U on a metal plate to help prevent noise. There should be electrical continuity between the
grounded enclosure and the mounting rails. Make sure that the system is bonded to earth.
You can use the 8LW system or the 8LX system mounting plates (see Catalog NV 21).
Adequate ventilation and heat dissipation are important to the proper operation of the system. You
must have at least 210 mm (8.3 in.) between each mounting rail (see Figures in Appendix B) for
proper ventilation.
Always locate the power supply and the CPU on the lowest tier to ensure better heat dissipation.
To measure cabinet ventilation, define the total heat loss by calculating the sum of all typical heat
losses (see Catalog ST 52.1).
IM 316 interface module

Metal plate
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Figure 3-5. Multi-Tier Configuration in a Cabinet with the IM 316 Interface

Module (6ES5 316-8MA12)
EWA 4NEB 812 6120-02b 3-7

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Figure 3-6. Cabinet Mounting with a Series of Devices
3.1.4 Vertical Mounting

You can also mount the standard mounting rails vertically and then attach the modules one over the
other. Because heat dissipation by convection is less effective in this case, the maximum ambient
temperature allowed is 40 °C (104 °F).
Use the same minimum clearances for a vertical configuration as for a horizontal configuration.
You must install a clamp (see Catalog SA 2) on the lower end of the programmable controller tier to
hold the modules mechanically in position.
CPU
Clamp
Figure 3-7. Vertically Mounting a Programmable Controller
3-8 EWA 4NEB 812 6120-02b

3.2 Wiring
3.2.1 Connection Methods: Screw-Type Terminals and Crimp Snap-in
SIGUT Screw-Type Terminal

When using screw-type terminals, you can clamp two cables per terminal. It is best to use a
3.5-mm screwdriver to tighten the screws.
Permissible cable cross-sections are:

• A stranded conductor with a core end sleeve: 2 x 0.5 to 1.5 mm2
• A solid conductor: 2 x 0.5 to 2.5 mm2
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Figure 3-8. SIGUT/Screw-Type Connection Method
EWA 4NEB 812 6120-02b 3-9

3.2.3 Connecting Digital Modules
All I/O modules are plugged into bus units. Connect the I/O modules to the terminal blocks of the
bus units. The connections illustrated in this section are of the screw terminal type (SIGUT
connection method).
You can also use the crimp snap-in connection method described in section 3.2.1. In both cases,
the terminal assignments are marked on the terminal blocks.
The assignments listed in Table 3-2 always apply for connecting the load voltage.
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Table 3-2. Connecting the Load Voltage
Load Voltage Terminal 1 Terminal 2
24 V DC L+ M
115/230 V AC L1 N
* 115/230 V AC digital modules can be operated with a load voltage of 120/230 V AC.
Note
For digital outputs, energy is temporarily stored in an internal capacitor for about
100 ms after the L+ supply is switched off.
Please note that this energy may be sufficient to activate low-rating loads (e.g., pulse
valves) for a triggered output.
EWA 4NEB 812 6120-02b 3-13

Connecting Four-Channel Digital Modules

All of these modules are designed for a two-wire connection. You can therefore wire directly to the
sensor or output field device. An external distribution block is not required.
The four channels of a module are numbered from .0 through .3. (Numbers .4 through .7 are only
significant for the ET 100 distributed I/O system.) Each channel has a pair of terminals on the ter-
minal block.
The terminal assignments and the connection diagram are printed on the front plate of the module.
Connecting Four-Channel Input Modules

Example: Connecting a sensor to channel 2 (address I 3.2) on the input module in slot 3
(see Figure 3-12)
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4 x 24 - 60 V DC
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Figure 3-12. Two-Wire Connection of a Sensor to Channel 2
3-14 EWA 4NEB 812 6120-02b

S5-100U
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EWA 4NEB 812 6120-02b

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Connecting Four-Channel Output Modules
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Example: Connecting a lamp to channel 3 (address Q 1.3) on the output module in slot 1
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Installation Guidelines
3-15
Connecting Eight-Channel Digital Modules

These modules do not have a two-wire connection. You therefore need an external distribution
block.
The eight channels of a module are numbered from .0 through .7. One terminal on the terminal
block is assigned to each channel. The terminal assignment and the connection diagram are printed
on the front plate of the module.
Connecting Eight-Channel Input Modules

The sensors must be connected to terminal 1 via the L+ terminal block.
Example: Connecting a sensor to channel 4 (address I 3.4) on an input module in slot 3

(see Figure 3-14)
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DIGITAL INPUT
8 x 24 V DC L+ M
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Figure 3-14. Connecting a Sensor to Channel 4
3-16 EWA 4NEB 812 6120-02b

S5-100U
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EWA 4NEB 812 6120-02b

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(see Figure 3-15)

Connecting Eight-Channel Output Modules
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6
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apply to the digital output module 8× 5 to 24 V DC/0.1 A (see section 14.6.2).
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The actuators must be connected to terminal 2 via the M (negative) terminal block. This does not
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3-17
Example: Connecting a lamp to channel 6 (address output Q 5.6) on an output module in slot 5
3.2.4 Connecting the Digital Input/Output Module

Use only slots 0 through 7 when you plug the module into the bus unit. Use a 40-pin cable
connector with a screw-type connection or crimp snap-in connection for wiring. The module does
not have a two-wire connection. You must therefore use an external distribution block.
Every channel is assigned a terminal on the 40-pin connector. The channel numbers are printed on
the front plate.
The 16 channels on the input side (IN) are numbered from n.0 through n.7 and from n+1.0 through
n+1.7. The 16 channels on the output side (OUT) are numbered from n.0 through n.7 and from
n+1.0 through n+1.7. “n” is the start address of the slot. Slot 0, for example, has the start
address of n=64 (see chapter 6).
OUT IN
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n L+ 11 11
n NC
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.1 13 13 .1
.2 14 14 .2
.3 0.5 A
15 15 .3
.4 16 16 .4
.5 17 17 .5
.6 18 18 .6
.7 19 19 .7
M 20 20 M
40-pin crimp
snap-in connector
Figure 3-16. Front View of the Digital I/O Module with a Crimp Snap-In Connector
(simplified view and not true to scale)
3-18 EWA 4NEB 812 6120-02b

Example: The start address for the modules is 65.3. Inputs and outputs have the same address.
A sensor is to be connected to input I 64.4 and a lamp to output Q 7.3.
Figure 3-17 illustrates the wiring on the front connector.
OUT IN
L+ L+
1 1
2 2
3 3
A 65.3 4 4
5 5
6 6
7 7
8 8
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M 9 9
10 10
11 11
12 12
13 13
14 14
15 15 E 64.4
16 16
17 17
18 18
19 19 M
20 20
L+ Lamp
M M
Sensor
L+
M Terminal
L+Terminal
Figure 3-17. Connecting a Sensor and a Load to Digital Input/Output Module 482
Note
Chapter 11 describes how to connect analog modules.
EWA 4NEB 812 6120-02b 3-19

3.3 Electrical Configuration
3.3.1 Electrical Configuration for the S5-100U

Power Supply
The entire control for the S5-100U consists of the following separate electrical circuits:
• Control circuit for the S5-100U (24 V DC)
• Control circuit for the sensors (24 V DC)
• Load circuit for the actuators (24 V DC or 115/230 V AC)
Control Circuit
The power source for the control circuit supplies the CPU, the bus units, the programmer interface,
and the internal control circuits for the I/O modules. When the incoming supply is 24 V DC/1 A, the
PS 931 power supply module provides an internal supply of +9 V up to a total of 1 A current input
to the I/O modules. The grounding spring on the CPU forces the control circuit to be connected to
the standard mounting rail. The grounding spring must also be protected from interference. The
grounding spring must be grounded.
Load Circuit
The power source for the load circuit supplies the actuators of the process peripherals.
It is suggested that you use one of the following for a 24 V DC power supply:
• The PS 931 power supply module (see Chapter 14)
• A Siemens load power supply from the 6EV1 series (see Appendix D)
If you use load power supplies other than the recommended ones, make certain that the load
voltage is in the range of 20 to 30 V (including ripple).
Note
If you use a switched-mode power supply unit to supply floating analog modules and
BEROs, then this supply must be filtered through a network.
You can connect several mutually independent load circuits adjacent to each other on a single
programmable controller. These connections can either be non-floating or floating (see
section 3.3.3).
3-20 EWA 4NEB 812 6120-02b

3.3.2 Electrical Configuration with External I/Os
Figures 3-18, 3-19, and 3-20 display different configuration possibilities. Pay attention to the
following points when you design your configuration. The numbers appearing in parentheses in the
following points refer to the numbers in Figures 3-18 to 3-20.
• You must have a main switch (1) in accordance with VDE 0100 for your S5-100U, the sensors,
and the actuators.
• You do not need an additional fuse (2) to connect your S5-100U and the load circuit to power if
your radial lines are a maximum of 3 meters (9.84 feet) long and are inherently earth-fault proof
and short-circuit proof.
• You need a load power supply (3) for 24 V DC load circuits.
- You need a back-up capacitor (rating: 200 µF per 1 A of load current) if you have non-
stabilized load power supplies.
• If you have AC load circuits, galvanic isolation via a transformer (4) is recommended.
• You should ground the load circuit at one end. Provide a removable connection (5) to the
ground conductor on the load power supply (terminal M) or on the isolating transformer.
- You must provide earth-fault monitoring for any non-grounded load circuits.
• You must separately fuse (6 and 7) the load voltage for sensor circuits and for actuator circuits.
• You must connect the standard mounting rail of the S5-100U to the ground conductor through a
capacitor (8, to suppress high-frequency noise) for a non-grounded configuration.
• You must have a low-resistance connection between the standard mounting rail and the
cabinet’s chassis ground (10) for a grounded configuration.
• You need a power fuse (9) to protect against a short-circuit occurring in the power supply.
EWA 4NEB 812 6120-02b 3-21

N
3-22
L3
L2
L1
PE
(5)
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for Programmable Controller, Sensors, and Actuators

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Figure 3-18. Configuration Possibility: S5-100U with 115/230 V AC Power Supply
EWA 4NEB 812 6120-02b

S5-100U
L1 (1)
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Figure 3.19 Configuration Possibility: S5-100U with 24 V DC Power Supply

(with Safe Electrical Isolation According to DIN VDE 0160)
for Programmable Controller, Sensors, and Actuators
EWA 4NEB 812 6120-02b 3-23

L1 (1)
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(2) (8)
1 µF/
100 K 500 V AC Install the standard mounting
rail electrically isolated
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Figure 3-20. Non-Grounded Operation; 24 V DC Power Supply

(with Safe Electrical Isolation According to DIN VDE 0160)
for Programmable Controller and I/Os
Interference voltages are discharged to the ground conductor (PE) via a capacitor. You can prevent
static charges by connecting a high-ohmic resistor (approx. 100 k / W) parallel to the capacitor.
3-24 EWA 4NEB 812 6120-02b

3.3.3 Non-Floating and Floating Configurations
The S5-100U is powered by its own control circuit. The I/Os are powered by the load circuit.
The circuits can either be connected to the same grounding point (non-floating) or galvanically
isolated (floating).
Example of a Non-Floating Connection of Digital Modules

A 24 V DC load circuit has the same chassis grounding as the control circuit of the CPU.
Central
grounding point
PS CPU
L+
M
Common
chassis ground
M L+
Load power
supply
Figure 3-21. Example: Non-Floating Connection of I/Os to the S5-100U
EWA 4NEB 812 6120-02b 3-25

The common chassis grounding connection makes it possible for you to use reasonably priced non-
floating I/Os. These modules function according to the following principles.
• Input modules
- The ground line, line M (control circuit chassis) is the reference potential. A voltage drop V1
on line affects the input signal level VI.
• Output modules
- Terminal 2 (M) of the terminal block is the reference potential. A voltage drop V2 on the
line raises the chassis potential of the output driver and thus reduces the resulting control
voltage VCV.
Figure 3-22 shows a simplified connection of the S5-100U with a non-floating external I/O.
+9 V
Data
GND
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Figure 3-22. Simplified Representation of a Non-Floating I/O Connection
3-26 EWA 4NEB 812 6120-02b

When you have a non-floating configuration, you must make certain that the voltage drop on
cables and does not exceed 1 V. If 1 V is exceeded, the reference potentials could change
and the modules could malfunction.
Warning
If you use non-floating I/O modules, you must provide an external connection between
the chassis ground of the non-floating I/O module and the chassis ground of the CPU.
Example of a Floating Configuration with Digital Modules

Floating configuration is required in the following situations.
• When you need to increase interference immunity in the load circuits
• When load circuits cannot be interconnected
• When you have AC load circuits
If you have a floating configuration, the PLC's control circuit and the load circuit must be galvanically
isolated.
Figure 3-23 shows a simplified connection of galvanically isolated I/Os.
Central
grounding point
PS CPU
L+
M
aa
a
aa
a
aa
aa
L+
aa
aa
M
a
aa
a
a
a
Load power
supply
Figure 3-23. Simplified Representation of a Galvanically Isolated Connection of the

I/Os to the S5-100U
EWA 4NEB 812 6120-02b 3-27

Figure 3-24 shows a simplified schematic for the connection of floating I/O modules.
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• •
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M
L1 2L+
N • • 2M
Figure 3-24. A Simplified Representation of a Floating I/O Connection
3-28 EWA 4NEB 812 6120-02b

3.4 Wiring Arrangement, Shielding and Measures against

Electromagnetic Interference
This section describes the wiring arrangements for bus cables, signal cables, and power supply
cables that guarantee the electromagnetic compatibility (EMC) of your installation.
3.4.1 Running Cables Inside and Outside a Cabinet
Dividing the lines into the following groups and running the groups separately will help you to
achieve electromagnetic compatibility (EMC).
Group A: Shielded bus and data lines (for programmer, OP, printer, SINEC L1, Profibus,
Industrial Ethernet, etc.)
Shielded analog lines
Unshielded lines for DC voltage 60 V
Unshielded lines for AC voltage 25 V
Coaxial lines for monitors
Group B: Unshielded lines for DC voltage > 60 V and 400 V

Unshielded lines for AC voltage > 25 V and 400 V
Group C: Unshielded lines for AC voltage > 400 V
You can use the following table to see the conditions which apply to the running of the various
combinations of line groups.
Table 3-3. Rules for Common Running of Lines

Group A Group B Group C
Group A
Group B
Group C
Legend for table:
Lines can be run in common bundles or cable ducts

Lines must be run in separate bundles or cable ducts (without minimum distance)
Inside cabinets, lines must be run in separate bundles or cable ducts and outside cabinets but
inside buildings, lines must be run on separate cable trays with a gap of a least of 10 cm
between lines.
EWA 4NEB 812 6120-02b 3-29

3.4.2 Running Cables Outside Buildings
Run lines outside buildings where possible in metal cable supports. Connect the abutting surfaces of
the cable supports galvanically with each other and ground the cable supports.
When you run cables outdoors, you must observe the regulations governing lightning protection and
grounding. Note the general guidelines:
Lightning Protection
If cables and lines for SIMATIC S5 devices are to be run outside buildings, you must take measures
to ensure internal and external lightning protection.
Outside buildings run your cables

either
- In metal conduits grounded at both ends

or
- In steel-reinforced concrete cable channels
Protect signal lines from overvoltage by using:
• Varistors
or
• Lightning arresters filled with inert gas
Install these protective elements at the point where the cable enters the building.
Note
Lightning protection measures always require an individual assessment of the entire
system. If you have any questions, please consult your local Siemens office or any
company specializing in lightning protection.
Grounding
Make certain that you have sufficient equipotential bonding between the devices.
3-30 EWA 4NEB 812 6120-02b

3.4.3 Equipotential Bonding
Potential differences may occur between separate sections of the system if

• Programmable controllers and I/Os are connected via non-floating interface modules or
• Cables are shielded at both ends but grounded via different sections of the system.
Potential differences may be caused, for instance, by differences in the system input voltage. These
differences must be reduced by means of equipotential bonding conductors to ensure proper
functioning of the electronic components installed.
Note the following for equipotential bonding:
• A low impedance of the equipotential bonding conductor makes equipotential bonding more
efficient.
• If any shielded signal cables connected to earth/protective earth at both ends are laid between
the system sections concerned, the impedance of the additional equipotential bonding conductor
must not exceed 10 % of the shield impedance.
• The cross-section of the equipotential bonding conductor must be matched to the maximum
compensating currents. The following cross-sections are recommendable:
- 16 mm2 copper wire for equipotential bonding line up to 200 m (656.2 ft).
- 25 mm2 copper wire for equipotential bonding line over 200 m (656.2 ft).
• Use equipotential bonding conductors made of copper or zinc-plated steel. Equipotential bonding
conductors are to be connected to earth/protective earth via a large contact area and to be
protected against corrosion.
• The equipotential bonding conductor should be laid in such a way as to achieve a relatively
small contact area between equipotential bonding conductor and signal cables (see Figure 3-25).
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Signal line
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Equipotential bonding conductor
Figure 3-25. Laying Equipotential Bonding Conductor and Signal Cable
EWA 4NEB 812 6120-02b 3-31

3.4.4 Shielding Cables
Shielding is a measure to weaken (attenuate) magnetic, electric or electromagnetic interference

fields.
Interference currents on cable shields are discharged to ground over the shield bar which has a
conductive connection to the housing. So that these interference currents do not become a source
of noise in themselves, a low-resistance connection to the protective conductor is of special
importance.
Use only cables with shield braiding if possible. The effectiveness of the shield should be more than
80%. Avoid cables with foil shielding since the foil can easily be damaged by tension and pressure;
this leads to a reduction in the shielding effect.
As a rule, you should always shield cables at both ends. Only shielding at both ends provides good
suppression in the high frequency range.
As an exception only, you can connect the shielding at one end. However, this attenuates only the
lower frequencies. Shielding at one end can be of advantage in the following cases:
• If you cannot run an equipotential bonding conductor

• If you are transmitting analog signals (e.g. a few microvolts or microamps)
• If you are using foil shields (static shields).
Always use metallic or metalized connectors for data lines for serial connections. Secure the shield
of the data line at the connector housing. Do not connect the shield to the PIN1 of the connector
strip!
In the case of stationary operation, you are recommended to insulate the shielded cable without
interrupt and to connect it to the shield/protective ground bar.
Note
If there are potential differences between the earthing points, a compensating current
can flow over the shielding that is connected at both ends. For this reason, connect an
additional equipotential bonding conductor.
3-32 EWA 4NEB 812 6120-02b

Note the following when connecting the cable shield:

• Use metal cable clamps for fixing the braided shield. The clamps have to enclose the shield over
a large area and make good contact (see Figure 3-26).
• Connect the shield to a shield bar immediately at the point where the cable enters the cabinet.
Route the shield to the module; do not connect it to the module.
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a a
Figure 3-26. Fixing Shielded Cables with Various Types of Cable Clamps
3.4.5 Special Measures for Interference-Free Operation
Arc Suppression Elements For Inductive Circuits
Normally, inductive circuits (e.g. contactor or relay coils) energized by SIMATIC S5 do not require to
be provided with external arc suppressing elements since the necessary suppressing elements are
already integrated on the modules.
It only becomes necessary to provide arc supressing elements for inductive circuits in the following
cases:
• If SIMATIC S5 output circuits can be switched off by additionaly inserted contactors (e.g. relay
contactors for EMERGENCY OFF). In such a case, the integral suppressing elements on the
modules become ineffective.
• If the inductive circuits are not energized by SIMATIC S5.
You can use free-wheeling diodes, varistors or RC elements for wiring inductive circuits.
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Wiring coils activated by direct current Wiring coils activated by alternating current
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with diode with Zener diode with varistor with RC element

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Figure 3-27. Wiring Coils
EWA 4NEB 812 6120-02b 3-33

Mains Connection for Programmers
Provide a power connection for a programmer in each cabinet. The plug must be supplied from the
distribution line to which the protective ground for the cabinet is connected.
Cabinet Lighting
Use, for example, LINESTRA® lamps for cabinet lighting. Avoid the use of fluorescent lamps since
these generate interference fields. If you cannot do without fluorescent lamps, you must take the
measures shown in Figure 3.28.
Shielding grid over lamp
Shielded cable
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Mains filter or shielded mains cable
Figure 3-28. Measures for Suppressing Interference from Fluorescent Lamps

in the Cabinet
3-34 EWA 4NEB 812 6120-02b

4 Start-up and Program Tests
4.1 Operating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 CPU Operator Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.3 Performing an Overall Reset on the Programmable Controller . . . . 4-2
4.2 Starting Up a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 Suggestions for Configuring and Installing the Product . . . . . . . . . 4-3
4.2.2 Procedures for Starting Up the Programmable Controller . . . . . . . 4-4
4.3 Loading the Program into the Programmable Controller ........ 4-5
4.4 Backing Up the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4.1 Backing Up the Program on a Memory Submodule . . . . . . . . . . . . 4-7
4.4.2 Function of the Back-Up Battery . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.5 Program-Dependent Signal Status Display “STATUS” ......... 4-8
4.6 Direct Signal Status Display “STATUS VAR” ................ 4-9
4.7 Forcing Outputs, “FORCE”, for CPU 103 and Higher .......... 4-10
4.8 Forcing Variables, “FORCE VAR” ........................ 4-10
4.9 Search Function .................................... 4-11
4.10 Program Check, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . 4-11
EWA 4NEB 812 6120-02b

Figures
4-1 CPU Operator Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

4-2 Procedure for Loading the Program Automatically . . . . . . . . . . . . . . . . . . . 4 - 5
4-3 Procedure for Loading the Program Manually . . . . . . . . . . . . . . . . . . . . . . 4 - 6
4-4 Procedure for Backing Up the Program on a Memory Submodule ....... 4 - 7
4-5 “STATUS” Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9
4-6 “STATUS VAR” Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9
Table
4-1 Starting Up the Programable Controller .......................... 4 - 4
EWA 4NEB 812 6120-02b

S5-100U Start-up and Program Tests
4 Start-up and Program Tests
4.1 Operating Instructions
4.1.1 CPU Operator Panel
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BATTERY Operating mode display
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(green LED: RUN)
LOW
(yellow LED lights:
Operating mode display
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battery discharged or STOP
not installed) (red LED: STOP)
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STOP Operating mode switch
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ON/OFF switch
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Figure 4.1 CPU Operator Panel
ON/OFF Switch
The ON/OFF switch turns on the CPU’s voltage regulators. This switch does NOT separate the
voltage regulator from the L+/M terminals.
Operating Mode Switch

Use the operating mode switch to select either the RUN or STOP operating mode. The CPU
automatically goes into the START-UP mode during the transition from STOP to RUN (see section
7.4.2).
4.1.2 Operating Modes
STOP Operating Mode

• The program is not executed.
• The current values for timers, counters, flags, and process image I/O tables are saved when the
STOP mode begins.
• The output modules are disabled (signal status “0”).
• The process image I/O tables, timers, and non-retentive flags and counters are set to “zero”
during the transition from STOP to RUN.
RUN Operating Mode

• The program is processed cyclically.
• Already started timers continue to run.
• The signal states for the input modules are stored.
• The output modules are addressed.
• The RUN operating mode can also be set after an OVERALL RESET, that is, when the program
memory is empty.
EWA 4NEB 812 6120-02b 4-1

Start-up and Program Tests S5-100U
START-UP Operating Mode

• The operating system processes DB1 and accepts the parameters (see section 9.1).
• Either the start-up organization block OB21 or OB22 is processed (see section 7.4.2).
• The amount of time start-up requires is not limited since the scan time monitor is not activated.
• Neither time-controlled program processing nor interrupt-driven program processing is possible.
• The input modules and output modules are disabled during start-up.
Changing Operating Modes

A change in operating mode can be caused by the following:
• The operating mode switch - when its position is changed.
• A programmer - if the operating mode switch on the programmable controller is set to RUN.
• Malfunctions - if one occurs that causes the programmable controller to go into the STOP
operating mode (see chapter 5).
4.1.3 Performing an Overall Reset on the Programmable Controller
You should perform an overall reset before you input a new program. An overall reset erases the
following:
• The programmable controller's program memory
• All data (flags, timers, and counters)
• All error IDs
Note
If you do not perform an overall reset, then the information indicated above is retained
even if the program is overwritten.
Manual Reset
To perform a manual overall reset, you must:
1. Set the operating mode switch to STOP.
2. Remove the battery.
3. Set the ON/OFF switch to “0”.
4. Change the ON/OFF switch to “1”.
5. Insert the battery.
Performing an Overall Reset with the Programmer

You can select the overall reset function from the programmer's menu line. Refer to the
programmer manual.
4-2 EWA 4NEB 812 6120-02b

4.2 Starting Up a System
The following section contains suggestions for configuring and starting up a system containing
programmable controllers.
4.2.1 Suggestions for Configuring and Installing the Product
A programmable controller is often used as a component in a larger system. The suggestions

contained in the following warning are intended to help you safely install your programmable
controller.
Warning
• Adhere to any safety and accident-prevention regulations applicable to your
situation and system.
• If your system has a permanent power connection (stationary equipment) that is
not equipped with an isolating switch and/or fuses that disconnect all poles,
install either a suitable isolating switch or fuses in the building wiring system.
Connect your system to a ground conductor.
• Before start-up, if you have units that operate using the main power supply,
make sure that the voltage range setting on the equipment matches the local
main power voltage.
• When using a 24 V supply, make sure to provide proper electric isolation
between the main supply and the 24-V supply. Power supply units must meet
the requirements of EN 60950 or be manufactured in accordance with
DIN VDE 0551/EN 60742 and DIN VDE 0160. The requirements of electro-
magnetic compatibility (EMC) must also be adhered to.
• Fluctuations or deviations of the supply voltage from the rated value may not
exceed the tolerance limit specified in the technical data. If they do, functional
failures or dangerous conditions can occur in the electronic modules or
equipment.
• Take suitable measures to make sure that programs that are interrupted by a
voltage dip or power failure resume proper operation when the power is restored.
Make sure that dangerous operating conditions do not occur even momentarily.
If necessary, force an EMERGENCY OFF.
• EMERGENCY OFF devices must be in accordance with EN 60204/IEC 204
(VDE 0113) and be effective in all operating modes of the equipment. Make
certain to prevent any uncontrolled or undefined restart when the
EMERGENCY OFF devices are released.
• Install power supply and signal cables so that inductive and capacitive
interference can not affect the automation functions.
• Install your automation system and its operative components so as to prevent
unintentional operation.
• Automation equipment can assume an undefined state in the case of a wire
break in the signal lines. To prevent this, take the proper hardware and software
safety measures when linking the inputs and outputs of the automation
equipment.
EWA 4NEB 812 6120-02b 4-3

4.2.2 Procedures for Starting Up the Programmable Controller
Table 4-1. Starting Up the Programmable Controller

Prerequisites Remarks Displays
Procedures
System and programmable Check the mechanical assembly
controller are off-load. (VDE 0100 and VDE 0160). Ter-
minal “M” of the load power
• Check the mechanical
supply and the ground terminal of
configuration and wiring.
the programmable controller must
(see section 3.1 and 3.2).
be connected to the central
grounding point (standard
mounting rail). For non-floating
modules, a module’s “M” terminal
must be connected to the
programmable controller’s “M”
terminal.
Set the ON/OFF switch to
“0” and the operating mode
switch to ”STOP”.
• Switch on the power supply • Red fault LEDs on the I/O
and load power supply. modules lights.
• Set ON/OFF switch to “1”. • Red LED of the CPU lights;.
• Connect programmer to yellow LED lights if the battery is
CPU. low or not installed.
• Reset the programmable
controller (see section 4.1.3).
• Set operating mode switch to • Green LED on the CPU lights.
RUN.
• Switch on sensor power • Red fault LEDs on the input
supply. modules darken.
• Actuate the sensors one after The input signals in the PII can be • Green LEDs on the input modules
the other. observed with the “STATUS VAR” light.
programmer function.
• Switch on power supply for • Red fault LEDs on the output
output modules and modules darken.
actuators.
• Force the outputs with the The switching states of the • Green LEDs of the output
“FORCE” programmer associated actuators change. modules light up.
function.
Program on memory sub-

module
• Set ON/OFF switch to “0”.
• Plug in the memory
submodule.
• Set ON/OFF switch to Program is loaded. • Red LED of the CPU lights.
“1”. *
• Test program and make any
necessary corrections.
• Set operating mode switch to
STOP.
• Switch on the load.
• Set operating mode switch to
RUN.
• Back up the program. The system is in operation. • Green LED of the CPU lights.
* For the CPU 102 only: press the <COPY> key simultaneously (manual loading).
4-4 EWA 4NEB 812 6120-02b

4.3 Loading the Program into the Programmable Controller
You can load a program from a connected programmer (online operation). When you load a
program, it is transferred to the programmable controller's program memory. There are specific
instructions in your programmer manual for doing this.
You can also load your program from a memory submodule, but only valid blocks can be loaded.
See section 7.5.2. The different memory submodules you can use are listed in Appendix D.
Section 4.3 describes how you can load a program from a memory submodule.
Warning
You can connect or disconnect memory submodules only in the Power OFF mode.
Loading the Program Automatically

Automatic loading copies the program from a memory submodule into the program memory of the
CPU. You can only load valid blocks. See section 7.5.2.
Figure 4-2 shows how a program can be loaded automatically.
No battery is installed
(yellow LED lights). PLC overall reset
Switch the S5-100U off.
Plug memory submodule

into the CPU.
Error
Switch the S5-100U on.
Red LED flashes.

CPU 100: red LED lights;
CPU 102/103: red LED flickers.
Perform error diagnostics

(see section 5.1).
Program is loaded.
Program is in the
S5-100U.
The CPU 102 is in

the Normal Mode.
Figure 4-2. Procedure for Loading the Program Automatically
EWA 4NEB 812 6120-02b 4-5

Loading the Program Manually

Manual loading copies the program from a memory submodule into the program memory of the
CPU. If a back-up battery is installed, any program in the memory is completely erased.
You can only load valid blocks. See section 7.5.2.
Figure 4-3 shows how a program can be loaded manually.
Turn off the S5-100U.
Plug memory sub-

module into the CPU.
Press <COPY> key

and hold it down.
Error
Turn on the S5-100U. Red LED flashes.
Red LED flickers; release Release <COPY>

<COPY> key. key.
Program is Red LED Red LED

lights. flashes.
loaded
Red LED shows Perform error

steady light; No valid program
program is in the diagnostics
is in submodule.
S5-100U. (see section 5.1).
The CPU 102 is

in Test Mode
Figure 4-3. Procedure for Loading the Program Manually
4-6 EWA 4NEB 812 6120-02b

4.4 Backing Up the Program
A program can be backed up only if the back-up battery is connected. Backing up copies a program
from the program memory of the CPU to a memory submodule. Only valid blocks are backed up.
As soon as you have changed the integral, default DB1 data block, it is a valid block that can be
backed up. See section 7.5.2.
4.4.1 Backing Up the Program on a Memory Submodule
You can use various EEPROM memory submodules to back up a program. Appendix D contains a
list of the submodules you may use. Figure 4-4 illustrates how to back up a program on a memory
submodule.
Battery low LED (yellow) Insert / replace

lights. Yes battery.
No
Turn off the S5-100U.
Plug EEPROM sub-

module into the CPU.
Turn on the S5-100U.
Press <COPY> key Error

Red LED flashes.
for at least 3 s.
Red LED flickers; Release <COPY>

Release <COPY> key.
Program is Red LED Red LED

loaded. 1) lights. flashes.
Red LED lights; - No / wrong sub-

Program backed up module plugged Perform error
on EEPROM in. diagnostics
submodule. (see section 5.1).
- No program is in
the S5-100U.
The CPU is in the

Normal Mode.
1) Program load time: 40 s/1024 statements
Figure 4-4. Procedure for Backing Up the Program on a Memory Submodule
EWA 4NEB 812 6120-02b 4-7

4.4.2 Function of the Back-Up Battery
If the power fails or the programmable controller is turned off, the contents of the internal (retentive)
memory are stored only if a back-up battery is connected. When power is recovered or when the
programmable controller is turned on, the following contents are available:
• Control program and data blocks (see section 7.3.5)
• Retentive flags and count values (see section 2.2.1)
• ISTACK contents (see section 5.3]
Note
• Insert and replace the battery while the programmable controller is turned on.
Otherwise, an OVERALL RESET is required when you turn the programmable
controller on.
• The lithium battery in the programmable controller has a life expectancy of at least
one year.
• The yellow LED on the operator panel lights up if the battery fails.
Warning
Do not charge lithium batteries. They could explode. Dispose of used batteries properly.
4.5 Program-Dependent Signal Status Display “STATUS”

This test function displays the current signal states and the Result of Logic Operations (RLO) of the
individual operands during program processing.
You can use this test function to make corrections to the program.
Note
The current signal states are displayed only in the RUN operating mode.
4-8 EWA 4NEB 812 6120-02b

Cycle trigger
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
ontrol
STATUS ogram
= Q 2.0 1 1
Transfer data
Figure 4-5. “STATUS" Test Function
Refer to your programmer manual for information about the test function on your programmer.
4.6 Direct Signal Status Display “STATUS VAR”
This test function specifies the status of the operands (inputs, outputs, flags, data words, counters,
or timers) at the end of program processing. You can obtain information about inputs and outputs
from the process image I/O tables of the selected operands.
Cycle trigger
Control program
Transfer data
STATUS
VAR
Figure 4-6. “STATUS VAR” Test Function
EWA 4NEB 812 6120-02b 4-9

4.7 Forcing Outputs, “FORCE”, for CPU 103 and Higher
Outputs can be set directly to a desired status even without the control program. This enables you
to control the wiring and functionality of output modules. This does not change the process I/O
image table, but the output disable condition is cancelled.
Note
The programmable controller must be in the STOP operating mode.
Refer to your programmer manual for information about calling up the test function on your
programmer.
4.8 Forcing Variables, “FORCE VAR”
The process image I/O table of the operands is changed regardless of the programmable controller's
operating mode. You can change the following variables: I, Q, F, T, C, and D.
The program is processed in the RUN operating mode using the changed process variables. They
can be changed again during program scanning without an acknowledgement being required. The
process variables are forced asynchronously to the program scanning.
Special characteristics
• You can change the I, Q, and F variables in the process I/O image table by bits, bytes, or words.
• For the T and C variables in KM and KH format, note the following:
- For programmers with screens, you must also enter “YES” in the system commands input
field in the presettings screen.
- You must be careful when you force edge trigger flags. You do not want to enable a higher-
order byte inadvertently because this could give you a timer or counter value you did not set.
• The signal status display breaks off if there is an error in the format entry or operand entry. The
programmer then displays the “NO FORCING POSSIBLE” message.
4-10 EWA 4NEB 812 6120-02b

4.9 Search Function
This function allows you to search for specific terms in the program and list them on the pro-
grammer's display panel. You can perform program changes at this point.
You can have search runs in the following programmer functions:

• INPUT
• OUTPUT
• STATUS
Some of the items you can search for are:

• Statements (e.g., A I 0.0)
• Operands (e.g., Q 3.5)
• Labels (e.g., X 01); possible only in function blocks
• Addresses (e.g., 0006 H)
Note
Search runs are handled differently by different programmers. The respective users
guides contain extensive information about search runs.
4.10 Program Check, for CPU 103 and Higher
When this programmer function is called up, program scanning is stopped at a definite point. The
cursor indicates this breakpoint, which is a statement in the program. The programmable controller
scans the program up to the statement selected. The current signal states and the RLO up to the
statement selected are displayed (as in the “STATUS” test function).
The program can be scanned section by section by shifting the breakpoint. Program scanning takes
place as follows:
• All jumps in the block called are executed.
• Block calls are executed immediately. The program check is not resumed until control is
returned to the calling block.
The following applies during the program check:

• The two mode LEDs are not lit.
• The program writes to the PIQ and reads out the PII.
• No process image (data cycle) is transferred.
• All outputs are set to zero.
EWA 4NEB 812 6120-02b 4-11

During the program check, you can execute the following additional test and programmable
controller functions from the programmer:
• Input and output (program modification possible)
• Direct signal status display (STATUS VAR)
• Forcing of outputs and variables (FORCE, FORCE VAR)
• Information functions (ISTACK, BSTACK)
If the function is aborted due to hardware faults or program errors, the programmable controller goes
into the STOP mode and the red LED on the control panel of the CPU lights.
Refer to your programmer manual for information about calling up these functions on your
programmer.
4-12 EWA 4NEB 812 6120-02b

5 Diagnostics and Troubleshooting
5.1 Indication of Errors by LEDs ............................ 5 - 1
5.2 CPU Malfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.2.1 “ISTACK” Analysis Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1
5.2.2 Interrupt Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4
5.2.3 Errors during Program Copying . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
5.2.4 Explanation of the Mnemonics Used in “ISTACK” . . . . . . . . . . . . . 5 - 6
5.3 Program Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8

5.3.1 Locating the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8
5.3.2 Tracing the Program with the “BSTACK” Function ............ 5 - 11
5.4 I/O Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12
5.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12
5.6 The Last Resort .................................... 5 - 13
EWA 4NEB 812 6120-02b

Figures
5-1 Structured Program with an Illegal Statement . . . . . . . . . . . . . . . . . . . . . . 5 - 8

5-2 Addresses in the CPU’s Program Memory . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9
5-3 Calculating the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 10
5-4 Tracing the Program with “BSTACK” ........................... 5 - 11
5-5 Analyzing the Cause of a Fault in the I/Os . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12
Tables
5-1 Error Indication and Error Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5-2 ISTACK Output (Bytes 1 to 16) ............................... 5 - 2
5-3 Interrupt Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4
5-4 Errors when Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
5-5 Meaning of the Remaining ISTACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 6
5-6 Mnemonics Used for the Interrupt Display . . . . . . . . . . . . . . . . . . . . . . . . 5 - 7
EWA 4NEB 812 6120-02b

S5-100U Diagnostics and Troubleshooting
5 Diagnostics and Troubleshooting
5.1 Indication of Errors by LEDs
The programmable controller's operator panel will show you if your device is not functioning
correctly (see Table 5-1).
Table 5-1. Error Indication and Error Analysis

Error Indication Error Analysis
CPU in STOP CPU malfunction

Red LED lights Use the programmer to execute an interrupt analysis
(see section 5.2).
CPU in STOP Error when loading or backing up the program

Red LED flashes Use the programmer to execute an interrupt analysis
(see section 5.2).
CPU in RUN Program error
Green LED lights (see section 5.3)
Faulty operation or
I/O fault
Execute a fault analysis
(see section 5.4).
If both LEDs light, your programmable controller is in the START-UP operating mode.
5.2 CPU Malfunctions
5.2.1 “ISTACK” Analysis Function

The interrupt stack is an internal CPU memory area where the causes of malfunctions are stored. If
there is a malfunction, a bit in the respective byte of the memory area is set. Using the pro-
grammer, you can read out the contents of this memory area byte-by-byte.
Calling the ISTACK

The call is made through the programmer menu in the STOP operating mode.
Refer to your programmer manual for the key sequence.
Note
Only ISTACK bytes 1 through 6 can be output in the RUN mode. There is no cause for
an interrupt to force the CPU to go into the STOP mode. The control bits are output in
bytes 1 through 6.
EWA 4NEB 812 6120-02b 5-1

5-2
9
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
Byte
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
a a
aa
aa
aa
aa
aa
aaaa
aa
a Bit
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
a a
aa
aa
aa
aa
aa
a a
aa
aa
a
aaaaaaaaaaaaaaaaa aaaaaa aaa
shaded bits).

7
aaaaaaaaaaaaaaaa aaaaaa aa
NAU
AS
aa
a aa
a
ZUS
STO
aa
aaa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aaa aa
aaa
aa
aa
aa
aaaaa
KEIN
ANZ1
STOPS
a
aa
aa
aa
aa
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aa
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aa a
aa
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aa
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aa
a
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a a
aa
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a a
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a
aaa
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6
a
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a a
aa
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a
ANZ
STO
FEH
SYN
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ANZ0
a
aa
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aaaaaaaa
aaaaaaaaa aaaaaa aaaaaaa aaaaaaaa

aaaaaaaaa aaaaaa aaaaaaa
5
aaaaaaaaa aaaaaa aaaaaaa aaaaaaaa
NI
Diagnostics and Troubleshooting
aaaaaaaaa aaaaaa aaaaaaa aaaa

BST
aaaaaaaaa aaaaaa aaaaaaa

STA
SUF
SCH
NEU
OVFL
aaaaaaaaa
KOPF
NINEU
a
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a aaaaaaaaaaaaaaaaaaaaa
a
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a
5th nesting level

4th nesting level
6th nesting level
aaaaaaaaaaaaaaaa
aa
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4
aa
aaa
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ZYK
TAE
SCH
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TRAF
a
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3
aaaaaaaaaaaaaaaaa
OR
aaaaaaaaaaaaaaaaa
BAT
PUF
BAU
ADR
NNN
IRRELEVANT
IRRELEVANT
IRRELEVANT
a
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aa
aa
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SYSFE
aa
aaa
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2
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AF
OR
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STS
STA
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aa
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1
a
aa
aa
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aa
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a
VKE
VKE
VKE
VKE
BAU
a
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aa
aa
aa
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aa
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STUEB
aaaaaaaaaaaaaaaaa
Table 5-2. ISTACK Output (Bytes 1 to 16)
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
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aaaaaaa
a
a
aa
aa
aa
aa
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0
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UR
aaaaaaaaaa
FKT
FKT
FKT
LAD
aaaaaaaaaa
ERAB
aaaaaaaaaa
ASPFA
a
aa
aa
aa
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aa
aa
aa
aa
aa
aaaaaaaaaa
a
lute
EBA6
EBA8
EA0E
EA0A
EA0C
EBAA
EBAC
Addr. (SD)
The following table shows which positions in the bit pattern are relevant for error diagnosis (gray-
SD 7
SD 6
SD 5
ta Word
(UAW)
SD 211
SD 212
SD 213
SD 214
Abso- Syst. Da-
EWA 4NEB 812 6120-02b

S5-100U
*
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Byte
Bit
S5-100U
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
a
a
aa
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aa
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aa
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aa
aa
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aa
aa
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a
aaaaaaaaaaaaaaaaaa
7
a
aa
aa
aa
aa
aa
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aa
aa
aa
aa
aa
aa
aa
aa
section 9.1).
aa
aaa
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a
a
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aa
EWA 4NEB 812 6120-02b

aa
aaa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aaaa
aaa
a
6
a
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a
aaaaaaaaaaaaaaaaaa
ACCU 1 (low)
ACCU 2 (low)
aaaaaaaaaaaaaaaaaa
ACCU 1 (high)
ACCU 2 (high)
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
a
1st nesting level
3rd nesting level
aaaaaaaaaaaaaaaaaa
2nd nesting level
aaaaaaaaaaaaaaaaaa

aaaaaaaaaaaaaaaaaa
5
a
aa
aa
aa
aa
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aa
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aa
aa
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a
aaaaaaaaaaaaaaaaa
aa
a
Nesting depth (0 to 6)
aa
aaa
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aa
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aa
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aa
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aaa
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Operation register (low)

aaaaaaaaaaaaaaaaaa
Operation register (high)

Block stack pointer (low)
aaaaaaaaaaaaaaaaaa
Block stack pointer (high)

a
aa
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aa
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aa
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4
Step address counter (low)*

aa
aaa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aaaa
aaa
a
Step address counter (high)*

a
aa
aa
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aa
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a
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a
aaaaaaaaaaaaaaaaaa
Start address of the data block (low)
3
aaaaaaaaaaaaaaaaaa
Start address of the data block (high)
a
aa
aa
aa
aa
aa
aa
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aa
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aa
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a
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2
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OR
OR
OR
aa
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aa
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a
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a
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a
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aa
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a
aa
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aa
aa
aa
aa
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aa
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aa
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aa
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aa
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a
aa
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aa
aa
aa
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aa
aa
aa
aa
aa
aa
a
1
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
a
VKE
VKE
VKE
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
a
a
aa
aa
aa
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aa
aa
aa
aa
aa
aa
aa
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aa
aa
aa
aa
aa
a
aa
aaaaaaaaaaaaaaaaa
aa
a
a
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
aaa
a
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0
a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
a
FKT
FKT
FKT
aaaaaaaaaaaaaaaaaa
Table 5-2. ISTACK Output (Bytes 17 to 32) [continued]
aa
aaaaaaaaaaaaaaaaa
aa
a
aaa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aaaaaaaaaaaaaaaaaa
a
lute
EB96
EB98
EB9A
EB9E
EBA0
EBA2
EBA4
EB9C
Addr. (SD)
If the step address counter displays a DB1 address, then there is a DB1 parameter setting error (see
The absolute memory address of the next statement to be processed from the faulty block is displayed.
ta Word
SD 203
SD 204
SD 205
SD 206
SD 207
SD 208
SD 209
SD 210
Abso- Syst. Da-
5-3
Diagnostics and Troubleshooting S5-100U
5.2.2 Interrupt Analysis

When there is an interrupt in program processing, you can use the following table to determine the
cause of the error. The CPU always goes into the STOP mode.
Table 5-3. Interrupt Analysis
ISTACK
Byte Cause of Error Remedy
Display
ASPFA and 10 Error during program transfer from the PG to the Shorten program.
KEIN AS 6 PLC: Compress memory.
and NNN 9 Overflow of the internal program memory during
and 25 and 26 compilation
SAZ=FFFF*
(CPU 102)
BAU 10 When automatically loading the program: Replace the battery and
- Battery is missing or dead and there is no recreate the program, or
valid program available on the memory load the program again.
submodule
NAU 10 Interruption in the power supply voltage to the

CPU
NINEU 6 The program in the PLC memory is defective. Perform an overall reset
Cause: and load the program
• A power failure has interrupted one of the again.
following operations.
- Compress
- Block transfer from the PG to the PLC or
memory submodule to the PLC
- PLC overall reset
• Battery has been replaced while the power
was off.
NNN 9 • Statement cannot be decoded. Eliminate program

• Nesting level is too high. errors.
• Parameter exceeds permitted limits.
PEU 10 • Expansion module not connected • Check the power

• I/O bus malfunction supply in the
• Maximum length of shift register exceeded expansion unit.
• Module unknown • Check the
• Module in wrong slot connections.
• Check the module
slots.
STOPS 9 Operating mode switch on STOP Set to RUN
STS 9 • Software stop by statement (STP)

• STOP requested by programmer
STUE 9 Block stack overflow: the maximum block call Eliminate program
nesting depth (16) has been exceeded. errors.
SYS** FEH 10 DB1 parameter setting error Correct DB1.
* SAZ = STEP address counter - The ISTACK bytes 25 and 26 read “1111 1111(FF)”.
** Relevant only for the PG 605U and for the CPU 103, version 8MA03 and higher.
5-4 EWA 4NEB 812 6120-02b

Table 5-3. Interrupt Analysis (continued)

ISTACK Byte Cause of Error Remedy
Display
SUF* 9 Substitution error: Change actual

Function block called with an incorrect actual parameter.
parameter
TRAF 9 Transfer error Eliminate program error

• Data block statement programmed with a (see your programmer
data word number larger than the data manual).
block length
• Data block statement programmed without
previously opening a data block
ZYK 10 Scan time exceeded: Check the program for

The program processing time exceeds the continuous loops or
set monitoring time. Causes: shorten program.
• Program too long
• Interrupts too frequent
* Relevant for CPU 102, version 8MA02 and higher
5.2.3 Errors during Program Copying
Error message: after the <COPY> key is released, the red LED continues flashing.
Table 5-4. Errors when Copying

ISTACK Cause of Error Remedy
Display
ASPFA Loading the memory submodule into the PLC: Check the program on the
• Program on the memory submodule is too long memory submodule.
for the PLC's program memory.
• Program on the module contains an invalid block

number.
ASPFA Saving from the PLC to the memory submodule: Replace the memory
EEPROM memory submodule is defective or too submodule, or use a larger
small for the program in the PLC memory. EEPROM memory
submodule.
ASPFA and Internal program memory overflow during Shorten program.

KEIN AS and compilation
NNN
and SAZ=FFFF*
(CPU 102)
* SAZ = STEP Address Counter
The ISTACK bytes 25 and 26 read “1111 1111(FF)”
EWA 4NEB 812 6120-02b 5-5

5.2.4 Explanation of the Mnemonics Used in “ISTACK”

Table 5-5. Meaning of the Remaining ISTACK Bits
ISTACK
Byte Explanation
Display
BST SCH 1 Shift block.
SCH TAE Execute shift operation.
ADR BAU Structure address list.
STO ANZ 3 PLC in STOP

STO ZUS Internal control bit for STOP/RUN change
BAT PUF Battery backup available
NEU STA PLC not yet in cycle after Power ON
- See bytes 9 and 10 for cause.
AF* 4 Interrupt enable/enabling of time-controlled OB13 and interrupt-
driven OB3
KOPFNI 5 Program contains errors.
Block header cannot be interpreted.
KEIN AS** 6 Not enough S5 statement memory available
URLAD Overall reset, program defective

SYNFEH Program contains errors.
ANZ 1/ANZ 0 12 Condition code bits for arithmetic, logic, and shift operations.
OV Arithmetic overflow
OR ID bit of OR memory
STATUS Status ID of operand of last binary statement executed
VKE Result of logic operation (RLO)
ERAB ID bit of first scan
FKT 13 0: O( OR parenthesis open
1: A( AND parenthesis open
* relevant for CPU 103 only

** for CPU 102: 0 = normal mode
1 = test mode
5-6 EWA 4NEB 812 6120-02b

Table 5-6. Mnemonics Used for the Interrupt Display

Mnemonics Used
Explanation
for the Interrupt Display
ANZ1/ANZ0 Condition codes for various operations (see section A.1.4)

ASPFA Illegal memory submodule
BAU Battery failure

ERAB First scan
FKT 0 : O( 1 : A(
KE1...KE6 Nesting stack entry 1 to 6 entered for A( and O(
KEINAS Insufficient S5 statement memory available
NAU Power failure

NINEU Cold restart not possible
NNN Statement cannot be interpreted in the PLC

OR OR memory (set by command “0”)
OVFL Arithmetic overflow (+ or -)

PEU I/Os not ready:
• First bus unit not connected
• Expansion module not connected
• I/O bus malfunction
• Maximum shift register length exceeded
• Unknown module
• Module in the wrong slot
STATUS STATUS of the operand of the last binary statement executed
STOPS Operating mode switch on STOP
STS Operation interrupted by a programmer STOP request or

programmed STOP statements
STUE Block stack overflow: The maximum block call nesting depth of 16
has been exceeded.
SUF Substitution error

SYSFEH* Error in DB1
TRAF Transfer error for data block statements:

• When accessing a data word even though no corresponding data
block was opened or
• When the data word number is larger than the data block length
UAW Interrupt display word
VKE Result of logic operation (RLO)

ZYK Scan time exceeded: the set maximum permissible program scan
time has been exceeded
* Relevant only for CPU 103 version 8MA03 and higher
EWA 4NEB 812 6120-02b 5-7

5.3 Program Errors
5.3.1 Locating the Error Address

The SAZ (STEP address counter) in the ISTACK (bytes 25 and 26) contains the absolute address
of the STEP 5 statement in the programmable controller before which the CPU went into the STOP
mode.
Use the “DIR PC” programmer function to determine the associated block start address.
Example: You have entered a control program consisting of OB1, PB0 and PB7. An illegal
statement has been programmed in PB7.
PB7
PB0
OB1
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Figure 5-1. Structured Program with an Illegal Statement
When it reaches the illegal statement, the CPU interrupts program scanning and enters the STOP
mode with the “NNN” message. The STEP address counter is at the absolute address of the next
(but not yet scanned) statement in the program memory.
5-8 EWA 4NEB 812 6120-02b

S5-100U
EWA 4NEB 812 6120-02b

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L PB 0
JU PB7
JU PB0
PB7 Header
OB1 Header
PB0 Header
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EE3E
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26
25
Byte
programmed blocks.
Figure 5-2. Addresses in the CPU’s Program Memory

Absolute addresses in
the CPU’s internal RAM
42
EE
Contents
paring these two addresses.
absolute start addresses of all
STEP address counter

The “DIR PC” function gives the
address of the illegal statement.
It is not possible to localize an error in
The error can then be localized by com-

the program on the basis of the physical
5-9
Calculating the Address (necessary only when using the PG 605U)

In order to be able to make program corrections, it is necessary to have the address of the
statement that led to the fault referenced to the particular block (relative address).
The faulty block is found by comparing the SAZ (STEP address counter) contents and the
“DIR PC” display.
The relative error address gives the difference between the SAZ value and the block start address.
Figure 5-3 gives you an example of how to calculate the relative error address.
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ISTACK byte 25 26 DIR PC
STEP address counter EE 42 Block Start Address
The absolute address EE42 is PB0 EE18

greater than the start address for PB7 EE3C
PB7. The faulty statement is
therefore in PB7. OB1 EE0A
Calculating the relative address: EE42 - EE3C = 0006
“0006” is the relative address of the statement in PB7 following the statement that
caused the CPU to go into the STOP mode.
Figure 5-3. Calculating the Error Address
Output of an Error Statement

Use the “SEARCH” programmer function to find certain program locations and to look for the
relative error address. Refer to your programmer manual for additional information about this
programmer function.
5-10 EWA 4NEB 812 6120-02b

5.3.2 Tracing the Program with the “BSTACK” Function

Program trace with “BSTACK” is not possible on the 605U programmer.
During program processing, the following information about jump operations is entered in the block
stack (BSTACK):
• The data block that was valid before program processing exited a block.
• The relative return address
- It specifies the address where program processing will continue after the return from the
called up block.
• The absolute return
- It specifies the memory address in the program memory where program processing will
continue after the return.
You can call up this information with the “BSTACK” programmer function in the STOP operating
mode if a fault caused the CPU to go into the STOP operating mode. “BSTACK” then reports the
status of the block stack at the time the interruption occurred.
Example:
Program scanning was interrupted at function block FB2. The CPU went into the STOP mode with
the error message “TRAF” (because of incorrect DB access, e.g., DB5 is two words long and DB3
is ten words long).
“BSTACK” lets you determine the path used to reach FB2 and lets you know which DB was open
at the time of call up. “BSTACK” contains the three (marked) return addresses.
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00 Interrupt with the
“TRAF” error
message
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PB4
OB1
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08 JC FB2
04 JU PB2 04 10
06
08 JC PB3
FB2
xx BE xx BE
10 00
PB3
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2A L DW4
xx BE 00 C DB3
16 JU FB2
18 BE xx BE
Figure 5-4. Tracing the Program with “BSTACK”
EWA 4NEB 812 6120-02b 5-11

5.4 I/O Faults
Fault
Module with fault

no
indication no Check supply
Power supply ok?
(red LED) leads.
yes yes
no Module addressable via
the process input image yes - Check module
Red LED lights. (exchange).
(PII) and the process out-
put image (PIQ) (STA- - Check program.
yes TUS VAR, FORCE VAR)
no Check no
Module power supply
supply ok? no
leads. Bus connection ok? Replace bus unit.
yes
yes Eliminate yes
Short circuit at
short
the outputs? Replace module with
circuit. yes
simulator module. Replaced module
no Is a check with STATUS is defective.
VAR or FORCE VAR
no possible?
Defective
Defective fuse module
no
yes Check connections of
other bus units and
Replace fuse. interface modules.
Figure 5-5. Analyzing the Cause of a Fault in the I/Os
5.5 System Parameters

The “SYSPAR” programmer function makes it possible to read out the system parameters (e.g.,
CPU software version) of the programmable controller (see programmer manual).
5-12 EWA 4NEB 812 6120-02b

5.6 The Last Resort

The programmable controller will not go back to the RUN operating mode:
Possible cause: The battery was installed or changed when the programmable controller
was turned off.
Remedy: Perform an overall reset and load the program again.
How to perform an overall reset without a programmer

1. Set the operating mode switch to STOP.
2. Remove the battery.
5. Install a battery.
Contact your local Siemens representative if the above measures are ineffective.
EWA 4NEB 812 6120-02b 5-13

EWA 4NEB 812 6120-02b

6 Addressing
6.1 Slot Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1
6.2 Digital Modules ..................................... 6 - 4
6.3 Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5
6.4 Combined Input Modules and Output Modules . . . . . . . . . . . . . . . 6 - 6

6.4.1 Output Modules with Error Diagnostics . . . . . . . . . . . . . . . . . . . . 6 - 6
for CPU 102, Version 8MA01, Revision 5 and Higher . . . . . . . . . . 6 - 7
6.4.3 Function Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 7
6.5 The Structure of Process Image Input and Output Tables ....... 6 - 8
6.5.1 Accessing the Process Image Input Table (PII) . . . . . . . . . . . . . . . 6 - 10
6.5.2 Accessing the Process Image Output Table (PIQ) . . . . . . . . . . . . . 6 - 11
6.6 Interrupt Process Images and Time-Controlled Program

Processing in OB13 for CPU 103, Version 8MA02 and Higher . . . . 6 - 12
6.6.1 Accessing the Interrupt PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 12
6.6.2 Accessing the Interrupt PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14
6.7 RAM Address Assignments ............................ 6 - 15
EWA 4NEB 812 6120-02b

Figures
6-1 Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1

6-2 Consecutive Numbering of Slots in a Single-Tier Configuration . . . . . . . . . 6 - 1
6-3 Slot Numbering in a Multi-Tier Configuration . . . . . . . . . . . . . . . . . . . . . . 6 - 2
6-4 Expanding from 14 to 18 Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3
6-5 Configuration of a Digital Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4
6-6 Address Assignment for Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5
6-7 Assignment of Process Images to the I/O Modules . . . . . . . . . . . . . . . . . . 6 - 9
6-8 Accesses to the PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 10
6-9 Accesses to the PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 11
6-10 Accesses to the Interrupt PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 13
6-11 Accesses to the Interrupt PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14
Tables
6-1 Error Messages for Output Modules with Error Diagnostics . . . . . . . . . . . . 6 - 6

6-2 Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 7
6-3 Structure of the PII and the PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8
6-4 Structure of the Interrupt PII and the Interrupt PIQ . . . . . . . . . . . . . . . . . . 6 - 12
6-5 Important Addresses in the RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 15
6-6 System Data Area Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 16
EWA 4NEB 812 6120-02b

S5-100U Addressing
6 Addressing
The inputs and the outputs have different assigned addresses so that you can access them
specifically. The I/O addresses are the same as the module slot addresses.
When you mount a module in a slot on a bus unit, the module is assigned a slot number and
consequently a fixed byte address in one or both process image I/O tables.
Connect the sensors and actuators to the terminal block. The terminal selected determines the
channel number.
Process image I/O

tables in the CPU Control
I/O module
program
Address in the pro-
cess image input
Slot number table (PII) Address
+
Address in the pro-
= in a
Channel number statement
cess image output
table (PIQ)
Data direction: module - CPU
Figure 6-1. Address Assignment
6.1 Slot Numbering

The programmable controller can have a maximum of four tiers. You can use up to 16 bus units
(32 slots). The slots are numbered consecutively. Numbering begins with “0” at the slot beside
the CPU. Whether a module is plugged in or not has no effect on the numbering.
Slot numbers
CPU 0 1 2 3 30 31
Figure 6-2. Consecutive Numbering of Slots in a Single-Tier Configuration
EWA 4NEB 812 6120-02b 6-1

Addressing S5-100U
If the programmable controller consists of more than one tier, numbering of the expansion tiers is
continued at the slot on the extreme left.
Slot numbers
26 27 28 29 30 31
18 19 20 21 22 23 24 25
8 9 10 11 12 13 14 15 16 17
CPU 0 1 2 3 4 5 6 7
Figure 6-3. Slot Numbering in a Multi-Tier Configuration
When expanding your system, always add the new bus units to the topmost tier on the right. Other-
wise, the slot numbers on the right of the new bus units will be changed, requiring address changes
in your control program.
Note
After every expansion, check to make certain that the addressing used in the control
program is the same as that in the actual configuration.
6-2 EWA 4NEB 812 6120-02b

S5-100U Addressing
Example: Expanding from 14 to 18 slots
Existing configuration
8 9 10 11 12 13
New bus units

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CPU 0 1 2 3 4 5 6 7
Correct expansion procedure
8 9 10 11 12 13 14 15 16 17
The new bus units are added at

the right. The interface module
is moved correspondingly to the
right. The old slot numbers are
retained. Continue numbering
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The slot numbers of the old bus

units move to numbers 12 to 17.
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bers 8 to 11.
CPU 0 1 2 3 4 5 6 7
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Figure 6-4. Expanding from 14 to 18 Slots
EWA 4NEB 812 6120-02b 6-3

Addressing S5-100U
6.2 Digital Modules

Digital modules can be plugged into all slots (0 through 31).
Only two information states (“0” or “1”, OFF or ON) per channel can be transferred from or to a
digital module. The memory requirement is one bit.
Each channel of a digital module is displayed by a bit. This is the reason that every bit must be
assigned its own number. Use the following form for a digital address:
x . y
Bit number (channel number)
Byte number (slot number)
Figure 6-5. Configuration of a Digital Address
The “X.Y” address consists of the following two components:

• Byte Address X (Slot Number X)
- The byte address is the same as the number of the slot the module is plugged into.
• Channel Number Y (Bit Address Y)
- The channel number comes from the connection of the actuators or sensors to the terminals
of the terminal block. The assignment for the channel number and the terminal number is
printed on the frontplate of the module.
Example: Address Assignment

You are connecting a 2-wire BERO proximity limit switch to an 8 x 24-V DC digital input module
(6ES5 421-8MA11) at terminal 3. The other wire is routed to an L+ (positive supply voltage) termi-
nal block (see section 3.2 for wiring). The module is plugged into slot 3.
This defines the address used by the control program to evaluate the signal states of the BERO.
• The byte address is 3 since the module is plugged into slot 3.
• As shown on the frontplate, channel number 1 is used.
• The complete address for the BERO switch is 3.1.
Note
You can address 4-channel digital modules only with channel numbers 0 through 3. The
channel numbers 4 through 7 printed on the frontplate are relevant only for the ET 100U
system.
6-4 EWA 4NEB 812 6120-02b

S5-100U Addressing
6.3 Analog Modules

You can plug analog modules only into slots 0 through 7. Transfer of 65,536 different items of
information is possible per channel from or to an analog module. The memory requirement is
16 bits=2 bytes=1 word. The modules are addressed byte-by-byte or word-by-word with load or
transfer operations.
The programmable controller takes this increased address requirement into account when an analog
module is plugged in.
• Eight bytes (=four words) are reserved per slot.
• Two bytes (=1 word) are reserved per channel.
• The slot addressing area is changed.
• The permissible address space extends from byte 64 (slot 0, channel 0) to byte 127 (slot 7,
channel 3).
Slot number 0 1 2 3 4 5 6 7 Channel number
64+65 72... 80... 88... 96... 104... 112... 120... 0

CPU
66+67 1
68+69 2
70+71 ...79 ...87 ...95 ...103 ...111 ...119 ...127 3
Figure 6-6. Address Assignment for Analog Modules
Examples: 1) Bytes 88+89=analog module in slot 3, channel number 0

2) Channel 1 address of an analog module in slot 5?
Solution: bytes 106+107
Note
Any combination of analog and digital modules is possible in slots 0 through 7.
EWA 4NEB 812 6120-02b 6-5

Addressing S5-100U
6.4 Combined Input Modules and Output Modules

With these modules it is possible to write data from the control program to the module and to read
in data from the module to the control program.
The byte addresses in the process image input table (PII) and process image output table (PIQ) are
identical. The meaning of the transferred data is usually different.
6.4.1 Output Modules with Error Diagnostics
In addition to the fault LED (red LED), the following output modules can signal errors to the CPU.
4 x 24 V DC / 0.5 A (6ES5 440-8MA12)
4 x 24 V DC / 2.0 A (6ES5 440-8MA22)
4 x 24 to 60 V DC / 0.5 A (6ES5 450-8MB11)
You can read the error messages on input channels I X.0 and I X.1 (not with CPU 100, version
8MA01).
The following error messages are possible.
Table 6-1. Error Messages for Output Modules with Error Diagnostics
Address Type of Error
I X.0 Short circuit on an output channel / fuse blown

or
no-load voltage
I X.1 Defective module (output transistor shorted)

X is the byte address (slot number) of the output module
Signal state “1” indicates an error is present. The PII is set to “0” for output modules without error
diagnostics.
6-6 EWA 4NEB 812 6120-02b

S5-100U Addressing

for CPU 102, Version 8MA01, Revision 5 and Higher
Plug the module only into slots 0 through 7.
This module occupies the same address space as an analog module. However, only the first two of
the eight reserved bytes are used.
The address consists of byte address n or n+1 and channel number Y. “n” is the start address of
a slot, the first of the reserved bytes (e.g., byte 64 for slot 0). “n+1” is therefore the second of the
reserved bytes. The designations “n” and “n+1” are printed on the frontplate of the module.
The input and output information occupies the same addresses.
The channel number is defined by the connection of the actuators and sensors to the crimp
connector. The channel numbers are printed on the frontplate.
Table 6-2. Address Assignment
Slot Number 0 1 2 3 4 5 6 7
Address Channel 64.0 to 72.0 to 80.0 to 88.0 to 96.0 to 104.0 to 112.0 to 120.0 to
PII (IN) n.0 to n.7 64.7 72.7 80.7 88.7 96.7 104.7 112.7 120.7
and
PIQ Channel 65.0 to 73.0 to 81.0 to 89.0 to 97.0 to 105.0 to 113.0 to 121.0 to
(OUT) n+1.0 to
n+1.7 65.7 73.7 81.7 89.7 97.7 105.7 113.7 121.7
Examples: Determining the Address

1) You plugged the module into slot 4 and connected an actuator at byte n,
channel 4. The address is 96.4.
2) Address 113.3 indicates a sensor or an actuator is connected at byte n+1,
channel 3. The module is plugged into slot 6.
6.4.3 Function Modules
Function modules have module-specific addressing. Some function modules are addressed like
digital modules, and other function modules are addressed like analog modules. The addressing for
each function module is explained in chapter 15.
EWA 4NEB 812 6120-02b 6-7

Addressing S5-100U
6.5 The Structure of Process Image Input and Output Tables

Information about inputs is stored in the process image input table (PII). Information about outputs
is stored in the process image output table (PIQ).
The PII and the PIQ each have an area of 128 bytes in the RAM memory.
The PII and the PIQ have identical structures. The PII and the PIQ can be divided into three address
areas as shown in Table 6-3.
Table 6-3. Structure of the PII and the PIQ

Byte Address in the PII
and PIQ Module Slot Number
0 to 31 Digital modules 0 to 31
32 to 63 Unassigned address space
64 to 127 Analog modules 0 to 7
• The address space for bytes 0 through 31 is reserved for information from or to modules that
are addressed like digital modules.
• The unassigned address space in bytes 32 to 63 can be used to store intermediate results.
• The address space in bytes 64 to 127 is reserved for information from or to modules that are
addressed like analog modules.
6-8 EWA 4NEB 812 6120-02b

S5-100U
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process I/O images.
aaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaa
EWA 4NEB 812 6120-02b

Slot
aaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa
Unassigned
address area
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7 6 5 4 3 2 1 0
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CPU
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Figure 6-7. Assignment of Process Images to the I/O Modules

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Figure 6-7 shows a possible programmable controller configuration and storage of information in the
Addressing
6-9
Addressing S5-100U
6.5.1 Accessing the Process Image Input Table (PII)

During a data cycle, data is read into the process image input table (PII) from input modules (see
section 2.2.2 - Data Cycle). This data is available to the control program for evaluation in the next
program processing cycle.
Access to the PII is expressed by the operand identifiers “I”, “IB”, or “IW” in a statement in the
control program.
The letter “L” identifies the “Load” operation (see chapter 8). The letter “A” identifies the “AND
logic” operation (see chapter 8).
PII
• Bit-by-bit reading “I <bit address>” Bit number
Example: Reading in the signal state of
7 6 5 4 3 2 1 0
channel 2 of a 4-channel digital input module
in slot 2
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• Byte-by-byte reading “IB <byte address>”

Example: Reading in the signal states of all
channels of an 8-channel digital input module
in slot 12
L IB 12
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• Word-by-word reading “IW <word address>”

Example: Reading in the analog value of
channel 3 of a 4-channel analog input module in
slot 4
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Always set to “0”
Figure 6-8. Accesses to the PII
6-10 EWA 4NEB 812 6120-02b

S5-100U Addressing
6.5.2 Accessing the Process Image Output Table (PIQ)
During a program cycle, data coming from the control program to the output modules is written into
the process image output table (PIQ). The data is transferred to the output modules in the following
data cycle.
Access to the PIQ is expressed by the operand identifiers “Q”, “QB”, or “QW” in a statement in
the control program.
The letter “T” identifies the “Transfer” operation (see Chapter 8). The “=” character assigns the
result of a logic operation (RLO) to the operand that follows the character (see chapter 8).
PIQ
• Bit-by-bit writing Bit number

“Q <bit address>” 7 6 5 4 3 2 1 0
Example: Writing the signal state to
channel 6 of an 8-channel digital output
module in slot 4
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“QB <byte address>”
Example: Writing the signal states to all
channels of an 8-channel digital output
module in slot 29
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“QW <word address>”
Example: Writing an analog value to
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module in slot 6
T QW 116
Byte 116
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Figure 6-9. Accesses to the PIQ
EWA 4NEB 812 6120-02b 6-11

Addressing S5-100U
6.6 Interrupt Process Images and Time-Controlled Program Processing

in OB13 for CPU 103, Version 8MA02 and Higher
In the event of a time-controlled or process interrupt, the CPU does not access the I/O modules
directly. The CPU stores its information in interrupt process images.
• The interrupt process images are used only for time-controlled or interrupt-driven program
processing.
• The interrupt process images and the “normal” process images have identical structures.
• The interrupt process input image (interrupt PII) and interrupt process output image (interrupt
PIQ) take up an area of 128 bytes each in the RAM.
The interrupt PII and interrupt PIQ can be divided into three address areas as shown in Table 6-4.
Table 6-4. Structure of the Interrupt PII and the Interrupt PIQ
Byte address in interrupt Module Slot number
PII and interrupt PIQ
0 to 31 Digital modules 0 to 31
32 to 63 Unassigned address space
64 to 127 Analog modules 0 to 7
Note
The interrupt process images can be accessed by byte or word operations only.
6.6.1 Accessing the Interrupt PII
• The interrupt PII can only be accessed in connection with time-controlled or interrupt-driven
program processing.
• Data from inputs is read into the interrupt PII only at the beginning of time-controlled program
processing. This data is available only to the time-controlled program for evaluation.
6-12 EWA 4NEB 812 6120-02b

S5-100U Addressing
Time-Controlled Program Processing

Access to the interrupt PII is expressed by the “PB” or “PW” operand identifiers in a statement in
the time-controlled program.
The letter “L” represents the “Load” operation (see chapter 8).
Interrupt PII
• Byte-by-byte reading “PB <byte address>”

Example: Reading in the signal states of all
channels of an 8-channel digital input module
in slot 21
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L PY 21 Byte 21
15 0
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ACCU 1
High byte Low byte
• Word-by-word reading “PW <word address>”

Example: Reading in the analog value of
channel 2 of a 4-channel analog input module
in slot 1
L PW 76
Byte 76
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ACCU 1
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Figure 6-10. Accesses to the Interrupt PII
Interrupt-Driven Program Processing

• When a process interrupt occurs, only the data of the interrupt inputs, slots 0 and 1, is read into
the interrupt PII.
• Only this data of the interrupt PII is available to the interrrupt-driven program for evaluation.
• In a statement in the interrrupt-driven program, access to the interrupt PII is possible only with
the following operands: PB0, PB1, and PW0.
• If other parameters are specified, the CPU goes into the STOP mode and the “NNN” error
message is specified in the ISTACK. See section 5.2.
EWA 4NEB 812 6120-02b 6-13

Addressing S5-100U
6.6.2 Accessing the Interrupt PIQ

When accessing the interrupt PIQ, the following rules apply.
• Data can be written to the interrupt PIQ only within time-controlled or interrupt-driven program
processing.
• Data from a time-controlled or interrupt-driven program to external outputs is written during time-
controlled or interrupt-driven program processing both to the “normal” PIQ and the interrupt
PIQ.
• Data from the interrupt PIQ is read out to the outputs in the next interrupt output data cycle.
• The PIQ is copied to the interrupt PIQ after the OB1 program cycle.
Note
The interrupt output data cycle is executed only after the interrupt PIQ has been written
to.
Access to the interrupt PIQ is expressed by the “PB” or “PW” operand identifiers in a statement in
the time-controlled or interrrupt-driven program.
The letter “T” identifies the “Transfer” operation (see chapter 8).
Interrupt PIQ
• Byte-by-byte writing
“PB <byte address>”
Example: Writing signal states to all
channels of an 8-channel digital output
module in slot 13
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High byte Low byte
• Word-by-word writing
“PW <word address>”
Example: Writing an analog value to channel 3
of a 4-channel analog output module in slot 5
T PW 110
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
Byte 110
Byte 111
15 0
ACCU 1
High byte Low byte
Figure 6-11. Accesses to the Interrupt PIQ
6-14 EWA 4NEB 812 6120-02b

S5-100U Addressing
6.7 RAM Address Assignments
The following table gives an overview of the major addresses in the RAM of the three CPUs (in
hexadecimal code).
Table 6-5. Important Addresses in the RAM
CPU 100 102* 103
Program memory EE00 to FFFF D000 to DFFF 8000 to CFFF
Memory submodule C000 to DFFF 4000 to 5FFF 0000 to 7FFF
PII, digital E400 to E41F EF00 to EF1F EF00 to EF1F

PII, analog E440 to E47F EF40 to EF7F EF40 to EF7F
PIQ, digital E480 to E49F EF80 to EF9F EF80 to EF9F

PIQ, analog E4C0 to E4FF EFC0 to EFFF EFC0 to EFFF
Timers E280 to E29F EC00 to EC39 EC00 to ECFF

Retentive counters E2A0 to E2AF ED00 to ED0F ED00 to ED0F
Non-retentive counters E2B0 to E2BF ED10 to ED3F ED10 to ED3F

Retentive flags E300 to E33F EE00 to EE3F EE00 to EE3F
Non-retentive flags E340 to E37F EE40 to EE7F EE40 to EE7F
Module address list
OB E080 to E0FF FC80 to FCFF DC00 to DDFF
FB E100 to E17F FD00 to FEFF DE00 to DFFF

PB E180 to E1FF FF00 to FF7F E000 to E1FF
SB ---- ---- E200 to E3FF
DB E200 to E27F FF80 to FFFF E400 to E5FF
System data EA00 to EBFF EA00 to EBFF EA00 to EBFF

* Program memory; block address list only in TEST mode.
EWA 4NEB 812 6120-02b 6-15

Addressing S5-100U
The following table gives an overview of the most important system data in the system data area.
Table 6-6. System Data Area Assignment
System data Chapter/

Contents
word Section Reference
5 to 7 ISTACK (Interrupt STACK) 5.2
8 to 12 Integral real-time clock 12

33 First free program memory address
35 Program memory starting address

37 Program memory end address
40 to 45 CPU version, software release

57 to 63 SINEC L1 13
96 Scan monitoring time (value . 10 ms)
97 Calling interval for OB 13 for time-controlled program 7.4.4

processing (value . 10 ms)
128 to 159 BSTACK (Block STACK) 5.3.2
203 to 214 ISTACK (Interrupt STACK) 5.2
6-16 EWA 4NEB 812 6120-02b

7 Introduction to STEP 5
7.1 Writing a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1

7.1.1 Methods of Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1
7.1.2 Operand Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.1.3 Circuit Diagram Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.2.1 Linear Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4
7.2.2 Structured Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5
7.3 Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.3.1 Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 9
7.3.2 Program Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.3 Sequence Blocks, for CPU 103 and Higher . . . . . . . . . . . . . . . . . 7 - 11
7.3.4 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.5 Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 16
7.4 Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18

7.4.1 Program Processing with CPU 102 . . . . . . . . . . . . . . . . . . . . . . . 7 - 19
7.4.2 START-UP Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 24
7.4.3 Cyclic Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 26
7.4.4 Time-Controlled Program Processing, for CPU 103
Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 28
7.4.5 Interrupt-Driven Program Processing, for CPU 103
Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 29
7.5 Processing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30

7.5.1 Changing Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.2 Changing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.3 Compressing the Program Memory . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.6 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 31
EWA 4NEB 812 6120-02b

Figures
7-1 Compatibility of STEP 5 Methods of Representation . . . . . . . . . . . . . . . . . 7 - 2

7-2 Nesting Depth of Programmed Organization Blocks . . . . . . . . . . . . . . . . . 7 - 6
7-3 Structure of a Block Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8
7-4 Example of Organization Block Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 10
7-5 Programming a Function Block Parameter, for CPU 103 and Higher . . . . . . 7 - 13
7-6 Programming a Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 16
7-7 Example of Data Block Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 17
7-8 Validity Areas of Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 17
7-9 Programm Scanning with CPU 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 19
7-10 Mode Change for CPU 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 21
7-11 Display of the Processing Mode in the ISTACK . . . . . . . . . . . . . . . . . . . . 7 - 22
7-12 Setting the Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 24
7-13 Cyclic Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 26
7-14 Calculating the Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 27
7-15 Compressing the Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7-16 Bit Assignment of a 16-Bit Fixed-Point Binary Number . . . . . . . . . . . . . . . 7 - 31
7-17 BCD and Decimal Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 32
Tables
7-1 Comparison of Operation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 2

7-2 Comparison of Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7
7-3 Overview of Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 9
7-4 Block Parameter Types and Data Types with Permissible Actual
Parameters, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 14
7-5 Programming Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18
7-6 Comparison of Number Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 32
EWA 4NEB 812 6120-02b

S5-100U Introduction to Step 5
7 Introduction to STEP 5
This chapter explains how to program the S5-100U. It describes how to write a program, how the
program is structured, the types of blocks the program uses, and the number representation of the
STEP 5 programming language.
7.1 Writing a Program

A control program specifies a series of operations that tell the programmable controller how it has to
control a system. For example, a control program might be the series of operations that tell the
S5-100U how to use open-loop control or closed-loop control for a specific system. You must write
the program in a special programming language and according to specific rules so that the pro-
grammable controller can understand it. The programming language that has been developed for the
SIMATIC S5 family is called STEP 5.
7.1.1 Methods of Representation
The following methods of representation are possible with the STEP 5 programming language.
• Statement List (STL)
STL represents the program as a sequence of operation mnemonics. A statement has the
following format:
Operation
Operand
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002: A I 0.1
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Parameter
Operand ID
Relative address of the statement
in a particular block
The operation tells the programmable controller what to do with the operand. The parameter
indicates the operand address.
• Control System Flowchart (CSF)
CSF represents logic operations with graphics symbols.
• Ladder Diagram (LAD)
LAD graphically represents control functions with circuit diagram symbols.
• GRAPH 5, for CPU 103 and higher
GRAPH 5 describes the structure of sequence control systems.
You cannot use CSF, LAD, or GRAPH 5 with the PG 605 programmers.
EWA 4NEB 812 6120-02b 7-1

Introduction to STEP 5 S5-100U
Each method of representation has its own special characteristics. A program block that has been
programmed in STL cannot necessarily be output in CSF or LAD. The three methods of graphic re-
presentation are not compatible. However, programs in CSF or LAD can always be converted to
STL. Figure 7-1 illustrates these points in a diagram.
CSF LAD
STL
Figure 7-1. Compatibility of STEP 5 Methods of Representation
The STEP 5 programming language has the following three operation types:
• Basic
• Supplementary
• System
Table 7-1 provides further information about these operations.
Table 7-1. Comparison of Operation Types
STEP 5 PROGRAMMING LANGUAGE
Supplementary
Basic Operations System Operations
Operations
Application In all blocks Only in function blocks Only in function blocks
Methods of
STL, CSF, LAD STL STL
representation
For users with good
Special features
system knowledge
Refer to Chapter 8 for a description of all operations and for programming examples.
7-2 EWA 4NEB 812 6120-02b

7.1.2 Operand Areas
The STEP 5 programming language has the following operand areas:
I (inputs) Interfaces from the process to the programmable controller
Q (outputs) Interfaces from the programmable controller to the process
F (flags) Memory for intermediate results of binary operations
D (data) Memory for intermediate results of digital operations
T (timers) Memory for implementing timers
C (counters) Memory for implementing counters
P (peripherals) Interfaces from the process to the programmable controller
K (constants) Defined numeric values
OB, PB, SB
FB, DB (blocks) Program structuring aids
Refer to Appendix A for a listing of all operations and operands.
7.1.3 Circuit Diagram Conversion
If your automation task is in the form of a circuit diagram, you must convert it to STL, CSF, or LAD.
EWA 4NEB 812 6120-02b 7-3

Example: Hard-Wired Control

A signal lamp (H1) is supposed to light up when a normally open contact (S1) is acti-
vated and a normally closed contact (S2) is not activated.
Programmable Control
The signal lamp is connected to an output (i.e., Q 1.0). The signal voltages of the two
contacts are connected to two programmable controller inputs (i.e., I 0.0 and I 0.1).
The S5-100U scans to see if the signal voltages are present (signal state “1” at the
activated normally open contact or non-activated normally closed contact). Both signal
states are combined through logic AND. The result of logic operation (RLO) is assigned
to output Q 1.0 (the lamp lights).
Circuit Diagram STL CSF LAD
S1
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A I 0.0 I 0.0 I 0.1 Q 1.0
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= Q 1.0
H1
7.2 Program Structure
An S5-100U program can be one of the two following types:

• Linear
• Structured
Sections 7.2.1 and 7.2.2 describe these program types.
7.2.1 Linear Programming
Programming individual operations in one section (block) is sufficient for handling simple automation
jobs. For the S5-100U, this is organization block 1 (see section 7.3.1). The S5-100U scans this
block cyclically. After the S5-100U scans the last statement, it goes back to the first statement and
begins scanning again. Please note the following rules:
• When OB1 is called, five words are assigned to the block header in the program memory (see
section 7.3).
• Normally, a statement takes up one word in the program memory.
Two-word statements also exist (e.g., with the operation “Load a constant”). Count these
statements twice when calculating the program length.
• Like all blocks, OB1 must be terminated by a Block End statement (BE).
7-4 EWA 4NEB 812 6120-02b

7.2.2 Structured Programming
To solve complex tasks, it is advisable to divide a program into individual, self-contained program
parts (blocks). This procedure has the following advantages:
• Simple and clear programming, even for large programs
• Program parts can be standardized
• Easy alterations
• Simple program test
• Simple start-ups
• Subroutine techniques (block call from different locations)
The STEP 5 programming language has the following five block types:
• Organization Block (OB)
Organization blocks manage the control program.
• Program Block (PB)
Program blocks arrange the control program according to functional or technical aspects.
• Sequence Block (SB)
Sequence blocks are special blocks that program sequence controls. They are handled like
program blocks. (This is available for CPU 103 and higher.)
• Function Block (FB)
Function blocks are special blocks for programming frequently recurring or especially complex
program parts (e.g., reporting and arithmetic functions). You can assign parameters to them
(available for CPU 103 and higher). They have an extended set of operations (e.g., jump
operations within a block).
• Data Block (DB)
Data blocks store data needed to process a control program. Actual values, limiting values, and
texts are examples of data.
EWA 4NEB 812 6120-02b 7-5

The program uses block calls to exit one block and jump to another. You can therefore nest pro-
gram, function, and sequence blocks randomly up to 16 levels (see section 7.3). Nesting can be up
to 32 levels for CPU 103 version 8MA03.
Note
When calculating the nesting depth, note that the system program in the programmable
controller can call an organization block automatically under certain circumstances
(e.g., OB2).
The total nesting depth is the sum of the nesting depths of call programmed organization blocks. If
nesting goes beyond 16 levels (32 levels for CPU 103 version 8MA03), the CPU goes into the
STOP mode with the error message “STUEB,” block stack overflow (see section 5.2). Figure 7-2
illustrates the nesting principle.
OB 1
.......
.......
Level 1 Level 2 Level 3 ....... Level 16
Figure 7-2. Nesting Depth of Programmed Organization Blocks
7-6 EWA 4NEB 812 6120-02b

S5-100U Introduction to STEP 5
7.3 Block Types
The following table lists the most important characteristics of the individual block types:
Table 7-2. Comparison of Block Types
OB1 PB SB FB2 DB3
Number 64 64 64 62
CPU 100 OB0 to OB63 PB0 to PB63 FB0 to FB63 DB2 to DB63
Number 64 64 64 62
CPU 102 OB0 to OB63 PB0 to PB63 FB0 to FB63 DB2 to DB63
Number 256 256 256 2562 254
CPU 103 OB0 to OB255 PB0 to PB255 SB0 to SB255 FB0 to FB255 DB2 to DB255
Length (max.)
4 Kbytes 4 Kbytes 4 Kbytes 256 data words
CPU 100
Length (max.)
4 Kbytes 4 Kbytes 4 Kbytes 256 data words
CPU 102
Length (max.)
8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes
CPU 103
Operations Basic Basic Basic Basic, Bit patterns,

set operations operations operations supple- numbers,
(contents) mentary, texts
system
operations
Representa- STL, CSF, STL, CSF, STL, CSF, STL

tion methods LAD LAD LAD
Block header 5 words 5 words 5 words 5 words 5 words

length
1 The operating system calls up particular OBs automatically (see section 7.3.1 and 9.3).
2 Function blocks are already integrated into the operating system (see section 9.2).
3 Data blocks DB0 and DB1 are reserved.
EWA 4NEB 812 6120-02b 7-7

•
•
7-8
byte
order)
Absolute
addresses
Programming
Block Structure
(in ascending
Introduction to STEP 5
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

1. Specify the block type (e.g., PB).

2. Specify the block number (e.g., 27).

Each block consists of the following parts:
3. Enter the control program statements.

aaaaaaaaaaaaaaaa
4. Terminate the block with the “BE” statement.

The block body that has the STEP 5 program or data
a
a aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaa
a
a
Program your blocks as follows (does not apply to data blocks):

a
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aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaa
a
a
aaaaaaaaaaa
aaaaaaaaaa aaaaaaaaaaaaaaaaaa
a aaaaaaaaaa aaaaaaaaaaaaaaaaaa
- Generated by the programmer when it transforms the block
a
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a aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaa
The block header that specifies the block type, number, and length
a
Figure 7-3. Structure of a Block Header
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a aaaaaaaaaaa aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
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a
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aaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaa
pattern
Block type
Block length
Block number
Library number
Programmer ID
Synchronization
EWA 4NEB 812 6120-02b

S5-100U
•
•
•
aaaaaaaa
aaaaaaaa
OB2
OB1
aaaaaaaa
7.3.1
OB31
OB34
OB22
OB21
OB13
OB251
OB No.
S5-100U
EWA 4NEB 812 6120-02b

Battery failure

When power returns
PID control algorithm

to events or at certain times:
Handling start-up procedures

Organization Blocks
Cyclic program processing

- By interrupts (OB2 and OB13)
Function
Interrupt-driven program processing

Interrupt-driven program processing
Time-controlled program processing

- By a switch from STOP to RUN (OB21)
When starting manually (STOP to RUN)
Handling programming errors and device errors

Table 7-3 provides an overview of organization blocks.
Scan time triggering (resets scan time monitor)
OB is ready or is supported by the operating system
must call the organization blocks from the control program.

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The OB is already programmed. You must call up the OB.

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Organization blocks are handled in one of the following three ways:
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Organization block OB1 is called cyclically by the operating system.
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CPU 100
You must program the OB. The operating system calls up the OB.
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Table 7-3. Overview of Organization Blocks
- By a switch from Power OFF to Power ON (OB22 (see Table 7-3))
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You can program all organization blocks using parameters from the permissible range. CPU 100
Some organization blocks are event-driven or time-controlled. They can be called in response
blocks). They can be called by the control program (for CPU 103 and higher; see section 9.3).

CPU 103
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and CPU 102 use organization blocks OB0 to OB63. CPU 103 uses OB0 to OB255. However, you
Organization blocks (OB) form the interface between the operating system and the control program.
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Some other organization blocks represent operating functions (similar to the the integral function
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organization blocks.
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System program
* For CPU 103 and higher
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FB2
PB1
Control program
SB1*
FB61
Figure 7-4. Example of Organization Block Use

Figure 7-4 shows how to set up a structured control program. It also illustrates the significance of
EWA 4NEB 812 6120-02b

S5-100U
7.3.2 Program Blocks
Self-contained program parts are programmed in program blocks (PB).

Special feature: Control functions can be represented graphically in program blocks.
Call
Block calls JU and JC activate program blocks. You can program these operations in all block types
except data blocks. Block call and block end cause the RLO to be reloaded. However, the RLO
can be included in the “new” block and be evaluated there.
7.3.3 Sequence Blocks, for CPU 103 and Higher
Sequence blocks (SB) are special program blocks that process sequence controls. They are treated
like program blocks.
7.3.4 Function Blocks
Frequently recurring or complex control functions are programmed in function blocks (FB).
Function blocks have the following special features.

• FBs can be assigned parameters (for CPU 103 and higher).
- Actual parameters can be assigned when the block is called (for CPU 103 and higher).
• FBs have an extended set of operations not available to other blocks.
• The FB program can be written and documented in STL only.
If you are using CPU 102 version 8MA02 or higher, you have the following types of function blocks
available:
• FBs that you can program
• FBs that are integrated in the operating system (see section 9.2)
• FBs that are available as software packages (standard function blocks, see Catalog ST 57)
EWA 4NEB 812 6120-02b 7-11

Block Header
Besides the block header, function blocks have organizational information that other blocks do not
have.
A function block's memory requirements consist of the following:

• Block header (five words) as for other blocks
• Block name (five words)
• Block parameter for parameter assignment (three words per parameter)
Creating a Function Block, for CPU 103 and Higher
In contrast to other blocks, parameters can be assigned to FBs.

To assign parameters, you must program the following block parameter information.
• Block Parameter Name (formal operand)
Each block parameter as a formal operand is given a designation (DES). Under this designation
it is replaced by an actual parameter when the function block is called.
The name can be up to four characters long and must begin with an alpha character. You can
program up to 40 block parameters per function block.
• Block Parameter Type
You can enter the following parameter types:
-I input parameters
-Q output parameters
-D data
-B blocks
-T timers
-C counters
In graphic representation, output parameters appear to the right of the function symbol. Other
parameters appear to the left.
• Block Parameter Data Type
You can specify the following data types:
- BI for operands with a bit address
- BY for operands with a byte address
-W for operands with a word address
-K for constants
7-12 EWA 4NEB 812 6120-02b

When assigning parameters, enter all block parameter specifications.
Block header
Name
NAME: EXAMPLE
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DES: IN 1 I BI Block parameter
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parameter DES: OUT 1 Q BI
. Data type
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: A = IN 1
: A = IN 2
Control
program : == OUT 1
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Memory assignment Program example
Figure 7-5. Programming a Function Block Parameter, for CPU 103 and Higher
EWA 4NEB 812 6120-02b 7-13

Table 7-4. Block Parameter Types and Data Types with Permissible Actual
Parameters, for CPU 103 and Higher
Parameter
Data Type Permissible Actual Parameters
Type
I, Q BI for an operand with bit address I x.y Inputs
Q x.y Outputs
F x.y Flags
BY for an operand with byte address IB x Input bytes

QB x Output bytes
FY x Flag bytes
DL x Data bytes left
DR x Data bytes right
PY x Peripheral bytes*
W for an operand with word address IW x Input words

QW x Output words
FW x Flag words
DW x Data words
PW x Peripheral words*
D KM for a binary pattern (16 digits) Constants

KY for two absolute numbers, one byte each,
each in the range from 0 to 255
KH for a hexadecimal pattern (maximum 4
digits)
KS for a character (maximum 2
alphanumeric characters)
KT for a time (BCD-coded time) with time
base 1.0 to 999.3
KC for a count (BCD-coded) 0 to 999
KF for a fixed-point number in the range
from -32768 to +32767
B Type designation not permitted DBx Data blocks. The C DBx operation is
executed.
OBx Organization blocks are called
unconditionally (JU ... x).
FBx Function blocks (permissible without
parameters only) are called
unconditionally (JU..x).
PBx Program blocks are called
SBx Sequence blocks are called
T Type designation not permitted T Timer. The time should be assigned

parameters as data or be programmed
as a constant in the function block.
C Type designation not permitted C Counter. The count should be

assigned parameters as data or be
programmed as a constant in the
function block.
* Not permitted for integral FBs
Calling a Function Block

Like other blocks, function blocks are stored under a specific number in the program memory (e.g.,
FB47). The numbers 240 to 255 are reserved for the integral function blocks (in CPU 103 version
8MA02 and higher).
You can program function block calls in all blocks except data blocks.
7-14 EWA 4NEB 812 6120-02b

A function block call consists of the following parts:

• Call statement
- JU FBx unconditional call (Jump Unconditional)
- JC FBx call if RLO = 1 (Jump Conditional)
• Parameter list (only if block parameters were defined in the FB)
Function blocks can be called only if they have been programmed. When a function block call is
being programmed, the programmer requests the parameter list for the FB automatically if block
parameters have been defined in the FB.
Setting Parameters for a Function Block

The program in the function block specifies how the formal operands (parameters defined as “DES”)
are to be processed.
As soon as you have programmed a call statement (for example JU FB2), the programmer displays
the parameter list. The parameter list consists of the names of the parameters. Each parameter
name is followed by a colon (:). You must assign actual operands to the parameters. The actual
operands replace the formal operands defined in the FB when the FB is called, so that the FB
operates with the actual operands.
A parameter list has a maximum of 40 parameters.
Example: The name (DES) of a parameter is IN1, the parameter type is I (as in input), the data
type is BI (as in bit). The formal operand for the FB has the following structure:
DES: IN1 I BI
Specify in the parameter list of the calling block which actual operand is to replace the
formal operand in the FB call. In our example it is : I 1.0.
Enter in the parameter list:
IN1: I 1.0
When the FB is called, it replaces the formal operand “IN1” with the actual operand
“I 1.0”.
Figure 7-6 provides you with a detailed example of how to set parameters for a function block.
The FB call takes up two words in the internal program memory. Each parameter takes up an
additional memory word.
You can find the memory requirements for standard function blocks and the run times in the
specifications in Catalog ST 57.
The name of the function block is stored in the function block. The designations (DES) of the
function block inputs and outputs that appear on the programmer during programming are also
stored in the function block. Before you begin programming on the programmer, you must choose
one of the following two options:
• Transfer all necessary function blocks to the program diskette (for off-line programming)
• Input all necessary function blocks directly into the program memory of the programmable
controller
EWA 4NEB 812 6120-02b 7-15

Executed
PB 3 FB 5 program
NAME : EXAMPLE
DES: X1 I BI
DES: X2 I BI
: JU FB5 DES: X3 Q BI
: A = X1
NAME : EXAMPLE : A = X2 First call
X1 : I 0.0 : = = X3 A I 0.0
Parameter list
X2 : F 1.3 for first call : BE A F 1.3
X3 : Q 1.0 = Q 1.0
. Formal operands
. Actual operands
: A I 0.1
: JC FB5
NAME : EXAMPLE Second call
X1 : I 0.3 A I 0.3
Parameter list
X2 : I 0.2 for second call A I 0.2
X3 : Q 1.0 = Q 1.0
Formal operands
Figure 7-6. Programming a Function Block
7.3.5 Data Blocks
Data blocks (DB) store data to be processed in a program.
The following data types are permissible:

• Bit pattern (representation of controlled system states)
• Hexadecimal, binary or decimal numbers (times, results of arithmetic operations)
• Alphanumeric characters (ASCII message texts)
7-16 EWA 4NEB 812 6120-02b

Programming Data Blocks

Begin programming a data block by specifying a block number between 2 and 63 for CPU 100 or
CPU 102, and between 2 and 255 for CPU 103. DB0 is reserved for the operating system, DB1 for
setting parameters for internal functions (see section 9.1). Data is stored in this block in words.
If the information takes up less than 16 bits, the high-order bits are padded with zeros. Data input
begins at data word 0 and continues in ascending order. A data block can hold up to 256 data
words. You can call up or change the data word contents with load or transfer operations.
Input Stored Values
0000 : KH = A13C DW0 A13C

0001 : KT = 100.2 DW1 2100
0003 : KF = +21874 DW2 5572
Figure 7-7. Example of Data Block Contents
You can also create or delete data blocks in the control program (see section 8.1.8).
Program Processing with Data Blocks

• A data block must be called in the program with the C DBx operation (x = DB number) before it
can be accessed.
• Within a block, a data block remains valid until another data block is called.
• When the program jumps back into the higher-level block, the data block that was valid before
the block call is again valid.
• After OB1, 2, 13, 21, 22 have been called by the operating system, no DB is valid.
Valid Valid
DB PB7 PB20 DB
C DB10 DB10
DB10
C DB11
JU PB20
DB11
DB10
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When PB20 is called, the valid data area is entered into memory.
When the program jumps back, this area is reopened.
Figure 7-8. Validity Areas of Data Blocks
The Function of DB1

DB1 is used for special functions. DB1 is already integrated into CPU 103 version 8MA03 and
higher and contains (default) values that you can either accept or change (see section 9.1). DB1 is
evaluated once during start-up: either after Power ON or after a transition from STOP to RUN.
EWA 4NEB 812 6120-02b 7-17

7.4 Program Processing
Some of the organization blocks (OBs) are responsible for structuring and managing the control
program.
These OBS can be grouped according to the following assignments:

• OBs for START-UP program processing
• One OB for cyclic program processing
• OBs for time-controlled program processing
• OBs for (process) interrupt-driven program processing
The S5-100U has additional OBs whose functions are similar to those of integral function blocks
(e.g., PID control algorithm). These OBs are described in chapter 9.
Section 7.3.1 summarizes all of the OBs.
Comparing Programming Possibilities for CPU 100, CPU 102, and CPU 103
Table 7-5. Programming Possibilities
CPU CPU 100 CPU 102 CPU 103
Cyclical Yes Yes Yes
Interrupt-driven No No Yes
(for 8MA02 and higher)
Time-controlled No No Yes
Integral FBs No Yes Yes
Graph 5 No No Yes
Programmable FBs No No Yes
Beginning with section 7.4.2, you learn which special organization blocks each of the CPUs has
available to perform the programming tasks described in Table 7-5. You also learn which pre-
cautions you need to take when you program.
7-18 EWA 4NEB 812 6120-02b

7.4.1 Program Processing with CPU 102
You can process the program in the following two modes:

• Normal mode
• Test mode
Program processing is faster in the normal mode, but you can not use the STATUS test function.
Transferring from one mode to the other is called a mode change.
Test Mode:
Scanning the STEP 5 program
Normal Mode:
The control program you have written in STEP 5 is not processed directly. What is processed is a
translated or runtime-optimized form of the program generated by the programmable controller.
Cycle trigger
Cycle trigger
Control Runtime-
Assemble
program optimized
(compile)
in STEP 5 program
Transfer
data
Transfer
data
Test mode Normal mode
Figure 7-9. Program Scanning with CPU 102
EWA 4NEB 812 6120-02b 7-19

Special Features of the Normal Mode
Significance of the Memory Submodule

Normal mode is only possible if the memory submodule is plugged in.
This submodule contains only the STEP 5 program.
The CPU RAM contains the STEP 5 program and the compiled program to be processed.
Program Change
You can enter, modify, or erase PBs, OBs and FBs only in the test mode.
You can read out the STEP 5 program with the programmer.
Signal Status Display

You can monitor and control signals states with the “STATUS VAR” and “FORCE VAR” functions.
The “STATUS” function can be used only in the test mode.
Diagnostics
The “BSTACK” diagnostics function cannot be activated.
Fault Analysis
The ISTACK bytes 23 to 27 are not valid. Therefore, you cannot determine the point in a program
where an interruption took place (programmable controller in STOP, e.g., programmed loop with
timeout). However, when compiling the program, errors (e.g., illegal operations and parameters) are
detected and displayed by the STEP address counter in the ISTACK. This counter points to the
error in the STEP 5 program.
7-20 EWA 4NEB 812 6120-02b

S5-100U
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a a a a a a a a a a a
aa a a a a a a a a a
a a
a a
a a
a a
a a
a a
a a
a a
a a
aa aa aa aa aa aa
aa a a a a a a a a a
Mode Change
aa a a a a a a a a a aaaaaaaaaaaaaaaaaaaa
a
a
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
aa
a
a a a a a a a a a a
aaa
aa a
a a
a a
a a
a a
a a
a a
a a
a a
aa
a
aaaa a
a a
a a
a a
a a
a a
a a
a a a a a a a a a a a a
a a
a a
a a
a a
a a
a a
a a
a a
a a
aa
a
a a a a a a a a a
a a
a a
a a
a a
a a
a a
a a
a a
a a
a a a a a a a a a a
aaaaaaaaaaaaaaaaaaa a a a a a a a a aaaaaaaaaaaaaaaaaaaa
module
aa a a a a a a a a
EWA 4NEB 812 6120-02b

aaaaaaaaaaaaaaaaaaa a a a a a a a a aaaaaaaaaaaaaaaaaaaa
aaa
a
aaaaa
aa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaaaaaaaaaaaaaaaaa aa
aaa
a
aaa
a
aaa
a
aaa
a
aaa
a
aaa
a
aaa
a
aaa
a aa
a aa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa a a a a a a a aaaaaaaaaaaaaaaaaaaa
hold it down
a a a a a a a a aaaaaaaaaaaaaaaaaaaa
submodule
Test
aa
aa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
a a a a a a a a a aaaaaaaaaaaaaaaaaaaa
(manual)
aa a a a a a a a a
mode
aaaaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
a a
a a
a a
a a
a a
a a
a a
a a
a a
aa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaaa a a a a a a a a a a a a a a a aa
Load program
a a a a a a a a a a a a a a a a a aaaaaaaaaaaaaaaaaaaa
Reset PLC
a a a a a a a a a a
4. Turn on the PLC

1. Turn off the PLC
(without PG)
a a a a a a a a aaaaaaaaaaaaaaaaaa a
aa a a a a a a a a
4. Turn on the PLC

2. Turn off the PLC
a a a a a a a a a a a a a a a a a aa a a a a a a a a
- Red LED flickers

aaa a a a a a a a a aaaa
a aaa
aaa
aaa
aaa
aaa
aaa
aaa aaaaaaaaaa
aaa
5. Release COPY key

program is loaded
aaa a a a a a a a a aaaaaaaaaaaaaaaaaa a
aa a a a a a a a a

2. Plug in memory sub-
1. Remove the battery

aaa a a a a a a a a a a a a a a a a a aa a a a a a a a a
3. Press COPY key and
a a a a a a a a a a
3. Remove the memory

aaa a a a a a a a a aaaaaaaaaaaaaaaaaa a
aa a a a a a a a a
- Red LED lights when

a
aa
aa
a a
a a
a a
a a
a a
a a
a a
a a
a a
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aa a
a
aa
a a
a a
a a
a a
a a
a a
a a
a a
aa a a a a a a a a a a aa a
aaa
aaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaa aa
a
aa
a a
aa
a
a
aa
a
aa
a
aa
a
aa
a
aa
aa
a
a a
a a
a a
a a
aa
aa
aa
aa
aa
aaaaaaaaaa a
least 3 s
flickering
submodule
Battery required
CPU’s RAM
(with PG)
1. Turn on the PLC

3. Turn on the PLC
1. Turn off the PLC
(without PG)
- Red LED lights
reset with the PG

2. Plug in EEPROM
Load program
the red LED starts
3. Perform an overall
4. Enter the program

With or without battery
Back up program
2. Switch PLC to STOP
5. Transfer the program

and compiled in the
5. Release it as soon as
- Program is stored in
4. Press COPY key for at
EEPROM submodule
a
aa
aa
aa
aa
aaaaaaaaaaaaa
a
aa
aa
aa
aa
aaaaaaaaaaaa
aaaaa a a a
a a
a a
a
aaaaaaaaaaaaa
a
a a a a aaaa a aaaaaaa
a a a a a a a aa
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aa
aaaa aa aa aa aa a
a
a a
a a
a a
a a
a a
a a
a a
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
a a
aa
a a
aa
a a
aa
a a
aa
a a
a
Figure 7-10. Mode Change for CPU 102

a a a a a a a aa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aa aa aa aa aa a
a
a a
a a
a a
a a
a a
a a
a a
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
a a
aa
a a
aa
a a
aa
a a
aa
a a
a
a a a a a a a aa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aaa
aa aa aa aa aa
a a a a a a a aaaaaaaaaaaaaaaaaaaaa aa aa aa aa
resumed.
a a aaaaaaaaaaaaaaaa a a a a a a a a a a
aa
a a
aa
a a
aa
a a
aa
a a
aa
a
a a aaaaaaaaaaaaaaaa a a a a a a a a a
loaded
interrupted
a aa aaaaaaaaaaaaaaaa aa
aaaa
aaaa
aaaa
aa a
aa
a a a a a a a a aaaaaaaaaaaaaaaaaaaa aa aa aa aa
submodule
aaa
a aa
aaaaaa
aaa
aaa
aaa
aaa
aaa
aaa
a a aa aa aa aa
aaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
a aa
a aa
a aa
a aa
a aa
a aa
a aa
a aa
a aa
a aa aa aa aa aa
(automatic)
aaaaaaaaaaaaaaaaaaaa a a a a a a a a a aa aa aa aa aa
1. Reset the PLC
aa aa aa aa aa
mode
aaaaaaaaaaaaaaaaaaaa a a a a a a a a a
Load program
3. Plug in memory
at STOP or Power
when program
OFF in the case of

Normal
4. Turn on the PLC
2. Turn off the PLC
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
mode when RUN is

a a a a a a a a a aaaaaaaaaaaaaaaaaaaaa aa aa aa aa a
battery backup), the

a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa
aa
a
will be the operating

- Red LED flickers
a a a a a a a a a a
(fault, mode selector

a a a a a a a a a a a
mode that was active

aa
a aa
a aa
a aa
a aa
a aa
a aa
a aa
a aa
a aa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
a aa
aaa
a aa
aaa
a aa
aaa
a aa
aaa
a aa
aaa
aa
a
If program scanning is
a a a a a a a a a
prior to the interruption

aaaaaaaaaaa a
aaaa a a a a a a a a aa aa aa a
a aaaaaaaaaaaa aa
a
a
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aaa
aa
aaa aaaaaaaaaaaa
aaa a
aaaaaaaaaa
7-21
Determining the Processing Mode in the ISTACK
Bit
Byte 7 6 ...
1
2
.
.
.
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
6 KEIN
AS
7
.
.
.
Figure 7-11. Display of the Processing Mode in the ISTACK
You can use a programmer to check the current processing mode in the ISTACK. The ISTACK
display, byte 6, is possible in RUN and STOP (see section 5.2).
KEIN AS=1 : Test mode

Execution time is 70 ms/1024 binary statements. There are no limitations on the test or operator
functions.
KEIN AS=0: Normal mode

Execution time is 7 ms/1024 binary statements. There are limited test and operator functions.
7-22 EWA 4NEB 812 6120-02b

Further Reduction in the Execution Time in Normal Mode

Logic operations executed in one input byte, output byte, or flag byte require only 2 µs per logic
operation. Program your control according to example 2.
Example 1: Example 2:
STL Time/ µs STL Time/ µs
A I 0.0 5 A I 0.0 5
AN I 1.1 6 AN I 0.1 2
ON I 2.3 6 ON I 0.3 2
O I 3.5 6 O I 0.5 2
= Q 4.2 8 = Q 4.2 8
A F 15.1 5 A F 15.1 5
A F 16.3 6 A F 15.3 2
AN F 17.7 6 AN F 15.7 2
= Q 4.5 8 = Q 4.5 8
Execution time 56 µs Execution time 36 µs
Approx. 6 µs/binary operation Approx. 4 µs/binary operation
EWA 4NEB 812 6120-02b 7-23

•
•
•
•
•
•
2
1
7-24
7.4.2
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Timers are processed.

OB has been programmed.
Interpret DB12

Processing OB21
counters, and flags.
Interrupts are not processed.
The red and green LEDs light.

the non-retentive timers,

Scan monitoring is not activated.

was previously in the RUN mode.
Clear the process image I/O table,

to RUN; Programmer command RUN
Operating mode switch set from STOP
For CPU 103 version 8MA03 and higher

directly to the RUN mode. See section 4.1.2.
Features of the start-up blocks (OB21, OB22):
OB21 is called up for a manual cold restart.
START-UP Program Processing
Process OB1
Read in the PII
Read out the PIQ

Enable the outputs

Figure 7-12. Setting the Start-Up Procedure

Interpret DB12
Processing OB22
Power recovery1
aaaaaaaaaaaaaaaaaaaaaaaaaaaa counters, and flags.

the non-retentive timers,
Clear the process image I/O table,
the battery was not inserted, you must insert a memory submodule containing the valid blocks.
If you have programmed start-up OBs, they are processed before the cyclic program processing
occurs. The start-up OB program is appropriate, for example, for a one-time presetting of certain
aaaaaaaaaaaaaaaaaaaaaaaaaaaa UP
Cold
RUN
system data. If the appropriate start-up OB is not programmed, the programmable controller jumps
restart
routine
In the START-UP mode, the operating system of the CPU automatically calls up a start-up OB if the
START-
OB22 is called up for an automatic cold start after power recovery if the programmable controller
This is the procedure if the programmable controller was in the RUN mode when the power went off,
if the mode switch was still on RUN when the power was restored, and if the battery was inserted. If
EWA 4NEB 812 6120-02b

S5-100U
The following two examples show you how you can program a start-up OB.
Example 1: Programming OB22
Example STL Explanation
After power recovery, you AN T 1 A 5 s time value is loaded in

want to be sure that the power L KT 500.0 ACCU 1.
supply voltage for the I/Os has SP T 1 Timer 1 is started.
attained its rated value before F001: A T 1 After 5 s, cyclic program
the cyclic program is pro- JC =F001 processing begins in OB1.
cessed. A time loop is there- BE
fore programmed in OB22.
Example 2: Programming OB21
After the operating mode L KH 0 Value “0” is loaded in

switch causes a cold restart, T FW 0 ACCU 1 and transferred into
flag bytes 0 to 9 are preset T FW 2 flag words 0, 2, 4, 6, and 8.
with “0”. The other flag bytes T FW 4
are retained since they contain T FW 6
important machine functions. T FW 8
BE
EWA 4NEB 812 6120-02b 7-25

7.4.3 Cyclic Program Processing
The operating system calls OB1 cyclically. If you want to

have structured programming, you should program only jump
operations (block calls) in OB1. The blocks you call up, PBs, Cycle trigger
FBs, and SBs, should contain completed functional units in
order to provide a clearer overview.
A time monitor is triggered at the beginning of each program
processing cycle (scan cycle trigger). If the scan cycle time
trigger is not reset within the scan monitoring time, the CPU
automatically enters the STOP mode and disables the output Control
modules. program
You can set the monitoring time (see Table 6-6). You could
have a control program that is so complex that it cannot be
processed within 300 ms. With CPU 103 and higher, you can
use OB31 (see section 9.3) to lengthen (retrigger) the scan
monitoring time in the control program. Transfer
Monitoring time is exceeded, for example, if you program data
endless loops or if there is a malfunction in the programmable
controller.
Figure 7-13. Cyclic Program Processing
7-26 EWA 4NEB 812 6120-02b

Response Time
Response time tR is defined as the time between a change in the input signal and the subsequent
change in the output signal.
Prerequisites for the following information:

• No interrupts are running.
• The programmer interface is not in use. (The load is very dependent on the function.)
The response time is influenced by the following factors:

• The input module delay (see chapter 14)
• The program processing time (see Appendix A)
• The data cycle times (number of data bits x 25 µs - a bus configuration of 256 data bits results
in a data cycle time of approximately 8 ms)
• The operating system run time (up to 3% of the program cycle)
• The processing of the internal timers T 0 to T15 for CPU 100
T 0 to T31 for CPU 102
T 0 to T127 for CPU 103
Calculating the maximum response time tRm:

• With tG= 2 x program processing time + 3 x data cycle time + 3 x operating system run time
+ delay time of the input modules
• Maximum processing time of the internal timers tTm
tTm = number of processed timers x 32 µs (number of processed timers for CPU 100: 16
number of processed timers for CPU 102: 32
number of processed timers for CPU 103: 128)
tTm = 103 µs for CPU 103 version 8MA03
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
a
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aa
tTm
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a
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a
a
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a
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a
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aa
tRm = tG ( 1 + ) + tTm.
a
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
aa
10 ms
a
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a
a
aa
a
a
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a
During the transition from STOP to RUN, there is a one-time increase in the response time to about
200 ms.
Response
a
a
a
a
aaaaa
a
a
a
a
a
a
aa
a
a
a
a
Input
aa
a
a
a
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
a
module
delay
1
I 0.0
0
1
Q 1.0 0
Time
Data Program processing Data

cycle A I 0.0 = Q 1.0 cycle
Figure 7-14. Calculating the Response Time
EWA 4NEB 812 6120-02b 7-27

7.4.4 Time-Controlled Program Processing, for CPU 103 Version 8MA02

and Higher
Time-controlled program processing can be defined as a (periodic) time signal causing the CPU to
interrupt cyclic program processing to process a specific program. Once this program has been
processed, the CPU returns to the interruption point in the cyclic program and resumes processing.
Prerequisites for time-controlled program processing

Time-controlled program processing is possible only if the following prerequisites have been fulfilled.
• Organization block OB13 must be programmed.
• The programmable controller must be set to Power ON and the RUN mode must be selected.
• Interrupt processing may not be disabled (by the IA - disable interrupt - operation). See
section 8.2.8.
• The OB13 call-up interval is set to > 0.
OB13 is available for time-controlled program processing when using CPU 103 version 8MA02 and
higher. You determine the intervals at which you want the operating system to process OB13. It is
also possible to change the call-up intervals during cyclic program processing. Cyclical program
processing continues if OB13 is not programmed.
• Setting the call-up interval

You can set the call-up interval in DB1 using the TFB: block ID. You can set the times from
10 ms to 655,530 ms (use 10-ms increments). The default for OB13 is 100 ms.
• Interrupt possibilities
OB13 can interrupt the cyclical program after any STEP 5 statement. After the current STEP 5
statement is executed, you can use process interrupts to interrupt time-controlled program
processing. After interrupt processing, time-controlled program processing continues until it is
finished.
OB13 cannot interrupt the operating system, the process interrupts (OB2), or the current time-
controlled program processing (OB13).
• Disabling/enabling the call-up
Use the IA command to disable, and the RA command to enable the OB13 call-up.
A call-up request can be stored during a call-up disable. The default is RA. See section 8.2.8.
7-28 EWA 4NEB 812 6120-02b

• Saving data
If a time-controlled OB uses scratchpad flags that are also used in the cyclic control program,
then these scratchpad flags must be saved in a data block during the processing of the time-
controlled OB.
Note
When processing OB13, you may not exceed the block nesting depth of 16 levels.
When processing with CPU 103 (6ES5 103-8MA03), you may not exceed the block
nesting depth of 32 levels.
• Reading out the interrupt PII

When OB13 is called, the signals of the input modules are read into the interrupt PII. The
interrupt PII can be scanned in OB13 by means of the L PY 0 to 127 or L PW 0 to 126 load
operations (load byte x or word x of the interrupt PII in ACCU 1). There is an interrupt input data
cycle prior to time-controlled program processing. The interrupt data cycle time lengthens the
response time of the cyclical program processing.
If other operands are entered, the CPU goes in the STOP mode (see section 5.2.1). This error
is indicated in ISTACK by the “NNN” error message.
• Writing to the interrupt PIQ
Data to the external I/Os can be written to the interrupt PIQ by means of transfer operations
T PY 0 to 127 or T PW 0 to 126. The “normal” PIQ is written to simultaneously. After OB13
has finished, the data that has been transferred to the interrupt PIQ is output to the peripheral
I/Os in an interrupt output data cycle (before “normal” program processing). The interrupt data
cycle time lengthens the response time of the cyclical program processing.
Note
The interrupt output data cycle is executed only if the interrupt PIQ has been written to.
7.4.5 Interrupt-Driven Program Processing, for CPU 103 Version 8MA02

and Higher
For CPU 103 version 8MA02 and higher, interrupt-driven program processing is initiated when a
signal from the process causes the CPU to interrupt the cyclic or time-controlled program
processing and execute a specific program. When this program has been scanned, the CPU returns
to the point of interruption in the cyclic or time-controlled program and resumes scanning at that
point. Chapter 10 contains detailed information about interrupt processing.
EWA 4NEB 812 6120-02b 7-29

7.5 Processing Blocks

Earlier sections in this chapter described how to use blocks. Chapter 8 introduces all of the
operations required to work with blocks. You can change any block that has been programmed.
The following sections will deal only briefly with the different ways you can change blocks. Refer to
the operator‘s guide for your programmer for more detailed information on changing blocks.
7.5.1 Changing Programs

You can use the following programmer functions to make program changes with any block type.
• INPUT
• OUTPUT
• STATUS (see section 4.5)
These three programmer functions make it possible for you to make the following types of changes:
• Delete, insert, or overwrite statements.
• Insert or delete segments.
7.5.2 Changing Blocks

Program changes refer to changing the contents of a block. You can also delete or overwrite a
complete block. When you delete a block, it is not deleted from the program memory but simply
becomes invalid. You cannot enter new information in the memory location of an invalid block. This
may cause new blocks not to be accepted. If a new block is not accepted, then the PG transmits
the “no space available” error message. You can make more space by compressing the
programmable controller memory.
7.5.3 Compressing the Program Memory

Figure 7-15 illustrates what takes place in the program memory during a COMPRESS operation.
Internally, one block is shifted per cycle.
Program memory Program memory

RAM RAM
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Valid
blocks
Invalid
Compress Input
possible
Input not
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaa
possible
PB
PB Available
memory space
Figure 7-15. Compressing the Program Memory
7-30 EWA 4NEB 812 6120-02b

You can use the COMPRESS programmer function to clean up internal program memory.
If there is a power failure during the compress operation when a block is being shifted and block
shifting can not be completed, the CPU remains in the STOP mode. The “NINEU” error message
appears. Both the“BSTSCH” and the “SCHTAE” bits are set in the ISTACK.
Remedy: Overall reset.
7.6 Number Representation
With STEP 5 you can work with numbers in the following five representations:
• Decimal numbers from -32768 to +32767 (KF)
• Hexadecimal numbers from 0000 to FFFF (KH)
• BCD-coded numbers (4 tetrads) from 0000 to 9999
• Bit patterns (KM)
• Constant byte (two-byte representation) from 0 to 255 for each byte (KY)
Number Formats
The programmable controller is designed to process binary signal states (only “0” and “1”).
Therefore the programmable controller represents all numbers internally as 16-bit binary numbers or
as bit patterns.
Four bits can be combined into a tetrad (BCD) to shorten the binary code representation. The value
of these tetrads can be displayed in hexadecimal representation.
Example: 16-bit binary coded number and shortened hexadecimal representation
Word no. n
Byte no. n (high byte) n+ 1 (low byte)
Bit no. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Binary code representation 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1

Meaning 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
aaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
Hexadecimal representation 1 F 6 3
Figure 7-16. Bit Assignment of a 16-Bit Fixed-Point Binary Number
EWA 4NEB 812 6120-02b 7-31

You can work with binary-coded decimals to program timers and counters in the decimal system.
BCD tetrads are defined in the range of 0 to 9.
Example: 12-bit timer or counter value in BCD and decimal formats
Word No. n
Byte No. n (high byte) n+ 1 (low byte)
Bit No. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BCD No. 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1
Meaning 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20

a
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aaaaa
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aaaaa
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Decimal format 0 9 3 1
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Figure 7-17. BCD and Decimal Formats
Table 7-6. Comparison of Number Formats
Binary Decimal BCD Hexadecimal
0000 0 0000 0000 0

0001 1 0000 0001 1
0010 2 0000 0010 2
0011 3 0000 0011 3
0100 4 0000 0100 4
0101 5 0000 0101 5
0110 6 0000 0110 6
0111 7 0000 0111 7
1000 8 0000 1000 8
1001 9 0000 1001 9
1010 10 0001 0000 A
1011 11 0001 0001 B
1100 12 0001 0010 C
1101 13 0001 0011 D
1110 14 0001 0100 E
1111 15 0001 0101 F
7-32 EWA 4NEB 812 6120-02b

You can use the “LC” operation to convert a binary number to a BCD number for timers and
counters.
Example: Comparing a count in counter 1 with decimal number 499
The comparison value must be stored in the accunulator by means of a load

operation. Use the “LKF + 499” statement so that you do not have to convert the
value 499 into other numerical systems (binary or hexadecimal) for the input. The
number 1F3H is then stored in the accumulator.
The current count must also be loaded into the accumulator.
Incorrect Method: Correct Method:

If you use the “LCC1” The formats are identical if the
statement, the current count will “LC1” statement is input.
be loaded in BCD. The “!=F”
comparison operation results in
a “not equal to” condition since
the comparison uses different
formats.
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High Byte Low Byte
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0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1
L KF+499 L KF+499
0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1
LC C 1 L C1
EWA 4NEB 812 6120-02b 7-33

EWA 4NEB 812 6120-02b

8 STEP 5 Operations
8.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1

8.1.1 Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8.1.2 Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8.1.3 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10
8.1.4 Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8.1.5 Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 25
8.1.6 Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30
8.1.7 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 31
8.1.8 Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 33
8.1.9 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 38
8.2 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 39

8.2.1 Load Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . 8 - 40
8.2.2 Enable Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . 8 - 41
8.2.3 Bit Test Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . 8 - 42
8.2.4 Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 44
8.2.5 Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 48
8.2.6 Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 50
8.2.7 Decrement/Increment, for CPU 103 and Higher . . . . . . . . . . . . . . 8 - 52
8.2.8 Disable/Enable Interrupt, for CPU 103 Version 8MA02 and Higher . 8 - 53
8.2.9 “DO” Operation, for CPU 103 and Higher .................. 8 - 54
8.2.10 Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 56
8.2.11 Substitution Operations, for CPU 103 and Higher . . . . . . . . . . . . . 8 - 58
8.3 System Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . 8 - 64

8.3.1 Set Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.2 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.3 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 67
8.3.4 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 68
8.4 Condition Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 69
8.5 Sample Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71

8.5.1 Momentary-Contact Relay/Edge Evaluation . . . . . . . . . . . . . . . . . 8 - 71
8.5.2 Binary Scaler/Binary Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71
8.5.3 Clock/Clock-Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 73
EWA 4NEB 812 6120-02b

Figures
8-1 Accumulator Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10

8-2 Execution of the Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12
8-3 Transferring a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12
8-4 Output of the Current Time (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 18
8-5 Outputting the Current Counter Status (Example) . . . . . . . . . . . . . . . . . . 8 - 27
8-6 Executing a “DO” Operation ................................ 8 - 55
Tables
Basic Operations
8-1 Overview of Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8-2 Overview of the Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8-3 Overview of Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . 8 - 11
8-4 Overview of Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8-5 Overview of Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 25
8-6 Overview of Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30
8-7 Overview of Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 31
8-8 Overview of Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 33
8-9 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 38
Supplementary Operations
8-10 Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 40
8-11 Enable Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 41
8-12 Overview of Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 42
8-13 Effect of “TB” and “TBN” on the RLO ......................... 8 - 42
8-14 Overview of Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 44
8-15 Overview of Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 48
8-16 Overview of Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 50
8-17 Decrement/Increment Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 52
8-18 Disable/Enable Interrupt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 53
8-19 Overview of the “DO” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 54
8-20 Overview of Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 56
8-21 Overview of Binary Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 58
8-22 Overview of Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 59
8-24 Overview of Timer and Counter Operations . . . . . . . . . . . . . . . . . . . . . . 8 - 61
8-25 “DO” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 63
8-26 Overview of Set Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
System Operations
8-28 Overview of the “ADD” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 67
8-29 The “TAK” and “STS” Operations ............................ 8 - 68
8-30 Condition Code Settings for Comparison Operations . . . . . . . . . . . . . . . . 8 - 69
8-31 Condition Code Settings for Fixed-Point Arithmetic Operations . . . . . . . . . 8 - 69
8-32 Condition Code Settings for Digital Logic Operations . . . . . . . . . . . . . . . 8 - 70
8-33 Condition Code Settings for Shift Operations . . . . . . . . . . . . . . . . . . . . . 8 - 70
8-34 Condition Code Settings for Conversion Operations . . . . . . . . . . . . . . . . 8 - 70
EWA 4NEB 812 6120-02b

S5-100U STEP 5 Operations
8 STEP 5 Operations
The STEP 5 programming language has the following three operation types:
• Basic Operations include functions that can be executed in organization, program, sequence,
and function blocks. Except for the addition (+F), subtraction (-F), and organizational ope-
rations, the basic operations can be input and output in the statement list (STL), control system
flowchart (CSF), or ladder diagram (LAD) methods of representation.
• Supplementary Operations include complex functions such as substitution statements, test
functions, and shift and conversion operations. They can be input and output in STL form only.
• System Operations access the operating system directly. Only an experienced programmer
should use them. System operations can be input and output in STL form only.
8.1 Basic Operations

Sections 8.1.1 through 8.1.9 use examples to describe the basic operations.
EWA 4NEB 812 6120-02b 8-1

STEP 5 Operations S5-100U
8.1.1 Boolean Logic Operations
Table 8-1 provides an overview of Boolean logic operations. Examples follow the table.
Table 8-1. Overview of Boolean Logic Operations

Operation Operand Meaning
O Combine AND operations through logic OR

Combine the result of the next AND logic operation (RLO) with the previous
RLO through logic OR.
A( Combine expression enclosed in parentheses through logic AND

Combine the RLO of the expression enclosed in parentheses with the
previous RLO through logic AND.
O( Combine expression enclosed in parentheses through logic OR

Combine the RLO of the expression enclosed in parentheses with the
previous RLO through logic OR.
) Close parenthesis
Conclude the expression enclosed in parentheses.
A Scan operand for “1” and combine with RLO through logic AND
The result is “1” when the operand in question carries signal state “1”.
Otherwise the scan results in “0”. Combine this result with the RLO in the
processor through logic AND1.
O Scan operand for “1” and combine with RLO through logic OR
The result is “1” when the operand in question has signal state “1”.
processor through logic OR1.
AN Scan operand for “0” and combine with RLO through logic AND
processor through logic AND1.
ON Scan operand for “0” and combine with RLO through logic OR
processor through logic OR1.
ID Parameter CPU 100 CPU 102 CPU 103

I 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
Q 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
F 0.0 to 127.7 0.0 to 127.7 0.0 to 255.7
T 0 to 15 0 to 31 0 to 127
C 0 to 15 0 to 31 0 to 127
1 If the scan follows an RLO limiting operation directly (first scan), the scan result is reloaded as a new
RLO.
8-2 EWA 4NEB 812 6120-02b

AND Operation
The AND operation scans to see if various conditions are satisfied simultaneously.
Example Circuit Diagram
Output Q 1.0 is “1” when all three inputs are “1”. I 0. 0

The output is “0” if at least one input is “0”.
The number of scans and the sequence of the logic I 0.1
statements are at random.
I 0.2
Q 1.0
STL CSF LAD

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OR Operation
The OR operation scans to see if one of two (or more) conditions has been satisfied.
Output Q 1.0 is “1” when at least one of the inputs is “1”.

Output Q 1.0 is “0” when all inputs are “0” simultaneously. I 0.0 I 0.1 I 0.2
The number of scans and the sequence of their
programming are optional.
Q 1.0
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EWA 4NEB 812 6120-02b 8-3

8-4
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STEP 5 Operations
has been satisfied.

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Output Q 1.0 is “1” when at least one AND condition has
Output Q 1.0 is “0” when neither of the two AND conditions
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EWA 4NEB 812 6120-02b

S5-100U
=
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EWA 4NEB 812 6120-02b

has been satisfied:
• Input I 0.0 is “1”.
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8-5
STEP 5 Operations
OR before AND Operation
Output Q 1.0 is “1” when both OR conditions have been

satisfied. I 0.0 I 0.1
Output Q 1.0 is “0” when at least one OR condition has not
been satisfied.
I 0.2 I 0.3
Q 1.0
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8-6 EWA 4NEB 812 6120-02b

8.1.2 Set/Reset Operations
Set/reset operations store the result of logic operation (RLO) formed in the processor. The stored
RLO represents the signal state of the addressed operand. Storage can be dynamic (assignment)
or static (set and reset). Table 8-2 provides an overview of the set/reset operations. Examples
follow the table.
Table 8-2. Overview of the Set/Reset Operations

S Set
The first time the program is scanned with RLO = “1”, signal state
“1” is assigned to the addressed operand. An RLO change does
not affect this status.
R Reset
The first time the program is scanned with RLO = “1”, signal state
“0” is assigned to the addressed operand. An RLO change does
not affect this status.
= Assign
Every time the program is scanned, the current RLO is assigned to
the addressed operand.
I 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
Q 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
F 0.0 to 127.7 0.0 to 127.7 0.0 to 255.7
EWA 4NEB 812 6120-02b 8-7

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STEP 5 Operations
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R
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CSF
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Q 1.0
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Q
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In this example, resetting output Q 1.0 has priority.
aaa
signal (input I 0.0) are applied at the same time, the
output Q 1.0 is maintained, i.e., the signal is latched.
When the “SET” signal (input I 0.1) and the “RESET”
aa
aaa
aaaaaaaaaaaaa
aaa
A I 0.0) is in effect during processing of the rest of the
aaa aaaaaaaa
A “1” at input I 0.0 resets the flip-flop (signal state “0”).
aaa
the signal state at input I 0.1 changes to “0”, the state of
aaa aaaaaaaa
Flip-Flop for a Latching Signal Output (reset dominant)
aaa
A “1” at input I 0.1 sets flip-flop Q 1.0 (signal state “1”). If
aaa aaaaaaaa
scanning operation that was programmed last (in this case
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I 0.0
I 0.1
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S
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I 0.0
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Q 1.0
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Q
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LAD
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Circuit Diagram
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Q 1.0
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a aaaa
with a screen. During programming in LAD and CSF, such “NOP 0” operations are allotted
I 0.1
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“NOP 0” is necessary if the program is to be represented in LAD or CSF form on programmers
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a
EWA 4NEB 812 6120-02b

aa
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aaaaaaaaa aaaaaaaaaaaaaa
S5-100U
RS Flip-Flop with Flags (set dominant)

A “1” at input I 0.0 sets flip-flop F 1.7 (signal state “1”).
If the signal state at input I 0.0 changes to “0”, the state of
flag F 1.7 is maintained, i.e., the signal is latched.
A “1” at input 0.1 resets the flip-flop (signal state “0”). If I 0.0 I 0.1
the signal state at input I 0.1 changes to “0”, flag F 1.7
retains signal state “0”.
If both inputs have a “1” signal state, the flip-flop is set (set
dominant).
The signal state of the flag is scanned and transferred to F 1.7
output Q 1.0.
STL CSF LAD
aaa
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A I 0.1 F 1.7 I 0.1 F 1.7
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A I 0.0 Q 1.0
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S F 1.7
S Q
A F 1.7 I 0.0 S Q Q 1.0
= Q 1.0
EWA 4NEB 812 6120-02b 8-9

8.1.3 Load and Transfer Operations
Use load and transfer operations to do the following tasks.

• Exchange information between various operand areas
• Prepare time and count values for further processing
• Load constants for program processing
Information flows indirectly via accumulators (ACCU 1 and ACCU 2). The accumulators are special
registers in the programmable controller that serve as temporary storage. They are each 16 bits
long. The accumulators are structured as shown in Figure 8-1.
ACCU 2 ACCU 1
15 8 7 0 15 8 7 0
High byte Low byte High byte Low byte
Figure 8-1. Accumulator Structure
You can load and transfer permissible operands in bytes or words. For exchange in bytes, infor-
mation is stored right-justified, i.e., in the low byte.
The remaining bits are set to zero.
You can use various operations to process the information in the two accumulators.
Load and transfer operations are executed independently of condition codes. Execution of these
operations does not affect the condition codes.
You can program load and transfer operations graphically only in combination with timer or counter
operations; otherwise you can represent them only in STL form.
Table 8-3 provides an overview of the load and transfer operations. Examples follow the table.
8-10 EWA 4NEB 812 6120-02b

Table 8-3. Overview of Load and Transfer Operations

Opera-
Operand Meaning
tion
L Load
The operand contents are copied into ACCU 1 regardless of the RLO.
The RLO is not affected.
T Transfer
The contents of ACCU 1 are assigned to an operand regardless of the
RLO.
ID Parameter
CPU 100 CPU 102 CPU 103
IB 0 to 127 0 to 127 0 to 127
IW 0 to 126 0 to 126 0 to 126
QB 0 to 127 0 to 127 0 to 127
QW 0 to 126 0 to 126 0 to 126
FY 0 to 127 0 to 127 0 to 255
FW 0 to 126 0 to 126 0 to 254
DR 0 to 255 0 to 255 0 to 255
DL 0 to 255 0 to 255 0 to 255
DW 0 to 255 0 to 255 0 to 255
T1 0 to 15 0 to 31 0 to 127
C1 0 to 15 0 to 31 0 to 127
PY ----- ----- 0 to 127
PW ----- ----- 0 to 126
KM1 random bit random bit random bit
pattern (16 bits) pattern (16 bits) pattern (16 bits)
KH1 0 to FFFF 0 to FFFF 0 to FFFF
KF1 -32768 to+32767 -32768 to +32767 -32768 to +32767
KY1 0 to 255 0 to 255 0 to 255
per byte per byte per byte
KB1 0 to 255 0 to 255 0 to 255
KS1 any 2 any 2 any 2
alphanumeric alphanumeric alphanumeric
characters characters characters
KT1 0.0 to 999.3 0.0 to 999.3 0.0 to 999.3
KC1 0 to 999 0 to 999 0 to 999
LD Load in BCD
Binary times and counts are loaded into ACCU 1 in BCD code regardless
of the RLO.
T 0 to 15 0 to 31 0 to 127
C 0 to 15 0 to 31 0 to 127
1 These operands cannot be used for transfer.
EWA 4NEB 812 6120-02b 8-11

Load Operation
During loading, information is copied from a memory area, e.g., from the PII, into ACCU 1.
The previous contents of ACCU 1 are shifted to ACCU 2.
The original contents of ACCU 2 are lost.
Example: Two consecutive bytes (IB7 and IB8) are loaded from the PII into the accumulator.
Loading does not change the PII (see Figure 8-2).
Lost Information
information ACCU 2 ACCU 1 from the PII
Byte d Byte c Byte b Byte a
L IB7
Byte d Byte c Byte b Byte a 0 IB7 IB7
L IB8
Byte b Byte a 0 IB7 0 IB8 IB
Figure 8-2. Execution of the Load Operation
Transfer Operation
During transfer, information from ACCU 1 is copied into the addressed memory area, e.g., into the
PIQ.
This transfer does not affect the contents of ACCU 1.
Example: Figure 8-3 shows how byte a, the low byte in ACCU 1, is transferred to QB5.
ACCU 2 ACCU 1 Information Lost

in the PIQ information
Byte d Byte c Byte b Byte a
T QB5
Previous value
Byte d Byte c Byte b Byte a Byte a of QB5
Figure 8-3. Transferring a Byte
8-12 EWA 4NEB 812 6120-02b

Loading and Transferring a Time (See also Timer and Counter Operations)
Example Representation
During graphic input, QW62 is assigned to output BI of
a timer. The programmer automatically stores the
corresponding load and transfer operation in the
control program. Thus the contents of the memory lo-
cation addressed with T 10 are loaded into ACCU 1. T 10 Load
Afterwards, the contents of the accumulator are
transferred to the process image addressed with
QW62. In this example, you can see timer T 10 at
QW62 in binary code.
Outputs BI and DE are digital outputs. The time at Transfer
QW62
output BI is in binary code. The time at output DE is
in BCD code with time base.
STL CSF LAD
A I 0.0 I 0.0 T 10
L IW 22 T 10 1
SP T 10 I 0.0 1
NOP 0
IW22 TV IW22
L T 10 BI QW62 TV
BI QW62
T QW 62 DE DE
R Q R Q
NOP 0
NOP 0
EWA 4NEB 812 6120-02b 8-13

Loading and Transferring a Time (Coded)
The contents of the memory location addressed with
T 10 are loaded into the accumulator in BCD code.
Then a transfer operation transfers the accumulator
T 10
contents to the process image memory location Load
addressed by QW50. A coding operation is possible

only indirectly for the graphic representation forms
LAD and CSF by assigning an address to output DE of
a timer or counter location. However, this operation Transfer
can be entered with a separate statement with STL. QW50
STL CSF LAD
A I 0.0 T 10
T 10 I0.0
L IW 22
1
SP T 10 I 0.0 1
NOP 0
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IW22 TV
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NOP 0
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BI IW22 TV
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LD T 10 DE QW50 BI
R Q DE QW50
T QW 50 R Q
NOP 0
8-14 EWA 4NEB 812 6120-02b

8.1.4 Timer Operations
The program uses timer operations to implement and monitor chronological sequences. Table 8-4
provides an overview of timer operations. Examples follow the table.
Table 8-4. Overview of Timer Operations

SP Pulse Timer
The timer is started on the leading edge of the RLO.
When the RLO is “0”, the timer is set to “0”.
Scans result in signal state “1” as long as the timer is running.
SE Extended Pulse Timer
When the RLO is “0”, the timer is not affected.
Scans result in signal state “1” as long as the timer is running.
SD On-Delay Timer
When the RLO is “0”, the timer is set to “0”.
Scans result in signal state “1” when the timer has run out and the
RLO is still pending at the input.
SS Stored On-Delay Timer
Scans result in signal state “1” when the timer has run out.
The signal state becomes “0” when the timer is reset with the “R”
operation.
SF Off-Delay Timer
The timer is started on the trailing edge of the RLO.
When the RLO is “1”, the timer is set to its initial value.
Scans result in signal state ”1” as long as the RLO at the input is
“1” or the timer is still running.
R Reset Timer
The timer is reset to its initial value as long as the RLO is “1”.
Scans result in signal state “0” as long as the timer is reset or has
not been started yet.
T 0 to 15 0 to 31 0 to 127
EWA 4NEB 812 6120-02b 8-15

Loading a Time
Timer operations call internal timers.
When a timer operation is started, the word in ACCU 1 is used as a time value. You must therefore
first specify time values in the accumulator.
You can load a timer with any of the following data types:
KT constant time value

or
DW data word
IW input word These data types must be
QW output word in BCD code.
FW flag word
Loading a Constant Time Value

The following example shows how you can load a time value of 40 s.
Operation
Operand
L KT 40.2
Coded time base (0 to 3)
Time (0 to 999)
Key for Time Base
Base 0 1 2 3
Factor 0.01 s 0.1 s 1s 10 s
8-16 EWA 4NEB 812 6120-02b

Example: KT 40.2 corresponds to 40 x 1 s.
Tolerance:
The time tolerance is equivalent to the time base.
Examples Operand Time Interval
Possible KT 400.1 400 x 0.1 s - 0.1 s 39.9 s to 40 s

settings for
KT 40.2 40 x 1s - 1s 39 s to 40 s
the time
40 s KT 4.3 4 x 10 s - 10 s 30 s to 40 s
Note
Always use the smallest time base possible.
Loading a Time as an Input, Output, Flag, or Data Word

Load Statement: L DW 2
The time 638 s is stored in data word DW2 in BCD code.

Bits 14 and 15 are insignificant for the time value.
15 11 0 Bit
1 0 0 1 1 0 0 0 1 1 1 0 0 0 DW2
Three-digit time value

(in BCD code)
Time base
Key for Time Base:
Base 00 01 10 11
Factor 0.01 s 0.1 s 1s 10 s
You can also use the control program to write to data word DW2.
Example: Store the value 270 x 100 ms in data word DW2 of data block DB3.
C DB 3
L KT 270.1
T DW2
EWA 4NEB 812 6120-02b 8-17

Output of the Current Time 1
You can use a load operation to put the current time into ACCU 1 and process it further from there
(see Figure 8-4).
Use the “Load in BCD” operation for digital display output.
Current time in T1
L T1 LD T1
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aaaaaaaaaaaaaa
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aaaaaaaaaaaaaa
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ACCU 1
Binary time value Time Three-digit time value

base in BCD code
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indicates bit positions occupied by “0”.

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Figure 8-4. Output of the Current Time (Example)
1 The current time is the time value in the addressed timer.
8-18 EWA 4NEB 812 6120-02b

Starting a timer
In the programmable controller, timers run asynchronously to program scanning. The time that has
been set can run out during a program scanning cycle. It is evaluated by the next time scan. In the
worst case, an entire program scanning cycle can go by before this evaluation. Consequently,
timers should not activate themselves.
Example:
Schematic Representation Explanation
Program Signal from The schematic shows the “nth + 1”

timer 17 processing cycle since timer T 17* was
0 1 started. Although the timer ran out
shortly after the statement “= Q 1.0”,
output Q 1.0 remains set. The change is
not considered until the next program
scanning cycle.
L KT 100.0
SP T 17
1s - n · tp
A T 17
= Q 1.0
n: number of program scanning cycles

tp: program scan time * KT 100.0 is equal to 1 s.
The following rules apply to timers:

• Except for “Reset timer”, all timer operations are started only when there is an edge change.
The RLO alternates between “0” and “1”.
• After being started, the loaded time is decremented in units corresponding to the time base until
it reaches zero.
• If there is an edge change while the timer is running, the timer is reset to its initial value and
restarted.
• The signal state of a timer can be scanned with Boolean logic operations.
EWA 4NEB 812 6120-02b 8-19

Pulse
Example:
Output Q 1.0 is set when the signal state at input I 0.0 changes from “0” to “1”.
However, the output should not remain set longer than 5 s.
Timing Diagram Circuit Diagram
Signal states
I 0.0
1
I 0.0
0
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Time in s
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Time relay with transitional
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NO contact
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STL CSF LAD
A I 0.0
T1 T1
L KT 500.0 I 0.0
SP T 1 I 0.0 1 1
NOP 0 KT 500.0 TV BI KT 500.0 TV BI
NOP 0 DE DE
NOP 0
R Q Q 1.0 R Q
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= Q 1.0
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Note
The time tolerance is equivalent to the time base. Always use the smallest time base
possible.
8-20 EWA 4NEB 812 6120-02b

=
A
L
A
SE
NOP 0
NOP 0
NOP 0
0
1
0
1
S5-100U
Example:
Q
T
T
I
IW
STL
t
2
2
Extended pulse
16
1.0
0.0
indicated in IW16.
Signal states
EWA 4NEB 812 6120-02b

I 0.0
IW16

1
t
R
TV
Timing Diagram
T2
V
CSF
BI
Q
DE
I 0.0
Q 1.0
Time
Q 1.0
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T2
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I 0.0
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1
R
aaaaaaa aaaaa
TV
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T2
LAD
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V
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BI
Q
DE
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Circuit Diagram
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Output Q 1.0 is set for a specific time when the signal at input I 0.0 changes to “1”. The time is
Q 1.0
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T 2: Time relay with pulse shaper
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STEP 5 Operations
8-21
On-Delay
Example:
Output Q 1.0 is set 9 s after input I 0.0 and remains set as long as the input carries signal “1”.
Signal states
I 0.0
1
0 I 0.0
1
Q 1.0
0
T3
Time in s
9 9
Q 1.0
STL CSF LAD
A I 0.0
T3 T3
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T 0 T 0
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SD T 3 I 0.0 a
NOP 0 KT 900.0 TV BI KT 900.0 TV BI
NOP 0
DE DE
NOP 0
A T 3 R Q Q 1.0 R Q
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8-22 EWA 4NEB 812 6120-02b

=
A
R
A
L
A
SS
0
1
0
1
0
1
NOP 0
NOP 0
S5-100U
Example:
Q
T
T
I
T
I
KT
STL
5
4
4
4
Note
Signal states
1.0
0.1
0.0
500.0
EWA 4NEB 812 6120-02b

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Output Q 1.0 is set 5 s after I 0.0.
R
TV
Timing Diagram
T4
s
CSF
BI
Q
DE
in s
I 0.1
I 0.0
Q 1.0
Time
Q 1.0
The time tolerance is equivalent to the time base.

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KT 500.0
Further changes in the signal state at input I 0.0 do not affect the output.
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Input I 0.1 resets timer T 4 to its initial value and sets output Q 1.0 to zero.
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H 1: Auxiliary relay
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LAD
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I 0.0
BI
Q
DE
I 0.1
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Circuit Diagram
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STEP 5 Operations
8-23
Off-Delay
Example:
When input I 0.0 is reset, output Q 1.0 is set to zero after a certain delay (t). The value in FW14
specifies the delay time.
Signal states
I 0.0
1
0 I 0.0
1
0 Q 1.0
Time in s T5
t t
Q 1.0
STL CSF LAD
A I 0.0 T5
T5
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L FW 14 I 0.0
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SF T 5 I 0.0 0 T 0 T
NOP 0 FW14 TV BI FW14 TV BI
NOP 0
DE DE
NOP 0
A T 5 R Q Q 1.0 R Q
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8-24 EWA 4NEB 812 6120-02b

8.1.5 Counter Operations
The programmable controller uses counter operations to handle counting jobs. Counters can count
up and down. The counting range is from 0 to 999 (three decades). Table 8-5 provides an
overview of the counter operations. Examples follow the table.
Table 8-5. Overview of Counter Operations

S Set Counter
The counter is set on the leading edge of the RLO.
R Reset Counter
The counter is set to zero as long as the RLO is “1”.
CU Count Up
The count is incremented by 1 on the leading edge of the RLO.
When the RLO is “0”, the count is not affected.
CD Count Down
The count is decremented by 1 on the leading edge of the RLO.
When the RLO is “0”, the count is not affected.

C 0 to 15 0 to 31 0 to 127
Loading a Count
Counter operations call internal counters.
When a counter is set, the word in ACCU 1 is used as a count. You must therefore first store
counts in the accumulator.
You can load a count with any of the following data types:
KC constant count
or
DW data word
IW input word The data for these words must
QW output word be in BCD code.
FW flag word
EWA 4NEB 812 6120-02b 8-25

Loading a Constant Count

The following example shows how the count 38 is loaded.
Operation
Operand
L KC 38
Count (0 to 999)
Loading a Count as an Input, Output, Flag, or Data Word

Load statement: L DW 3
The count 410 is stored in data word DW3 in BCD code.

Bits 12 to 15 are insignificant for the count.
15 11 0 Bit
0 1 0 0 0 0 0 1 0 0 0 0 DW3
Three-digit count
(in BCD code)
Scanning the Counter

Use Boolean logic operations to scan the counter status (e.g., A Cx). As long as the count is not
zero, the scan result is signal state “1”.
8-26 EWA 4NEB 812 6120-02b

Outputting the Current Counter Status

You can use a load operation to put the current counter status into ACCU 1 and process it further
from there. The “Load in BCD” operation outputs a digital display (see Figure 8-5).
Current Counter Status in C2
L C2 LD C2
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ACCU 1
Binary count Three-digit count

in BCD code
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indicates bit positions occupied by “0”.

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Figure 8-5. Outputting the Current Counter Status (Example)
EWA 4NEB 812 6120-02b 8-27

Setting a Counter “S” and Counting Down “CD”
Example:
When input I 0.1 is switched on (set), counter 1 is set to count 7. Output Q 1.0 is now “1”.
Every time input I 0.0 is switched on (count down), the count is decremented by 1.
The output is set to “0” when the count is “0”.
I 0.1
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0 I 0.0
KC 7
1 I 0.1 R S CI
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Binary
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Time
Q 1.0 Count
S C1 S C1
STL CSF LAD

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CD C 1
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I 0.0 CD CD
NOP 0
A I 0.1 CU CU
I 0.1
L KC 7 S
I 0.1 S
S C 1 KC 7
KC 7 CV BI CV BI
NOP 0 DE
DE
NOP 0
R Q Q 1.0 R Q
NOP 0
A C 1 Q 1.0
= Q 1.0
8-28 EWA 4NEB 812 6120-02b

Resetting a Counter “R” and Counting Up “CU”
Example:
When input I 0.0 is switched on, the count in counter 1 is incremented by 1. As long as a second
input (I 0.1) is “1”, the count is reset to “0”.
The A C 1 operation results in signal state “1” at output Q 1.0 as long as the count is not “0”.

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CU C 1 I 0.0
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NOP 0
NOP 0 CD CD
NOP 0 S S
A I 0.1
CV BI CV BI
R C 1 DE DE
NOP 0 I 0.1
I 0.1 R Q Q 1.0 R Q
NOP 0
A C 1 Q 1.0
= Q 1.0
EWA 4NEB 812 6120-02b 8-29

8.1.6 Comparison Operations
Comparison operations compare the contents of the two accumulators. The comparison does not
change the accumulators' contents. Table 8-6 provides an overview of the comparison operations.
An example follows the table.
Table 8-6. Overview of Comparison Operations

! = F Compare for “equal to”

The contents of the two accumulators are interpreted as bit patterns
and scanned to see if they are equal.
> < F Compare for “not equal to”
The contents of the two accumulators are interpreted as bit patterns
and compared to see if they are not equal.
> F Compare for “greater than”
The contents of the two accumulators are interpreted as fixed-point
numbers. They are compared to see if the operand in ACCU 2 is
greater than the operand in ACCU 1.
> = F Compare for “greater than or equal to”

greater than or equal to the operand in ACCU 1.
< F Compare for “less than”
less than the operand in ACCU 1.
< = F Compare for “less than or equal to”

less than or equal to the operand in ACCU 1.
Processing Comparison Operations

To compare two operands, load them consecutively into the two accumulators. Execution of the
operations is independent of the RLO.
The result is binary and is available as RLO for further program processing. If the comparison is
satisfied, the RLO is “1”. Otherwise it is “0”.
Executing the comparison operations sets the condition codes (see section 8.4).
Note
When using comparison operations, make sure the operands have the same number
format.
8-30 EWA 4NEB 812 6120-02b

Example: The values of input bytes IB19 and IB20 are compared. If they are equal, output
Q 1.0 is set.
Circuit Diagram STL CSF/LAD
IB19 IB20
L IB 19
L IB 20
!=F C1 F
C1 C2 IB19
= Q 1.0
!=
=
IB20 C2 Q Q 1.0
Q 1.0
8.1.7 Arithmetic Operations
Arithmetic operations interpret the contents of the accumulators as fixed-point numbers and
manipulate them. The result is stored in ACCU 1. Table 8-7 provides an overview of the arithmetic
operations. An example follows the table.
Table 8-7. Overview of Arithmetic Operations

+F Addition
The contents of both accumulators are added.
-F Subtraction
The contents of ACCU 1 are subtracted from the contents of
ACCU 2.
CPU 102 and higher have integral function blocks for multiplication and division (see section 9.2).
EWA 4NEB 812 6120-02b 8-31

Processing an Arithmetic Operation

Before an arithmetic operation is executed, both operands must be loaded into the accumulators.
Note
When using arithmetic operations, make sure the operands have the same number
format.
Arithmetic operations are executed independently of the RLO. The result is available in ACCU 1 for
further processing. The contents of ACCU 2 are not changed.
These operations do not affect the RLO. The condition codes are set according to the results.
STL Explanation
L C 3 The value of counter 3 is loaded into ACCU 1.
L C 1 The value of counter 1 is loaded into ACCU 1. The previous contents of

ACCU 1 are shifted to ACCU 2.
+ F The contents of the two accumulators are interpreted as 16-bit fixed-point

numbers and added.
T QW12 The result, contents of ACCU 1, is transferred to output word QW12.
Numeric Example
15 0
876 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 ACCU 2
+ +F
668 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 ACCU 1
=
1544 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 ACCU 1
8-32 EWA 4NEB 812 6120-02b

8.1.8 Block Call Operations

Block call operations specify the sequence of a structured program. Table 8-8 provides an overview
of the block call operations. Examples follow the table.
Table 8-8. Overview of Block Call Operations

JU Jump unconditionally
Program scanning continues in a different block regardless of the
RLO.
JC Jump conditionally
Program scanning jumps to a different block when the RLO is “1”.
Otherwise program scanning continues in the same block.
The RLO is set to “1”.
OB 0 to 63 0 to 63 0 to 255
PB 0 to 63 0 to 63 0 to 255
FB 0 to 63 0 to 63 0 to 255
SB 0 to 255
C Call a data block

A data block is activated regardless of the RLO.
Program scanning is not interrupted.
G Generate and delete a data block*
An area is set up in the RAM to store data regardless of the RLO.
DB 2 to 63** 2 to 63** 2 to 255**
BE Block end
The current block is terminated regardless of the RLO.
Program scanning continues in the block in which the call originated.
The RLO is “carried along” but not affected. BE is always the last
statement in a block.
BEU Block end, unconditional

The current block is terminated regardless of the RLO.
The RLO is “carried along” but not affected.
BEC Block end, conditional
When the RLO is “1”, the current block is terminated.
During the block change, the RLO remains “1”.
If the RLO is “0”, the operation is not executed.
The RLO is set to “1” and linear program scanning continues.
* The length of the DB must be loaded into ACCU 1 before execution of the operation. A length of 0
makes the DB invalid.
** Data blocks DB0 and DB1 are reserved for special functions.
EWA 4NEB 812 6120-02b 8-33

Unconditional Block Call “JU”
One block is called within another block, regardless of conditions.
Example: A special function has been programmed in FB26. It is called at several locations in
the program, e.g., in PB63, and processed.
Program Sequence STL Explanation
.
PB63 FB26 . The “JU FB26” statement in program
. block PB63 calls function block FB26.
.
.
JU FB 26
.
JU FB26
Conditional Block Call “JC”

One block is called within another block when the previous condition has been satisfied
(RLO = “1”).
Example: A special function has been programmed in FB63. It is called and processed under
certain conditions, e.g., in PB10.
.
PB10 FB63 . The “JC FB63” statement in program
. block PB10 calls function block FB63
S F 1.0 if input I 0.0 is “1”.
A I 0.0 A I 0.0
JC FB 63
JC FB63 .
8-34 EWA 4NEB 812 6120-02b

Call a Data Block “C DB”

Data blocks are always called unconditionally. All data processed following the call refers to the data
block that has been called. This operation cannot generate new data blocks. Blocks that are called
must be programmed or created before program scanning.
Example: Program block PB3 needs information that has been programmed as data word DW1 in
data block DB10. Other data, e.g., the result of an arithmetic operation, is stored as
data word DW3 in data block DB20.
PB3 DB10
C DB 10 The information from data word DW1
in data block DB10 is loaded into the
C DB10 DW1 L DW 1 accumulator. The contents of ACCU 1
L DW1 . are stored in data word DW3 of data
. block DB20.
.
C DB20 .
DB20
C DB 20
T DW3
DW3
T DW 3
Generating and Deleting a Data Block

The “G DB x” statement does not call a data block. Instead, it generates a new block. If you want
to use the data in this data block, call it with the “C DB” statement.
Before the “G DB” statement, indicate in ACCU 1 the number of data words the block is to have
(see the example below).
If you specify zero as the data block length, the data block in question is deleted, i.e., it is removed
from the address list. It is considered nonexistent.
Note
The block is stored in memory and is designated as invalid until the programmable
controller memory is compressed (see section 7.5.3).
If you try to set up a data block that already exists, the “G DB x” statement is not executed.
A data block can be a maximum of 256 data words (DW0 to 255) in length.
EWA 4NEB 812 6120-02b 8-35

Generating a Data Block

Generate a data block with 128 data L KF + 127 The constant fixed-point number
words without the aid of a pro- G DB 5 +127 is loaded into ACCU 1. At
grammer. the same time, the old contents
of ACCU 1 are shifted to ACCU 2.
Data block 5 is generated with a
length of 128 data words (0000)
in the RAM of the PLC and
entered in the block address list.
The next time the “G DB5”
operation is processed, it has no
effect if the contents of
ACCU 1 are not 0.
Deleting a Data Block

Delete a data block that is no longer L KF + 0 The constant fixed-point number
needed. G DB 5 +0 is loaded into ACCU 1. At the
same time, the old contents of
ACCU 1 are shifted to ACCU 2.
Data block 5, which must be in
the RAM of the PLC, is declared
invalid and removed from the
block address list.
8-36 EWA 4NEB 812 6120-02b

Block End “BE”

The “BE” operation terminates a block. Data blocks do not need to be terminated. “BE” is always
the last statement in a block.
In structured programming, program scanning jumps back to the block where the call for the current
block was made.
Boolean logic operations cannot be continued in a higher-order block.
Example: Program block PB3 is terminated by the “BE” statement.

.
OB1 PB3
. The “BE” statement terminates
. program block PB3 and causes
. program scanning to return to
JU PB3 . organization block OB1.
.
BE
BE
Unconditional Block End “BEU”

The “BEU” operation causes a return within a block. However, jump operations can bypass the
“BEU” operation in function blocks (see sections 8.2.10 and 8.3.4).
Binary logic operations cannot be continued in a higher-order block.
Example: Scanning of function block FB21 is terminated regardless of the RLO.
PB8 FB21 .
. The “BEU” statement causes program
. scanning to leave function block FB21
. and return to program block PB8.
JC=
JC= BEU
.
JU FB21 BEU .
.
.
BE
BE
EWA 4NEB 812 6120-02b 8-37

Conditional Block End “BEC”

The “BEC” operation causes a return within a block if the previous condition has been satisfied
(RLO = 1).
Otherwise, linear program scanning is continued with RLO “1”.
Example: Scanning of program block FB20 is terminated if the RLO = “1”.
PB7 FB20 .
. The “BEC” statement causes program
. scanning to return to program block
. PB7 from function block FB20 if input
A I 0.0 I 0.0 is “1”.
A I 0.0 BEC
.
JU FB20 BEC .
.
.
8.1.9 Other Operations
Table 8-9 lists other basic operations. Explanations follow the table.
Table 8-9. Other Operations

STP Stop at the end of program scanning (in OB1)

Current program scanning is terminated.
The PIQ is read out. Then the PLC goes into the STOP mode.
NOP 0 “No” Operation

Sixteen bits in the RAM are set to “0”.
NOP 1 “No” Operation

Sixteen bits in the RAM are set to “1”.
BLD Display Generation Operation

“BLD” means a display generation operation for the programmer.
ID Parameter
130, 131, 132, 133, 255
Note
These operations can be programmed in STL form only.
8-38 EWA 4NEB 812 6120-02b

STOP Operation
The “STP” operation puts the programmable controller into the STOP mode. This can be desirable
for time-critical system circumstances or when a programmable controller error occurs.
After the statement is processed, the control program is scanned to the end, regardless of the RLO.
Afterwards the programmable controller goes into the STOP mode with the error ID “STS”. You
can restart the programmable controller with the mode selector (STOP to RUN) or with a
programmer.
“NOP” (No Operations)

The “NOP” operations reserve or overwrite memory locations.
Display Generation Operations

“BLD” display generation operations divide program parts into segments within a block.
“NOP” operations and display generation operations are significant only for the programmer when
representing the STEP 5 program.
The programmable controller does not execute any operation when these statements are processed.
8.2 Supplementary Operations
Supplementary operations extend the operations set. However, compared to basic operations,
which can be programmed in all blocks, supplementary operations have the following limitations.
• They can be programmed in function blocks only.
• They can be represented in STL form only.
The following sections describe the supplementary operations.
EWA 4NEB 812 6120-02b 8-39

8.2.1 Load Operation, for CPU 103 and Higher
As with the basic load operations, the supplementary load operation copies information into the
accumulator. Table 8-10 explains the load operation. An example follows the table.
Table 8-10. Load Operation

L Load
A word from the system data is loaded into ACCU 1 regardless of the
RLO.
ID Parameter
RS 0 to 255
In order to set parameters for ...

SINEC L1 bus operation via the L RS 57 Load ACCU 1 with the pro-
system data, the programmer and ... grammer and slave numbers.
slave numbers from SD57 should
be input into ACCU 1.
8-40 EWA 4NEB 812 6120-02b

8.2.2 Enable Operation, for CPU 103 and Higher
You can use the enable operation (FR) to execute the following operations even without an edge
change.
• Start a timer
• Set a counter
• Count up and down
Table 8-11 presents the enable operation. An example follows the table.
Table 8-11. Enable Operation

FR Enable a Timer/Counter
Timers and counters are enabled on the leading edge of the RLO.
This operation restarts a timer, sets a counter, or causes a counter
to count up or down when the RLO “1” is pending at the “Start”
operation.
ID Parameter
T 0 to 127
C 0 to 127
Input I 0.0 starts a timer T 2 as an A I 0.0

extended pulse (pulse width 50 s). L KT 500.1
This timer sets output Q 1.0 for the SE T 2 Start a timer T 2 as an extended
duration of the pulse. A T 2 pulse.
= Q 1.0 Output Q 1.0 is set for 50 s.
. .
. .
. .
. .
If output Q 1.1 is reset repeatedly, the A Q 1.1 If output Q 1.1 is set (positive
timer should also be restarted FR T 2 edge change of the RLO) during
repeatedly. the time in which input I 0.0 is
BE set, timer T 2 is restarted. Output
Q 1.0 therefore remains set at the
restarted time or is reset.
If input I 0.0 is not set during the
edge change of output Q 1.1, the
timer is not restarted.
EWA 4NEB 812 6120-02b 8-41

8.2.3 Bit Test Operations, for CPU 103 and Higher
Bit test operations scan digital operands bit by bit and affect them. Bit test operations must always
be at the beginning of a logic operation. Table 8-12 provides an overview of these operations.
Table 8-12. Overview of Bit Operations

TB Test a bit for signal state “1”

A single bit is scanned regardless of the RLO. The RLO is affected
according to the bit's signal state (see Table 8-13).
TBN Test a bit for signal state “0”

A single bit is scanned regardless of the RLO. The RLO is affected
according to the bit's signal state (see Table 8-13).
SU Set a bit unconditionally

The addressed bit is set to “1” regardless of the RLO. The RLO is
not affected.
RU Reset a bit unconditionally
The addressed bit is set to “0” regardless of the RLO. The RLO is
not affected.
ID Parameter
T 0.0 to 127.15
C 0.0 to 127.15
D 0.0 to 255.15
RS1 0.0 to 255.15
1 RS applies only to TB and TBN
Table 8-13 shows how the RLO is formed during the bit test operations “TB” and “TBN”. An
example for applying the bit operations follows the table.
Table 8-13. Effect of “TB” and “TBN” on the RLO

Operation TB TBN
Signal state of the bit in 0 1 0 1

the operand indicated
Result of logic operation 0 1 1 0
8-42 EWA 4NEB 812 6120-02b

A photoelectric barrier that counts C DB 10 Call data block 10.

piece goods is installed at input A I 0.0
I 0.0. After every 100 pieces, the CU C 10 Input I 0.1 loads the count of
program is to jump to FB5 or FB6. A I 0.1 counter 10 with the constant 0. With
After 800 pieces, counter 10 is to L KC 000 each positive edge change at I 0.0,
be reset automatically and start S C 10 the counter is incremented by 1. The
counting again. O I 0.2 counter is reset by either input I 0.2
O F 5.2 or flag F 5.2.
R C 10
LD C 10 The current count of the counter is
T DW 12 stored in data word DW12 in BCD
code.
TBN D 12.8 As long as bit 8 of data word DW12

is zero, program processing jumps to
JC FB 5 function block FB5. This is the case
for the first, third, fifth etc. batch of
100 pieces.
TB D 12.8 As long as bit 8 of data word DW12
is “1”, program scanning jumps to
JC FB 6 function block FB 6. This is the case
for the second, fourth, sixth, etc.
batch of 100 pieces.
TB D 12.11 When data bit 11 of data word DW12
becomes “1” (the count is then 800),
= F 5.2 flag F 5.2 is set conditionally.
A photoelectric barrier that counts :A I 0.3 Input I 0.4 loads the count of counter
piece goods is installed at input :CU C 2 20 with the constant 0. The count is
I 0.3. After every 256 pieces, the :A I 0.4 incremented by 1 with each positive
counter is supposed to be reset and :L KC 000 edge change at input I 0.3. If the
start counting again. :S C 20 count has reached 256 = 100H (bit 8
is “1”), program scanning jumps to
:TB C 20.8 the label “FULL”. Otherwise the
block is terminated.
:JC = FULL
:BEU
FULL:RU C 20.8 Bit 8 of counter C 20 is set to “0”

:BE unconditionally. Then the count is
again 000H.
Note
Times and counts are stored in the timer/counter word in hexadecimal notation in the
10 least significant bits (bits 0 to 9).
The time base is stored in bits 12 and 13 of the timer word.
EWA 4NEB 812 6120-02b 8-43

8.2.4 Digital Logic Operations
Digital logic operations combine the contents of both accumulators logically bit by bit.
Table 8-14 provides an overview of these digital logic operations. Examples follow the table.
Table 8-14. Overview of Digital Logic Operations

AW Combine bit by bit through logic AND

OW Combine bit by bit through logic OR
XOW Combine bit by bit through logic EXCLUSIVE OR
Processing a Digital Logic Operation

A digital logic operation is executed regardless of the RLO. It also does not affect the RLO.
However, it sets condition codes according to the result of the arithmetic operation (see section 8.4).
Note
Make sure both operands have the same number format. Then load them into the
accumulators before executing the operation.
8-44 EWA 4NEB 812 6120-02b

The result of the arithmetic operation is available in ACCU 1 for further processing. The contents of
ACCU 2 are not affected.
STL Explanation
L IW 92 Load input word IW92 into ACCU 1.
L KH 00FF Load a constant into ACCU 1. The previous contents of ACCU 1 are shifted
to ACCU 2.
AW Combine the contents of both accumulators bit by bit through logic AND.
T QW 82 Transfer the resulting contents from ACCU 1 to output word QW82.
Numeric Example
IW92 Set the 8 high-order bits in input

15 0
word IW92 to “0”.
ACCU 2 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0 Compare both words bit by bit. If
AND corresponding bits are both “1”, the
KH 00FF result bit is set to “1”.
ACCU 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Result
ACCU 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0
EWA 4NEB 812 6120-02b 8-45

STL Explanation
L KH 00FF Load a constant into ACCU 1. The previous contents of ACCU 1 are shifted
to ACCU 2.
OW Combine the contents of both accumulators bit by bit through logic OR.
T IW 36 Transfer the result (contents of ACCU 1) to input word IW36.
Numeric Example
IW36
15 0 Set the 8 low-order bits in input word
ACCU 2 1 1 1 0 0 1 0 0 1 1 0 0 0 1 1 0 IW36 to “1”. Compare both words
bit by bit.
OR If either of the corresponding bits is
KH 00FF “1”, a “1” is set in the result word.
ACCU 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Result
ACCU 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1
8-46 EWA 4NEB 812 6120-02b

STL Explanation
L IW 6 Load input word IW6 into ACCU 1. The previous contents of ACCU 1 are
shifted to ACCU 2.
XOW Combine the contents of both accumulators bit by bit through logic
EXCLUSIVE OR.
T QW 86 Transfer the result (contents of ACCU 1) to output word QW86.
Numeric Example
IW70 Check to see if input words IW70

15 0
and IW6 are equal.
ACCU 2 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 The result bit is set to “1” only if
X-OR corresponding bits in ACCU 1 and
IW6 ACCU 2 are unequal.
ACCU 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0
Result
ACCU 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0
EWA 4NEB 812 6120-02b 8-47

8.2.5 Shift Operations
Shift operations shift a bit pattern in ACCU 1. The contents of ACCU 2 are not affected. Shifting
multiplies or divides the contents of ACCU 1 by powers of two. Table 8-15 provides an overview of
the shift operations. Examples follow the table.
Table 8-15. Overview of Shift Operations

SLW Shift to the left.

The bit pattern in ACCU 1 is shifted to the left.
SRW Shift to the right.

The bit pattern in ACCU 1 is shifted to the right.
Parameter 0 to 15
Processing a Shift Operation

Execution of shift operations is unconditional. The RLO is not affected. However, shift operations
set condition codes.
Consequently, the status of the last bit that is shifted out can be scanned with jump functions.
The shift statement parameter indicates the number of bit positions by which the contents of
ACCU 1 are to be shifted to the left (SLW) or to the right (SRW). Bit positions vacated during
shifting are assigned zeros.
The contents of the bits that are shifted out of ACCU 1 are lost. Following execution of the
operation, the state of bit 20 (SRW) or bit 215 (SLW) has an influence on the CC1 bit, which can
then be evaluated.
A shift operation with parameter “0” is handled like a “NOP” operation. The central processor pro-
cesses the next STEP 5 statement with no further reaction.
Before executing a shift operation, load the operand to be processed into ACCU 1.
The altered operand is available there for further processing.
8-48 EWA 4NEB 812 6120-02b

STL Explanation
L DW 2 Load the contents of data word DW2 into ACCU 1.
SLW 3 Shift the bit pattern in ACCU 1 three positions to the left.
T DW 3 Transfer the result (contents of ACCU 1) to data word DW3.
Numeric Example
46410 (DW2) The value 46410 is stored in data

15 0
word DW2. Multiply this value by
ACCU 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0
23=8. Do so by shifting the bit
pattern of DW2 in ACCU 1 three
SLW 3 positions to the left.
371210
15 0
ACCU 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0
STL Explanation
L IW 124 Load the value of input word IW124 into ACCU 1.
SRW 4 Shift the bit pattern in ACCU 1 four positions to the right.
T QW 126 Transfer the result (contents of ACCU 1) to output word QW126.
Numeric Example
35210 (IW124) The value 35210 is stored in IW124.

15 0
Shift the corresponding bit pattern in
ACCU 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0
ACCU 1 four positions to the right to
divide the value 35210 by 24 = 16.
SRW 4
2210
15 0
ACCU 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0
EWA 4NEB 812 6120-02b 8-49

8.2.6 Conversion Operations
Conversion operations convert the values in ACCU 1. Table 8-16 provides an overview of the
conversion operations. Examples follow the table.
Table 8-16. Overview of Conversion Operations

CFW One's complement

The contents of ACCU 1 are inverted bit by bit.
CSW Two's complement

The contents of ACCU 1 are inverted bit by bit. Afterwards the word
0001H is added.
Processing Conversion Operations

Execution of these operations does not depend on the RLO nor does it affect the RLO.
The “CSW” operation sets the condition codes (see section 8.4).
STL Explanation
L DW 12 Load the contents of data word DW12 into ACCU 1.
CFW Invert all bits in ACCU 1.
T QW 20 Transfer the new contents of ACCU 1 to output word QW20.
Numeric Example
DW12 In a system, normally open contacts

15 0
ACCU 1 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0
have been replaced by normally
closed contacts. If the information in
data word DW12 is to maintain its
CFW previous effect, DW12 must be
15 0
inverted.
ACCU 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1
8-50 EWA 4NEB 812 6120-02b

STL Explanation
L IW 12 Load the contents of input word IW12 into ACCU 1.
CSW Invert all bits and add a “1”.
T DW 100 Transfer the altered word to data word DW100.
Numeric Example
Form the negative value of the value

IW12 in input word IW12.
15 0
ACCU 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1
CSW +1
15 0
ACCU 1 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1
EWA 4NEB 812 6120-02b 8-51

8.2.7 Decrement/Increment, for CPU 103 and Higher
The decrement/increment operations change the data loaded into ACCU 1. Table 8-17 provides an
overview of the decrement/increment operations. An example follows the table.
Table 8-17. Decrement/Increment Operations

D Decrement
Decrement the contents of the accumulator.
I Increment
Increment the contents of the accumulator.
The contents of ACCU 1 are either decremented or incremented by
the number indicated in the parameter.
Execution of the operation is unconditional and is limited to the
right-hand byte (without carry).
Parameter
0 to 255
Processing
Execution of the decrement and increment operations is independent of the RLO and does not affect
the RLO or the condition codes.
The parameter indicates the value by which the contents of ACCU 1 are to be changed.
The operations refer to decimal values; however, the result is stored in ACCU 1 in binary form.
Changes relate only to the low byte in the accumulator.
Increment the hexadecimal constant C DB 6 Call data block DB6.

1010H by 16 and store the result in L KH 1010 Load hexadecimal constant 1010H
data word DW8. into ACCU 1.
I 16 Increment the low byte of ACCU 1
by 16. The result, 1020H, is
located in ACCU 1.
In addition, decrement the incremen- T DW 8 Transfer the contents of ACCU 1
tation result by 33 and store the new (1020H) to data word DW8. Since
result in data word DW9. the incrementation result is still in
ACCU 1, you can decrement by 33
directly.
D 33 The result would be FFFH.
However, since the high byte of
ACCU 1 is not decremented along
with the low byte, the result in
ACCU 1 is 10FFH.
T DW 9 The contents of ACCU 1 are
transferred to DW9 (10FFH).
8-52 EWA 4NEB 812 6120-02b

8.2.8 Disable/Enable Interrupt, for CPU 103 Version 8MA02 and Higher
The disable/enable interrupt operations affect interrupt-driven and time-controlled program scanning.
They prevent process or time interrupts from interfering with the processing of a sequence of state-
ments or blocks. Table 8-18 lists the disable/enable interrupt operations. An example follows the
table.
Table 8-18. Disable/Enable Interrupt Operations

IA Disable interrupt
RA Enable interrupt
Processing
Execution of the disable/enable interrupt operations does not depend on the RLO. These operations
do not affect the RLO or the condition codes. After the “IA” statement is processed, no more
interrupts are executed. The “RA” statement cancels the effect of “IA”.
Disable interrupt processing in a .

specific program section and then .
enable it again. .
.
.
= Q 1.0
IA Disable interrupt.
A I 0.0
.
.
.
JU FB 3 If an interrupt occurs, the program
. section between the “IA” and
. “RA” is scanned without
. interruption.
RA Enable interrupt.
. Interrupts that occurred in the
. meantime are processed after the
. “RA” operation.
EWA 4NEB 812 6120-02b 8-53

8.2.9 “DO” Operation, for CPU 103 and Higher
Use the “DO” operation to process STEP 5 statements as indexed operations. This allows you to
change the parameter of an operand during control program processing (see Table 8-19).
Table 8-19. Overview of the “DO” Operation

DO Processing a flag word or data word

ID Parameter
FW 0 to 254
DW 0 to 255
“DO” Statements
“DO flag word or data word x” is a two-word statement that is unaffected by the RLO. “DO”
consists of the following two statements:
• The first statement contains the “DO” operation and a flag word or data word.
• The second statement defines the operation and the operand identifier you want the control
program to process. You must enter 0 or 0.0 as the parameter.
The control program works with the parameter that is stored in the flag word or data word. This
parameter is the one called up in the first statement. If you want to index binary operations, inputs,
outputs, or flags, you input the bit address in the high byte of this word. You input the byte address
in the low byte. In any other instance, the high byte must be “0”.
You can combine the following operations with the “DO” statement:
Operations Explanations
A1, AN, O, ON Boolean logic operations

S, R, = Set/reset operations
FR T, RT, SF T, SD T, SP T, SS T, SE T, Timer operations
FR C, RC, SC, CD C, CU C Counter operations
L, LD, T Load and transfer operations
JU=, JC=JZ=, JN=, JP=, JM=, JO= Jump operations
SLW, SRW Shift operations
D, I Decrement and increment
C DB, JU, JC, TNB Block calls
1 In combination with “DO FW,” the “A I” operation becomes the “A Q” operation if the byte address in
the data word or flag word is higher than 127.
! Caution
Damage to the system.
Performing operations that are not listed in Table 8-20 will damage your system.
Perform only those operations that are listed in Table 8-20.
8-54 EWA 4NEB 812 6120-02b

Figure 8-6 shows how the contents of a data word determine the parameter of the next statement.
DB6 FBx Actual program

:C DB 6 :C DB 6
. .
. .
. .
:DO DW 12 .
DW 12 KH = 0108 :A I 8.1
:A I 0.0
DW 13 KH = 0001 :DO DW 13 .
:FR T 0 :FR T 1
Figure 8-6. Executing a “DO” Operation
The following example illustrates how new parameters are generated in every program scan.

Set the contents of data words :C DB 202 Call data block DB202.
DW20 to DW100 to signal state :L KB 20 Load constant number 20 in
“0”. The index register for the ACCU 1.
parameter for the data words is :T DW 1 Transfer contents from ACCU 1 to
DW1. data word DW1.
F 1 :L KH 0 Load hex constant 0 in ACCU 1.
:DO DW 1 DO data word DW1.
:T DW 0 Transfer the contents from ACCU 1

to the data word whose address is
stored in data word DW1.
:L DW 1 Load data word DW1 in ACCU 1.
:L KB 1 Load constant number 1 in ACCU 1.

Data word DW1 is shifted to
ACCU 2.
:+F ACCU 2 und ACCU 1 are added,
and the result is stored in ACCU 1
(data word address is higher).
:T DW 1 Transfer contents of ACCU 1 to data

word DW1 (new data word address).
:L KB 100 The constant number 100 is loaded
in ACCU 1 and the new data word
address is shifted to ACCU 2.
:<=F Compare the ACCUs for less than or

equal to: ACCU 2 ACCU 1.
:JC = F 1 Jump conditionally to label F1, if
ACCU 2 ACCU 1.
EWA 4NEB 812 6120-02b 8-55

8.2.10 Jump Operations
Table 8.20 provides an overview of the jump operations. An example follows the table.
Table 8-20. Overview of Jump Operations

JU = Jump unconditionally
The unconditional jump is executed independently of conditions.
JC= Jump conditionally
The conditional jump is executed if the RLO is “1”. If the RLO is
“0”, the statement is not executed and the RLO is set to “1”.
JZ = Jump if the result is “zero”
The jump is executed only if CC 1 = 0 and CC 0 = 0
The RLO is not changed.
JN = Jump if the result is “not zero”

The jump is executed only if CC 1 CC 0
JP = Jump if the result is positive

JM = Jump if the result is negative
JO = Jump on overflow
The jump is executed if an overflow occurs. Otherwise the jump is
not executed. The RLO is not changed.
ID
Jump label (up
to 4 characters)
8-56 EWA 4NEB 812 6120-02b

Processing Jump Operations

A symbolic jump destination (jump label) must always be entered next to a jump operation. This
jump label can have up to four characters. The first character must be a letter of the alphabet.
When programming, please be aware of the following items:

• The absolute jump displacement cannot exceed +127 or - 128 words in the program memory.
Some statements take up two words (e.g., “Load a constant”). For long jumps, insert an inter-
mediate destination.
• Jumps can be executed only within a block.
• Jumping over segment boundaries (“BLD 255”) is not permitted.
• Jump labels can be set only at the start of a series of scans for CPU 102.
If no bit of input word IW1 is AN0 :L IW 1 Load input word IW1 into
set, program scanning jumps to :L KH 0000 ACCU 1. If the contents of
the label “AN 1”. If input word :+F ACCU 1 equal zero1, jump to
IW1 and output word QW3 do :JZ= AN 1 the label “AN 1”. Otherwise
not agree, program processing :A I 0.0 process the next statement
jumps back to the label “AN 0”. . (I 0.0).
Otherwise input word IW1 and .
data word DW12 are compared. .
If input word IW1 is greater than .
or less than data word DW12, .
program scanning jumps to the .
“DEST” label. AN1 :L IW 1 Compare input word IW1 and
:L QW 3 output word QW3. If they are
:XOW not equal, set individual bits in
ACCU 1.
:JN = AN 0 If the contents of ACCU 1 are
:L IW 1 not zero, jump to the label
:L DW12 “AN 0”. Otherwise process the
:>< F next statements.
Compare input word IW1 and
data word DW12. If they are
not equal, set RLO to “1”.
:JC = DEST If the RLO = “1”, jump to the
. “DEST” label. If the RLO =
. “0”, process the next
. statement.
.
.
DEST :A I 0.1
.
.
1 The “L...” statement does not affect the condition codes. An addition (+F) is executed with the constant
0000H so that the “JZ” operation can evaluate the contents of the accumulator.
EWA 4NEB 812 6120-02b 8-57

8.2.11 Substitution Operations, for CPU 103 and Higher
If you plan to process a program with various operands and without a lot of changes, it is advisable
to assign parameters to individual operands (see section 7.3.4). If you have to change the ope-
rands, you only need to reassign the parameters in the function block call.
These parameters are processed in the program as “formal operands”.

Special operations are necessary for this processing. However, these special operations are no
different in their effect than operations without substitution. A brief description of these operations
and examples follows.
Binary Logic Operations

Table 8-21 provides an overview of binary logic operations.
Table 8-21. Overview of Binary Logic Operations

A = AND operation
Scan a formal operand for “1”.
AN = AND operation
O = OR operation
ON = OR operation
Actual operands permitted Parameter Data

Formal operand type type
Inputs, outputs, and flags I, Q, F BI

addressed in binary form
Timers and counters T, C
8-58 EWA 4NEB 812 6120-02b

Set/Reset Operations
Table 8-22 provides an overview of the set/reset operations. An example follows the table.
Table 8-22. Overview of Set/Reset Operations

S = Set a formal operand (binary).
RB = Reset a formal operand (binary).
= = Assign
The RLO is assigned to a formal operand.
Parameter Data
Formal operand Actual operands permitted
type type
Inputs, outputs, and flags I, Q, F BI

addressed in binary form
Example: FB30 is assigned parameters in OB1.
Call in OB1 Program in FB30 Executed Program

:JU FB 30 :A =ON 1 :A I 0.0
NAME :COMBINE :AN =ON 2 :AN I 0.1
ON 1 : I 0.0 :O =ON 3 :O I 0.2
ON 2 : I 0.1 :S =MOT 5 :S Q 1.2
ON 3 : I 0.2 := =OFF 1 := Q 1.0
VAL1 : I 0.3 :A =VAL 1 :A I 0.3
OFF1 : Q 1.0 :A =ON 2 :A I 0.1
OFF2 : Q 1.1 :ON =ON 3 :ON I 0.2
MOT5 : Q 1.2 :RB =MOT 5 :R Q 1.2
: BE := =OFF 2 := Q 1.1
:BE :BE
EWA 4NEB 812 6120-02b 8-59

Load and Transfer Operations

Table 8-23 lists the various load and transfer operations. An example follows the table.

L = Load a formal operand.
LD = Load a formal operand in BCD code.
LW = Load the bit pattern of a formal operand.

T = Transfer to a formal operand.
Actual operands permitted Parameter Data

Formal operand type type
Inputs, outputs, and flags I, Q, F BY, W
For L =
addressed in binary form PW*, PY*
Data DW, DR, DL
Timers and counters T, C
For LD = Timers and counters T, C
For LW = Bit pattern D KF, KH, KM,

KY, KS, KT, KC
Inputs, outputs, data (DW, I, Q BY, W
For T =
DR, DL) and flags DW, DR, DL
addressed in binary form F, PW*, PY*
* Not for integral function blocks
Example: FB34 is assigned parameters in PB1.
Call in PB1 Program in FB34 Executed Program
:A =I 0 :A I 0.0
:JU FB 34 :L =L1 :L FW 10
NAME :LOAD/TRAN :S C 6 :S C 6
I0 : I 0.0 :A =I 1 :A I 0.1
I1 : I 0.1 :LW =LW1 :L KC 140
L1 : FW 10 :S C 7 :S C 7
LW1 : : KC 140 :A I 0.2 :A I 0.2
LC1 : C 7 :CU C 6 :CU C 6
T1 : QW 4 :CU C 7 :CU C 7
LW2 : : KC 160 :LD =LC1 :LD C 7
:BE :T =T1 :T QW 4
:A I 0.3 :A I 0.3
:R C 6 :R C 6
:R C 7 :R C 7
:LW =LW2 :L KC 160
:LD =LC1 :LD C 7
:!=F :!=F
:R C 7 :R C 7
:BE :BE
8-60 EWA 4NEB 812 6120-02b

Timer and Counter Operations

Table 8-24 provides an overview of timer and counter operations. Examples follow the table.
Table 8-24. Overview of Timer and Counter Operations

FR = Enable a formal operand for a cold restart. (For a description,

see “FT” or “FC”, according to the formal operand).
RD = Reset a formal operand (digital).
SP = Start a pulse timer specified as a formal operand using the value

stored in the accumulator.
SD = Start an on-delay timer specified as a formal operand using the
value stored in the accumulator.
SEC = Start an extended pulse timer specified as a formal operand

using the value stored in the accumulator or set a counter
specified as a formal operand using the count specified in the
accumulator.
SSU = Start a stored on-delay timer specified as a formal operand using

the value stored in the accumulator or start the count up of a
counter specified as a formal operand.
SFD = Start an off-delay timer specified as a formal operand using the

value stored in the accumulator or start the count down of a
counter specified as a formal operand.
Formal operand Actual operands permitted Parameter Data

type type
Timers and counters1 T, C1
1 “SP” and “SD” do not apply to counters.
Specifying Times and Counts

As with the basic operations, you can specify a time or count as a formal operand. In this case, you
must distinguish as follows whether the value is located in an operand word or is specified as a
constant.
• Operand words can be of parameter type “I” or “Q” and of data type “W”. Use the
“L=” operation to load them into the accumulator.
• Constants can be of parameter type “D” and of data type “KT” or “KC”. Use “LW=” to load
these formal operands into the accumulator.
EWA 4NEB 812 6120-02b 8-61

The following examples show how to work with timer and counter operations:
Example 1:
Function Block Call Program in Function Block (FB32) Executed Program
:AN =I 5 :AN I 0.0

:JU FB 32 :A =I 6 :A I 0.1
NAME :TIME :L KT 005.2 :L KT 5.2
I 5 : I 0.0 :SFD =TIM5 :SF T 5
I 6 : I 0.1 :A =I 5 :A I 0.0
TIM5 : T 5 :AN =I 6 :AN I 0.1
TIM6 : T 6 :L KT 005.2 :L KT 5.2
OFF6 : Q 1.0 :SSU =TIM6 :SS T 6
:BE :A =TIM5 :A T 5
:O =TIM6 :O T 6
:= =OFF6 := Q 1.0
:A I 0.2 :A I 0.2
:RD =TIM5 :R T 5
:RD =TIM6 :R T 6
:BE :BE
Example 2:
Function Block Call Program in Function Block (FB33) Executed Program

:A =I 2 :A I 0.0
:JU FB 33 :L KC 017 :L KC 017
NAME :COUNT :SEC =CNT5 :S C 5
I2 : I 0.0 :A =I 3 :A I 0.1
I3 : I 0.1 :SSU =CNT5 :CU C 5
I4 : I 0.2 :A =I 4 :A I 0.2
CNT5 : C 5 :SFD =CNT5 :CD C 5
OFF3 : Q 1.0 :A =CNT5 :A C 5
:BE := =OFF3 := Q 1.0
:A I 0.3 :A I 0.3
:RD =CNT5 :R C 5
:BE :BE
8-62 EWA 4NEB 812 6120-02b

“DO” Operation
Table 8-25 and the example that follows explain the processing operation.
Table 8-25. “DO” Operation

DO = Process formal operand

The substituted blocks are called unconditionally.
Formal operands Actual operands permitted Parameter Data

type type
DB, PB, SB, FB1 B

1 As actual operands, function blocks cannot have block parameters.
Example:
Function Block Call Program in Function Block FB35 Executed Program

STL
:JU FB 35 :DO =D5 :C DB 5
NAME :DO :L =DW2 :L DW 2
D5 : DB 5 :DO =D6 :C DB 6
DW2 : DW 2 :T =DW1 :T DW 1
D6 : DB 6 :T =Q4 :T QW 4
DW1 : DW 1 :DO =MOT5 :JU FB 36
Q4 : QW 4 :BE :BE
MOT5 : FB 36
:BE
EWA 4NEB 812 6120-02b 8-63

8.3 System Operations, for CPU 103 and Higher
System operations and supplementary operations have the following limitations:

• You can program them only in function blocks.
• You can program them only in the STL method of representation.
Since system operations access system data, only users with system knowledge should use them.
If you want to program system operations, you must select “SYS: OPS. Y” in the programmer
presets menu.
8.3.1 Set Operations
Like the supplementary bit operations, these set operations can change individual bits. Table 8-26
provides an overview of the set operations.
Table 8-26. Overview of Set Operations

SU Set bit unconditionally
A specific bit is set to “1” in the system data area.
RU Reset bit unconditionally
A specific bit is set to “0” in the system data area.
ID Parameter
RS 0.0 to 255.15
Processing Set Operations

Execution of set operations does not depend on the RLO.
8.3.2 Load and Transfer Operations
Use these load and transfer operations to address the entire program memory of the programmable
controller. They are used mainly for data exchange between the accumulator and memory locations
that cannot be addressed by operands. Table 8-27 provides an overview of the load and transfer
operations.
8-64 EWA 4NEB 812 6120-02b


LIR Load the register indirectly
The contents of a memory word are loaded into the specified
register (ACCU 1, 2). The address is in ACCU 1.
TIR Transfer the register indirectly

The contents of the indicated register are transferred to a memory
location. The address is in ACCU 1.
Parameter
0 (for ACCU 1), 2 (for ACCU 2)
TNB Transfer a data field (byte-by-byte)

A memory area is transferred in the program memory as a field.
End address destination area: ACCU 1
End address source area: ACCU 2
T Transfer
A word is transferred to the system data area.
ID Parameter
RS 0 to 255
Loading and Transferring Register Contents

Both accumulators can be addressed as registers. Each register is 16 bits wide. Since the “LIR”
and “TIR” operations transmit data by words, the registers are addressed in pairs.
Loading and transferring register contents are independent of the RLO. The processor goes to
ACCU 1 to get the address of the memory location referenced during data exchange. Conse-
quently, make sure that the desired address is stored in ACCU 1 before this system operation is
processed.
STL Explanation
.
.
L KH 6100 Load the address 6100H into ACCU 1.
LIR 0 Load the information from the memory location with the address 6100H into
ACCU 1.
EWA 4NEB 812 6120-02b 8-65

Processing a Field Transfer
A field transfer is processed independently of the RLO. The parameter indicates the length of the
data field (in bytes) that is to be transferred. The field can be up to 255 bytes long.
The address of the source field is in ACCU 2. The address of the destination field is in ACCU 1.
The higher address of each field must be specified because a field transfer takes place by
decrementing. The bytes in the destination field are overwritten during the transfer.
Transfer a 12-byte
data field from EE85
address F0A2H to Destination
address EE90H.
EE90
. .
. . TNB
. .
F097
Source
F0A2
STL Explanation
:L KH F0A2 Load the end address of the source field into ACCU 1.
:L KH EE90 Load the end adress of the destination field into ACCU 1. The
source address is shifted to ACCU 2.
:TNB 12 Transfer the data field to the destination field.
8-66 EWA 4NEB 812 6120-02b

Transferring to the System Data Area

Example: Set the scan monitoring time to 100 ms after each mode change from “STOP” to
“RUN”. You can program this time in multiples of 10 ms in system data word 96. The
following function block can be called from OB21, for example.
STL Explanation
FB 11 Block number and type
L KF +10 Load ACCU 1 with the factor 10.
T RS 96 Transfer this value to system data word 96.
BE
! Caution
The TIR, TRS and TNB operations are memory-changing operations with which you can
access the user memory and the system data area. These accesses are not monitored
by the operating system. Improper use of the operations can lead to changes in the
program and to a programmable controller crash.
8.3.3 Arithmetic Operations

An arithmetic operation changes the contents of ACCU 1 by a specified value. The parameter re-
presents this value as a positive or negative decimal number. Table 8-28 shows the essential
features of the “ADD” operation. An example follows the table.
Table 8-28. Overview of the “ADD” Operation

ADD Add a constant
Add byte or word constants.
ID Parameter
BF -128 to +127
KF -32768 to +32767
Processing
An arithmetic operation is executed independently of the RLO. It does not affect the RLO or the
condition codes.
You can subtract by entering a negative parameter.
Even if the result cannot be represented by 16 bits, no carry is made to ACCU 2, i.e., the contents
of ACCU 2 are not changed.
EWA 4NEB 812 6120-02b 8-67

Decrement the constant 1020H by 33 L KH 1020 The constant 1020H is loaded into
and store the result in flag word ACCU 1.
FW28. Afterwards add the constant ADD BF -33 The constant -330D is added to
256 to the result and store the sum in the ACCU contents.
flag word FW30. T FW 28 The new ACCU contents (0FFFH)
are stored in flag word FW28.
ADD KF 256 The constant 2560D is added to
the last result.
T FW 30 The new ACCU contents (10FFH)
are stored in flag word FW30.
8.3.4 Other Operations

Table 8-29 provides an overview of the remaining system operations.
Table 8-29. The “TAK” and “STS” Operations

TAK Swap accumulator contents

Swap the contents of ACCU 1 and ACCU 2 regardless of the
RLO. The RLO and the condition codes are not affected.
STS Stop immediately

The PLC goes into the STOP mode regardless of the RLO.
Processing the “STS” Operation

When the “STS” operation is executed, the programmable controller goes into the STOP mode
immediately. Program processing is terminated at this point. The STOP state can only be cancelled
manually (with the mode selector) or with the programmer function “PC START”.
8-68 EWA 4NEB 812 6120-02b

8.4 Condition Code Generation

The processor of the programmable controller has the following three condition codes:
• CC 0
• CC 1
• OV (overflow)
The following operations affect the condition codes.

• Comparison operations
• Arithmetic operations
• Shift operations
• Some conversion operations
The state of the condition codes represents a condition for the various jump operations.
Condition Code Generation for Comparison Operations

Execution of comparison operations sets condition codes CC 0 and CC 1 (see Table 8-30). The
overflow condition code is not affected. Comparison operations do affect the RLO. When a
comparison is satisfied, the RLO is 1. This allows you to use the “JC” conditional jump operation
after a comparison operation.
Table 8-30. Condition Code Settings for Comparison Operations

Contents of ACCU 2 as Condition Codes Possible
Compared to Contents Jump Operations
of ACCU 1 CC 1 CC 0 OV
Equal to 0 0 JZ
Less than 0 1 JN, JM

Greater than 1 0 JN, JP
Condition Code Generation for Arithmetic Operations

Execution of arithmetic operations sets all condition codes according to the result of the arithmetic
operation (see Table 8-31).
Table 8-31. Condition Code Settings for Fixed-Point Arithmetic Operations
Result after Condition Codes Possible
Arithmetic Operation Jump Operations
is Executed CC 1 CC 0 OV
< - 32768 1 0 1 JN, JP, JO
- 32768 to - 1 0 1 0 JN, JM
0 0 0 0 JZ
+1 to +32767 1 0 0 JN, JP
> +32767 0 1 1 JN, JM, JO
(-) 65536* 0 0 1 JZ, JO

* This number is the result of the calculation -32768 - 32768
EWA 4NEB 812 6120-02b 8-69

Condition Code Generation for Digital Logic Operations

Digital logic operations set CC 0 and CC 1. They do not affect the overflow condition code (see
Table 8-32). The setting depends on the contents of the ACCU after the operation has been pro-
cessed.
Table 8-32. Condition Code Settings for Digital Logic Operations

Contents Condition Codes Possible
of the
Jump Operations
ACCU CC 1 CC 0 OV
Zero (KH = 0000) 0 0 JZ

Not zero 1 0 JN, JP
Condition Code Generation for Shift Operations

Execution of shift operations sets CC 0 and CC 1. It does not affect the overflow condition code
(see Table 8-33). Code setting depends on the state of the last bit shifted out.
Table 8-33. Condition Code Settings for Shift Operations

Value of Condition Codes Possible
the Last Bit Jump Operations
Shifted Out CC 1 CC 0 OV
“0” 0 0 JZ
“1” 1 0 JN, JP
Condition Code Generation for Conversion Operations

The formation of the two's complement (CSW) sets all condition codes (see Table 8-34). The state
of the condition codes is based on the result of the conversion function.
Table 8-34. Condition Code Settings for Conversion Operations

Result after Condition Codes Possible
Arithmetic Operation
Jump Operations
is Executed CC 1 CC 0 OV
- 32768 * 0 1 1 JN, JM, JO
- 32767 to - 1 0 1 0 JN, JM
0 0 0 0 JZ
+1 to +32767 1 0 0 JN, JP
* This number is the result of the conversion of KH = 8000.
8-70 EWA 4NEB 812 6120-02b

8.5 Sample Programs
Sections 8.5.1 through 8.5.3 provide a few sample programs that you can enter and test in all three
methods of representation on a programmer.
8.5.1 Momentary-Contact Relay/Edge Evaluation

On each leading edge of the signal at input I 0.0, the AND
condition “A I 0.0 and AN F 64.0” is satisfied; the RLO is “1”.
This sets flags F 64.0 and F 2.0 (“edge flags”).
In the next processing cycle, the AND condition “A I 0.0 and
I 0.0
AN F 64.0” is not satisfied since flag F 64.0 has already been I 0.0
set. F 64.0
Flag 2.0 is reset.
Therefore, flag F 2.0 is “1” for only one program run.
When input I 0.0 is switched off, flag F 64.0 is reset. F 2.0
This resetting prepares the way for evaluation of the next F 2.0
leading edge of the signal at input I 0.0.
STL CSF LAD
A I 0.0
AN F 64.0 I 0.0 & I 0.0 F 64.0 F 2.0 F 64.0
= F 2.0 F 2.0 F 64.0 (#) S
S F 64.0
F 64.0 (#) S I 0.0
AN I 0.0
R F 64.0 R Q
NOP 0 I 0.0 R Q
8.5.2 Binary Scaler/Binary Divider

This section describes how to program a binary scaler.
Example: The binary scaler (output Q 1.0) changes its state each time I 0.0 changes its signal
state from “0” to “1” (leading edge). Therefore, half the input frequency appears at the
output of the flip-flop.
EWA 4NEB 812 6120-02b 8-71

Signal states
I 0.0
0 I 0.0
1 Q 1.0
0 Q 1.0
Time
STL CSF LAD
A I 0.0 I 0.0 &
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I 0.0 F 1.0 F 1.1
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AN F 1.0
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= F 1.1 F 1.0 F 1.1 ( )
***
A F 1.1 F 1.0
S F 1.0 F 1.1 F 1.0
F 1.1 S
AN I 0.0 S
R F 1.0
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R Q
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I 0.0 I 0.0
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NOP 0 a
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***
R Q
A F 1.1
A Q 1.0 F 1.1 &
= F 2.0 F 1.1 Q 1.0 F 2.0
***
Q 1.0 F 2.0 ( )
A F 1.1
AN Q 1.0
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AN F 2.0
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F 1.1 F 1.1 Q 1.0 F 2.0 Q 1.0

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S Q 1.0 &
Q 1.0 S
A F 2.0 Q 1.0
R Q 1.0 F 2.0 S F 2.0
NOP 0
R Q
*** F 2.0 R Q
Note
Output in CSF or LAD is possible only if you enter the segment boundaries “***” when
programming in STL.
8-72 EWA 4NEB 812 6120-02b

8.5.3 Clock/Clock-Pulse Generator
This subsection describes how to program a clock-pulse generator.

Example: A clock-pulse generator can be implemented using a self-clocking timer that is followed
in the circuit by a binary scaler. Flag F 2.0 restarts timer T 7 each time it runs down,
i.e., flag F 2.0 is “1” for one cycle each time the timer runs down. The pulses of flag
F 2.0 applied to the binary scaler result in a pulse train with pulse duty factor 1:1 at
output Q 1.0. The period of this pulse train is twice as long as the time value of the
self-clocking timer.
Signal states
1 G F 2.0
0 F 2.0
F 3.0
1
Q 1.0
0
Q 1.0
Time
T T
STL CSF LAD
AN F 2.0
L KT 010.1
F 2.0
SD T 7 T 7 T 7
NOP 0 F 2.0 T 0 T 0
NOP 0
KT 10.1 TV TV BI
NOP 0 BI KT 10.1 DE
A T 7 DE
R Q F 2.0 F 2.0
= F 2.0
*** R Q ( )
Q 1.0
A F 2.0 F 2.0 &
S F 2.0 F 3.0 Q 1.0
AN F 3.0
F 3.0 S
S Q 1.0
A F 2.0
F 2.0 &
A F 3.0 R Q F 2.0 F 3.0
R Q 1.0 F 3.0 R Q
NOP 0 F 3.0
*** F 2.0 &
S F 2.0 Q 1.0
AN F 2.0 F 3.0
Q 1.0
A Q 1.0 S
S F 3.0 F 2.0 &
AN F 2.0 R Q
Q 1.0 F 2.0 Q 1.0
AN Q 1.0 R Q
R F 3.0
NOP 0
EWA 4NEB 812 6120-02b 8-73

EWA 4NEB 812 6120-02b

9 Integrated Blocks and Their Functions
9.1 Assigning Internal Functions to DB1,

for CPU 103 Version 8MA03 and Higher . . . . . . . . . . . . . . . . . . . . 9 - 1
9.1.1 Configuration and Default Settings for DB1 . . . . . . . . . . . . . . . . . . 9 - 1
9.1.2 Setting the Address for the Parameter Error Code in DB1 . . . . . . . . 9 - 2
9.1.3 Assigning Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.4 Rules for Setting Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.5 How to Recognize and Correct Parameter Errors . . . . . . . . . . . . . . 9 - 6
9.1.6 Transferring DB1 Parameters to the Programmable Controller . . . . . 9 - 9
9.1.7 Reference Guide for Setting Parameters in DB1 . . . . . . . . . . . . . . . 9 - 10
9.1.8 Defining System Characteristics in DB1 .................... 9 - 11
9.2 Integrated Function Blocks,

9.2.1 Code Converter : B4 - FB240 - .......................... 9 - 12
9.2.2 Code Converter : 16 - FB241 - .......................... 9 - 12
9.2.3 Multiplier : 16 - FB242 - ............................... 9 - 13
9.2.4 Divider : 16 - FB243 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 13
9.2.5 Analog Value Conditioning Modules FB250 and FB251 . . . . . . . . . . 9 - 14
9.3 Integrated Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14

9.3.1 Scan Time Triggering OB31, for CPU 103 and Higher . . . . . . . . . . . 9 - 14
9.3.2 Battery Failure OB34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14
9.3.3 OB251 PID Algorithm,
EWA 4NEB 812 6120-02b

Figures
9-1 DB1 with Default Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1

9-2 Inputting the Address for the Parameter Error Code . . . . . . . . . . . . . . . . . . 9 - 3
9-3 Parameter Error Codes and Their Meaning . . . . . . . . . . . . . . . . . . . . . . . . 9 - 7
9-4 Erroneous Parameter Assignment in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 8
9-5 Inputting the System Data Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11
9-6 Calling Up the OB251 PID Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 15
9-7 Block Diagram of the PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 16
9-8 Principle of Interval Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 21
9-9 Process Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 22
Tables
9-1 Parameter Blocks and Their IDs ............................... 9 - 2

9-2 Call and Parameter Assignments of FB240 . . . . . . . . . . . . . . . . . . . . . . . . 9 - 12
9-6 Legend for the Block Diagram of the PID Controller . . . . . . . . . . . . . . . . . . 9 - 16
9-7 Description of the Control Bits in Control Word ”STEU” ............... 9 - 17
9-8 Structure of the Controller DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 19
EWA 4NEB 812 6120-02b

S5-100U Integrated Blocks and Their Functions
9 Integrated Blocks and Their Functions
9.1 Assigning Internal Functions to DB1, for CPU 103 Version 8MA03 and
Higher
You can program the following CPU functions:

• Using the integral real-time clock (see chapter 12)
• Exchanging data via SINEC L1 (see chapter 13)
• Changing polling interval for time-controlled program processing (OB 13) (see chapter 7)
• Assigning system parameters (see chapter 9)
• Setting the address for the parameter error code (see chapter 9)
To assign parameters to these functions, you must configure data block 1 (DB1).
9.1.1 Configuration and Default Settings for DB1
To make it easier for you to assign parameters, data block 1 is already integrated in the CPU with
default parameters. After performing an overall reset, you can load the default DB1 from the
programmable controller into your programmer and display it on the screen (see Figure 9-1). The
character string “DB1” must remain before the parameter blocks and be followed by at least one
filler (such as a blank space or a comma).
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0: KS = 'DB1 SL1: SLN 1 SF ';

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12: KS = 'DB2 DW0 EF DB3 DW0 ';

24: KS = ' KBE MB100 KBS MB101 ';
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36: KS = 'PGN 1 ; #CLP: CF 0 ';

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48: KS = 'CLK DB5 DW0 STW ';

60: KS = 'MW102 STP Y SAV Y ';
72: KS = 'OHE N SET 4 01.04.92 ';
84: KS = '12:10:00 TIS 4 ';
96: KS = '01.04. 13:00:00 OHS ';
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108: KS = '000000:00:00 # ; SDP: WD';

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120: KS = ' 500 ; TFB: OB13 100 ';

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132: KS = ' ; END ';
Figure 9-1. DB1 with Default Parameters
This preset DB1 has one parameter block for each function. Each parameter block begins with a
block ID (shown in Figure 9-1 in the shaded background). The block ID is followed by a colon. The
individual parameters for each function are contained in these parameter blocks.
Each parameter block begins with a block ID followed by a colon. This colon must be followed by
at least one filler (such as a blank space or a comma). A semicolon must be at the end of each
parameter block with at least one filler between the semicolon and the next block ID.
EWA 4NEB 812 6120-02b 9-1

Integrated Blocks and Their Functions S5-100U
The parameter blocks listed in Table 9-1 are used for the S5-100U.
Table 9-1. Parameter Blocks and Their IDs

Block ID Explanation/Default Setting
'DB1 '; Start ID
'SL1: '; SINEC L1: Parameter block for SINEC L1 configuration /

(see chapter 13)
’CLP: ’: Clock-Parameters: Parameter block for integral time clock/

clock function not activated (see chapter 12)
'SDP: '; System-Dependent Parameter: Parameter block for system specifications /

default setting for cycle time monitoring is 500 ms (see section 9.1.8)
'TFB: '; Timer Function Blocks: Parameter block for time-controlled program
processing: OB13 is called up every 100 ms. (see chapter 7)
'ERT: '; Error ReTurn: Address for parameter error code / no default setting (see
section 9.1.2)
'END '; END block ID for DB1
The sequence of the parameters in DB1 is not fixed. A semicolon must be at the end of each
parameter block with at least one filler between the semicolon and the next block ID.
The structure of the following parameter blocks is described here in detail.

• ERT: (Error code position)
• SDP: (System specifications)
The parameter blocks that are not discussed here are explained in the chapters that describe their
functions.
9.1.2 Setting the Address for the Parameter Error Code in DB1
For the following reasons, we recommend that you use this example when you start setting your
parameters:
• Parameter block “ERT:” is the only block with no default parameters in DB1. You must there-
fore enter all the parameters. We will explain the rules for assigning parameters step by step,
so that you can learn the rules quickly.
• The correctly input “ERT:” parameter block makes it easy for you to correct parameter setting
errors; therefore, you should complete this block in DB1 before you change or add other
parameters.
The error parameter block is only important during the start-up phase. You should erase it
during “normal” operation because it takes up a lot of memory space.
9-2 EWA 4NEB 812 6120-02b

To help find parameter errors more easily and to help correct them, you can ask the programmable
controller to output error messages in a coded form. All you have to do is to tell the programmable
controller where it should store the error code. Make this input in parameter block “ERT:” of DB1.
The error code can be stored in either of the following locations:

• In flagwords
• In data words in a data block
How to Proceed:
1. Perform an overall reset on the programmable controller.

2. Display DB1 on the programmer.
3. Position the cursor on the E of the “END” ID at the end of the default DB1.
4. Enter the characters that are highlighted in Figure 9-2.
DB1 Explanation
0: KS = 'DB1 SL1: SLN 1 SF ';

12: KS = 'DB2 DW0 EF DB3 DW0 ';
24: KS = ' KBE MB100 KBS MB101 ';
36: KS = 'PGN 1 ; #CLP: CF 0 ';
72: KS = 'OHE N SET 4 01.04.92 ';
84: KS = '12:10:00 TIS 4 ';
96: KS = '01.04. 13:00:00 OHS ';
108: KS = '000000:00:00 # ; SDP: WD';
120: KS = ' 500 ; TFB: OB13 100 '; The parameter error code is stored in flag
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word MW1 after start-up.

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132: KS = ' ; ERT: ERR MW1 ; END ';

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Figure 9-2. Inputting the Address for the Parameter Error Code
5. Use the following check list to make sure your entries are correct.
- Is the block ID “ERT:” terminated by a colon? ............................
- Is at least 1 filler (a blank space in Figure 9-2) added after the colon? . . . . . . . . . . . .
- Is the parameter name (ERR) entered correctly? . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Does at least 1 filler (a blank space) follow the parameter name? . . . . . . . . . . . . . . .
- Is the argument (MW1) entered correctly? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Does at least 1 filler (a blank space) follow the argument? . . . . . . . . . . . . . . . . . . . .
- Does a semicolon (;) indicate the block end? . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Does DB1 end with the end ID “END” followed by a space? ..................
6. Transfer the changed DB1 to the programmable controller.
7. Switch the programmable controller from STOP to RUN.
- The programmable controller accepts the changed DB1.
If you did not store the parameter block “ERT:” in DB1, you can localize the error in the ISTACK if
there was an incorrect parameter setting. However, you will not know what type of error is present.
The same applies if you made an error when you input the parameter block “ERT:”
EWA 4NEB 812 6120-02b 9-3

9-4
DB1:
9.1.4
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Note
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A block end symbol

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DB1 consists of the following:

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Integrated Blocks and Their Functions

3. Change or expand the parameters.
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Changed DB1 parameters are accepted.
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9.1.3 Assigning Parameters in DB1

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One or more parameters

A parameter block consists of:

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2. Position the cursor on the desired parameter block.
A parameter consists of:

Rules for Setting Parameters in DB1
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5. Switch the programmable controller from STOP to RUN.
lights up) even after a switch from STOP to RUN.
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A start ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A block ID . . . . . . . . . . . . . . . . . . . . . . . . .
One or more parameter blocks . . . . . . . . . . . . . . . . . . . .
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A parameter name . . . . . . . . . . .
One or more arguments . . . . . . .

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(for an explanation and possible parameter values see section 9.1.7)
A block end ID . . . . . . . . . . . . . . . . . . . . . . . . .
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e.g.:
e.g.:
e.g.:
e.g.:
e.g.:
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DB1
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1. Display the default DB1, with its parameter block “ERT:” on the programmer.
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: END
STW
CLP:
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FW 102
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: ; (Semicolon)
STW FW 102
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As discussed in section 9.1.2, you use the following steps to change or expand the preset values of
If the CPU recognizes an error in DB1, then it remains in the STOP mode (red LED
CLP:STW FW102

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EWA 4NEB 812 6120-02b

S5-100U
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In the following section are the rules for changing or expanding entire parameter blocks. Follow
these steps or the CPU will not understand what you have entered.
1. Enter the start ID “DB1”, followed by a filler.

- DB1 must begin with the start ID “DB1”. Do not separate the three characters from each
other. After the start ID, there must be at least one filler. Use a blank space or a comma
as a filler.
2. Enter the block ID for the parameter block, followed by a filler.

- The start ID and filler are followed by the block ID for the parameter block. The sequence
of the parameter blocks in DB1 is random. The block ID identifies a block and its
corresponding parameter. The block ID “SL1”, for example, stands for the SINEC-L1
parameter. You must enter a colon immediately after the block ID. If the colon is missing,
then the CPU skips this block and displays an error message. You must add at least one
filler after the colon of a block ID.
3. Enter the parameter name, followed by a filler.

- The parameter name comes next. Parameter names are names for single parameters within
a parameter block. Within a block, the first four characters of a parameter name must be
different from each other. After the parameter name, you must add at least one filler.
4. Enter the argument that is attached to the parameter name, followed by a filler.
- At least one argument is attached to each parameter name. An argument is either a
number or a STEP 5 operand that you must enter. If several arguments belong to a
parameter name, then every argument must be followed by at least one filler (even the last
one).
5. Enter a semicolon (; ) to identify the block end, followed by a filler.

- After the semicolon, you must enter at least one filler. Leaving out the semicolon leads to
misinterpretation in the CPU.
6. Enter additional parameter blocks after the semicolon.

- (Use steps 2 through 5 to create additional parameter blocks.)
7. Enter the end ID “END”.

- This identifies the end of DB1. If you forget to enter an end ID, this leads to errors in the
CPU.
EWA 4NEB 812 6120-02b 9-5

The preceding steps present the minimal requirements for setting the parameters. Beyond that,
there are additional rules that make it easier for you to assign parameters.
For example:
• You have the ability to add comments.
• You can expand the German mnemonics used as parameter names by using plain English text.
Comments can be added anywhere a filler is allowed. The comment symbol is the pound (#) sign.
The comment symbol must be placed at the beginning and at the end of your comment. The text
between two comment symbols may not contain an additional #.
Example: #Comment# .
At least one filler must follow the comment.
If you wish to change the default settings in parameter blocks SL1: or CLP:, you must first of all
overwrite the two comment characters (#) with blanks. If you fail to do this, the changes are
ignored.
If you wish to retain the default settings for one of the two parameter blocks, you must place it
between comment characters (overwrite blanks with “#”).
In order to make it easier to read parameter names, you can add as many characters as you wish if
you add an underscore (_) after the abbreviated parameter name.
Example: SF becomes SF_SENDMAILBOX.
At the end of the input, you must add at least one filler.
There is a rule of thumb that will help you check DB1. You should include at least one filler in the
following instances:
• After the start ID
• Before and after the block ID, parameter name, argument, and semicolon
9.1.5 How to Recognize and Correct Parameter Errors
If an error occurs while assigning parameters and the programmable controller does not go to the
“RUN” mode, you have two possibilities for recognizing errors:
• By using a parameter error code
• By using the analysis function “ISTACK”
Both possibilities are described below.
Scanning the Parameter Error Code

If you have entered a start address for the parameter error code in parameter block “ERT:” of DB1
(see section 9.1.2), then you can retrieve the cause of the error, and the error location information
at this address.
The entire error code occupies 10 data words or 20 flag bytes. In the following examples and
tables, we assume that the error code is stored in a data block starting with data word 0. The error
code occupies DW0 through DW9. In the “Flag” operand area, this corresponds to FW0 through
FW19.
9-6 EWA 4NEB 812 6120-02b

END
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No error
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S5-100U
Example:
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Not defined
Not defined
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10:
9:
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6:
5:
4:
3:
2:
1:
0:
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in an argument
Error in the date

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Range exceeded
DB is not present
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Error in inputting time

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EWA 4NEB 812 6120-02b

Syntax error - block ID
Irregular time format in

Error inputting weekday
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Syntax error - argument
Not enough space in DB

Syntax error - parameter
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Start or end ID is missing

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Cause of the error

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KH=
KH=
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KH=
KH=
KH=
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Comment not closed off correctly

(which error occurred?)

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parameter blocks (24h/12h mode)

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Parameter combination is not allowed

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Before END; semicolon missing in front of

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15
14
13
12
11
10
09
08
07
06
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04
03
02
01
00
DL
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0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 6 0 3
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CO DE
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99
11
09
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00
F0
FF
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DR
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SL1:
TFB:
CLP:
ERT:
SDP:
to any block
to any block
SINEC L1
Error return
Figure 9-3. Parameter Error Codes and Their Meaning

Screen display with
parameter error codes
occur?)
Clock parameter
Timer function block

Error cannot be assigned
Location of error
Error can not be assigned

System data parameter
controller remains in the STOP mode. You suspect that the reason for this is a
parameter error. To find the error, display DB3 on the programmer. The entire
parameters to the programmable controller, you find out that the programmable
the screen display is a complete list of parameter error codes and their meanings.
continue to set parameters in DB1. While attempting to transfer the changed DB1
contents of DB3 appear on the screen. DW0 through DW9 contain the code for the
set in DB1 have already been transferred to the programmable controller. Then you
You entered the start address DB3 DW0 in parameter block “ERT:”. The parameters
parameter error. In the following figure, you see how your screen could look. Below
(in which parameter block did the error

9-7
•
•
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9-8
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aaaaaaaaaaaaaaaaa aaaaaaa
132:
120:
108:
96:
84:
72:
60:
48:
36:
24:
12:
0:
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aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa aaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
000CH
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addresses.
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aaaaaaaaaaaaaaaaaa
KS
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byte address
Hexadecimal
=
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= 'OHE N
= 'MW102
12D
= ' ; END
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= '12:10:00
= 'DB2 DW0
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The relative (error) address:

= 'CLK DB5 DW0
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The absolute (error) address:

byte address
= '01.04. 13:00:00
= 'DB1 SL1: SLN 40
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aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
The error is due to a range violation.

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a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
EF DB3
TIS 4
STW
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aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
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= 'PGN 1 ; #CLP: CF 0
the programmer displays a DB in words.

= ' KBE MB100 KBS MB101
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Locating Parameter Errors in “ISTACK”
DW0
SF
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';
= ' 500 ; TFB: OB13 100 ';
= '000000:00:00 # ; SDP: WD';
OHS ';
';
SET 4 01.04.92 ';
STP Y SAV Y ';
';
';
';
';
';
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12D
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
82F2H
000CH
:
The error causes ISTACK to display the following addresses.
2D =
6D
(relative SAC)
(absolute SAC)
contains the absolute error address as well as the relative error address.
characters (2 bytes).
Decimal
Figure 9-4. Erroneous Parameter Assignment in DB1
word address
Example: Your inputs into DB1 are as follows. The position shaded contains an error.
incorrect input or in front of the address that contains the incorrect input. These are byte
character that can be entered for that

represent the word address for the first
If the CPU recognizes an error in DB1 in the initial start-up, then the CPU remains in the STOP
The information displayed in the chart above shows that the error occurred after address 0 and
respective line. Each word consists of two
mode and stores a message in “ISTACK” describing where the error happened. The “ISTACK”
The STEP Address Counter (SAC) in the ISTACK points either to the address that contains the
So that you can locate the error in DB1 exactly, you must convert the relative byte address that is
before address 12. In Figure 9-4, argument 40 occupies address 6; the “40” is an incorrect entry.
displayed in hexadecimal format into a decimal word address. Decimal format is required because
The decimal numbers in front of each input line
EWA 4NEB 812 6120-02b

S5-100U
9.1.6 Transferring DB1 Parameters to the Programmable Controller

Unlike other data blocks, DB1 is processed only one time. This occurs when a cold restart is
performed on the programmable controller. This was done so that DB1 could handle certain special
functions.
One such special function is the assignment of parameters in the programmable controller with the
help of DB1. Setting parameters means that you enter parameters in DB1 for those internal
functions that your programmable controller should work with.
The programmable controller's operating system accepts these inputs into DB1 only when there is a
cold restart. You must perform a cold restart anytime you make changes to DB1. You can perform a
cold restart by switching from Power OFF to Power ON or from STOP to RUN.
The programmable controller accepts the parameters from DB1 and stores them in the system data
area.
Note
The CPU remains in the STOP mode if a parameter assignment error is found during
start-up. The red LED lights up on the operator panel and ISTACK displays a DB1
addressing error.
EWA 4NEB 812 6120-02b 9-9

9.1.7 Reference Guide for Setting Parameters in DB1
Parameter Argument Meaning
Block ID: SL1: SINEC L1 (SL1)

SLN p Slave number
SF DBx DWy Location of Send Mailbox
EF DBxDWy Location of Receive Mailbox
KBE MBy Location of Coordination Byte “Receive”
KBS MBy Location of Coordination Byte “Send”
PGN p Programmer bus number
p=1 to 3 x=2 to 255 y=0 to 255
Block ID:SDP: System-Dependent-Parameter (SDP)
WD p Number of timers being processed(Watch-Dog-Timer)

p=1 to 2550
Block ID: TFB: Timer-Funktions-Baustein (TFB)
OB13 p Intervals (ms) at which OB13 is called up and is
processed
p=0 to 655350 (State in 10-ms steps)
Block ID: CLP: ClockParameters (CP)
CF p Inputting the correction factor (Correction Factor)

CLK DBxDWy,MWz,EWv Location of the clock data (CLocK Data)
or AWv
STW DBxDWy,MWz,EWv Location of the status word (STatus Word)
or AWv
STP J/Y/N Updating the clock during STOP (SToP)
SAV J/Y/N Saving the clock time after the last change from RUN
to STOP or Power OFF (SAVe)
OHE J/Y/N Enabling the operating hours counter
(Operation Hour counter Enable)
SET wd dd.mm.jj Setting the clock time and date
hh:mn:ss1 AM/PM2
TIS wd dd.mm. Setting the prompting time (TImer Set)
hh:mn:ss1 AM/PM2
OHS hhhhhh:mn:ss1 Setting the operating hours counter
(Operation Hour counter Set)
wd =1 to 7 (weekday = Sun..Sat) p=– 400 to 400
dd =01 to 31 (day) v=0 to 126
mm =01 to 12 (month) x=2 to 255
yy =0 to 99 (year) y=0 to 255
hh =00 to 23 (hours) z=0 to 254
mn =00 to 59 (minutes) j/J=ja(yes)
ss =00 to 59 (seconds) y/Y=yes
hhhhhh =0 to 999999 (hours) n/N=no
1 If an argument such as seconds, for example, is not to be entered, input XX. The clock continues to run
with the updated data. The TIS parameter block does not acknowledge this argument..
2 If you input AM or PM after the clock time, the clock runs in the 12-hour mode. If you omit this
argument, the clock runs in the 24-hour mode. You must use the same time mode in the SET and TIS
parameter blocks.
9-10 EWA 4NEB 812 6120-02b

9.1.8 Defining System Characteristics in DB1

Each cyclical program processing triggers the beginning of a monitoring period. If the cycle trigger
is not retriggered during the monitoring period, the programmable controller is forced into the STOP
mode and disables the output modules. The default for the monitoring time is set to 500 ms in
DB1. You can increase the cycle time monitoring in the parameter block SDP.
Example: You wish to increase the monitoring time to 700 ms since your user program is very
large.
How to Proceed:
1. Display DB1 on the programmer.
2. Change the parameter block “SDP” as shown in Figure 9.5.
- Position the cursor on the arguments for the parameter
- Overwrite the arguments
4. Switch the programmable controller from STOP to RUN. The programmable controller now
accepts the changed parameters.
0: KS = 'DB1 SL1: SLN 1 SF ';

12: KS = 'DB2 DW0 EF DB3 DW0 ';
24: KS = ' KBE MB100 KBS MB101 ';
36: KS = 'PGN 1 ; #CLP: CF 0 ';
72: KS = 'OHE N SET 4 01.04.92 ';
84: KS = '12:10:00 TIS 4 ';
96: KS = '01.04. 13:00:00 OHS ';
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108: KS = '000000:00:00 # ; SDP: WD';

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120: KS = ' 700 ; TFB: OB13 100 ';

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132: KS = ' ; END ';
Figure 9.5. Inputting the System Data Parameter
You can also set the cycle monitoring time in OB31 (see section 9.3.1).
9.2 Integrated Function Blocks, for CPU 102 Version 8MA02 and Higher
Some standard function blocks are integrated in your S5-100U. You can call up these blocks in
your control program with the commands “JU FB” or “JC FB x”. The character “x” stands for the
block number.
Overview:
Block No. FB240 FB241 FB242 FB243 FB250 FB251

Block name COD:B4 COD:16 MUL:16 DIV:16 RLG:AI RLG:AQ
Call length 5 6 7 10 10 9
(in words)
Processing time
(in ms) < 0.6 < 1.0 < 0.9 < 2.1 2.4 4.8
EWA 4NEB 812 6120-02b 9-11

9.2.1 Code Converter : B4 - FB240 -

Use function block FB240 to convert a number in BCD (4 tetrads) with sign to a fixed-point binary
number (16 bits).
You must change a two-tetrad number to a four-tetrad number before you convert it.
• If a tetrad is not in the BCD defined range, then FB240 displays the value “0”. An error bit
message does not follow.
Table 9-2. Call and Parameter Assignments of FB240
Parameter Meaning Type Assignment STL
BCD BCD number IW 0 to 9999 : JU FB240

-
SBCD Sign of the I BI “1” for “-” NAME : COD:B4
BCD number “0” for “+” BCD :
SBCD :
DUAL Fixed-point QW 16 bits “0” DUAL :
number (KF) or “1”
9.2.2 Code Converter : 16 - FB241-

Use function block FB 241 to convert a fixed-point binary number (16 bits) to a number in BCD code
with additional consideration of the sign. An eight-bit binary number must be transferred to a 16-bit
word before conversion.
DUAL Binary number I W -32768 to+32767

: JU FB241
SBCD Sign of the BCD I BI “1” for “-” NAME : COD:16
number “0” for “+” DUAL :
SBCD :
BCD2 BCD number 4th and Q BY 2 tetrads BCD2 :
5th tetrads BCD1 :
BCD1 BCD number tetrads QW 4 tetrads

0 to 3
9-12 EWA 4NEB 812 6120-02b

9.2.3 Multiplier : 16 - FB242 -

Use function block FB 242 to multiply one fixed-point binary number (16 bits) by another. The pro-
duct is represented by two fixed-point binary numbers (16 bits each). The result is also scanned for
zero. An eight-bit number must be transferred to a 16-bit word prior to multiplication.
Z1 Multiplier I W -32768 to+32767

: JU FB242
Z2 Multiplicand I W -32768 to+32767 NAME : MUL:16
Z1 :
Z3=0 Scan for zero Q BI “0” : product is zero Z2 :
Z3=0 :
Z32 Product high-word QW 16 Bits
Z32 :
Z31 Product low-word QW 16 Bits Z31 :
9.2.4 Divider : 16 - FB243 -
Use function block FB 243 to divide one fixed-point binary number (16 bits) by another. The result
(quotient and remainder) is represented by two fixed-point binary numbers (16 bits each).
The divisor and the result are also scanned for zero. An eight-bit number must be transferred to a
16-bit word prior to division.
Parameter Explanation Type Assignment STL
Z1 Dividend IW -32768 to+32767

: JU FB243
Z2 Divisor IW -32768 to+32767 NAME : DIV:16
Z1 :
OV Overflow bit Q BI “1” : overflow Z2 :
OV :
FEH Q BI “1” : division by zero
FEH :
Z3=0 Scan for zero Q BI “0”: quotient is zero Z3=0 :
Z4=0 :
Z4=0 Scan for zero Q BI “0”: remainder is zero Z3 :
Z4 :
Z3 Quotient QW 16 bits
Z4 Remainder QW 16 bits
EWA 4NEB 812 6120-02b 9-13

9.2.5 Analog Value Conditioning Modules FB250 and FB251

Function block FB250 reads in an analog value from an analog input module and outputs a value XA
in the scale range specified by the user.
Function block FB251 allows you to output analog values to analog output modules. Values from the
range between the “UGR” (lower limit) parameters and the “OGR” (upper limit) parameters are
converted to the nominal range of the selected module.
You will find more information on the following topics in section 11.6:
• Calling up and setting parameters in FB250.
• Calling up and setting parameters in FB251.
• An example of analog value processing with FB250 and FB251.
9.3 Integrated Organization Blocks
9.3.1 Scan Time Triggering OB31, for CPU 103 and Higher
A scan time monitor monitors the program scan time. If program scanning takes longer than the
specified scan monitoring time, the CPU goes into the STOP mode. This can happen when one of
the following errors occurs:
• The control program is too long.
• The program enters a continuous loop.
You can retrigger the scan time monitor at any point in the control program by calling up OB31.
Calling up this block restarts the scan time monitor.
Call up OB31
• Prerequisite: SYSTEM COMMANDS “YES” has been specified on the programmer.
• JU OB31 can be programmed at any point in the control program.
Programming
One statement in OB31 is sufficient, e.g. “BE” to make the retriggering effective. Other
statements are also possible.
9.3.2 Battery Failure OB34
The CPU constantly checks the status of the battery in the power supply. If a battery fails (BAU),
OB34 is processed before every cycle until the battery is replaced. You can program the reaction of
the programmable controller to battery failure in OB34. If OB34 is not programmed, there is no
reaction.
9-14 EWA 4NEB 812 6120-02b

9.3.3 OB251 PID Algorithm, for CPU 103 Version 8MA02 and Higher
A PID algorithm is integrated in the operating system of the S5-100U. OB251 helps you use this
algorithm to meet your needs.
Before calling up OB251, you must first open a data block called the controller DB. It contains the
controller parameters and other controller specific data. The PID algorithm must be called up peri-
odically to generate the manipulated variable. The more closely the scan time is maintained, the
more accurately the controller fulfills its task. The control parameters specified in the controller DB
must be adapted to the scan time.
You should always call OB251 from the time OB (OB13). You can set time OBs at a call up interval
ranging between 10 ms and 655,350 ms. The PID algorithm requires no more than 1.7 ms to
process.
OB13 DBN
Time-Controlled Controller
Processing Data Block
C DB N OB251 DW 1
JU OB 251 PID Control .
. Algorithm .
. .
. .
. .
. .
BE DW 49
Figure 9-6. Calling Up the OB251 PID Algorithm
The continuous action controller is designed for controlled systems such as those present in
process engineering for controlling pressure, temperature, or flow rate.
The “R” variable sets the proportional element of the PID controller. If proportional action is
required, most controller designs use the value R = 1.
The individual Proportional action, Integral action, and Derivative action elements can be deactivated
via their parameters (R, TI, and TD) by presetting the pertinent data words to zero. This enables
you to implement all required controller structures without difficulty, e.g., PI, PD, or PID controllers.
You can forward the system deviation XW or, using the XZ input, any disturbance variable or the
inverted actual value X to the derivative action element. Specify a negative K value for a reverse
acting controller.
When the manipulated information (dY or Y) is at a limit, the integral action component is
automatically deactivated in order not to impair the dynamic response of the controller.
The switch settings in the block diagram are implemented by setting the respective bits in control
word “STEU”.
EWA 4NEB 812 6120-02b 9-15

aaaaaaaaaaaaaa
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Z STEU BGOG STEU
Bit 5 Bit 2
aaaaaaaa
aaaa
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aaaa
1 0
0
R Zk-Zk-1
aaaaaaaa
aaaa
Y OG
Sum-
ming
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aaaaaaaa
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- + unit
aaaaaa
aaaaaa
aaaaaaaa
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+ dY + 0 +
X TI K
Limiter
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aaa aaaa
XW + + + 1 + 0 YA,
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
0 1 dY dYA
TD 1
UG
aaaaaaaa
aaaa
XZ 1 Manual 0
function
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STEU STEU STEU STEU
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Bit 1 Bit 0 Bit 3 Bit 4
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Figure 9-7. Block Diagram of the PID Controller
Table 9-6. Legend for the Block Diagram of the PID Controller
Designation Explanation
K Proportional coefficient: K>0 direct acting
K<0 reverse acting
R R parameter (usually 1000)
TA Scan time
TN Integral-action time
TV Derivative-action time
TI Constant TI TI=Scan time TA/Integral action time TN
TD Constant TD TD=Derivative action time TV/Scan time TA
W Setpoint
STEU Control word
YH, dYH Output value: YH Control Word Bit 3=0
dYH Control Word Bit 3=1
Z Disturbance variable
XW System deviation
X Actual value
XZ Substitute value for system deviation
Y, dY Manipulated variable, manipulated increments
BGOG Upper limit of the manipulated variable
BGUG Lower limit of the manipulated variable
YA, dYA Output word : YA Control Word Bit 3=1
dYA Control Word Bit 3=0
9-16 EWA 4NEB 812 6120-02b

Table 9-7. Description of the Control Bits in Control Word “STEU”
Control Signal
Name Description
Bit State
0 AUTO 0 Manual mode

The following variables are updated in Manual mode:
1) XK, XWK-1 and PWK-1
2) XZK, XZK-1 and PZK-1, when STEU bit 1=1
3) ZK and ZK-1, when STEU bit 5=0
Variable dDK-1 is set to 0: The algorithm is not computed.
1 Automatic mode
1 XZ EIN 0 XWk is forwarded to the derivative action element. The XZ input

1 is ignored. A variable other than XWk is forwarded to the derivative
action element .
2 REG AUS 0 Normal controller processing

1 When the controller is called up (OB251), all variables (DW18 to
DW 48 ) with the exception of K, R, TI, TD, BGOG, BGUG, YHk
and Wk are reset in the controller DB. The controller is
deactivated.
3 GESCHW 0 Positioning algorithm

1 Correction rate algorithm
4 HANDART 0 When GESCHW=0:

Following the transfer to Manual mode, the specified manipulated
variable value YA is adjusted exponentially to the manual value in
four sampling steps. Additional manual values are then forwarded
immediately to the controller output.
When GESCHW=1:
The manual values are forwarded immediately to the controller
output. The limiting values are in force in Manual mode.
1 When GESCHW=0:
The manipulated variable last output is retained.
When GESCHW=1:
Correction increment dYK is set to zero.
5 NO Z 0 With feedforward control

1 No feedforward control
6 and 7 - These bits are not assigned.
8 to 15 - The PID algorithm uses these bits as auxiliary flags.
The control program can be supplied with fixed values or parameters. Parameters are input via the
assigned data words. The controller is based on a PID algorithm. Its output signal can be either a
manipulated variable (positioning algorithm) or a manipulated variable modification (correction rate
algorithm).
EWA 4NEB 812 6120-02b 9-17

Correction Rate Algorithm

The relevant correction increment dYk is computed at instant t= k • TA according to the following
formula:
• Without feedforward control (D11.5=1); XW is forwarded to the differentiator (D11.1=0)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XWk - 2XWk-1 + XWk-2) + dDk-1)]
= K (dPWkR + dIk + dDk)
• With feedforward control (D11.5=0); XW is forwarded to the differentiator (D11.1=0)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XWk - 2XWk-1 + XWk-2) + dDk-1)]+(Zk-Zk-1)
= K (dPWkR + dIk + dDk)+dZk
• Without feedforward control (D11.5=1); XZ is forwarded to the differentiator (D11.1=1)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XZk - 2XZk-1 + XZk-2) + dDk-1)]
= K (dPWkR + dIk + dDk)
• With feedforward control (D11.5=0); XZ is forwarded to the differentiator (D11.1=1)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XZk - 2XZk-1 + XZk-2) + dDk-1)]+(Zk-Zk-1)
= K (dPWkR + dIk + dDk)+dZk
P element I element D element Z element k: kth element
When XWk is applied: XWk = W k - Xk

PWk = XWk - XWk-1
QWk = PWk - PWk-1
= XWk-2XWk-1+XWk-2
When XZ is applied: PZk = XZk - XZk-1

QZk = PZk - PZk-1
= XZk-2XZk-1+XZk-2
The result is: dPWk = (XWk- XWk-1)R

dIk = TI•XWk
dDk = (TD•QWk+dDk-1) when XW is applied
= (TD•QZk+dDk-1) when XZ is applied
dZk = Zk - Zk-1
Positioning Algorithm
The formula used to compute the correction rate algorithm is also used to compute the positioning
algorithm.
In contrast to the correction rate algorithm, however, the sum of all correction increments computed
(in DW 48), rather than the correction increment dYk is output at sampling instant tk.
9-18 EWA 4NEB 812 6120-02b

At instant tk , manipulated variable Yk is computed as follows:

m=k
Y k= dYm
m=0
Initializing the PID Algorithm

OB251's interface to its environment is the controller DB. All data needed to compute the next
manipulated variable value is stored in this DB. Each controller has its own controller data block.
The controller-specific data are initialized in a data block that must comprise at least 49 data words.
The CPU goes to STOP with a transfer error (TRAF) if no DB is open or if the DB is too short.
! Caution
Make sure that the right controller DB is open before calling control algorithm OB251.
Table 9-8. Structure of the Controller DB
Data Word Name Comments
1 K Proportional coefficient (-32 768 to + 32 767) for controllers

without a derivative-action element
Proportional coefficient (- 1500 to +1500) for controllers with a
derivative-action element*
K is greater than zero when the control is direct acting, and less
than zero when the control is reverse acting; the specified value is
multiplied by a factor of 0.001**.
3 R R parameter (- 32 768 to + 32 767) for controllers without

aderivative-action element
R parameter (- 1500 to + 1500) for controllers with a derivative-
action element*
Normally 1 for controllers with P element; the specified value is
multiplied with a factor of 0.001**
5 TI Constant TI (0 to 9999)
Sampling interval TA
TI=
Integral-action time
The specified value is multiplied by a factor of 0.001
3 Constant TD (0 to 999)
Derivative-action time TV
TD=
Sampling interval TA
9 W Setpoint (- 2047 to +2047)
11 STEU Control word (bit pattern)
12 YH Value for Manual operation (- 2047 to +2047)
14 BGOG Upper limit value (- 2047 to +2047)
16 BGUG Lower limit value (- 2047 to +2047)

aaaaaaaaaaaaaaaaa
* It is possible to have larger gains, if sudden incremental changes to the system deviation are small
enough. This is the reason you have to divide larger deviations into smaller ones such as adding
the setpoint via a ramp function.
** The factor 0.001 is an approximate value. The exact value of the factor is 1/1024 or 0.000976.
EWA 4NEB 812 6120-02b 9-19

Table 9-8. Structure of the Controller DB (continued)
Data
Name Comments
Word
22 X Actual value (- 2047 to +2047)
24 Z Disturbance variable (- 2047 to +2047)
29 XZ Derivative time (- 2047 to +2047)
48 YA Output variable (- 2047 to +2047)
All parameters (with the exception of the control word STEU) must be specified as 16-bit fixed point
numbers.
! Caution
The PID algorithm uses the data words that are not listed in Table 9-8 as auxiliary flags.
9-20 EWA 4NEB 812 6120-02b

Initialization and Call Up of the PID Controller in a STEP 5 Program

Several different PID controllers can be implemented by calling up OB251 repeatedly. A data block
must be initialized prior to each OB251 call up. These DBs serve as data interface between the
controllers and the user.
Note
Important controller data are stored in the high-order byte of control word DW11 (DL11).
Therefore make sure that only T DR 11/SU D11.0 to D11.7 or RU D 11.0 to D11.7
operations are used to modify user-specific bits in the control word.
Selecting the Sampling Interval

In order to be able to use the known analog method of consideration for digital control loops, do not
select a sampling interval that is too large.
Experience has shown that a TA sampling interval of approximately 1/10 of the time constant
TRK, dom* produces a control result comparable to the equivalent analog result. Dominant system
time constant TRK, dom determines the step response of the closed control loop.
TA = 1/10 • TRK, dom
In order to ensure the constancy of the sampling interval, OB251 must always be called up in the
service routine for time interrupts (OB13).
x = Control variable
x
t = Time
TA = Sampling interval
TRK,dom TRK,dom= Dominant system
time constant of
the closed control
loop
xd w = Reference
variable / Setpoint
xd = Control deviation
w
t
aaaaaaaaaa
aaaaaaaaaa
TA
Figure 9-8. Principle of Interval Sampling
* TRK, dom = dominant system time constant of the closed control loop
EWA 4NEB 812 6120-02b 9-21

Example for the Use of the PID Controller Algorithm:

A PID controller is supposed to keep an annealing furnace at a constant temperature.
The temperature setpoint is entered via a potentiometer.
The setpoints and actual values are acquired using an analog input module and forwarded to the
controller. The computed manipulated variable is then output via an analog output module.
The controller mode is set in input byte 0 (see control word DW11 in the controller DB).
You must use the well-known controller design procedure to determine how to tune the controller
for each controlled system.
IB32 Control byte (DR11) Manipulated

W PID Y variable
+ Channel0 Channel 0
X control
Channel1 algorithm
OB251 with S5-100U
controller DB
(call in OB13)
Setpoint
adjuster
Analog input module Analog output module
(e.g. 6ES5 460) (e.g. 6ES5 470)
Controlled
Actual system
value
= Temperature sensor
=
Annealing furnace Final control
Transducer element
Fuel gas flow
Figure 9-9. Process Schematic
The analog signals of the setpoint and actual values are converted into corresponding digital values
in each sampling interval (set in OB13). OB251 uses these values to compute the new digital
manipulated variable, from which, in turn, the analog output module generates a corresponding
analog signal. This signal is then forwarded to the controlled system.
9-22 EWA 4NEB 812 6120-02b

Calling the Controller in the Program:
OB 13 STL Description
:
: JU FB 10 PROCESS CONTROLLER
NAME : CONTROLLER 1
: THE CONTROLLER'S SAMPLING INTERVAL
: DEPENDS ON THE TIME BASE USED
: TO CALL OB13 (SET IN DB1).
: THE DECODING TIME OF THE ONBOARD
: ANALOG INPUTS MUST BE TAKEN
: INTO ACCOUNT WHEN SELECTING
THE SAMPLING INTERVAL.
:
:
: BE
EWA 4NEB 812 6120-02b 9-23

FB10 STL Description
NAME :CONTROLLER 1
:
:C DB 30 SELECT CONTROLLER'S DB
:
: **********************************
: READ CONTROLLER'S CONTROL BITS
: **********************************
:
:L PY 0 READ CONTROLLER'S
:T FY 10 CONTROL BITS
:T DR 11 AND STORE IN DR11
: NOTE CAREFULLY:
: DR11 CONTAINS IMPORTANT CONTROL
: DATA FOR OB251
: THE CONTROL BITS MUST
: THEREFORE BE TRANSFERRED WITH
: T DR11 TO PREVENT
: CORRUPTING DL11
:
: ********************************
: READ ACTUAL VALUE AND SETPOINT
: ********************************
:
:A F 12.0 FLAG 0 (FOR UNUSED FUNCTIONS
:R F 12.0 IN FB 250)
: AN F 12.1 FLAG 1
:S F 12.1
:
: JU FB250 READ ACTUAL VALUE
NAME : RLG: AI
BG : KF +8 MODULE ADDRESS
KNKT : KY 0,6 CHANNEL NO. 0, FIXED-POINT BIPOLAR
OGR : KF +2047 UPPER LIMIT FOR ACTUAL VALUE
UGR : KF - 2047 LOWER LIMIT FOR ACTUAL VALUE
EINZ : F 12.0 NO SELECTIVE SAMPLING
XA : DW 22 STORE SCALED ACTUAL VAL. IN CONTR. DB
FB : F 12.2 ERROR BIT
BU : F 12.3 RANGE VIOLATION
:
9-24 EWA 4NEB 812 6120-02b

FB10 (continued) STL Explanation
:
: JU FB250 READ SETPOINT
NAME : RLG: AI
KNKT : KY 1,6 CHANNEL NO. 1, FIXED-POINT BIPOLAR
OGR : KF +2047 UPPER LIMIT FOR SETPOINT
UGR : KF - 2047 LOWER LIMIT FOR SETPOINT
EINZ : F 12.0 NO SELECTIVE SAMPLING
XA : DW 9 STORE SCALED SETPOINT IN CONTR. DB
FB : F 13.1 ERROR BIT
BU : F 13.2 RANGE VIOLATION
:
:A F 10.0 IN MANUAL MODE, THE SETPOINT IS
: JC =WEIT SET TO THE ACTUAL VALUE TO FORCE
:L DW 22 THE CONTROLLER TO REACT
:T DW 9 TO A SYSTEM DEVIATION, IF ANY,
: WITH A P STEP
: ON TRANSFER
: TO AUTOMATIC
: MODE
WEIT :
: ********************
: JU OB251 CALL CONTROLLER
: ********************
:
: **********************************
: OUTPUT MANIPULATED VALUE
: **********************************
: JU FB251
NAME : RLG:AQ
XE : DW 48
KNKT : KY 0,1 CHANNEL 0, FIXED-POINT BIPOLAR
OGR : KF +2047 UPPER LIMIT FOR ACTUATING SIGNAL
UGR : KF - 2047 LOWER LIMIT FOR ACTUATING SIGNAL
FEH : F 13.5 ERROR BIT WHEN LIMITING VAL. DEFINED
BU : F 13.6 MANIPULATED VARIABLE Y TO ANALOG
: OUTPUT
: BE RANGE VIOLATION
EWA 4NEB 812 6120-02b 9-25

DB 30 STL Explanation
0: KH = 0000;
1: KF = +01000; K PARAMETER (HERE=1), FACTOR 0.001
2: KH = 0000; (VALUE RANGE: - 32768 TO 32767)
3: KF = +01000; R PARAMETER (HERE=1), FACTOR 0.001
4: KH = 0000; (VALUE RANGE: - 32768 TO 32767)
5: KF = +00010; TI=TA/TN (HERE=0.01), FACTOR 0.001
6: KH = 0000; (VALUE RANGE: 0 TO 9999)
7: KF = +00010; TD=TV/TA (HERE=10), FACTOR 1
8: KH = 0000; (VALUE RANGE: 0 TO 999)
9: KF = +00000; SETPOINT W, FACTOR 1
10: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
11: KM = 00000000 00100000; CONTROL WORD
12: KF = +00500; MANUAL VALUE YH, FACTOR 1
13: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
14: KF = +02000; UPPER CONT. LIMIT BGOG, FACTOR 1
15: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
16: KF = -02000; LOWER CONT. LIMIT BGUG, FACTOR 1
17: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
18: KH = 0000;
19: KH = 0000;
20: KH = 0000;
21: KH = 0000;
22: KF = +00000; ACTUAL VALUE X, FACTOR 1
23: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
24: KF = +00000; DISTURBANCE VARIABLE Z, FACTOR 1
25: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
26: KH = 0000;
27: KH = 0000;
28: KH = 0000;
29: KF = +00000; FEEDFORWARD XZ FOR DIFF.,
30: KH = 0000; FACTOR 1, (- 2047 TO 2047)
31: KH = 0000;
32: KH = 0000;
33: KH = 0000;
34: KH = 0000;
35: KH = 0000;
36: KH = 0000;
37: KH = 0000;
38: KH = 0000;
39: KH = 0000;
40: KH = 0000;
41: KH = 0000;
42: KH = 0000;
43: KH = 0000;
44: KH = 0000;
45: KH = 0000;
46: KH = 0000;
47: KH = 0000;
48: KF = +00000; CONTROLLER OUTPUT Y, FACTOR 1
49: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
50:
9-26 EWA 4NEB 812 6120-02b

10 Interrupt Processing
10.1 Interrupt Processing with OB2, for CPU 103

Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10.2 Calculating Interrupt Reaction Times . . . . . . . . . . . . . . . . . . . . . . . 10 - 5
EWA 4NEB 812 6120-02b

Figures
10-1 Possible Configuration of the Programmable Controller

with Bus Units Having Interrupt Capability . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10-2 Program Interruptions by Process Interrupts . . . . . . . . . . . . . . . . . . . . . . . 10 - 2
10-3 Accessing the Process Image Tables from OB2 ................... 10 - 4
Tables
10-1 Additional Reaction Times ................................... 10 - 5
EWA 4NEB 812 6120-02b

S5-100U Interrupt Processing
10 Interrupt Processing, for CPU 103 Version

8MA02 and Higher
Interrupt-driven program processing starts when a signal from the CPU causes the programmable
controller to interrupt cyclic or time-controlled program scanning in order to process a specific
program. Once this program has been scanned, the CPU returns to the point of interruption in the
cyclic or time-controlled program and resumes processing at that point.
Prerequisites for Interrupt-Driven Program Processing

Interrupt-driven program processing is possible only if the following conditions are met:
• The bus unit with interrupt capability is directly adjacent to the CPU (slots 0 and 1).
• Four-channel digital input modules or comparator modules must be mounted on the bus unit to
transfer process interrupts.
- You may plug other modules in, but these modules will have no interrupt handling capability.
• The programmable controller is in the Power ON state and in the RUN operating mode.
• Interrupt processing is not disabled by an IA operation in your program. See section 8.2.8.
• OB2 has been programmed.
Slot 0 1 2 3
° ° ° °
° ° ° °
° ° ° °
° ° ° °
CPU ° °
° °
° °
° °
4 8 4 8
DI DI DI DI
Bus unit with interrupt capability (but
acts only like a “normal” bus unit)
Interrupts are handled
only by this module
Bus unit with interrupt capability
Figure 10-1. Possible Configuration of the Programmable Controller with Bus Units
Having Interrupt Capability
10.1 Interrupt Processing with OB2, for CPU 103 Version 8MA02 and
Higher
For interrupt-driven processing, OB2 must have been programmed. OB2 is called up by a process
interrupt and interrupts in turn the cyclic or time-controlled program scanning. Other blocks can be
called from OB2. After the interrupt-driven program has been processed, the CPU resumes cyclic
or time-controlled program scanning.
EWA 4NEB 812 6120-02b 10-1

Interrupt Processing S5-100U
Triggering an Interrupt
Interrupts can only be triggered by four-channel digital input modules and comparator modules that
are plugged into slots 0 and 1 on a bus unit with interrupt capability.
Interrupts are triggered by a change in the signal state (0 1=positive edge; 1 0=negative edge)
at the respective interrupt input. Then the programmable controller automatically branches to OB2.
If you have not programmed OB2, either the cyclic or time-controlled program resumes immediately
after the interrupt.
The cyclically processed program can be interrupted after every STEP 5 statement.
The processing of integral FBs can be interrupted at certain points (see section 9.2). The data cycle
(see section 2.2.2) can be interrupted after each data packet consisting of four data bits and a check
bit.
Cyclic or time-controlled Interrupt-driven

program processing program processing
. . . Interrupt PII
A I 0.2 OB2
S Q 14.0 L PY2
INTERRUPT!
. . . .
.
BE .
BE
Interrupt PIQ
Figure 10-2. Program Interruptions by Process Interrupts
Use the IA command to disable interrupt processing. Use the RA command to enable interrupt
processing. The default setting is RA (see section 8.2.8).
Note
Even for interrupt processing, you may not exceed the general block nesting depth of 16
levels.
Interrupt Priorities
If a second interrupt is triggered during an interrupt processing, the second interrupts is processed
at the end of the first interrupt processing.
Note
If both a positive and negative pulse edge occur at an interrupt input while the IA
operation is valid (disable interrupt), it is no longer possible to determine the channel that
has triggered the interrupt.
But after an RA operation, OB2 is still called up.
10-2 EWA 4NEB 812 6120-02b

Reading Out the Interrupt PII
If a process interrupt occurs, only the signal states of the interrupt inputs in slots 0 and 1 are read
out to the interrupt PII.
This data in the interrupt PII is the only data provided to the interrupt-driven program for evaluation.
The interrupt PII can be scanned in OB2 by means of the following load operations:
Overview:
Operation Operand Description
L PY 0 Load byte 0 of the interrupt PII into ACCU 1

L PY 1 Load byte 1 of the interrupt PII into ACCU 1
L PW 0 Load word 0 of the interrupt PII into ACCU 1
If you enter other parameters, the CPU goes into the STOP mode and enters the “NNN” error
message in the ISTACK (see section 5.2). When data is read into the interrupt PII, the normal PII is
not written to simultaneously.
Writing to the Interrupt PIQ
Data from time-controlled or interrupt-driven programs to I/O modules are written to the interrupt PIQ
and simultaneously to the “normal” PIQ.
After OB2 is finished, the data that has been transferred to the interrupt PIQ is output to the
peripheral I/Os in an interrupt output data cycle (before “normal” program processing).
After the OB1 program cycle, the PIQ is copied to the interrupt PIQ.
The interrupt output data cycle is executed only if the interrupt PIQ has been written to. Use
transfer statements to write data for I/O modules to the interrupt PIQ. When data is written to the
interrupt PIQ, data is written simultaneously to the normal PIQ.
Overview:
Operation Operand Description
T PY 0 to 127 Transfer contents of ACCU 1 into the interrupt PIQ
T PW 0 to 126 Transfer contents of ACCU 1 into the interrupt PIQ
EWA 4NEB 812 6120-02b 10-3

Interrupt Processing S5-100U
Possibilities of Accessing Process I/O Image Tables

The following figure shows how data transfer between the process I/O image tables and ACCU 1
takes place when using various load and transfer statements in OB2.
Interrupt
PII PII
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
T IBX/T IW X L IBX/L IW X L PYX/L PY1/L PW0
ACCU 1
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
T QBX/T QW X
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
T PYX/T PW X
Interrupt
PIQ PIQ
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
a
a
a
a
a
aaaaaa
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
aa
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
a
a
a
a
X=byte or word address

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
aa
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
aa
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
aa
a
a
a
a
a
a
aa
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
Figure 10-3. Accessing the Process Image Tables from OB2
Example of How OB2 Can Be Programmed

Binary statements can access only the normal PII and PIQ. In order to determine the channel that
triggered an interrupt, transfer the I/O byte or word, for example, to a flag byte or word and then
evaluate using binary statements.
Example STL OB2 Explanation
Two sensors are L PY 0 Load byte 0 of the interrupt PII into ACCU 1 and
connected on channels 0 T FY 0 transfer it to flag byte 0.
and 1 on a four-channel A F 0.0 Did a positive edge occur on channel 0?
digital input module on AN I 0.0 OR
slot 0. O
Branch to FB12 if sensor 1 AN F 0.0 Did a negative edge occur on channel 0?
(channel 0) triggers an A I 0.0
interrupt. JC FB 12 If a pulse edge has occurred, a branch is made
... to FB12.
Caution
Be sure to save the flags (in a data block, for example) if these flags are to be
overwritten during interrupt processing and are needed again in the cycle.
10-4 EWA 4NEB 812 6120-02b

10.2 Calculating Interrupt Reaction Times
The total reaction time is is the sum of the following times:

• Signal delay of the module triggering the interrupt (= time from the input signal change
triggering the interrupt to the activation of the interrupt line)
• Interrupt reaction time of the CPU
• Execution time of the interrupt program (= sum of all STEP 5 statements in the interrupt
evaluation program)
Calculate the interrupt reaction times as follows:

CPU’s interrupt reaction time = basic reaction time + additional reaction times
The basic reaction time is 0.6 ms and is valid if the following conditions exist:
• No integrated FBs were used.
• No parameters for the integral clock are set.
• No programmer/OP functions are present.
• OB13 has not been programmed.
• No SINEC L1 is connected.
The additional reaction times are variable. They are listed in Table 10-1.
Table 10-1. Additional Reaction Times
Additional Running Functions of the Interrupt Reaction

Programmable Controller Times
Integrated FBs 0.5 ms

Parameters set for clock 0.2 ms
SINEC L1 bus to the programmer interface 8.0 ms

OP functions Depending on the number of bytes used
for loading the memory
Programmer functions:
Status block/Transfer block 0.5 ms

Output address 18 ms per kbyte
Compress
• If no blocks are moved • Depending on the number of blocks
present (after overall reset 31 ms)
• If blocks are moved • 600 ms per each 1kword of

instructions in the block to be
moved
EWA 4NEB 812 6120-02b 10-5

EWA 4NEB 812 6120-02b

11 Analog Value Processing
11.1 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1
11.2 Connecting Current and Voltage Sensors to Analog

Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1
11.2.1 Voltage Measurement with Isolated/Non-Isolated
Thermocouples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11.2.2 Two-Wire Connection of Voltage Sensors . . . . . . . . . . . . . . . . . . . 11 - 3
11.2.3 Two-Wire Connection of Current Sensors . . . . . . . . . . . . . . . . . . . 11 - 4
11.2.4 Connection of Two-Wire and Four-Wire Transducers . . . . . . . . . . . . 11 - 4
11.2.5 Connection of Resistance Thermometers . . . . . . . . . . . . . . . . . . . . 11 - 6
11.3 Start-Up of Analog Input Modules ......................... 11 - 7
11.4 Analog Value Representation of Analog Input Modules .......... 11 - 11
11.5 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19

11.5.1 Connection of Loads to Analog Output Modules . . . . . . . . . . . . . . . 11 - 19
11.5.2 Analog Value Representation of Analog Output Modules . . . . . . . . . 11 - 20
11.6 Analog Value Conversion: Function Blocks FB250 and FB251 . . . . . 11 - 22

11.6.1 Reading in and Scaling an Analog Value -FB250- . . . . . . . . . . . . . . 11 - 22
11.6.2 Output of Analog Value -FB251- . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
EWA 4NEB 812 6120-02b

Figures
11-1 Voltage Measuring with Isolated Thermocouples

(6ES5 464-8MA11/8MA21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11-2 Voltage Measuring with Non-Isolated Thermocouples
(6ES5 464-8MA11/8MA21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11-3 Two-Wire Connection of Voltage Sensors
(6ES5 464-8MB11, 464-8MC11, 466-8MC11) . . . . . . . . . . . . . . . . . . . . . . 11 - 3
11-4 Two-Wire Connection for Current Sensors (6ES5 464-8MD11) . . . . . . . . . . 11 - 4
11-5 Connection of Two-Wire Transducers (6ES5 464-8ME11) . . . . . . . . . . . . . 11 - 4
11-6 Connection for Four-Wire Transducers (6ES5 464-8ME11) ............ 11 - 5
11-7 Wiring Method for PT 100 (6ES5 464-8MF11/8MF21) . . . . . . . . . . . . . . . . 11 - 6
11-8 Wiring Possibilities for Input Modules (6ES5 464-8MF11) . . . . . . . . . . . . . . 11 - 6
11-9 Load Connection via a Four-Wire Circuit
(6ES5 470-8MA11, 6ES5 470-8MD11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19
11-10 Load Connection via a Two-Wire Circuit
(6ES5 470-8MB11, 6ES5 470-8MC11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 20
11-11 Scaling Schematic for FB250 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 22
11-12 Schematic for “Display of Tank Make-Up Quantity” .................. 11 - 23
11-13 Conversion of the Nominal Range into the Defined Range ............. 11 - 23
11-14 Schematic for “Display of Tank Contents” . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
11-15 Transformation of the Analog Value to the Nominal Range . . . . . . . . . . . . . 11 - 26
EWA 4NEB 812 6120-02b

Tables
11-1 Operating Mode Switch Settings for Analog Input Modules 464-8 to 11 .... 11 - 7
11-2 Operating Mode Switch Settings for Analog Input
Module 464-8MA21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 8
11-3 Operating Mode Switch Settings for Analog Input
Module 464-8MF21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 10
11-4 Representation of an Analog Input Value as Bit Pattern . . . . . . . . . . . . . . . . 11 - 11
11-5 Analog Input Module 464-8MA11, -8MF11, -8MB11
(Bipolar Fixed-Point Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 11
11-6 Analog Input Module 464-8MC11, -8MD11
(Bipolar Fixed-Point Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 12
11-7 Analog Input Module 464-8ME11, 4x4 to20 mA
(Absolute Value Representation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 12
11-8 Analog Input Module 464-8MF11, 2x PT 100 (Unipolar)
Analog Input Module 464-8MF21, 2x PT 100 “No Linearization”
(Unipolar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 12
11-9 Analog Input Module 464-8MF21, 2x PT 100 “with Linearization”
(Bipolar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 13
11-10 Analog Input Module 464-8MA21, 4x±50 mV “with Linearization” and
“with Temperature Compensation” (Bipolar); Thermoelement Type K
(Nickel-Chromium/Nickel-Aluminium, according to IEC 584) . . . . . . . . . . . . . 11 - 14
“with Temperature Compensation” (Bipolar); Thermoelement Type J
(Iron/Copper-Nickel (Konstantan), according to IEC 584) . . . . . . . . . . . . . . . 11 - 15
“with Temperature Compensation” (Bipolar); Thermoelement Type L
(Iron/Copper-Nickel (Konstantan) according to DIN 43710) . . . . . . . . . . . . . 11 - 16
11-13 Analog Input Module 466-8MC11, 4x 0 to10 V . . . . . . . . . . . . . . . . . . . . . . 11 - 16
11-14 Representation of an Analog Output Value as a Bit Pattern ............ 11 - 20
11-15 Output Voltages and Currents for Analog Output Modules
(Fixed-Point Number Bipolar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21
11-16 Output Voltages and Currents for Analog Output Modules (Unipolar) . . . . . . 11 - 21
EWA 4NEB 812 6120-02b

EWA 4NEB 812 6120-02b

S5-100U Analog Value Processing
11 Analog Value Processing
11.1 Analog Input Modules
Analog input modules convert analog process signals to digital values that the CPU can process (via
the process image input table, PII). In the following sections, you will find information about the
operating principle, wiring methods, and start-up and programming of analog input modules.
11.2 Connecting Current and Voltage Sensors to Analog Input Modules
Observe the following rules to connect current and voltage sensors to analog input modules:
• When you have multi-channel operations, assign the channels in ascending order. This shortens
the data cycle.
• Use terminals 1 and 2 for the connection of a compensating box (464-8MA11 ) or for the supply
of two-wire transducers (464-8ME11).
- Terminals 1 and 2 cannot be used with the remaining analog input modules.
• Short-circuit the terminals of unused inputs.
• Set the reference potentials of the sensors to a common reference potential. Do this to prevent
the potential difference between the common references from exceeding 1 V.
EWA 4NEB 812 6120-02b 11-1

Analog Value Processing S5-100U
11.2.1 Voltage Measurement with Isolated/Non-Isolated Thermocouples
Module 464-8MA11/8MA21 is recommended for voltage measurement with thermocouples. With

floating sensors (e. g., isolated thermocouples), the permissible potential difference VCM between
terminals of the inputs and the potential of the standard mounting rail must not be exceeded. To
avoid this, the negative potential of the sensor must be connected to the central ground point (see
Figure 11-1). Jumper terminals 1 and 2 together if you do not use compensation boxes.
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Figure 11-1. Voltage Measuring with Isolated Thermocouples (6ES5 464-8MA11/8MA21)
With non-floating sensors (e. g., non-isolated thermocouples), the permissible potential difference
VCM must not be exceeded (see maximum values of the individual modules).
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Figure 11-2. Voltage Measuring with Non-Isolated Thermocouples

(Module 6ES5 464-8MA11/8MA21)
11-2 EWA 4NEB 812 6120-02b

Connection of Thermocouples with Compensating Box to Module 464-8MA11/8MA21
The influence of the temperature on the reference junction (e. g., terminal box) can be compensated
for with a compensation box. Observe the following rules:
• The compensation box must have a floating supply.
• The power supply must have a grounded shielding winding.
• The compensation box must be connected to terminals 1 and 2 of the terminal block.
11.2.2 Two-Wire Connection of Voltage Sensors
You can use the following three modules for the connection of voltage sensors:
• Analog Input Module 464-8MB11 for voltages of±1 V
• Analog Input Module 464-8MC11 for voltages of±10 V
• Analog Input Module 466-8MC11 for voltages from 0 to 10 V
Figure 11-3 shows the two-wire connection of voltage sensors.

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Figure 11-3. Two-Wire Connection of Voltage Sensors

(6ES5 464-8MB11, 464-8MC11, 466-8MC11)
EWA 4NEB 812 6120-02b 11-3

11.2.3 Two-Wire Connection of Current Sensors
You can use module 464-8MD11 for the two-wire connection of current sensors.
Figure 11-4 shows the two-wire connections of current sensors.
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Figure 11-4. Two-Wire Connection for Current Sensors (6ES5 464-8MD11)
11.2.4 Connection of Two-Wire and Four-Wire Transducers
Use the 24-V inputs 1 and 2 of analog input module 464-8ME11 to supply the two-wire transducers.
The two-wire transducer converts the supplied voltage to a current of 4 to 20 mA.
For wiring connections, see Figure 11-5.
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Figure 11-5. Connection of Two-Wire Transducers (6ES5 464-8ME11)
11-4 EWA 4NEB 812 6120-02b

If you use a four-wire transducer connect it as shown in Figure 11-6.
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Figure 11-6. Connection for Four-Wire Transducers (6ES5 464-8ME11)
Four-wire transducers require their own power supply. Connect the “+” pole of the four-wire
transducer to the corresponding “-” pole of the terminal block (a connection technique that is the
opposite of the two-wire transducer). Connect negative terminals of the four-wire transducer to
terminal two of the terminal block.
Inputs 4, 6, 8, and 10 of the analog input module 464-8ME11 are connected internally via shunt
resistors. Because of the internal shunt resistors, broken wire signaling is not possible.
EWA 4NEB 812 6120-02b 11-5

11-6
11.2.5
circuits.
(e.g., PT 100).
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connection and short circuit the terminals IC+ and IC-.

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Figure 11-7. Wiring Method for PT 100 (6ES5 464-8MF11/8MF21)
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Figure 11-8. Wiring Possibilities for Input Modules (6ES5 464-8MF11)

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inputs have a high resistance so that only a negligible current loss develops in the measuring
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Measuring circuit M0
channel for voltage measurement (± 500 mV). In this case, use terminals M+/M- for the signal

Measuring circuits M1
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drops in these “constant current circuits” do not affect the measurement results. The measuring

Analog input module 464-8MF11/8MF21 is suited for the connection of resistance thermometers
The resistance of the PT 100 is measured in a four-wire circuit. A constant current is supplied to
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If you use only one channel for PT 100 measurement (e.g., channel 0), then you can use the other
the resistance thermometer via terminals 7 and 8 as well as via terminals 9 and 10, so that voltage
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Constant current circuit IC 0
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EWA 4NEB 812 6120-02b

S5-100U
11.3 Start-Up of Analog Input Modules

Set the intended operating mode using the switches on the front panel of analog input modules
464-8 through 11. These switches are located on the right side at the top of the front panel of the
module.
Power supply Set the switch to the available power supply frequency. This selects the inte-
frequency: gration time of the A/D converters for optimal interference voltage suppression.
Power frequency 50 Hz: Integration time 20 ms
Power frequency 60 Hz: Integration time 16.66 ms
Operation: Set the number of channels you wish to assign on the input module. If there are
fewer than four channels, less address space will be assigned and measured
values will be updated faster.
Broken wire: Once the broken wire signal has been activated, a break on one of the lines to
the sensor (thermocouple or PT 100) or of the sensor itself causes the red LED
above the function selection switch to light up. At the same time, the broken wire
error bit F (bit 1, byte 1) for the faulty channel is set.
The module “recognizes” a wire break by applying a conventional tripping current

to the input terminals and by comparing the resulting voltage to a limit value. If
there is a wire break in the sensor or the lines, the voltage exceeds the limit value
and a “wire break” signal is sent. When the signal at the input is measured with
a digital voltmeter, the tripping current pulses cause apparent fluctuations of the
signal. Deactivation of the wire break signal does not turn off the tripping current.
Table 11-1. Operating Mode Switch Settings for Analog Input Modules 464-8 to 11
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Function Settings for Operating Mode Switch
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50 Hz 60 Hz
Power supply 4 4
3 3
frequency 2 2
1 1
1 channel 2 channels (channel 0 4 channels (channel 0

(channel 0) and channel 1) - channel 3)
Operation 4 4 4
3 3 3
2 2 2
1 1 1
With wire break signal No wire break signal
Wire break 4 4
3 3
2 2
1 1
EWA 4NEB 812 6120-02b 11-7

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11-8
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Temperature
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Linearization:
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Function
frequency
Operation
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Thermocouples:
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1 channel
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(channel 0)
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Type L: - 199° C to + 900° C
Type K: - 200° C to +1369° C
Type J: - 200° C to +1200° C
50 Hz
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With wire break signal

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a
and channel 1)
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(-328° F to 2497° F)
(-328° F to 2192° F)

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2 channels (channel 0
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directly to the module, i.e., without a copper extension cable.

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Settings for Operating Mode Switch
corresponding compensation of the reference point temperature.

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compensation: the temperature of the reference point using a compensating box.

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Additional operating mode switch selections possible with analog module 464-8MA21:
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60 Hz
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No wire break signal

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464-8MA21, the linearization must always be activated together with the

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order to accomplish this, the terminals of the sensors have to be connected
Table 11-2. Operating Mode Switch Settings for Analog Input Module 464-8MA21
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a
1
2
3
4
5
6
7
8
With this function, you can obtain a characteristic linearization of the thermo-
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- channel 3)
When thermocouples are directly connected, an internal circuit on the module

the front of the module by activating the “temperature compensation” function.
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the terminal when the temperature at the measuring junction is 0° C (32° F). In
causes the digital value “0” to be displayed independently of the temperature of

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For the thermocouples of type J, K, and L, you can compensate, on the one hand,
4 channels (channel 0
(See Figure 11-1). On the other hand, it is possible to move the reference point to
couples of type J, K, and L or of the resistance thermometer PT 100. With module
(-326° F to 1652° F) in steps each of 1° C (1.8° F)
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EWA 4NEB 812 6120-02b

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S5-100U
•
•
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played.
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S5-100U
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input offset.
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Function
Table 11-2.
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Temperature
Characteristic
compensation
linearization of
thermocouples
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EWA 4NEB 812 6120-02b

“No linearization”
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the following two settings:

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aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa

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(continued)
“No temperature compensation”

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without
1
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8

linearization
1
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8 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
compensation

without temperature

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464-8MA21 functions just like module 464-8MA11.

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type K
1
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8

Linearization

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1
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sation for type K

Temperature compen-

type J
1
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8

Linearization


1
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8

Operating Mode Switch Settings for Analog Input Module 464-8MA21
type L

1
2
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6
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8
is 0° C (32° F). This means that with 0° C (32° F) at the measuring junction, the value “0” is dis-
box if you use the thermostat temperature in the application software to adjust the thermocouple
If you have set “Characteristic linearization” and “Temperature compensation” with the operating
When you set the switches to “no linearization” and “no temperature compensation”, then module
designed only for a certain type of thermocouple. It is possible to use a thermostat in the terminal
mode switches on module 464-8MA21 for the thermocouple used, then the reference temperature
Linearization

mixed thermocouples, or if you use thermocouples other than type J, K, or L, then you must choose
Temperature compen-
Compensation is then not possible even with a compensating box because the compensating box is
If you equip several channels with thermocouples, use the same type of thermocouple. If you select
sation for types J and L

11-9
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11-10
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PT 100:
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Function
frequency
Operation
Wire break
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linearization
for the PT 100
Power supply
Characteristic
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functions just like module 464-8MF11.

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1 channel
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(channel 0)
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-100° C to+850° C (-148° F to 1569° F)

With wire break signal
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No linearization
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Position 1 and 2 on the operating mode switch have no function.

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Set the switches on analog module 464-8MF21 as illustrated in Table 11-3.
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The characteristic linearization is possible for the following temperature ranges.

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(in steps of 0.5° C (0.9° F))

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60 Hz
aaaaaaaaa aaaaa aaaaaaaaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaa

1
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channel 1)
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1
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No wire break signal
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Table 11-3. Operating Mode Switch Settings for Analog Input Module 464-8MF21
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Linearization for PT 100
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2 channels (channel 0 and
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If you set the switch to “no linearization” and “no temperature compensation”, module 464-8MF21
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EWA 4NEB 812 6120-02b

aaaaaaaaa
S5-100U
11.4 Analog Value Representation of Analog Input Modules

Each analog process signal has to be converted into a digital format, to be stored in the process
image input table (PII). The analog signals are converted into a binary digit that is written in one of
the following ways:
• In one byte (466-8MC11)
• In two bytes (the remaining analog input modules)
Each bit position has a fixed value in powers of two (see Tables 11-4 and 11-14). Analog values
are represented in two's complement.
The following tables show the analog value representations of the different analog inputs in 2-byte
format. You will need this information to program FB250 and FB251 (see section 11.6).
Table 11-4. Representation of an Analog Input Value as Bit Pattern

High Byte Low Byte
Bit Number 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Analog Value Represent. S 211 210 29 28 27 26 25 24 23 22 21 20 X E OV
Key: S Sign bit 0="+", 1="-"

X Irrelevant bits
E Error bit 0= no wire break; 1=wire break
OV Overflow bit 0= Measured value 4095 units at the most
1= Measured value greater than or equal to 4096 units
Analog value representation for analog input modules 464-8...

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Table 11-5. Analog Input Module 464-8MA11, -8MF11, -8MB11 (Bipolar Fixed-Point Number)
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Measured Value
Units High Byte Low Byte Range
in mV
>4095 100.0 1000.0 2000.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow

4095 99.976 999.75 1999.5 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
2049 50.024 500.24 1000.48 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Overrange
2048 50.0 500.0 1000.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1024 25.0 250.0 500.0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0.024 0.24 0.48 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0.0 0.0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
-1 - 0.024 -0.24 -0.48 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-1024 - 25.0 - 250.0 - 500.0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
-2048 -50.0 -500.0 -1000.0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-2049 -50.024 -500.24 -1000.48 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
-4095 -99.976 -999.75 -1999.5 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
<-4095 -100.0 -1000.0 -2000.0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Overflow
464-8MA11/-8MA21 “No linearization” (4x±50 mV)

464-8MF11 (2x±500 mV)
464-8MB11 (4x±1 V)
EWA 4NEB 812 6120-02b 11-11

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Table 11-6. Analog Input Module 464-8MC11, -8MD11 (Bipolar Fixed-Point Number)
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Measured Value
in V in mA
>4095 20.000 40.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow

4095 19.995 39.9902 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
2049 10.0048 20.0098 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0
2048 10.000 20.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1024 5.000 10.0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0.0048 0.0098 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0.0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
-1 -0.0048 -0.0098 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-1024 - 5.000 -10.0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
-2048 -10.000 -20.0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-2049 -10.0048 -20.0098 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
-4095 -19.995 - 39.9902 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
<-4095 -20.000 -40.0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Overflow
464-8MC11 (4x±10 V)
464-8MD11 (4x±20 mA)
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Table 11-7. Analog Input Module 464-8ME11, 4x4 to 20 mA (Absolute Value Representation)
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Measured Value
Units High Byte Low Byte Range*
in mA
>4095 > 32.769 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow
4095 31.992 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
2561 20.008 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0
2560 20.0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
2048 16.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
512 4.0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
511 3.992 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0
384 3.0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transducer
-1 -0.008 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 failure?
<-4095 <-32.769 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
* Because of tolerances of components used in the module, the converted value can also be negative
(e.g. FFF8H Unit: -1).
Table 11-8. Analog Input Module 464-8MF11, 2x PT 100 (Unipolar)

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Analog Input Module 464-8MF21, 2x PT 100 “No Linearization” (Unipolar)

Resistance
in
>4095 400.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow
4095 399.90 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
2049 200.098 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0
2048 200.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1024 100.0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
1 0.098 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11-12 EWA 4NEB 812 6120-02b

Table 11-9. Analog Input Module 464-8MF21, 2x PT 100 “with Linearization” (Bipolar)
Resis- Temperature in
tance in °C °F
>1766 >400 >883 >1531 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 1 Overflow
1766 883 1531 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 1 Overrange*
1702 851 1564 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 1
1700 390.26 850 1562 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0
1400 345.13 700 1292 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0
1000 280.90 500 932 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0
600 212.02 300 572 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0
300 157.31 150 302 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0
200 138.50 100 212 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 Nominal range
2 100.39 1 34 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 100.00 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-40 92.16 -20 -4 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0
-80 84.27 -40 -40 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0
-200 60.25 -100 -148 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0
-202 -101 -150 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 Overrange*
-494 -247 -413 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1
<-494 <-247 <-403 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 Overflow
* In the overrange area, the current slope of the characteristic curve is maintained when leaving the linearized nominal range.
EWA 4NEB 812 6120-02b 11-13

Table 11-10. Analog Input Module 464-8MA21, 4x±50 mV “with Linearization”

and “with Temperature Compensation” (Bipolar); Thermoelement Type K
(Nickel-Chromium/Nickel-Aluminium, according to IEC 584)
Thermal Temperature
Units Voltage High Byte Low Byte Range
in mV* °C °F
>2359 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 Overflow
Overrange**
1370 1370 2498 0 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1
1369 54.773 1369 2496 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0
1000 41.269 1000 1832 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0
500 20.640 500 932 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
150 6.137 150 302 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0
100 4.095 100 212 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 Nominal range
1 0.039 1 34 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-1 -0.039 1 -30 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-100 -3.553 -100 -148 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0
-101 -3.584 -101 -150 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 Accuracy
-150 -4.912 -150 -238 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 0 2K
-200 -5.891 -200 -328 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0
-201 -201 -330 1 1 1 1 1 0 0 1 1 0 1 1 1 0 0 1 Overrange**
-273 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 Overflow
X X X X X X X X X X X X X X X 0 1 0 Wire break
This value corresponds to the terminal temperature at wire break
* For a reference temperature of 0° C (32° F)

** In the overrange area, the current slope of the characteristic curve is maintained when leaving
the linearized nominal range.
11-14 EWA 4NEB 812 6120-02b


and “with Temperature Compensation” (Bipolar); Thermoelement Type J
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(Iron/Copper-Nickel (Konstantan), according to IEC 584)
Thermal
Units Temperature
Voltage High Byte Low Byte Range
°C °F
in mV*
1485 0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 Overflow
Overrange**
1201 1201 2194 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1
1200 69.536 1200 2192 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0
1000 57.942 1000 1832 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0
500 27.388 500 932 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
100 5.268 100 212 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
1 0.05 1 34 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Nominal range
0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-1 -0.05 -1 -30 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-100 -4.632 -100 -148 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0
-150 -6.499 -199 -238 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 0
-199 -7.868 -200 -326 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0
-200 -7.890 -200 -328 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0
-201 -201 -330 1 1 1 1 1 0 0 1 1 0 1 1 1 0 0 1 Overrange**
-273 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 Overflow
X X X X X X X X X X X X X X X 0 F 0 Wire break
This value corresponds to the terminal temperature at wire break

** In the overrange area, the current slope of the characteristic curve is maintained when leaving the
linearized nominal range.
EWA 4NEB 812 6120-02b 11-15


and “with Temperature Compensation” (Bipolar); Thermoelement Type L
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(Iron/Copper-Nickel (Konstantan), according to DIN 43710)
Thermal
Temperature
Units Voltage High Byte Low Byte Range
in mV* °C °F
1361 0 0 1 0 1 0 1 0 1 0 0 0 1 0 0 1 Overflow
Overrange**
901 901 1654 0 0 0 1 1 1 0 0 0 0 1 0 1 0 0 1
900 53.14 900 1652 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0
500 27.85 500 932 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
250 13.75 250 482 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0

100 +5.37 100 212 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 Nominal range
1 0.05 1 34 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-1 -0.05 -1 -30 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-100 -4.75 -100 -148 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0
-150 -6.60 -150 -238 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 0
-190 -7.86 -190 -310 1 1 1 1 1 0 1 0 0 0 0 1 0 0 0 0
-199 -8.12 -199 -326 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0
-200 -200 -328 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 Overrange**
-273 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 Overflow
X X X X X X X X X X X X X X X 0 1 0 Wire break
This value corresponds to the terminal temperature at wire

break
** In the overrange area, the current slope of the characteristic curve is maintained when leaving the
linearized nominal range.
Analog value representation of analog input module 466-8MC11
The 466-8MC11 analog input module stores each analog value in a single byte. The other analog
input modules store the analog values in words (see Table 11-4).
Table 11-13. Analog Input Module 466-8MC11, 4x 0 to 10 V
Units Voltage in mV Bit Representation
255 9961 1 1 1 1 1 1 1 1
254 9922 1 1 1 1 1 1 1 0
. . .
128 5000 1 0 0 0 0 0 0 0
. . .
1 39 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
11-16 EWA 4NEB 812 6120-02b

If you want to read in the analog value with function block FB250 (analog value reading), you have to
pre-process the analog value before calling up FB250.
Example 1:
Analog input module 466-8MC11 is inserted in slot 1, which means that the module's start address
is 72.
The analog values are stored in four consecutive bytes:

1st analog value (channel 0) in IB72
2nd analog value (channel 1) in IB73
3rd analog value (channel 2) in IB74
4th analog value (channel 3) in IB75
Function block FB72, pictured below, reads in the analog values and pre-processes them for
function block FB250 (analog value reading).
FB72 Explanation
NAME :READ 466

READ IN ALL CHANNELS
0005 : OF AI 466
0006 :L IW 72 READ ALL FOUR CHANNELS
0007 :T FW 72 AND REARRANGE
0008 :L IW 74
0009 :T FW 74
000A :
000B :L FY 72 PROCESS EACH ANALOG VALUE
000C :SLW 6 AND REWRITE THEM IN
000D :T IW 72 THE PII SO THAT FB250
000E : CAN ACCESS THEM
000F :L FY 73 WITHIN THAT SCAN.
0010 :SLW 6
0011 :T IW 74
0012 :
0013 :L FY 74
0014 :SLW 6
0015 :T IW 76
0016 :
0017 :L FY 75
0018 :SLW 6
0019 :T IW 78
001A :
001B :BE
EWA 4NEB 812 6120-02b 11-17

Example 2:
Analog input module 466-8MC11 is inserted in slot 0, which means that the module’s start address
is 64.
The analog values that are read in are stored in four consecutive bytes:
1st analog value (channel 0) in IB64
2nd analog value (channel 1) in IB65
3rd analog value (channel 2) in IB66
4th analog value (channel 3) in IB67
Function block 73, pictured below, reads in the analog values and pre-processes them for FB250.
The additional processing with FB250 is done just like module 464, however without an overflow bit.
FB73 Explanation
NAME :READ AI
:
:
000A :L IB 67 Read in channel 3
000C :SLW 6
000E :T IW 70
0010 :
0012 :L IB 66 Read in channel 2
0014 :SLW 6
0016 :T IW 68
0018 :
001A :L IB 65 Read in channel 1
001C :SLW 6
001E :T IW 66
0020 :
0022 :L IB 64 Read in channel 0
0024 :SLW 6
0026 :T IW 64
0028 :
002A :
002C :JU FB 250
002E NAME :RLG:AI
0030 BG : KF +0 Module on slot 0
0032 KNKT : KY 0,4 Channel/No. 0, unipolar representation
0034 OGR : KF +1000 Upper limit 1000 (1000 mV)
0036 UGR : KF +0 Lower limit 0
0038 EINZ : F 0.0 No meaning
003A XA : FW 100 Output, 0 to 1000 mV in KF
003C FB : F 102.0 Error bit for parameter assignment
003E BU : F 102.1 Range overflow
0040 : (always 0 with this module)
0042 :BE
11-18 EWA 4NEB 812 6120-02b

•
•
•
•
•
11.5
S5-100U
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QV
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S+
voltages or currents.
be compensated for.
EWA 4NEB 812 6120-02b

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(4/8) (3/7)
L+
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1
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470-8MA12 (2x±10 V)
24 V DC
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2
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470-8MD12 (2x+1 to 5 V)
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3
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S+
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4
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(5/9) (6/10)
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Analog Output Modules
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6
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MANA
7
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Unused outputs must be left open-circuited.
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Terminals
8
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Check the following items before connecting loads:
QV
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9
S-
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10
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Terminal assignment
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MANA
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11.5.1 Connection of Loads to Analog Output Modules
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The load voltage 24 V DC must be connected to terminals 1 and 2.
S±:
QV:
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Key:
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MANA:
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No adjustments are necessary if you want to connect loads to the analog outputs.
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The maximum permissible potential difference between the outputs is 60 V AC.
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Sensor line
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Load resistor
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Figure 11-9 shows how to connect loads to the voltage outputs of the following modules:
aaaaaaaaaaaa
The sensor lines (S+ and S-) must be directly connected to the load, so that the voltage is
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of the analog unit

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Analog output modules convert the bit patterns that are output by the CPU into analog output
aa
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the load resistance. In such a case, connect terminal S+to terminal QV, and terminal S- to MANA.
Analog output "Voltage" aaaaaaaaaaaa
Chassis ground terminal

The sensor lines can be left out if the resistances of the QV and M lines are negligible compared to
measured and regulated directly at the load. In this manner, voltage drops of up to 3 V per line can
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Figure 11-9. Load Connection via a Four-Wire Circuit (6ES5 470-8MA12 or 6ES5 470-8MD12)
11-19
•
•
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Key:
11-20
(PIQ).
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Bit number
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Analog value represent.

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RL
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470-8MB12 (2x±20 mA)
4
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sign bit
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470-8MC12 (2x+4 to 20 mA).
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irrelevant bits
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RGB ELEKTRONIKA AGACIAK CIACIEK

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EWA 4NEB 812 6120-02b

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The reproduction, transmission or use of this document or its contents is not

Copyright© Siemens AG 1992

EWA 4NEB 812 6120-02b

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The SIMATIC S5 System Family 1

EWA 4NEB 812 6120-02b

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How to Use This Manual ............................................. xv

1 The SIMATIC S5 System Family .................................. 1 - 1

2 Technical Description ......................................... 2 - 1

2.1 Programmable Controller Design ............................. 2 - 1

2.2 Principle of Operation for the Programmable Controller . . . . . . . . . . . . . . 2 - 3

3 Installation Guidelines ......................................... 3 - 1

3.1 Installing S5-100U Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1

3.3 Electrical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20

3.4 Wiring Arrangement, Shielding, and Measures to

EWA 4NEB 812 6120-02b v

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4 Start-Up and Program Tests ..................................... 4 - 1

4.1 Operating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

4.2 Starting Up a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3

4.3 Loading the Program into the Programmable Controller . . . . . . . . . . . . . . 4 - 5

4.4 Backing Up the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 7

4.5 Program-Dependent Signal Status Display “STATUS” .............. 4 - 8

4.6 Direct Signal Status Display “STATUS VAR” ..................... 4 - 9

4.8 Forcing Variables, “FORCE VAR” ............................ 4 - 10

4.9 Search Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11

4.10 Program Check, for CPU 103 and Higher ....................... 4 - 11

5 Diagnostics and Troubleshooting ................................ 5 - 1

5.1 Indication of Errors by LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.2 CPU Malfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.3 Program Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8

5.4 I/O Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12

5.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12

5.6 The Last Resort ......................................... 5 - 13

vi EWA 4NEB 812 6120-02b

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6.1 Slot Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1

6.2 Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4

6.3 Analog Modules ......................................... 6 - 5

6.4 Combined Input Modules and Output Modules . . . . . . . . . . . . . . . . . . . . 6 - 6

6.5 The Structure of Process Image Input and Output Tables . . . . . . . . . . . . 6 - 8

6.6 Interrupt Process Images Tables and Time-Controlled Program

6.7 RAM Address Assignments ................................. 6 - 15

7 Introduction to STEP 5 ......................................... 7 - 1

7.1 Writing a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1

7.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.3 Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.4 Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18

EWA 4NEB 812 6120-02b vii

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