Scribd Logo
Upload

Welcome to Scribd!

  • 88 views

    74HC HCT08 CNV 2 PDF

    Uploaded by

    outmane
    The document describes the 74HC/HCT08 integrated circuit, which provides a quad 2-input AND function. It lists key specifications such as propagation delay, input/output capacitance, and power dissipation. The document also includes pin descriptions, logic diagrams, truth tables, ordering information and AC/DC characteristic specifications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    74HC HCT08 CNV 2 PDF

    Uploaded by

    outmane
    88 views5 pages
    The document describes the 74HC/HCT08 integrated circuit, which provides a quad 2-input AND function. It lists key specifications such as propagation delay, input/output capacitance, and power dissipation. The document also includes pin descriptions, logic diagrams, truth tables, ordering information and AC/DC characteristic specifications.

    Original Title

    74HC_HCT08_CNV_2.pdf

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document describes the 74HC/HCT08 integrated circuit, which provides a quad 2-input AND function. It lists key specifications such as propagation delay, input/output capacitance, and power dissipation. The document also includes pin descriptions, logic diagrams, truth tables, ordering information and AC/DC characteristic specifications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    88 views5 pages

    74HC HCT08 CNV 2 PDF

    Uploaded by

    outmane
    The document describes the 74HC/HCT08 integrated circuit, which provides a quad 2-input AND function. It lists key specifications such as propagation delay, input/output capacitance, and power dissipation. The document also includes pin descriptions, logic diagrams, truth tables, ordering information and AC/DC characteristic specifications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 5

    INTEGRATED CIRCUITS

    DATA SHEET
    For a complete data sheet, please also download:

    • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications


    • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
    • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

    74HC/HCT08
    Quad 2-input AND gate
    Product specification December 1990
    File under Integrated Circuits, IC06
    Philips Semiconductors Product specification

    Quad 2-input AND gate 74HC/HCT08

    FEATURES
    • Output capability: standard
    • ICC category: SSI

    GENERAL DESCRIPTION
    The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
    They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT08 provide the 2-input AND function.

    QUICK REFERENCE DATA


    GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

    TYPICAL
    SYMBOL PARAMETER CONDITIONS UNIT
    HC HCT
    tPHL/ tPLH propagation delay nA, nB to nY CL = 15 pF; VCC = 5 V 7 11 ns
    CI input capacitance 3.5 3.5 pF
    CPD power dissipation capacitance per gate notes 1 and 2 10 20 pF

    Notes
    1. CPD is used to determine the dynamic power dissipation (PD in µW):
    PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
    fi = input frequency in MHz
    fo = output frequency in MHz
    CL = output load capacitance in pF
    VCC = supply voltage in V
    ∑ (CL × VCC2 × fo) = sum of outputs
    2. For HC the condition is VI = GND to VCC
    For HCT the condition is VI = GND to VCC −1.5 V

    ORDERING INFORMATION
    See “74HC/HCT/HCU/HCMOS Logic Package Information”.

    December 1990 2
    Philips Semiconductors Product specification

    Quad 2-input AND gate 74HC/HCT08

    PIN DESCRIPTION

    PIN NO. SYMBOL NAME AND FUNCTION


    1, 4, 9, 12 1A to 4A data inputs
    2, 5, 10, 13 1B to 4B data inputs
    3, 6, 8, 11 1Y to 4Y data outputs
    7 GND ground (0 V)
    14 VCC positive supply voltage

    Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

    FUNCTION TABLE

    INPUTS OUTPUT
    nA nB nY
    L L L
    Fig.5 HC logic diagram L H L
    (one gate). H L L
    H H H
    Note
    1. H = HIGH voltage level
    L = LOW voltage level

    Fig.6 HCT logic diagram


    Fig.4 Functional diagram. (one gate).

    December 1990 3
    Philips Semiconductors Product specification

    Quad 2-input AND gate 74HC/HCT08

    DC CHARACTERISTICS FOR 74HC


    For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
    Output capability: standard
    ICC category: SSI

    AC CHARACTERISTICS FOR 74HC


    GND = 0 V; tr = tf = 6 ns; CL = 50 pF

    Tamb (°C) TEST CONDITIONS


    74HC
    SYMBOL PARAMETER UNIT VCC
    +25 −40 to +85 −40 to +125 WAVEFORMS
    (V)
    min. typ. max. min. max. min. max.
    tPHL/ tPLH propagation delay 25 90 115 135 2.0
    nA, nB to nY 9 18 23 27 ns 4.5 Fig.7
    7 15 20 23 6.0
    tTHL/ tTLH output transition 19 75 95 110 2.0
    time 7 15 19 22 ns 4.5 Fig.7
    6 13 16 19 6.0

    December 1990 4
    Philips Semiconductors Product specification

    Quad 2-input AND gate 74HC/HCT08

    DC CHARACTERISTICS FOR 74HCT


    For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
    Output capability: standard
    ICC category: SSI

    Note to HCT types


    The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
    To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

    INPUT UNIT LOAD COEFFICIENT


    nA, nB 0.6

    AC CHARACTERISTICS FOR 74HCT


    GND = 0 V; tr = tf = 6 ns; CL = 50 pF

    Tamb (°C) TEST CONDITIONS


    74HCT
    SYMBOL PARAMETER UNIT VCC
    +25 −40 to +85 −40 to +125 WAVEFORMS
    (V)
    min. typ. max. min. max. min. max.
    tPHL/ tPLH propagation delay
    14 24 30 36 ns 4.5 Fig.7
    nA, nB to nY
    tTHL/ tTLH output transition
    7 15 19 22 ns 4.5 Fig.7
    time

    AC WAVEFORMS

    (1) HC : VM = 50%; VI = GND to VCC.


    HCT: VM = 1.3 V; VI = GND to 3 V.

    Fig.7 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.

    PACKAGE OUTLINES
    See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

    December 1990 5

    You might also like