a Dual Precision,

Low Power BiFET Op Amp

AD648
FEATURES CONNECTION DIAGRAMS
DC Performance
400 mA max Quiescent Current
10 pA max Bias Current, Warmed Up (AD648C)
300 mV max Offset Voltage (AD648C)
3 mV/8C max Drift (AD648C)
2 mV p-p Noise, 0.1 Hz to 10 Hz
AC Performance
1.8 V/ms Slew Rate
1 MHz Unity Gain Bandwidth
Available in Plastic Mini-DIP, Cerdip, Plastic SOIC
and Hermetic Metal Can Packages
MIL-STD-883B Parts Available
Surface Mount (SOIC) Package Available in Tape and
Reel in Accordance with EIA-481A Standard
Single Version: AD548

PRODUCT DESCRIPTION The AD648S and AD648T are rated over the military tempera-
The AD648 is a matched pair of low power, precision mono- ture range of –55°C to +125°C and are available processed to
lithic operational amplifiers. It offers both low bias current MIL-STD-883B, Rev. C.
(10 pA max, warmed up) and low quiescent current (400 µA
max) and is fabricated with ion-implanted FET and laser wafer The AD648 is available in an 8-pin plastic mini-DIP, cerdip,
trimming technologies. Input bias current is guaranteed over the SOIC, TO-99 metal can, or in chip form.
AD648’s entire common-mode voltage range.
PRODUCT HIGHLIGHTS
The economical J grade has a maximum guaranteed offset volt- 1. A combination of low supply current, excellent dc and ac
age of less than 2 mV and an offset voltage drift of less than performance and low drift makes the AD648 the ideal op
20 µV/°C. The C grade reduces offset voltage to less than amp for high performance, low power applications.
0.30 mV and offset voltage drift to less than 3 µV/°C. This level
of dc precision is achieved utilizing Analog’s laser wafer drift 2. The AD648 is pin compatible with industry standard dual op
trimming process. The combination of low quiescent current amps such as the LF442, TL062, and AD642, enabling
and low offset voltage drift minimizes changes in input offset designers to improve performance while achieving a reduc-
voltage due to self-heating effects. Five additional grades are tion in power dissipation of up to 85%.
offered over the commercial, industrial and military temperature 3. Guaranteed low input offset voltage (2 mV max) and drift
ranges. (20 µV/°C max) for the AD648J are achieved utilizing Analog
The AD648 is recommended for any dual supply op amp appli- Devices’ laser drift trimming technology.
cation requiring low power and excellent dc and ac perfor- 4. Analog Devices specifies each device in the warmed-up con-
mance. In applications such as battery-powered, precision dition, insuring that the device will meet its published specifi-
instrument front ends and CMOS DAC buffers, the AD648’s cations in actual use.
excellent combination of low input offset voltage and drift, low 5. Matching characteristics are excellent for all grades. The
bias current and low 1/f noise reduces output errors. High input offset voltage matching between amplifiers in the
common-mode rejection (86 dB, min on the “C” grade) and AD648J is within 2 mV, for the C grade matching is within
high open-loop gain ensures better than 12-bit linearity in high 0.4 mV.
impedance, buffer applications.
6. Crosstalk between amplifiers is less than –120 dB at 1 kHz.
The AD648 is pinned out in a standard dual op amp configura-
tion and is available in seven performance grades. The AD648J 7. The AD648 is available in chip form.
and AD648K are rated over the commercial temperature range
of 0°C to +70°C. The AD648A, AD648B and AD648C are
rated over the industrial temperature range of –40°C to +85°C.

REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD648–SPECIFICATIONS (@ + 258C and V = 615 V dc, unless otherwise noted) S

Model AD648J/A/S AD648K/B/T AD648C

Min Typ Max Min Typ Max Min Typ Max Units
INPUT OFFSET VOLTAGE 1
Initial Offset 0.75 2.0 0.3 1.0 0.10 0.3 mV
TMIN to TMAX 3.0/3.0/3.0 1.5/1.5/2.0 0.5 mV
vs. Temperature 20 10 3.0 µV/°C
vs. Supply 80 86 86 dB
vs. Supply, T MIN to TMAX 76/76/76 80 80 dB
Long-Term Offset Stability 15 15 15 µV/month
INPUT BIAS CURRENT
Either Input, 2 VCM = 0 5 20 3 10 3 10 pA
Either Input 2 at TMAX, VCM = 0 0.45/1.3/20 0.25/0.65/10 0.65 nA
Max Input Bias Current Over
Common-Mode Voltage Range 30 15 15 pA
Offset Current, V CM = 0 5 10 2 5 2 5 pA
Offset Current at T MAX 0.25/0.7/10 0.15/0.35/5 0.35 nA
MATCHING CHARACTERISTICS 3
Input Offset Voltage 1.0 2.0 0.5 1.0 0.2 0.4 mV
Input Offset Voltage T MIN to T MAX 3.0/3.0/3.0 1.5/1.5/2.0 0.5 mV
Input Offset Voltage vs. Temperature 8 5 2.5 µV/°C
Input Bias Current 10 5 5 pA
Crosstalk –120 –120 –120 dB
INPUT IMPEDANCE
Differential 1 × 101 2i3 1 × 1012i3 1 × 1012i3 ΩipF
Common Mode 3 × 1012i3 3 × 1012i3 3 × 1012i3 ΩipF
INPUT VOLTAGE RANGE
Differential 4 ± 20 ± 20 ± 20 V
Common Mode ± 11 ± 12 ± 11 ± 12 ± 11 ± 12 V
Common-Mode Rejection
VCM = ± 10 V 76 82 86 dB
TMIN to TMAX 76/76/76 82 86 dB
VCM = ± 11 V 70 76 76 dB
TMIN to TMAX 70/70/70 76 76 dB
INPUT VOLTAGE NOISE
Voltage 0.1 Hz to 10 Hz 2 2 2 4.0 µV p-p
f = 10 Hz 80 80 80 nV/√Hz
f = 100 Hz 40 40 40 nV/√Hz
f = 1 kHz 30 30 30 nV/√Hz
f = 10 kHz 30 30 30 nV/√Hz
INPUT CURRENT NOISE
f = 1 kHz 1.8 1.8 1.8 fA/√Hz
FREQUENCY RESPONSE
Unity Gain, Small Signal 0.8 1.0 0.8 1.0 0.8 1.0 MHz
Full Power Response 30 30 30 kHz
Slew Rate, Unity Gain 1.0 1.8 1.0 1.8 1.0 1.8 V/µs
Settling Time to ± 0.01% 8 8 8 µs
OPEN-LOOP GAIN
VO = ± 10 V, RL ≥ 10 kΩ 300 1000 300 1000 300 1000 V/mV
TMIN to TMAX, RL ≥ 10 kΩ 300/300/300 700 300 700 300 700 V/mV
VO = ± 10 V, R L ≥ 5 kΩ 150 500 150 500 150 500 V/mV
TMIN to TMAX, RL ≥ 5 kΩ 150/150/150 300 150 300 150 300 V/mV
OUTPUT CHARACTERISTICS
Voltage @ R L ≥ 10 kΩ,
TMIN to TMAX ± 12/± 12/± 12 ± 13 ± 12 ± 13 ± 12 ± 13 V
Voltage @ R L ≥ 5 kΩ,
TMIN to TMAX ± 11/± 11/± 11 ± 12 ± 11 ± 12 ± 11 ± 12 V
Short Circuit Current 15 15 15 mA
POWER SUPPLY
Rated Performance ± 15 ± 15 ± 15 V
Operating Range ± 4.5 ± 18 ± 4.5 ± 18 ± 4.5 ± 18 V
Quiescent Current (Both Amplifiers) 340 400 340 400 340 400 µA
TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0°C to +70°C) AD648J AD648K
Industrial (–40°C to +85°C) AD648A AD648B AD648C
Military (–55°C to +125°C) AD648S AD648T
PACKAGE OPTIONS
SOIC (R-8) AD648JR AD648KR
Plastic (N-8) AD648JN AD648KN
Cerdip (Q-8) AD648AQ, AD648SQ, AD648SQ/883B AD648BQ, AD648TQ/883B AD648CQ
Metal Can (H-08A) AD648AH AD648BH, AD648TH/883B
Tape and Reel AD648JR-REEL, AD648JR-REEL7 AD648KR-REEL, AD648KR-REEL7
Chips Available AD648JChips, AD648SChips

–2– REV. C
 AD648
NOTES
1
Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C.
2
Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C. For higher temperature, the current doubles
every 10°C.
3
Matching is defined as the difference between parameters of the two amplifiers.
4
Defined as voltages between inputs, such that neither exceeds ± 10 V from ground.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS 1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (Q, H) . . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD648J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD648A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD648S/T . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Thermal Characteristics:
8-Pin Plastic Package: θJA = 165°C/Watt
8-Pin Cerdip Package: θJC = 22°C/Watt; θJA = 110°C/Watt
8-Pin Metal Package: θJC = 65°C/Watt; θJA = 150°C/Watt
8-Pin SOIC Package: θJC = 42°C/Wat; θJA = 160°C/Watt
3
For supply voltages less than ± 18 V, the absolute maximum input voltage is equal
to the supply voltage.

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD648 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. C –3–
AD648—Typical Characteristics

–4– REV. C
 AD648

REV. C –5–
AD648
APPLICATION NOTES
The AD648 is a pair of JFET-input op amps with a guaranteed
maximum IB of less than 10 pA, and offset and drift laser-
trimmed to 0.3 mV and 3 µV/°C, respectively (AD648C). AC
specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and
8 µs settling time for a 20 V step to ± 0.01%—all at a supply
current less than 400 µA. To capitalize on the device’s perfor-
mance, a number of error sources should be considered.
The minimal power drain and low offset drift of the AD648 re-
Figure 22. Board Layout for Guarding Inputs
duce self-heating or “warm-up” effects on input offset voltage,
making the AD648 ideal for on/off battery powered applica-
INPUT PROTECTION
tions. The power dissipation due to the AD648’s 400 µA supply
The AD648 is guaranteed to withstand input voltages equal to
current has a negligible effect on input current, but heavy out-
the power supply potential. Exceeding the negative supply volt-
put loading will raise the chip temperature. Since a JFET’s
age on either input will forward bias the substrate junction of
input current doubles for every 10°C rise in chip temperature,
the chip. The induced current may destroy the amplifier due to
this can be a noticeable effect.
excess heat.
The amplifier is designed to be functional with power supply
Input protection is required in applications such as a flame de-
voltages as low as ± 4.5 V. It will exhibit a higher input offset
tector in a gas chromatograph, where a very high potential may
voltage than at the rated supply voltage of ± 15 V, due to power
be applied to the input terminals during a sensor fault condi-
supply rejection effects. Common-mode range extends from 3 V
tion. Figures 23a and 23b show simple current limiting schemes
more positive than the negative supply to 1 V more negative
that can be used. RPROTECT should be chosen such that the
than the positive supply. Designed to cleanly drive up to 10 kΩ
maximum overload current is 1.0 mA (for example 100 kΩ for a
and 100 pF loads, the AD648 will drive a 2 kΩ load with re-
100 V overload).
duced open-loop gain.
Figure 21 shows the recommended crosstalk test circuit. A typi-
cal value for crosstalk is –120 dB at 1 kHz.

Figure 23a. Input Protection of l-to-V Converter

Figure 21. Crosstalk Test Circuit

LAYOUT
To take full advantage of the AD648’s 10 pA max input current,
parasitic leakages must be kept below an acceptable level. The
practical limit of the resistance of epoxy or phenolic circuit
board material is between 1 × 1012 Ω and 3 × 1012 Ω. This can
result in an additional leakage of 5 pA between an input of 0 V Figure 23b. Voltage Follower Input Protection Method
and a –15 V supply line. Teflon or a similar low leakage material Figure 23b shows the recommended method for protecting a
(with a resistance exceeding 1017 Ω) should be used to isolate voltage follower from excessive currents due to high voltage
high impedance input lines from adjacent lines carrying high breakdown. The protection resistor, RP, limits the input current.
voltages. The insulator should be kept clean, since contaminants A nominal value of 100 kΩ will limit the input current to less
will degrade the surface resistance. than 1 mA with a 100 volt input voltage applied.
A metal guard completely surrounding the high impedance The stray capacitance between the summing junction and
nodes and driven by a voltage near the common-mode input ground will produce a high frequency roll-off with a corner
potential can also be used to reduce some parasitic leakages. frequency equal to:
The guarding pattern in Figure 22 will reduce parasitic leakage
due to finite board surface resistance; but it will not compensate f corner = 1
for a low volume resistivity board. 2 π RP Cstray
Accordingly, a 100 kΩ value for RP with a 3 pF Cstray will cause
a 3 dB corner frequency to occur at 531 kHz.

–6– REV. C
 AD648
Figure 23c shows a diode clamp protection scheme for an I-to-V CMOS DAC’s output current to a voltage and provides the
converter using low leakage diodes. Because the diodes are con- necessary level shifting to achieve a bipolar voltage output. The
nected to the op amp’s summing junction, which is a virtual circuit operates with a 12-bit plus sign input code. The transfer
ground, their leakage contribution is minimal. function is shown in Figure 25.
The AD7592 is a fully protected dual CMOS SPDT switch with
data latches. R4 and R5 should match to within 0.01% to main-
tain the accuracy of the converter. A mismatch between R4 and
R5 introduces a gain error. Overall gain is trimmed by adjusting
RIN. The AD648’s low input offset voltage, low drift over tem-
perature, and excellent dynamics make it an attractive low
power output buffer.
Figure 23c. I-to-V Converter with Diode Input Protection The input offset voltage of the AD648 output amplifier results
in an output error voltage. This error voltage equals the input
Exceeding the negative common-mode range on either input offset voltage of the op amp times the noise gain of the amplifier.
terminal causes a phase reversal at the output, forcing the ampli-
fier output to the corresponding high or low state. Exceeding That is:
the negative common mode on both inputs simultaneously
VOS Output = VOS Input 1 + FB 
R
forces the output high. Exceeding the positive common-mode
RO
range on a single input doesn’t cause a phase reversal; but if
both inputs exceed the limit, the output will be forced high. In RFB is the feedback resistor for the op amp, which is internal to
all cases, normal amplifier operation is resumed when input the DAC. RO is the DAC’s R-2R ladder output resistance. The
voltages are brought back within the common-mode range. value of RO is code dependent. This has the effect of changing
the offset error voltage at the amplifier’s output. An output am-
D/A CONVERTER BIPOLAR OUTPUT BUFFER plifier with a sub millivolt input offset voltage is needed to pre-
The circuit in Figure 24 provides 4 quadrant multiplication with serve the linearity of the DAC’s transfer function.
a resolution of 12 bits. The AD648 is used to convert the AD7545

Figure 24. 12-Bit Plus Sign Magnitude D/A Converter

SIGN BIT BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT

0 1111 1111 1111 +VIN 3 (4095/4096)

0 0000 0000 0000 0 VOLTS
1 0000 0000 0000 0 VOLTS
1 1111 1111 1111 –VIN 3 (4095/4096)

NOTE: SIGN BIT AT "0" CONNECTS THE NONINVERTING INPUT OF

A2 TO ANALOG COMMON

Figure 25. Sign Magnitude Code Table

REV. C –7–
AD648
The AD648 in this configuration provides a 700 kHz small sig- DUAL PHOTODIODE PREAMP
nal bandwidth and 1.8 V/µs typical slew rate. The 33 pF capaci- The performance of the dual photodiode preamp shown in Fig-
tor across the feedback resistor optimizes the circuit’s response. ure 27 is enhanced by the AD648’s low input current, input
The oscilloscope photos in Figures 26a and 26b show small and voltage offset, and offset voltage drift. Each photodiode sources
large signal outputs of the circuit in Figure 24. Upper traces a current proportional to the incident light power on its surface.
show the input signal VIN. Lower traces are the resulting output RF converts the photodiode current to an output voltage equal
voltage with the DAC’s digital input set to all 1s. The circuit to RF × IS.
settles to ± 0.01% for a 20 V input step in 14 µs. An error budget illustrating the importance of low amplifier in-
put current, voltage offset, and offset voltage drift to minimize
output voltage errors can be developed by considering the
equivalent circuit for the small (0.2 mm2 area) photodiode
shown in Figure 27. The input current results in an error pro-
portional to the feedback resistance used. The amplifier’s offset
will produce an error proportional to the preamp’s noise gain
(1+RF/RSH), where RSH is the photodiode shunt resistance. The
amplifier’s input current will double with every 10°C rise in
temperature, and the photodiode’s shunt resistance halves with
every 10°C rise. The error budget in Figure 28 assumes a room
temperature photodiode RSH of 500 MΩ, and the maximum in-
put current and input offset voltage specs of an AD648C.
The capacitance at the amplifier’s negative input (the sum of the
photodiode’s shunt capacitance, the op amp’s differential input
capacitance, stray capacitance due to wiring, etc.) will cause a
Figure 26a. Response to ± 20 V p-p Reference Square rise in the preamp’s noise gain over frequency. This can result in
Wave excess noise over the bandwidth of interest. CF reduces the
noise gain “peaking” at the expense of signal bandwidth.

Figure 26b. Response to ± 100 mV p-p Reference Square

Wave
Figure 27. A Dual Photodiode Pre-Amp

TEMP RSH VOS IB

8C (MV) (mV) (1 + RF/RSH) VOS (pA) IBRF TOTAL
–25 15,970 150 151 mV 0.30 30 mV 181 mV
0 2,830 225 233 mV 2.26 262 mV 495 mV
+25 500 300 360 mV 10.00 1.0 mV 1.36 mV
+50 88.5 375 800 mV 56.6 5.6 mV 6.40 mV
+75 15.6 450 3.33 mV 320 32 mV 35.3 mV
+85 7.8 480 6.63 mV 640 64 mV 70.6 mV

Figure 28. Photodiode Pre-Amp Errors Over Temperature

–8– REV. C
 AD648
INSTRUMENTATION AMPLIFIER Gains of 1 to 100 can be accommodated with gain nonlinearities
The AD648J’s maximum input current of 20 pA per amplifier of less than 0.01%. The maximum input current is 30 pA over
makes it an excellent building block for the high input imped- the common-mode range, with a common-mode impedance of
ance instrumentation amplifier shown in Figure 29. Total cur- over 1 × 1012Ω. The capacitors C1, C2, C3 and C4 compensate
rent drain for this circuit is under 600 µA. This configuration is for peaking in the gain over frequency which is caused by input
optimal for conditioning differential voltages from high imped- capacitance.
ance sources. To calibrate this circuit, first adjust trimmer R1 for common-
The overall gain of the circuit is controlled by RG, resulting in mode rejection with +10 volts dc applied to the input pins.
the following transfer function: Next, adjust R2 for zero offset at VOUT with both inputs
VOUT (R3 + R4) grounded. Trim the circuit a second time for optimal
= 1+ performance.
V IN RG
The –3 dB small signal bandwidth for this low power instru-
mentation amplifier is 700 kHz for a gain of 1 and 10 kHz for a
gain of 100. The typical output slew rate is 1.8 V/µs.

Figure 29. Low Power Instrumentation Amplifier

REV. C –9–
AD648
LOG RATIO AMPLIFIER which have a positive 3500 ppm/°C temperature coefficient.
Log ratio amplifiers are useful for a variety of signal condition- The transfer function for the output voltage is:
ing applications, such as linearizing exponential transducer out- VOUT = 1 V log10 (I2/I1)
puts and compressing analog signals having a wide dynamic
range. The AD648’s picoamp level input current and low input Frequency compensation is provided by R11, R12, C1, and C2.
offset voltage make it a good choice for the front-end amplifier Small signal bandwidth is approximately 300 kHz at input cur-
of the log ratio circuit shown in Figure 30. This circuit produces rents above 100 µA and will proportionally decrease with lower
an output voltage equal to the log base 10 of the ratio of the in- signal levels. D1, D2, R13, and R14 compensate for the effects
put currents I1 and I2. Resistive inputs R1 and R2 are provided of the two logging transistors’ ohmic emitter resistance.
for voltage inputs. To trim this circuit, set the two input currents to 10 µA and ad-
Input currents I1 and I2 set the collector currents of Q1 and Q2, just VOUT to zero by adjusting the potentiometer on A3. Then
a matched pair of logging transistors. Voltages at points A and B set I2 to 1 µA and adjust the scale factor such that the output
are developed according to the following familiar diode equation: voltage is 1 V by trimming potentiometer R10. Offset adjust-
ment for A1 and A2 is provided to increase the accuracy of the
VBE = (kT/q) ln (IC/IES) voltage inputs.
In this equation, k is Boltzmann’s constant, T is absolute tem- This circuit ensures a 1% log conformance error over an input
perature, q is an electron charge, and IES is the reverse satura- current range of 300 pA to l mA, with low level accuracy limited
tion current of the logging transistors. The difference of these by the AD648’s input current. The low level input voltage accu-
two voltages is taken by the subtractor section and scaled by a racy of this circuit is limited by the input offset voltage and drift
factor of approximately 16 by resistors R9, R10 and R8. Tem- of the AD648.
perature compensation is provided by resistors R8 and R15,

Figure 30. Precision Log Ratio Amplifier

–10– REV. C
 AD648
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

REV. C –11–
–12–
PRINTED IN U.S.A. C1023–5–10/88