Ordering number : EN4921B

CMOS LSI

LC72131, 72131M

AM/FM PLL Frequency Synthesizer

Overview Package Dimensions

The LC72131 and LC72131M are PLL frequency unit: mm
synthesizers for use in tuners in radio/cassette players. 3059-DIP22S
They allow high-performance AM/FM tuners to be
implemented easily. [LC72131]

Applications
PLL frequency synthesizer

Functions
• High speed programmable dividers
— FMIN: 10 to 160 MHz ..........pulse swallower
(built-in divide-by-two prescaler)
— AMIN: 2 to 40 MHz ..............pulse swallower
0.5 to 10 MHz ...........direct division
• IF counter
— IFIN: 0.4 to 12 MHz ...........AM/FM IF counter SANYO: DIP22S
• Reference frequencies
— Twelve selectable frequencies unit: mm
(4.5 or 7.2 MHz crystal) 3036B-MFP20
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50 and 100 kHz
• Phase comparator [LC72131M]
— Dead zone control
— Unlock detection circuit
— Deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 4
— Input or output ports: 2
— Support clock time base output
• Serial data I/O
— Support CCB format communication with the
system controller.
SANYO: MFP20
• Operating ranges
— Supply voltage........................4.5 to 5.5 V
— Operating temperature............–40 to +85°C
• Packages
— DIP22S/MFP20

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
62096HA (OT)/O3195HA (OT)/92294TH (OT) No. 4921-1/23

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 LC72131, 72131M

Pin Assignments

No. 4921-2/23

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Block Diagram

No. 4921-3/23

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Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter Symbol Pins Ratings Unit

Supply voltage VDD max VDD –0.3 to +7.0 V
VIN1 max CE, CL, DI, AIN –0.3 to +7.0 V
Maximum input voltage VIN2 max XIN, FMIN, AMIN, IFIN –0.3 to VDD + 0.3 V
VIN3 max IO1, IO2 –0.3 to +15 V
VO1 max DO –0.3 to +7.0 V
Maximum output voltage VO2 max XOUT, PD –0.3 to VDD + 0.3 V
VO3 max BO1 to BO4, IO1, IO2, AOUT –0.3 to +15 V
IO1 max BO1 0 to 3.0 mA
Maximum output current IO2 max AOUT, DO 0 to 6.0 mA
IO3 max BO2 to BO4, IO1, IO2 0 to 10.0 mA
LC72131: DIP22S 350
Allowable power dissipation Pd max Ta ≤ 85°C mW
LC72131M: MFP20 180
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V

Parameter Symbol Pins Conditions min typ max Unit

Supply voltage VDD VDD 4.5 5.5 V
VIH1 CE, CL, DI 0.7 VDD 6.5 V
Input high-level voltage
VIH2 IO1, IO2 0.7 VDD 13 V
Input low-level voltage VIL CE, CL, DI, IO1, IO2 0 0.3 VDD V
VO1 DO 0 6.5 V
Output voltage BO1 to BO4, IO1, IO2,
V O2 0 13 V
AOUT
fIN1 XIN VIN1 1 8 MHz
fIN2 FMIN VIN2 10 160 MHz
Input frequency fIN3 AMIN VIN3, SNS = 1 2 40 MHz
fIN4 AMIN VIN4, SNS = 0 0.5 10 MHz
fIN5 IFIN VIN5 0.4 12 MHz
VIN1 XIN fIN1 400 1500 mVrms
VIN2-1 FMIN f = 10 to 130 MHz 40 1500 mVrms
VIN2-2 FMIN f = 130 to 160 MHz 70 1500 mVrms
Input amplitude VIN3 AMIN fIN3, SNS = 1 40 1500 mVrms
VIN4 AMIN fIN4, SNS = 0 40 1500 mVrms
VIN5-1 IFIN fIN5, IFS = 1 40 1500 mVrms
VIN5-2 IFIN fIN6, IFS = 0 70 1500 mVrms
Supported crystals Xtal XIN, XOUT * 4.0 8.0 MHz

Note: * Recommended crystal oscillator CI values:

CI ≤ 120Ω (For a 4.5 MHz crystal)
CI ≤ 70Ω (For a 7.2 MHz crystal)

<Sample Oscillator Circuit>

Crystal oscillator: HC-49/U (manufactured by Kinseki, Ltd.), CL = 12 pF
C1 = C2 = 15 pF
The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board
pattern, and other items. Therefore we recommend consulting with the manufacturer of the crystal for
evaluation and reliability.

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Electrical Characteristics for the Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V

Parameter Symbol Pins Conditions min typ max Unit

Rf1 XIN 1.0 MΩ
Rf2 FMIN 500 kΩ
Built-in feedback resistance
Rf3 AMIN 500 kΩ
Rf4 IFIN 250 kΩ
Rpd1 FMIN 200 kΩ
Built-in pull-down resistor
Rpd2 AMIN 200 kΩ
Hysteresis VHIS CE, CL, DI, IO1, IO2 0.1 VDD V
Output high level voltage VOH1 PD IO = –1 mA VDD – 1.0 V
VOL1 PD IO = 1 mA 1.0 V
IO = 0.5 mA 0.5 V
VOL2 BO1
IO = 1 mA 1.0 V
IO = 1 mA 0.2 V
VOL3 DO
Output low level voltage IO = 5 mA 1.0 V
IO = 1 mA 0.2 V
VOL4 BO2 to BO4, IO1, IO2 IO = 5 mA 1.0 V
IO = 8 mA 1.6 V
VOL5 AOUT IO = 1 mA, AIN = 1.3 V 0.5 V
IIH1 CE, CL, DI VI = 6.5 V 5.0 V
IIH2 IO1, IO2 VI = 13 V 5.0 µA
IIH3 XIN VI = VDD 2.0 11 µA
Input high level current
IIH4 FMIN, AMIN VI = VDD 4.0 22 µA
IIH5 IFIN VI = VDD 8.0 44 µA
IIH6 AIN VI = 6.5 V 200 nA
IIL1 CE, CL, DI VI = 0 V 5.0 µA
IIL2 IO1, IO2 VI = 0 V 5.0 µA
IIL3 XIN VI = 0 V 2.0 11 µA
Input low level current
IIL4 FMIN, AMIN VI = 0 V 4.0 22 µA
IIL5 IFIN VI = 0 V 8.0 44 µA
IIL6 AIN VI = 0 V 200 nA
BO1 to BO4, AOUT,
IOFF1 VO = 13 V 5.0 µA
Output off leakage current IO1, IO2
IOFF2 DO VO = 6.5 V 5.0 µA
High level three-state
IOFFH PD VO = VDD 0.01 200 nA
off leakage current
Low level three-state
IOFFL PD VO = 0 V 0.01 200 nA
off leakage current
Input capacitance CIN FMIN 6 pF
Xtal = 7.2 MHz,
IDD1 VDD fIN2 = 130 MHz, 5 10 mA
VIN2 = 40 mVrms
PLL block stopped
Current drain (PLL INHIBIT),
IDD2 VDD 0.5 mA
Xtal oscillator operating
(Xtal = 7.2 MHz)
PLL block stopped
IDD3 VDD 10 µA
Xtal oscillator stopped

No. 4921-5/23

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Pin Functions

Pin No.
Symbol (MFP pin Nos. are Type Functions Circuit configuration
in parentheses.)

XIN 1 (1) • Crystal resonator connection

Xtal OSC
XOUT 22 (20) (4.5/7.2 MHz)

• FMIN is selected when the serial data input DVS bit is

set to 1.
• The input frequency range is from 10 to 160 MHz.
Local oscillator • The input signal passes through the internal divide-by-
FMIN 16 (14)
signal input two prescaler and is input to the swallow counter.
• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.

• AMIN is selected when the serial data input DVS bit is

set to 0.
• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and
Local oscillator
AMIN 15 (13) the divisor used will be the value set.
signal input
• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.

Set this pin high when inputting (DI) or outputting (DO)

CE 3 (2) Chip enable
serial data.

• Used as the synchronization clock when inputting (DI) or

CL 5 (4) Clock
outputting (DO) serial data.

• Inputs serial data transferred from the controller to the

DI 4 (3) Data input
LC72131.

• Outputs serial data transferred from the LC72131 to the

controller.
DO 6 (5) Data output
The content of the output data is determined by the
serial data DOC0 to DOC2.

• The LC72131 power supply pin (VDD = 4.5 to 5.5 V)

VDD 17 (15) Power supply • The power on reset circuit operates when power is first
applied.

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Continued from preceding page.

Pin No.
Symbol (MFP pin Nos. are Type Functions Circuit configuration
in parentheses.)

VSS 21 (19) Ground • The LC72131 ground —

• Dedicated output pins

• The output states are determined by BO1 to BO4 bits in
the serial data.
Data: 0 = open, 1 = low
BO1 7 (6)
• A time base signal (8 Hz) can be output from the BO1
BO2 8 (7)
Output port pin. (When the serial data TBC bit is set to 1.)
BO3 9 (8)
• Care is required when using the BO1 pin, since it has a
BO4 10 (9)
higher on impedance that the other output ports (pins
BO2 to BO4).
• All output ports are set to the open state following a
power on reset.

• I/O dual-use pins

• The direction (input or output) is determined by bits IOC1
and IOC2 in the serial data.
Data: 0 = input port, 1 = output port
• When specified for use as input ports:
The state of the input pin is transmitted to the controller
over the DO pin.
IO1 11 (10)
I/O port Input state: low = 0 data value
IO2 13 (12)
high = 1 data value
• When specified for use as output ports:
The output states are determined by the IO1 and IO2
bits in the serial data.
Data: 0 = open, 1 = low
• These pins function as input pins following a power on
reset.

• PLL charge pump output

When the frequency generated by dividing the local
oscillator frequency by N is higher than the reference
Charge pump
PD 18 (16) frequency, a high level is output from the PD pin.
output
Similarly, when that frequency is lower, a low level is
output. The PD pin goes to the high impedance state
when the frequencies match.

AIN 19 (17) LPF amplifier • The n-channel MOS transistor used for the PLL active
AOUT 20 (18) transistor low-pass filter.

• Accepts an input in the frequency range 0.4 to 12 MHz.

• The input signal is directly transmitted to the IF counter.
• The result is output starting the MSB of the IF counter
IFIN 12 (11) IF counter
using the DO pin.
• Four measurement periods are supported: 4, 8, 32, and
64 ms.

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Serial Data I/O Methods

The LC72131 inputs and outputs data using the Sanyo CCB (computer control bus) audio LSI serial bus format. This
LSI adopts an 8-bit address format CCB.

Address
I/O mode Function
B0 B1 B2 B3 A0 A1 A2 A3

• Control data input mode (serial data input)

• 24 data bits are input.
1 IN1 (82) 0 0 0 1 0 1 0 0
• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.

• Control data input mode (serial data input)

• 24 data bits are input.
2 IN2 (92) 1 0 0 1 0 1 0 0
• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.

Data output mode (serial data output)

• The number of bits output is equal to the number of clock
3 OUT (A2) 0 1 0 1 0 1 0 0 cycles.
• See the “DO Output Data (serial data output) Structure”
item for details on the meaning of the output data.

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1. DI Control Data (Serial Data Input) Structure

• IN1 Mode

• IN2 Mode

No. 4921-9/23

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2. DI Control Data Functions

No. Control block/data Functions Related data

Programmable divider data • Data that sets the divisor of the programmable divider.
P0 to P15 A binary value in which P15 is the MSB. The LSB changes depending on
DVS and SNS. (*: don’t care)

DVS SNS LSB Divisor setting (N) Actual divisor

1 * P0 272 to 65535 Twice the value of the setting
0 1 P0 272 to 65535 The value of the setting
0 0 P4 4 to 4095 The value of the setting
(1) Note: P0 to P3 are ignored when P4 is the LSB.
DVS, SNS • Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches
the input frequency range. (*: don’t care)

DVS SNS Input pin Input frequency range

1 * FMIN 10 to 160 MHz
0 1 AMIN 2 to 40 MHz
0 0 AMIN 0.5 to 10 MHz
Note: See the “Programmable Divider Structure” item for more information.
Reference divider data • Reference frequency (fref) selection data.
R0 to R3
R3 R2 R1 R0 Reference frequency (kHz)
0 0 0 0 100
0 0 0 1 50
0 0 1 0 25
0 0 1 1 25
0 1 0 0 12.5
0 1 0 1 6.25
0 1 1 0 3.125
0 1 1 1 3.125
1 0 0 0 10
1 0 0 1 9
1 0 1 0 5
(2) 1 0 1 1 1
1 1 0 0 3
1 1 0 1 15
1 1 1 0 PLL INHIBIT + Xtal OSC STOP
1 1 1 1 PLL INHIBIT
Note: PLL INHIBIT
The programmable divider block and the IF counter block are stopped, the FMIN,
AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump
goes to the high impedance state.
XS • Crystal resonator selection
XS = 0: 4.5 MHz
XS = 1: 7.2 MHz
The 7.2 MHz frequency is selected after the power-on reset.
IF counter control data • IF counter measurement start data
CTE CTE = 1: Counter start
CTE = 0: Counter reset
GT0, GT1 • Determines the IF counter measurement period. IFS

GT1 GT0 Measurement time (ms) Wait time (ms)

(3)
0 0 4 3 to 4
0 1 8 3 to 4
1 0 32 7 to 8
1 1 64 7 to 8
Note: See the “IF Counter Structure” item for more information.
I/O port specification data • Specifies the I/O direction for the bidirectional pins IO1 and IO2.
(4)
IOC1, IOC2 Data: 0 = input mode, 1 = output mode
Output port data • Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports
BO1 to BO4, IO1, IO2 Data: 0 = open, 1 = low IOC1
(5)
IOC2
• The data = 0 (open) state is selected after the power-on reset.

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Continued from preceding page.

No. Control block/data Functions Related data

DO pin control data • Data that determines the DO pin output
DOC0, DOC1, DOC2
DOC2 DOC1 DOC0 DO pin state
0 0 0 Open
0 0 1 Low when the unlock state is detected
0 1 0 end-UC*1
0 1 1 Open
1 0 0 Open
1 0 1 The IO1 pin state*2
1 1 0 The IO2 pin state*2
1 1 1 Open

The open state is selected after the power-on reset.

Note: 1. end-UC: Check for IF counter measurement completion
UL0, UL1,
(6) CTE,
IOC1, IOC2

➀ When end-UC is set and the IF counter is started (i.e., when CTE is changed
from zero to one), the DO pin automatically goes to the open state.
➁ When the IF counter measurement completes, the DO pin goes low to indicate
the measurement completion state.
➂ Depending on serial data I/O (CE: high) the DO pin goes to the open state.
2. Goes to the open state if the I/O pin is specified to be an output port.
Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE
high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).
Also, the DO pin during a data output period (an OUT mode period with CE high)
will output the contents of the internal DO serial data in synchronization with the
CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2).
Unlock detection data • Selects the phase error (øE) detection width for checking PLL lock.
UL0, UL1 A phase error in excess of the specified detection width is seen as an unlocked state.

UL1 UL0 øE detection width Detector output

0 0 Stopped Open DOC0,
(7) 0 1 0 øE is output directly DOC1,
DOC2
1 0 ±0.55 µs øE is extended by 1 to 2 ms
1 1 ±1.11 µs øE is extended by 1 to 2 ms
Note: In the unlocked state the DO pin goes low and the UL bit in the serial data
becomes zero.
Phase comparator • Controls the phase comparator dead zone.
control data
DZ0, DZ1 DZ1 DZ0 Dead zone mode
0 0 DZA
0 1 DZB
(8)
1 0 DZC
1 1 DZD

Dead zone widths: DZA < DZB < DZC < DZD
Clock time base Setting TBC to one causes an 8 Hz, 40% duty clock time base signal to be output
(9) BO1
TBC from the BO1 pin. (BO1 data is invalid in this mode.)
Charge pump control data • Forcibly controls the charge pump output.
DLC
DLC Charge pump output
0 Normal operation
(10) 1 Forced low
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to
low and setting Vtune to VCC. (This is the deadlock clearing circuit.)

Continued on next page.

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Continued from preceding page.

No. Control block/data Functions Related data

IF counter control data • This data must be set 1 in normal mode.
(11) IFS Though if this value is set to zero, the system enters input sensitivity degradation mode,
and the sensitivity is reduced to 10 to 30 mVrms.
* See the “IF Counter Operation” item for details.
LSI test data • LSI test data
TEST 0 to TEST3 TEST0
(12) TEST1 These values must all be set to 0.
TEST2
These test data are set to 0 automatically after the power-on reset.
(13) DNC Don’t care. This data must be set to 0.

3. DO Output Data (Serial Data Output)

• OUT Mode

No. Control block/data Functions Related data

I/O port data • Latched from the pin states of the IO1 and IO2 I/O ports.
I2, I1 • These values follow the pin states regardless of the input or output setting.
IOC1,
(1) • Bits I2, I1 reflect the data latched into each input port when the device changes to OUT Mode.
IOC2
I1 ← IO1 pin state High: 1
I2 ← IO2 pin state Low: 0
PLL unlock data • Latched from the state of the unlock detection circuit.
UL0,
(2) UL UL ← 0: Unlocked
UL1
UL ← 1: Locked or detection stopped mode
IF counter binary data • Latched from the value of the IF counter (20-bit binary counter). CTE,
(3) C19 to C0 C19 ← MSB of the binary counter GT0,
C0 ← LSB of the binary counter GT1

4. DO Output Data

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5. Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75 µs, tLC ≤ 0.75 µs

6. Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75 µs, tDC, tDH ≤ 0.35 µs

Note: Since the DO pin is an n-channel open-drain pin, the time for the data to change (tDC and tDH) will differ depending on the value of the pull-up
resistor and printed circuit board capacitance.

No. 4921-13/23

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7. Serial Data Timing

Parameter Symbol Pins Conditions min typ max Unit

Data setup time tSU DI, CL 0.75 µs
Data hold time tHD DI, CL 0.75 µs
Clock low-level time tCL CL 0.75 µs
Clock high-level time tCH CL 0.75 µs
CE wait time tEL CE, CL 0.75 µs
CE setup time tES CE, CL 0.75 µs
CE hold time tEH CE, CL 0.75 µs
Data latch change time tLC 0.75 µs

tDC DO, CL Differs depending on the

value of the pull-up resistor
Data output time 0.35 µs
and the printed circuit board
tDH DO, CE capacitances.

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Programmable Divider Structure

DVS SNS Input pin Set divisor Actual divisor: N Input frequency range (MHz)
A 1 * FMIN 272 to 65535 Twice the set value 10 to 160
B 0 1 AMIN 272 to 65535 The set value 2 to 40
C 0 0 AMIN 4 to 4095 The set value 0.5 to 10
Note: * Don’t care.

1. Programmable Divider Calculation Examples

• FM, 50 kHz steps (DVS = 1, SNS = *, FMIN selected)
FM RF = 90.0 MHz (IF = +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0)
100.7 MHz (FM VCO) ÷ 25 kHz (fref) ÷ 2 (FMIN: divide-by-two prescaler) = 2014 → 07DE (HEX)

• SW, 5 kHz steps (DVS = 0, SNS = 1, AMIN high-speed side selected)

SW RF = 21.75 MHz (IF = +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1)
22.2 MHz (SW VCO) ÷ 5 kHz (fref) = 4440 → 1158 (HEX)

• MW, 10 kHz steps (DVS = 0, SNS = 0, AMIN low-speed side selected)

MW RF = 1000 kHz (IF = +450 kHz)
MW VCO = 1450 kHz
PLL fref = 10 kHz (R0 to R2 = 0, R3 = 1)
1450 kHz (MW VCO) ÷ 10 kHz (fref) = 145 → 091 (HEX)

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IF Counter Structure

The LC72131 IF counter is a 20-bit binary counter. The result, i.e., the counter’s msb, can be read serially from the DO pin.

Measurement time
GT1 GT0
Measurement period (GT) (ms) Wait time (twu) (ms)
0 0 4 3 to 4
0 1 8 3 to 4
1 0 32 7 to 8
1 1 64 7 to 8

The IF frequency (Fc) is measured by determining how many pulses were input to an IF counter in a specified
measurement period, GT.
C
Fc = (C = Fc × GT) C: Count value (number of pulses)
GT

1. IF Counter Frequency Calculation Examples

• When the measurement period (GT) is 32 ms, the count (C) is 53980 hexadecimal (342400 decimal):
IF frequency (Fc) = 342400 ÷ 32 ms = 10.7 MHz

• When the measurement period (GT) is 8 ms, the count (C) is E10 hexadecimal (3600 decimal):
IF frequency (Fc) = 3600 ÷ 8 ms = 450 kHz

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2. IF Counter Operation

Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0.

The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the
LC72131 when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period
between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF counter at
the end of the measurement period must be read out during the period that CTE is 1. This is because the IF counter is
reset when CTE is set to 0.

Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station
detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an
IF count operation. Autosearch techniques that use only the IF counter are not recommended, since it is
possible for IF buffer leakage output to cause incorrect stops at points where there is no station.

IFIN minimum input sensitivity standard

f (MHz)
IFS 0.4 ≤ f < 0.5 0.5 ≤ f < 8 8 ≤ f ≤ 12
40 mVrms 40 mVrms
1: Normal mode 40 mVrms
(0.1 to 3 mVrms) (1 to 10 mVrms)
70 mVrms 70 mVrms
0: Degradation mode 70 mVrms
(10 to 15 mVrms) (30 to 40 mVrms)
Note: Values in parentheses are actual performance values presented as reference data.

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Unlock Detection Timing

1. Unlock Detection Determination Timing

Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle,
unlock determination requires a time longer than the period of the reference frequency. However, immediately after
changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the
reference frequency.

Figure 1 Unlocked State Detection Timing

For example, if fref is 1 kHz, i.e., the period is 1 ms, after changing the divisor N, the system must wait at least 2 ms
before checking for the unlocked state.

Figure 2 Circuit Structure

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2. Unlock Detection Software

Figure 3

3. Unlocked State Data Output Using Serial Data Output

In the LC72131, once an unlocked state occurs, the unlocked state serial data (UL) will not be reset until a data input
(or output) operation is performed. At the data output ① point in Figure 3, although the VCO frequency has
stabilized (locked), since no data output has been performed since the divisor N was changed the unlocked state data
remains in the unlocked state. As a result, even though the frequency has stabilized (locked), the system remains
(from the standpoint of the data) in the unlocked state.
Therefore, the unlocked state data acquired at data output ①, which occurs immediately after the divisor N was
changed, should be treated as a dummy data output and ignored. The second data output (data output ②) and
following outputs are valid data.

Locked State Determination Flowchart

4. Directly Outputting Unlocked State Data from the DO Pin (Set by the DO pin control data)

Since the unlocked state (high = locked, low = unlocked) is output directly from the DO pin, the dummy data
processing described in section 3 above is not required. After changing the divisor N, the locking state can be
checked after waiting at least two reference frequency periods.

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Clock Time Base Usage Notes

The pull-up resistor used on the clock time base output pin (BO1) should be at least 100 kΩ. This is to prevent degrading
the VCO C/N characteristics when a loop filter is formed using the built-in low-pass filter transistor. Since the clock time
base output pin and the low-pass filter have a common ground internal to the IC, it is necessary to minimize the time
base output pin current fluctuations and to suppress their influence on the low-pass filter. Also, to prevent chattering we
recommend using a Schmitt input at the controller (microprocessor) that receives this signal.

Other Items

DZ1 DZ0 Dead zone mode Charge pump Dead zone

0 0 DZA ON/ON – –0 s
0 1 DZB ON/ON –0 s
1 0 DZC OFF/OFF +0 s
1 1 DZD OFF/OFF + +0 s

1. Notes on the Phase Comparator Dead Zone

Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the
ON/ON state, the loop can easily become unstable. This point requires special care when designing application
circuits.

The following problems may occur in the ON/ON state.

• Side band generation due to reference frequency leakage

• Side band generation due to both the correction pulse envelope and low frequency leakage

Schemes in which a dead zone is present (OFF/OFF) have good loop stability, but have the problem that acquiring a
high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in
which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA
or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100 dB, or in
which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD,
which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which
either AM stereo is not used or an adequate AM stereo pilot margin can be achieved.

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Dead Zone
The phase comparator compares fp to a reference frequency (fr) as shown in Figure 4. Although the characteristics of
this circuit (see Figure 5) are such that the output voltage is proportional to the phase difference ø (line A), a region
(the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal
circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide
a high S/N ratio.
However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularly-
priced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the
VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit
outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF
signal.

Figure 4 Figure 5

2. Notes on the FMIN, AMIN, and IFIN Pins

Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100 pF is
desirable. In particular, if a capacitance of 1000 pF or over is used for the IF pin, the time to reach the bias level will
increase and incorrect counting may occur due to the relationship with the wait time.

3. Notes on IF Counting → SD must be used in conjunction with the IF counting time

When using IF counting, always implement IF counting by having the microprocessor determine the presence of the
IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in which
auto-searches are performed with only IF counting are not recommended, since they can stop at points where there is
no signal due to leakage output from the IF counter buffer.

4. DO Pin Usage Techniques

In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and for
unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the
controller.

5. Power Supply Pins

A capacitor of at least 2000 pF must be inserted between the power supply VDD and VSS pins for noise exclusion.
This capacitor must be placed as close as possible to the VDD and VSS pins.

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Pin States After the Power ON Reset

Application System Example (Package: MFP20)

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■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.

This catalog provides information as of June, 1996. Specifications and information herein are subject to change
without notice.

No. 4921-23/23

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