A

Project Report On
ELECTRONIC VOTING MACHINE ON FPGA
Submitted in partial fulfilment of the requirements for award of the degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
S.ABHINAYA (15RH1A04L5)
T.SHARANYA (15RH1A04L7)
TANIA PANJWANI (15RH1A04M1)
Under the guidance of
Mr. Dr. T. THIRUMALAI
DGM, CED
Of
ECIL-ECIT
ELECTRONICS CORPORATION OF INDIA LIMITED
(A Government of India Enterprise)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

MALLA REDDY ENGINEERING COLLEGE FOR WOMEN
(Permanently Affiliated to JNTU, Hyderabad, Approved by AICTE - ISO 9001:2015 Certified)
Accredited by NBA & NAAC with ‘A’ Grade
 DECLARATION

We hereby declare that the project entitled “ELECTRONIC VOTING

MACHINE ON FPGA” submitted in partial fulfilment of the requirements for the award of
degree of Bachelor of Technology in Electronics and Communication Engineering. This
dissertation is our original work and the project has not formed the basis for the award of any
degree, associate ship, fellowship or any other similar titles and no part of it has been published
or sent for the publication at the time of submission.

S.ABHINAYA (15RH1A04L5)
T.SHARANYA (15RH1A04L7)
TANIA PANJWANI (15RH1A04M1)
 ACKNOWLEDGEMENT

We wish to take this opportunity to express our deep gratitude to all those who helped,
encouraged, motivated and have extended their cooperation in various ways during our project
work. It is our pleasure to acknowledgement the help of all those individuals who was
responsible for foreseeing the successful completion of our project.

We would like to thank Dr. T. THIRUMALAI (DGM, CED) and express our gratitude
with great admiration and respect to our project guideMs K. Siva Rama Lakshmiand Mr T.
Naveen Kumar Reddyfor their valuable advice and help throughout the development of this
project by providing us with required information without whose guidance, cooperation and
encouragement, this project couldn’t have been materialized.

Last but not the least; we would like to thank the entire respondents for extending their
help in all circumstances.

S.ABHINAYA (15RH1A04L5)
T.SHARANYA (15RH1A04L7)
TANIA PANJWANI (15RH1A04M1)
CONTENTS

1. Introduction to VLSI
1.1) Historical perspective
1.2) VLSI design flow
1.3) Design hierarchy
1.4) Concepts of Regularity, Modularity and Locality

2. FPGA
2.1) Introduction to FPGA
2.2) Programming of FPGA
2.3) Architecture
2.4) Design flow

3. Introduction to VHDL

4. IDEA Algorithm
4.1) Introduction
4.2) History
4.3) Design and Technology
4.4) Procedure to use
4.5) Benefits
4.6) Limitations
4.7) Applications
4.8) Advantages
4.9) Disadvantages
4.10) Conclusion

5. Xilinx Procedure and Waveforms

Organization profile

ECIL was setup the department of Atomic Energy in the year 1967 with a view to
generate a strong indigenous capability in the field of professional grade electronic. The initial
accent was on self-reliance and ECIL was engaged in the Design Development Manufacture and
Marketing of several products emphasis on three technology lines viz. Computers, control
systems and communications. ECIL thus evolved as a multi-product company serving multiple
sectors of Indian economy with emphasis on import of country substitution and development of
products and services that are of economic and strategic significance of the country.

Electronics Corporation of India Limited (ECIL) entered into collaboration with OSI
Systems Inc.(www.osi-systems.com) and set up a joint venture “ECIL_RAPSICAN LIMITED”.
This joint venture manufacture the equipment’s manufactured by RAPSICAN, U.K, and U.S.A
with the same state of art Technology, Requisite Technology is supplied by RAPSICAN and the
final product is manufactured at ECIL facility.

Recognizing the need for generating quality IT professionals and to meet the growing
demand of IT industry, a separate division namely CED had been established to impart quality
and professional IT training under the brand name of ECIT. ECIT, the prestigious offshoot of
ECIL is an emerging winner and is the fore front of IT education in the country.

Mission

ECIL’s mission is to consolidate its status as a valued national asset in the area of
strategic electronics with specific focus on Atomic Energy, Defence, Security and such critical
sectors of strategic national importance.

Objectives

 To continue services to the country’s needs for the peaceful uses Atomic Energy. Special
and Strategic requirements of Defence and Space, Electronics Security System and
Support for Civil aviationsector.
 To establish newer Technology products such as Container Scanning Systems and
Explosive Detectors.
 To re-engineer the company to become nationally and internationally competitive by
paying particular attention to delivery, cost and quality in all its activities.
 To explore new avenues of business and work for growth in strategic sectors in additional
to working realizing technological solutions for the benefit of society in areas like
Agriculture, Education , Health, Power, Transportation, Food, Disaster Management etc.,
Divisions

The company is organized into divisions serving various sectors, national and
commercial importance. They are divisions serving nuclear sector like control and automation
division (CAD), instruments and system division (ISD), divisions serving defense sector like
communication division (CMD), antenna products division (APD), servo system division (SSD)
etc., divisions handling commercial products are telecom division (TCD), customer support
division (CSD), computer education division (CED).

Exports

ECIL is currently operating in major business exports segments like instruments and
system design, industrial / nuclear, servo system, antenna products, communication, control and
automation and several other components.

Services

The company played a very significant role in the training and growth of high caliber
technical managerial man power especially in the fields of computers and information
technology. Though the initial trust was on meeting the control and instrumentation
requirements of the nuclear power program, the expanded scope of self – reliance perused by
ECIL enable the company to develop various products to cater to the needs of defense, civil
aviation, information and broadcasting, telecommunication etc,
ABSTRACT

Electronic Voting Machine (EVM) is a simple electronic device used to record votes in place of
ballot papers and boxes which were used earlier in conventional voting system. Fundamental
right to vote or simply voting in elections forms the basis of democracy. All earlier elections be it
state elections or centre elections a voter used to cast his/her favorite candidate by putting the
stamp against his/her name and then folding the ballot paper as per a prescribed method before
putting it in the Ballot Box. This is a long, time-consuming process and very much prone to
errors. This situation continued till election scene was completely changed by electronic voting
machine. No more ballot paper, ballot boxes, stamping, etc. all this condensed into a simple box
called ballot unit of the electronic voting machine. Because biometric identifiers cannot be easily
misplaced, forged, or shared, they are considered more reliable for person recognition than
traditional token or knowledge based methods. So the Electronic voting system has to be
improved based on the current technologies viz., biometric system. This article discusses
complete review about voting devices, Issues and comparison among the voting methods and
biometric EVM.
 1.Introduction to VLSI

Very – large- scale integration (VLSI) is the process of creating an integrated circuit (IC) by
combining hundreds of thousands of transistors or devices into a single chip. VLSI began in the
1970’s when complex semiconductor and communication technologies were being developed.
The microprocessor is a VLSI device. Before the information of VLSI technology most IC’s had
a limited set of functions they could perform. An electronic circuit might consists of a CPU,
ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.

1.1 History perspective

The history of the transistor dates to the mid- 1920s when several inventors attempted
devices that were indented to control current in solid-state diodes and convert them into triodes.
Success came after World War II, when the use of siliconand germanium crystals as radar
detectors led to improvements if fabrication and theory, Scientist who had worked on radar
returned to solid- state device development. With the invention of transistors at Bell Labs in
1947, the field of electronics shifted from vacuum tubes to solid-state devices.

With the small transistors at their hands, electrical engineers of the 1950’s saw the possibilities
of constructing far more advanced circuits. However, as the complexity of the circuits grew,
problems arose.

One problem was the size of the circuit. A complex circuit like a computer was depended on
speed. If the components were large, the wires interconnecting them must be long. The electric
signals took time to go through the circuit, thus solving the computer.

The invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by
making all the components and the chip out of the same block(monolith) of semiconductor
material. The circuits could be made smaller, and the manufacturing process could be automated.
This led to the idea of integrating all components on a single silicon wafer, which led to small-
scale integration (SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and
then large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of thousands
of transistors on a single chip(later hundreds of thousands, then millions, and now billions (109))
1.2 VLSI Design Flow

At the beginning of a design it is important to specify the recruitments without unduly restricting
the design. The object is to describe the purpose of the design including all aspects, such as the
functions to the realized; timing constrains, and power dissipation requirements, etc.
Descriptions in block level may show either data flow, control flow, or both. The individual
blocks generally correspond to hardware modules. Functional design specifies the functional
relationships among subunits or registers. In general, a description of the IC in either the
functional or the block diagrams domain consists both of the input-output description, and the
way that this behavior is to realized in terms of subordinate modules. In turn each of these
modules is described both in terms of input-output behaviors and as an interconnection of other
modules. These hierarchicalinstead apply to all the domains. The internal description of a
module any be given in another domain. If a module has to internal description is in terms of
mask geometry, which is primitive. Hierarchy and modularity are used in block diagrams or
computer programs. In these domains hierarchy suppresses details, simplifies system design
through a “divide-and-conquer” strategy and leads to more easily understood designs that are
more readily debugged and documented. It can be summarized in a way that when we want to
design a digital system, we need to specify the system performance which is called “system
specifications”. Then the system must be broken down into subunits or registers. So we have a
functional design which specifies the functional relationships among subunits or registers.
“Architecture” usually means the functional design, system specification are often including part
of the subsequent logic design. To plan the Architecture of a VLSI chip, it is always easier to
conceive the system in a similar line to Mead & Conway approach, which they described as OM
project at CALTECH. It consists of

1. Manager chip
2. Data path chip
3. Memory chip
4. Controller chip
5. I/O devices and
6. Clock chip

The data path chip performs mainly the data computations. The sequence of computations is
mainly controlled either by the controller or by the instructions fetched from the microcode
instructions unit. The main subsystems of the data path unit are Arithmetic Logic Unit (ALU),
shifter, register array, and different type of processing elements (PEs) which perform some
definite jobs.

The memory manager chip contains the addresses of the data memory and provided the link to
communicate between the sub blocks. It supports the different data structures. It takes the
decision to push or pop data.

The clock generation block supplies the two clock signals for the chip. According to the need in
some chip a signal clock is available, which can generate two clock phases on chip. The
controller part is generally having the micro program counter that stores the microcode memory
address and its structure is very similar controller of computer system. The system bus interface
sub block provides synchronous / asynchronous communication with the outer systems.

The design of VLSI processor may be subdivided in for major sections.

1. High level design

2. Operative part design
3. Control part design
4. Memory design
5. Design of miscellaneous parts (internal mechanism, clock systems, pads etc…)

The next step is the Logic design of networks which constitutes subunits or registers. When a
system architecture or logic networks are designed, performance and errors are checked by CAD
programs, called as logic simulation. The subject of the logic design is to decide overall structure
of clocks, their interconnection pattern, to specify the structure of data path and to control
sequences of data path. Logic simulator does the logic verification considering the propagating
delays of interconnection signals and the element delay. Simulator also checks whether the
network contains hazards analysis. Logic design and simulating is key issue in VLSI CAS. The
flow of logic design process is determined by the level at which the design can begin steps
leading from a higher level to a circuit description at the logic level.

Today, the following design phases of digital circuits have become widely recognized.

1. Architecture design
2. Register transfer level design
3. Gate level design
4. Cell design
5. Layout design
6. Test program design

Simulators are used in every design phase except for the layout design phase, and play important
roles for the evaluation of system performance, the functional verification and the timing
verification.

There are the following four types of logic simulators according to the levels of abstraction of
simulated elements as shown in table 1.

Simulation primitive Example Signal value

SWITCH TRANSISTOR 0/1 strength

GATE AND GATE 0/1
FUCTION ADDER ETC. 0/1
RTL USER CODED PRIMITIVE 0/1, vector
Table 1 : Simulation primitive

Logic networks have to be converted into electronic circuits. When designers specify electronic
circuit requirements such as speed, power supply voltage, types of logic operations, and signal
level tolerances, it is desirable to have CAD programs which automatically design electronic
circuits, meeting all requirements, and specify parameters such as dimensions of transistors and
magnitudes of currents. For this electronic circuit design and simulation, CAD programs perform
complex numerical analysis calculations of nonlinear differential equations which characterize
electronic circuits since we need to finish calculation within a reasonable time limit, keeping the
required accuracy; many advanced numerical analysis techniques are used. The CAD programs
usually yield the analysis of transient behavior, direct-current performance, stationary alternating
–current performance, temperature, signal distortion, noise interference, sensitivity and
parameter optimization of the electronic, circuits. The layout system is used to convert block/call
placement data into actual locations, and to construct a routing maze containing all spacing rules.
The format used for relative cell placement data is the same for automatic as for manual
placements in order to simplify their interchange. In the fact, the output of the automatic
placement program can be modified by hand before input into the chip building step as manual
placement data.The layout for random-logic networks in the most time-consuming stage
throughout the entire sequence of LSI/VLSI chip design. After having finished the layout,
designers usually check by CAD programs whether the layout conforms to the layout rules. As
the integration size of LSI/VLSI chips design. After having finished the layout designers usually
check by CAD programs whether the layout conforms to the layout rules. As the integration size
of LSI/VLSI chips becomes larger, design verification and testing at each design stage is vitally
important, because any errors which sneak in from the previous design stages are more difficult
to find out more expensive, since once found we need to redo the previous design stages. As the
integration size increases, the test time increases are very rapidly, so it is very difficult to find
good solutions. Complete test and design verification with software or hardware (i.e. computers
specialized in testing) is usually done to find a design mistake. The last domain in which the
design of an IC an exist include the mask set, and of course, the final fabricated chip followed by
prototype testing. In the summary, the following domains of description have been used in the
design.

1. Architectural level (including fictional and block diagram)

2. Logic and network level
3. Electronic circuit level
4. Layout Placement & Routing
5. Prototype testing

1.3 Design Hierarchy

The use of hierarchy or divide and conquer technique involves diving a module into sub modules
and then repeating this operation on the sub-modules until the complexity of the smaller parts
becomes manageable. This approach is very similar to the software case where large programs
are split into smaller and smaller sections until simple subroutines, with well-defined functions
and interfaces can be written. We have seen that the design of a VLSI chip can be represented in
three domains. Correspondingly,a hierarchy structure can be described in each domain
separately. However, it is important for the simplicity of design that the hierarchies in different
domains can be mapped into each other easily.

As an example of structure hierarchy. The adder can be decomposed progressively into one- bit
adders, separate carry and sum circuits and finally into individual logic gates. At this lower level
of the hierarchy, the design of a simple circuit realizing a well-defined Boolean function is much
easier to handle than at the higher levels of the hierarchy.

In the physical domain, portioning a complex system into its various functional blocks will
provide a valuable guidance for the actual realization of these blocks on a chip. Obviously, the
approximate shape and size (area) of each sub-module should be estimated in order to provide a
useful floor plan. The hierarchical decomposition of a four-bit adder in physical description
domain, resulting in a simple floor plan. This physical view describes the eternal geometry of the
adder, the location of input and output pins, and how pin locations allow some signals (in this
case the carry signals) to be transferred from one sub-block to the other without external routing.
At lower levels of the physical hierarchy, the internal mask layout of each adder cell defines the
locations and the connections of each transistor and wire

1.4 Concepts of Regularity, Modularity and Locality

The hierarchical design approach reduces the design complexity by dividing the large system
into several sub-modules. Usually, other design concepts and design approaches are also needed
to simplify the process. Regularity means that the hierarchical decomposition of a large system
should result in not only simple, but also similar blocks, as much as possible. A good example of
regularity is the design of array structures consisting of identical cells-such as a parallel
multiplication array. Regularity can exist at all levels of abstraction: At the transistor
level,uniformly sized transistors simplify the design. At the logic level, identical gate structures
cabe used etc, if the designer has a small library of well-defined and well-characterized basic
building blocks, a number of different functions can be constructed by using this principle.
Regularity usually reduces the number of different modules that need to be designed and
verified, at all levels of abstraction.

Modularity in design means that the various functional blocks which make up the lager system
must have well-defined functions and interfaces. Modularity allows that each block or module
can be designed relatively independently from each other, since there is no ambiguity about the
function and signal interface of these blocks. All of the blocks can be combined with ease at the
end of the design process, to form the large system. The concept of modularity enables the
parallelization of the design process. It also allows the of generic modules in various designs –
the well-defined functionality and signals interface allow plug-and-play design.

By defining well-characterized interfaces for each module in the system, we effectively ensure
that the internals of each module become unimportant to the exterior modules; internal details
remain at the local level. The concept of locality also ensures that connections are mostly
between neighboring modules, avoiding long-distance connections as much as possible. This last
point is extremely important for avoiding excessive interconnection delays. Time-critical
operations should be performed locally, without the need to access distant modules or signals. If
necessary. The replication of some logic may solve this problem in large system architectures.
 2.FPGA

2.1 Introduction to FPGA

A Field-programmable gate array (often shortened to FPGA) is an electronic component used

to build reconfigurable digital circuits. That means that an FPGA is different from a logic gate,
because a logic gate has a fixed function. In contrast an FPGA has an undefined function at the
time of manufacture. Before the FPGA can be used in a circuit it must be programmed, that is,
reconfigured.
FPGAs are integrated circuits in the category ofprogrammable logic design or PLDs. FPGAs are
the highest performance, most flexible and also the most expensive of the PLD types. A
drawback of FPGAs compared to other PLDs is that they do not remember their design when the
power is removed. An FPGA therefore needs a separate configuration memory chip that holds
the FPGA design. When the power is given back to the FPGA a fixed part of the FPGA reads the
configuration from the configuration memory chip. After the FPGA is configured it will be able
to do the function it was given by the design.
An FPGA is different from a microprocessor or microcontroller. An FPGA in its basic form is
not able to run software. Only when the FPGA is given a configuration that contains a processor-
architecture it has the ability to run software.
FPGA manufacturers provide engineering software for Windows and sometimes also Linux, to
develop designs for FPGAs. The design is commonly written in human readable computer files
called a Hardware Description Language (HDL). The most popular are VHDL and Verilog.
Hardware description languages are strongly comparable to programming languages. But the
intention of HDLs is to design digital logic circuits while programming languages design
software.
The FPGA engineering software has to translate the abstract HDL code into the logic elements
available in the selected FPGA. That is called logic synthesis. Then a process of place and route
is done to position the logic elements in the FPGA. The result is a bit file that can be
programmed into the FPGA or the configuration memory. This is usually done with a USB
programmer connected to the JTAG port of the FPGA.
Because the FPGA is an integrated circuit, an FPGA manufacturer can decide to add other
commonly used integrated circuit components. These fixed parts are called cores. These are for
example Ethernet controllers or even a complete processor-architecture. For different market
segments such as defense, medical, communications and robotics the FPGA manufacturer tries to
add the most valuable set of these additional cores.\

Why there was a need for FPGA?

Before programmable logic?

1. Fixed hardware = fixed usability

2. Limited flexibility only possible by adding software support
3. Upgrade or alternation ion hardware was not guaranteed. An upgrade meant a completely
new system.

World’s first programmable logic device (PLD)

1. EP300:320 Gates, 3-micro meter CMOS

2. 10-Mhz Performance, 20 I/O Pins
3. Desktop Programming

With FPGAs

1. Reprogrammable Logic reusability

2. Lower Non-Recurring Engineering (NRE) Cost
3. Good for Prototyping
4. Less Time to Market
5. Can act as a testing device for other digital circuits
6. Economical to be used for small volumes of products
7. Students can understand digital design concepts in a better way by designing their custom
logic

2.2 Programming FPGA

Small processors are, by far, the largest selling class of computers and form the basis of
many embedded systems. The first single-chip microprocessors contained approximately
10,000 gates of logic and 10,000 bits of memory. Today, field programmable gate arrays
(FPGAs) provide single chips approaching 10 million gates of logic and 10 million bits of
memory. Figure 1 compares one of these microprocessors with an FPGA.
Figure 1: Comparison of first microprocessors to current FPGAs

Powerful tools exist to program these powerful chips. Unlike microprocessors, not only the
memory bits, but also the logical gates are under your control as the programmer. This article
will show the programming process used for FPGA design.

As an embedded systems programmer, you're aware of the development processes used with
microprocessors. The development process for FPGAs is similar enough that you'll have no
problem understanding it but sufficiently different that you'll have to think differently to use it
well. We'll use the similarities to understand the basics, and then discuss the differences and how
to think about them.

Similarities
Table 1 shows the steps involved in designing embedded systems with a microprocessor and an
FPGA. This side-by-side comparison lets you quickly assess the two processes and see how
similar they are.

Table 1: Step-by-step design process for microprocessors and FPGAs

Microprocessor FPGA

Architectural design Architectural design

Choice of language Choice of language (Verilog,

(C, JAVA) VHDL)

Editing programs Editing programs

Compiling programs Compiling programs

 (.DLL, .OBJ)

Synthesizing programs
(.EDIF)

Linking programs Placing and routing programs

(.EXE) (.VO, .SDF, .TTF)

Loading programs to Loading programs to FPGA

ROM

Debugging P programs Debugging FPGA programs

Documenting programs Documenting programs

Delivering programs Delivering programs

2.3 Architectural design

The architectural-design phase is surprisingly similar. Although people will argue design
philosophies, it's not unusual to perform a "first cut" at programming in a pseudo-language that
can be translated into and refined as a specific language, say assembly, C++, or JAVA. I describe
my first FPGA architectural design in a pseudo-C language then translate it to Verilog for an
FPGA. Thus the ability to express yourself in C is a good start in learning Verilog. Architectural
issues could fill a book; therefore we'll focus on development issues.

Because you understand editing, compiling, assembling, linking, and loading in microprocessor
programming, you can relate this to editing, compiling, synthesizing, placing, routing, and
loading in FPGA programming.

Editing

Not only is Verilog syntax C-like, but, since it's 100% ASCII, you can use any editor to prepare
fpga.v files. Nothing new here.

Compiling

The process of compiling a program for the microprocessor combines the edited files and builds
a logically correct sequence of bits that are used to control the sequencing of logical gates. These
gates write data onto buses, into latches and registers, out ports, and across channels. The gates
have fixed relationships designed to accomplish fixed functions. The assembly-language
instructions represent these functions. Thus microprocessor compilers either produce assembly-
language programs that are then assembled into bit patterns or directly produce the bits to drive
the gates and fill the registers and the memories.

The analogous operation in FPGA programming is the compilation of Verilog into register
transfer logic (RTL) net lists. As the name implies, data is transferred into registers, subject to
some clocking condition. At this stage FPGA programming departs from microprocessor
programming in that an additional synthesis process is required to produce bits (or intermediate
objects that can be converted to bits) that will control gates and fill registers and memories on an
FPGA. This level is called gate-level logic, since it describes the logical gates of which the
system will be composed. The output format is typically an Electronic Design Interchange
Format (EDIF) file.

There's a large difference between compiling and synthesizing, and you have to stretch some to
encompass it. Whereas the compiler produces bits to control fixed-gate patterns (the
microprocessor decoders, registers, arithmetic logic unit, and so on) the synthesizer defines gate
patterns described by the logic of the program. That is, your program logic gets synthesized, or
mapped into, logical gates, not into processor instructions that control multigame structures. This
is absolutely amazing, and good FPGA programmers give thanks every day for living in the rare
time in history (post 1990+) when you can design architectures with words and then synthesize
your logic into (mostly silicon) gates that execute your logic. Not to get carried away, but it's
absolutely wonderful.

Linking

Linking was a latecomer to programming—maybe 1950. Previous computers and programs

simply put bits into console switches, and thereby into registers. (Read about the development of
linking in the sidebar.)

The bit-based outputs of the microprocessor compilation process typically don't directly control
gates but must be connected to other bit patterns. This is true because most programs run under
the control of an operating system and must be connected, or linked, to the operating system. In
fact, the location in memory of the actual compiled bits is usually unknown and not determined
until linking and loading is completed. Further, there may be programs existing in a library that
must also be linked to the compiled program before a useful product exists.

The synthesis process, as we have discussed, produces bit patterns, in an intermediate format.
We compile Verilog to RTL net lists, and then synthesize Verilog to EDIF, then place and route
EDIF to produce HEX or TTF files that can be loaded into an FPGA. These bit patterns will end
up controlling logic gates and filling memory and registers.
In the same way that C and other programs include objects defined in (possibly third-party)
libraries, FPGA programs can include or import portions of systems from third-party intellectual
property, in the form of FPGA-implementable programs or objects.

Also, in the same way that the linking and loading process of embedded systems design connects
various system objects, subsystems, or super systems like the operating system, including library
objects (and loads or places them into specific memory locations), the place and route function in
FPGA design places the synthesized subsystems into FPGA locations and makes connections
(microprocessor links ~ FPGA routes) between these subsystems, enabling their operation as an
integrated system. The actual linking and loading of compiled bits is essentially a process of
fitting, in one dimension, the bit patterns distributed over a set of available linear memory
addresses. The FPGA place and route process fits, in two dimensions, the bit patterns (logic
subsystems) over a two dimensional array of available logic gates, and routes buses between
these logic subsystems as necessary.

Loading

Finally, just as embedded programs are often embedded in physical ROM, flash, or downloaded
live, FPGA programs (compiled, synthesized, placed, and routed) must be embedded in the
physical FPGAs. The actual programming file may be a.HEX or similar. Programmers typically
download or burn the bits from these files into the hardware. If nonvolatile, this is a one-time
proposition. If not, it's a download-at-power-up proposition. Many variations exist with FPGAs
as with microprocessor-based embedded systems, but in the end, in a functioning
microprocessor-based product, the bits compiled, linked, and loaded must "get into" the physical
memory to control the gates of the processor, and in an FPGA-based functioning product, the
bits compiled, synthesized, placed, and routed, must "get into" the FPGA, to implement the gates
of the system.

Debugging programs

All experienced programmers know that complex programs, even subprograms, don't run
correctly the first time. When we first see how to solve a problem, we tend to be overjoyed, (it's
possible!) and then underestimate the time required to implement the solution. This is because
our powers of abstraction, based on experience, enable us to see solutions without worrying
about every nitty-gritty detail. But the hard truth is that the physical system in which we're
embedding our programs requires that every nitty-gritty detail must be handled before it will
work. No doubt, you have had the experience of fixing a single bit (or flag) that caused a
crashing program to suddenly run correctly. Hallelujah! It works. I can sleep now.

Anyway, things don't work right out of the gate. We generally have to kick them and see what
they do and where they expire. In embedded systems program development, we typically use
debuggers, simulators, and emulators. These tools enable us to step through the program
execution and observe the effects on flags, register contents, memory locations, and so on, and to
try to match what we expect at a given place and time with what we see, in the simulator or
emulator.

Comparing VHDL, Verilog, System Verilog

VHDL and Verilog are considered general-purpose digital design languages, while
SystemVerilog represents an enhanced version of Verilog. Each has its own style and
characteristics. VHDL has roots in the Ada programming language in both concept and syntax,
while Verilog’s roots can be tracked back to an early HDL called Hilo and the C programming
language. With Verilog and VHDL, engineers can represent the desired functionality as a
software program. Then the model is simulated to confirm the design will work as intended. Any
problems can be corrected in the model, and simulation will verify the correction.VHDL is a rich
and strongly typed language, deterministic and more verbose than Verilog. As a result, designs
written in VHDL are considered self-documenting. Its syntax is non-C-like and engineers
working in VHDL need to do extra coding to convert from one data type to another. VHDL often
catches errors missed by Verilog. VHDL emphasizes unambiguous semantics and allows
portability between tools.

Archicture of FPGA

FPGAs are prefabricated silicon chips that can be programmed electrically to implement
digitaldesigns. The first static memory based FPGA called SRAM is used for configuring both
logic and interconnection using a stream of configuration bits. Today’s modern EPGA contains
approximately 3,30,000 logic blocks and around 1,100 inputs and outputs.

The FPGA Architecture consists of three major components

  Programmable Logic Blocks, which implement logic functions
 Programmable Routing (interconnects), which implements functions
 I/O blocks, which are used to make off-chip connections

Programmable Logic Blocks

The programmable logic block provides basic computation and storage elements used in digital
systems. A basic logic element consists of programmable combinational logic, a flip-flop, and
some fast carry logic to reduce area and delay cost.

Modern FPGAs contain a heterogeneous mixture of different blocks like dedicated memory
blocks, multiplexers. Configuration memory is used throughout the logic blocks to control the
specific function of each element.

Programmable Routing

The programmable routing establishes a connection between logic blocks and Input/output
blocks to complete a user-defined design unit.

It consists of multiplexers pass transistors and tri-state buffers. Pass transistors and multiplexers
are used in a logic cluster to connect the logic elements.

Programmable I/O

The programmable I/O pads are used to interface the logic blocks and routing architecture to the
external components. The I/O pad and the surrounding logic circuit form as an I/O cell.These
cells consume a large portion of the FPGA’s area. And the design of I/O programmable blocks is
complex, as there are great differences in the supply voltage and reference voltage.

The selection of standards is important in I/O architecture design. Supporting a large number of
standards can increase the silicon chip area required for I/O cells.With advancement, the basic
FPGA Architecture has developed through the addition of more specialized programmable
function blocks. The special functional blocks like ALUs, block RAM, multiplexers, DSP-48,
and microprocessors have been added to the FPGA, due to the frequency of the need for such
resources for applications.

2.4 Design flow

Design Entry

The design entry is done in different techniques like schematic based, hardware description
language (HDL) and a combination of both etc. If the designer wants to deal with hardware, then
the schematic entry is a good choice. If the designer thinks the design in an algorithmic way,
then the HDL is the better choice. The schematic based entry gives the designer a greater
visibility and control over the hardware.

Design Synthesis

This process translates VHDL code into a device net list format, i.e., a complete circuit with
logical elements. The design synthesis process will check the code syntax and analyze the
hierarchy of the design architecture.

This ensures the design optimized for the design architecture. The net list is saved as Native
Generic Circuit (NGC) file.

Design Implementation

The implementation process consists of

 Translate
 Map
 Place and Route

Translate
This process combines all the input net lists to the logic design file which is saved as NGD
(Native Generic Database) file. Here the ports are assigned to the physical elements like pins,
switches in the design. This is stored in a file called User Constraints File (UCF).

Map

Mapping divides the circuit into sub-blocks such that they can be fit into the FPGA logic blocks.
Thus this process fits the logic defined by NGD into the combinational Logic Blocks, Input-
Output Blocks and then generates an NCD file, which represents the design mapped to the
components of FPGA.

Routing

The routing process places the sub-blocks from the mapping process into the logic block
according to the constraints and then connects the logic blocks.
 3. Introduction to VHDL

VHDL is an acronym for Very high speed integrated circuit (VHSIC) Hardware Description
Language which is a programming language that describes a logic circuit by function, data flow
behaviour, and/or structure. This hardware description is used to configure a programmable logic
device (PLD), such as a field programmable gate array (FPGA), with a custom logic design.

The general format of a VHDL program is built around the concept of BLOCKS which are the
basic building units of a VHDL design. Within these design blocks a logic circuit of function can
be easily described.

A VHDL design begins with an ENTITY block that describes the interface for the design. The
interface defines the input and output l1ogic signals of the circuit being designed. The
ARCHITECTURE block describes the internal operation of the design. Within these blocks are
numerous other functional blocks used to build the design elements of the logic circuit being
created.

After the design is created, it can be simulated and synthesized to check its logical operation.
SIMULATION is a bare bones type of test to see if the basic logic works according to design and
concept. SYNTHESIS allows timing factors and other influences of actual field programmable
gate array (FPGA) devices to effect the simulation thereby doing a more thorough type of check
before the design is committed to the FPGA or similar device.

VHDL Application

VHDL is used mainly for the development of Application Specific Integrated Circuits (ASICs).
Tools for the automatic transformation of VHDL code into a gate-level net list were developed
already at an early point of time. This transformation is called synthesis and is an integral part of
current design flows.

For the use with Field Programmable Gate Arrays (FPGAs) several problems exist. In the first
step, Boolean equations are derived from the VHDL description, no matter, whether an ASIC or
a FPGA is the target technology. But now, this Boolean code has to be partitioned into the
configurable logic blocks (CLB) of the FPGA. This is more difficult than the mapping onto an
ASIC library. Another big problem is the routing of the CLBs as the available resources for
interconnections are the bottleneck of current FPGAs.

While synthesis tools cope pretty well with complex designs, they obtain usually only
suboptimal results. Therefore, VHDL is hardly used for the design of low complexity
Programmable Logic Devices(PLDs).
 VHDL can be applied to model system behaviour independently from the target technology.
This is either useful to provide standard solutions, e.g. for micro controllers, error correction (de-
)coders, etc, or behavioural models of microprocessors and RAM devices are used to simulate a
new device in its target environment.

An ongoing field of research is the hardware/software co-design. The most interesting question is
which part of the system should be implemented in software and which part in hardware. The
decisive constraints are the costs and the resulting performance.

VHDL Program Structure

entity entity-name is

[port(interface-signal-declaration);]

end [entity] [entity-name];

architecture architecture-name of entity-name is

[declarations]

Begin
architecture body

end [architecture] [architecture-name];

Entity Block

An entity block is the beginning building block of a VHDL design. Each design has only one
entity block which describes the interface signals into and out of the design unit. The syntax for
an entity declaration is:

entityentity_name is

port (signal_name,signal_name : mode type;

signal_name,signal_name : mode type);

endentity_name;

An entity block starts with the reserve word entity followed by the entity_name. Names and
identifiers can contain letters, numbers, and the underscore character, but must begin with an
alpha character. Next is the reserved word is and then the port declarations. The indenting shown
in the entity block syntax is used for documentation purposes only and is not required since
VHDL is insensitive to white spaces.

A single PORT declaration is used to declare the interface signals for the entity and to assign
MODE and data TYPE to them. If more than one signal of the same type is declared, each
identifier name is separated by a comma. Identifiers are followed by a colon (:), mode and data
type selections.

In general, there are five types of modes, but only three are frequently used. These three will be
addressed here. They are in, out, and in out setting the signal flow direction for the ports as input,
output, or bidirectional. Signal declarations of different mode or type are listed individually and
separated by semicolons (;). The last signal declaration in a port statement and the port statement
itself are terminated by a semicolon on the outside of the port's closing parenthesis.

The entity declaration is completed by using an end operator and the entity name. Optionally,
you can also use an end entity statement. In VHDL, all statements are terminated by a semicolon.

Architecture Block

The architecture block defines how the entity operates. This may be described in many ways,
two of which are most prevalent: STRUCTURE and DATA FLOW or BEHAVIOR formats. The
BEHAVIOR approach describes the actual logic behavior of the circuit. This is generally in the
form of a Boolean expression or process. The STRUCTURE approach defines how the entity is
structured - what logic devices make up the circuit or design. The general syntax for the
architecture block is:

architecturearch_name of entity_name is

declarations;

begin

statements defining operation;

endarch_name;

example:

Let q`=nq

libraryieee;

use ieee.std_logic_1164.all;

-- entity block

entity latch is

-- interface signal declarations

port (s,r : in std_logic;

q,nq : out std_logic);

end latch;

-- architecture block architecture flipflop of latch is begin

-- assignment statements

q <= r nor nq;

nq<= s nor q;

endflipflop;

The first two lines imports the IEEE standard logic library std_logic_1164 which contains
predefined logic functions and data types such as std_logic and std_logic_vector. The use
statement determines which portions of a library file to use. In this example we are selecting all
of the items in the 1164 library. The next block is the entity block which declares the latch's
interface inputs, r and s and outputs q and nq. This is followed by the architecture block which
begins by identifying itself with the name flipflop as a description of entity latch. Within the
architecture block's body (designated by the begin reserved word) are two assignment
statements. Signal assignment statements follow the general syntax of:

signal_identifier_name<= expression;

The <= symbol is the assignment operator for assigning a value to a signal. This differs from
the := assignment operator used to assign an initial literal value to generic identifier used earlier.
In our latch example, the state of the signal q is assigned the logic result of the nor function using
input signals r and nq. The nor operator is defined in the IEEE std_logic_1164 library as a
standard VHDL function to perform the nor logic operation. Through the use of Boolean
expressions, the operation of the NOR latch's behavior is described and translated by a VHDL
compiler into the hardware function appearing in figure.

VHDL Operators

Predefined VHDL operators can be grouped into seven classes:

1. Binary logical operators

and, or, nand, nor, xor, xnor
andlogical and result is Boolean,

nandlogical complement of and result is Boolean,

nor logical complement of or result is Boolean,

xorlogical exclusive or result is Boolean,

xnor logical complement of exclusive or result is Boolean,

2. Relational operators

= test for equality, result is Boolean

/= test for inequality, result is Boolean

< test for less than, result is Boolean

<= test for less than or equal, result is Boolean

> test for greater than, result is Boolean

>= test for greater than or equal, result is Boolean

3. Shift operators

sll shift left logical,

srlshift right logical,

sla shift left arithmetic,

sra shift right arithmetic,

rol rotate left,

ror rotate right,

4. Adding operators

+addition, numeric + numeric, result numeric

-subtraction, numeric - numeric, result numeric

& concatenation, array or element & array or element, result array

5. Unary sign operators

+unary plus, + numeric, result numeric

-unary minus, - numeric, result numeric

6. Multiplying operators

*multiplication, numeric * numeric, result numeric

/division, numeric / numeric, result numeric

mod modulo, integer mod integer, result integer

rem remainder, integer rem integer, result integer

7. Miscellaneous operators

abs absolute value, abs numeric, result numeric

not complement, not logic or boolean, result same

** exponentiation, numeric ** integer, result numeric

Packages

A package is used as a collection of often used data types, components, functions, and so on.
Once these objects are declared and defined in a package, they can be used by different VHDL
design units. In particular, the definition of global information and important shared parameters
in complex designs or within a project team is recommended to be done in packages.

It is possible to split a package into a declaration part and the so-called body. The advantage of
this splitting is that after changing definitions in the package body only this part has to be
recompiled and the rest of the design can be left untouched. Therefore, a lot of time consumed by
compiling can be saved.
STD_LOGIC_1164

The STD_LOGIC_1164 package has been developed and standardized by the IEEE. It
introduces a special type called std_ulogic which has nine different logic values. The reason for
this enhancement is that the type bit is not suitable for the precise modeling of digital circuits due
to the missing values, such as uninitialized or high impedance.

Syntax:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

STD_LOGIC_ARITH or NUMERIC_STD

Two additional packages, STD_LOGIC_ARITH (provided by SYNOPSYS) and

NUMERIC_STD (provided by the IEEE), represent an additional part for the
STD_LOGIC_1164 package. They contain basic arithmetic functions to enable calculations and
comparisons based on the typesstd_ulogic_vector and std_logic_vector. These types represent
buses - a bunch of signal lines - whose state can be interpreted as a binary or as a two's
complement number. Therefore, it is necessary to specify which number representation is valid
for a given bus system. This can be done by a conversion into the data types unsigned and
signed. The appropriate conversion functions are also defined in these packages.
Data Types

VHDL is a very strongly typed language. It does not allow a lot of intermixing of data types. The
idea here is that since you are describing a piece of hardware, you need to keep things like
signals and numbers separate. We shall start by looking at the different types of data that can be
used with VHDL which include bits, buses, Boolean, strings, real and integer number types,
physical, and user defined enumerated types.

Defining Signals

There are two data types used for defining interfacing and interconnecting signals - bits and
bit_vectors. The bit type defines a single binary bit type of signal like RESET or ENABLE. It is
used anytime you need to define a single control or data line. For multiple bus signals, such as
data or address buses, an array called a bit vector is used. Bit vectors require a range of bits to be
defined and has the syntax: bit vector (range) The range for a bit vector is defined from the least
significant bit (LSB) to the most significant bit (MSB) and can be set to go from one to the other
in ascending or descending order by using: LSB to MSB or MSB downto LSB. Here are some
examples of bit vector forms:

addressbus(0 to 7);

databus(15 downto 0);

The first defines an 8-bit address bus from addressbus(0) to addressbus(7). The second, a data
bus from databus(15) downtodatabus(0).

Process

Statements within architecture blocks, to this point, are executed concurrently - that is at the
same time. Also, there is no way to synchronize their execution with clocking or any other kind
of signals. To incorporate sequential statement execution and some manner of synchronization,
we need to use a PROCESS block whose general syntax form is:

process_name : process (sensitivity list)

variablevariable_names : variable_type;

begin

statements;

end process;
EXAMPLE:

entity AND_OR_XOR is

port (A,B : in bit;

Z_OR, Z_AND, Z_XOR : out bit);

end AND_OR_XOR;

architecture RTL of AND_OR_XOR is

begin

A_O_X: process (A, B)

begin

Z_OR <= A or B;

Z_AND <= A and B;

Z_XOR <= A xor B;

end process A_O_X ;

end RTL;

VHDL Sequential Statements

There are several statements that may only be used in the body of a process. These statements are
called sequential statements because they are executed sequentially. That is, one after the other
as they appear in the design from the top of the process body to the bottom. In this section we
will examine some of these statements

Sequential Statements:

1. wait statement
2. assertion statement
3. report statement
4. signal assignment statement
5. variable assignment statement
6. procedure call statement
7. if statement
8. case statement
 9. loop statement
10. next statement
11. exit statement
12. return statement
13. null statement

1. Wait statement

Cause execution of sequential statements to wait.

[ label: ] wait [ sensitivity clause ] [ condition clause ] ;

wait for 10 ns; -- timeout clause, specific time delay.

2. Assertion statement

Used for internal consistency check or error message generation.

[ label: ] assert boolean_condition [ report string ] [ severity name ] ;

assert a=(b or c); assert j<i report "internal error, tell someone";

assert clk='1' report "clock not up" severity WARNING;

3.Report statement

Used to output messages.

[ label: ] report string [ severity name ] ;

report "finished pass1"; -- default severity name is NOTE

report "Inconsistent data." severity FAILURE;

4. Signal assignment statement

The signal assignment statement is typically considered a concurrent statement rather than a
sequential statement. It can be used as a sequential statement but has the side effect of obeying
the general rules for when the target actually gets updated.

In particular, a signal cannot be declared within a process or subprogram but must be declared is
some other appropriate scope. Thus, the target is updated in the scope where the target is
declared when the sequential code reaches its end or encounters a 'wait' or another event that
triggers the update.

[ label: ] target <= [ delay_mechanism ] waveform ;

delay_mechanism

transport

rejecttime_expression

inertial

waveform

waveform_element [, waveform_element]

unaffected

waveform_element

value_expression[ aftertime_expression ]

null [ after time_expression ]

5. Variable assignment statement

Variables can only be defined in a process and they are only accessible within this process.
Variables and signals show a fundamentally different behavior. In a process, the last signal
assignment to a signal is carried out when the process execution is suspended. Value assignments
to variables, however, are carried out immediately. To distinguish between a signal and a
variable assignment different symbols are used: ' <= ' indicates a signal assignment and ' := '
indicates a variable assignment.

[ label: ] target := expression ;

6. Procedure call statement

Call a procedure.

[ label: ] procedure-name [ ( actual parameters ) ] ;

do_it; -- no actual parameters

compute(stuff, A=>a, B=>c+d); -- positional association first,

-- then named association of

-- formal parameters to actual parameters

7. If statement
 The if condition must evaluate to a boolean value ('true' or 'false'). After the first if condition,
any number of elsif conditions may follow. Overlaps may occur within different conditions. An
else branch, which combines all cases that have not been covered before, can optionally be
inserted last. The if statement is terminated with 'end if'. The first if condition has top priority: if
this condition is fulfilled, the corresponding statements will be carried out and the rest of the 'if -
end if' block will be skipped.

if CONDITION then -- sequential statements

end if;

if CONDITION then -- sequential statements

else -- sequential statements

end if;

if CONDITION then -- sequential statements

elsif CONDITION then -- sequential statements

· · · else -- sequential statements

end if;

8. Case statement

While the priority of each branch is set by means of the query's order in the IF case, all branches
are equal in priority when using a CASE statement. Therefore, it is obvious that there must not
be any overlaps. On the other hand, all possible values of the CASE EXPRESSION must be
covered. For covering all remaining, i.e. not yet covered, cases, the keyword ' others ' may be
used.

The type of the EXPRESSION in the head of the CASE statement has to match the type of the
query values. Single values of EXPRESSION can be grouped together with the '|' symbol, if the
consecutive action is the same. Value ranges allow to cover even more choice options with
relatively simple VHDL.

case EXPRESSION is

when VALUE_1 => -- sequential statements

when VALUE_2 | VALUE_3 => -- sequential statements

when VALUE_4 to VALUE_5 => -- sequential statements

when others => -- sequential statements

end case ;

9. Loop statement

The loop label is optional. By defining the range, the direction as well as the possible values of
the loop variable are fixed. The loop variable is only accessible within the loop. For synthesis
the loop range has to be locally static and must not depend on signal or variable values. While
loops are not generally synthesizable.

Three kinds of iteration statements.

[ label: ] loop

sequence-of-statements -- use exit statement to get out

end loop [ label ] ;

[ label: ] for variable in range loop

sequence-of-statements

end loop [ label ] ;

[ label: ] while condition loop

sequence-of-statements

end loop [ label ] ;

loop

input_something;

exit when end_file;

end loop;

10. Next statement

A statement that may be used in a loop to cause the next iteration.

[ label: ] next [ label2 ] [ when condition ] ;

next; next outer_loop;

next when A>B;

nextthis_loop when C=D or done; -- done is a Boolean variable

11. Exit statement

A statement that may be used in a loop to immediately exit the loop.

[ label: ] exit [ label2 ] [ when condition ] ;

exit;

exitouter_loop;

exit when A>B;

exitthis_loop when C=D or done; -- done is a Boolean variable

12. Return statement

Required statement in a function, optional in a procedure.

[ label: ] return [ expression ] ;

return; -- from somewhere in a procedure return a+b; -- returned value in a function

13. Null statement

Used when a statement is needed but there is nothing to do.

[ label: ] null ;

null;

GENERATE

VHDL has an additional concurrent statement which can be used in architecture bodies to
describe regular structures, such as arrays of blocks, component instances or processes. The
syntax is:

generate_statement ::=

generate_label :

generation_scheme generate

{ concurrent_statement }

end generate [ generate_label ] ;

generation_scheme ::=
forgenerate_parameter_specification

if condition

Component

A structural way of modeling describes a circuit in terms of components and its interconnection.
Each component is supposed to be defined earlier (e.g. in package) and can be described as
structural, a behavioral or dataflow model. At the lowest hierarchy each component is described
as a behavioral model, using the basic logic operators defined in VHDL. In general structural
modeling is very good to describe complex digital systems, though a set of components in a
hierarchical fashion.

A structural description can best be compared to a schematic block diagram that can be described
by the components and the interconnections.

VHDL provides a formal way to do this by

• Declare a list of components being used

• Declare signals which define the nets that interconnect components

• Label multiple instances of the same component so that each instance is uniquely defined.

The components and signals are declared within the architecture body,

architecturearchitecture_name of NAME_OF_ENTITY is

-- Declarations

component declarations

signal declarations begin

-- Statements

component instantiation and connections :

endarchitecture_name;

Component declaration

Before components can be instantiated they need to be declared in the architecture declaration
section or in the package declaration. The component declaration consists of the component
name and the interface (ports). The syntax is as follows:
componentcomponent_name [is]

[port (port_signal_names: mode type;

port_signal_names: mode type;

port_signal_names: mode type);]

end component [component_name];

VHDL Test bench

The test bench is a specification in VHDL that plays the role of complete simulation
environment for analysed system. The testbench consists of both UUT (unit under test) and
stimuli for simulation.

The UUT is instantiated as a component of the testbench and the architecture of the testbench
specifies stimuli for the UUT ports, usually as waveforms assigned to all output and bidirectional
ports of UUT.

Syntax:

Entity testbench_ent is

End entity testbench_ent;

Architecture testbench_arch of testbench_ent is

Signal declarations

Component declarations

begin

component instantiations

stimuli (test vectors)

end architecture testbench_arch;

 4. ELECTRONIC VOTING MACHINE (EVM)

4.1 Introduction
Electronic Voting Machines ("EVM") are being used in Indian General and State Elections to
implement electronic voting in part from 1999 elections and recently in 2017 state elections held
in five states across India. EVMs have replaced paper ballots in local, state and general
(parliamentary) elections in India. There were earlier claims regarding EVMs tamparability and
security which have not been proved. After rulings of Delhi High Court, Supreme Court and
demands from various political parties, Election Commission decided to introduce EVMs
with voter-verified paper audit trail (VVPAT) system. The VVPAT system was introduced in 8
of 543 parliamentary constituencies as a pilot project in Indian general election, 2014.

4.2 History
In 1980, M. B. Haneefa invented the first Indian voting machine, gazetted "Electronically
operated vote counting machine" (Gazette: 191/Mas/80, 15 October 1980). His original design
(using Integrated Circuits) was exhibited to the public in Government Exhibitions held in six
cities across Tamil Nadu. The EVMs were commissioned in 1989 by Election Commission of
India in collaboration with Bharat Electronics Limited and Electronics Corporation of India
Limited. The Industrial designers of the EVMs were faculty members at the Industrial Design
Centre, IIT Bombay. The EVMs were first used in 1982 in the by-election to North
Paravur Assembly Constituency in Kerala for a limited number of polling stations.

4.3 Design and Technology

An EVM consists of two units, control unit and balloting unit. The two units are joined by a five-
meter cable. Balloting unit facilitates voting by voter via labelled buttons while control unit
controls the ballot units, stores voting counts and displays the results on 7 segment LED
displays. The controller used in EVMs has its operating program etched permanently in silicon at
the time of manufacturing by the manufacturer. No one (including the manufacturer) can change
the program once the controller is manufactured.

EVMs are powered by an ordinary 6 volt alkaline battery manufactured by Bharat Electronics
Limited, Bangalore and Electronics Corporation of India Limited, Hyderabad. This design
enables the use of EVMs throughout the country without interruptions because several parts of
India do not have power supply and/or erratic power supply.
An EVM can record a maximum of 3840 votes and can cater to a maximum of 64 candidates.
There is provision for 16 candidates in a single balloting unit and up to a maximum of 4 units
can be connected in parallel. The conventional ballot paper/box method of polling is used if the
number of candidates exceeds 64. It is not possible to vote more than once by pressing the button
again and again. As soon as a particular button on the balloting unit is pressed, the vote is
recorded for that particular candidate and the machine gets locked. Even if one presses that
button further or any other button, no further vote will be recorded. This way the EVMs ensure
the principle of "one person, one vote".

4.4 Procedure to use

The control unit is with the presiding officer or a polling officer and the balloting Unit is placed
inside the voting compartment. The balloting unit presents the voter with blue buttons
(momentary switch) horizontally labelled with corresponding party symbol and candidate names.
The Control Unit on the other hand provides the officer in-charge with a "Ballot" marked button
to proceed to the next voter, instead of issuing a ballot paper to them. This activates the ballot
unit for a single vote from the next voter in queue.The voter has to cast his vote by once pressing
the blue button on the balloting unit against the candidate and symbol of his choice.
As soon as the last voter has voted, the Polling Officer in-charge of the Control Unit will press
the 'Close' Button. Thereafter, the EVM will not accept any votes. Further, after the close of poll,
the Balloting Unit is disconnected from the Control Unit and kept separately. Votes can be
recorded only through the Balloting Unit. Again the Presiding officer, at the close of the poll,
will hand over to each polling agent present an account of votes recorded. At the time of
counting of votes, the total will be tallied with this account and if there is any discrepancy, this
will be pointed out by the Counting Agents. During the counting of votes, the results are
displayed by pressing the 'Result' button. There are two safeguards to prevent the 'Result' button
from being pressed before the counting of votes officially begins. (a) This button cannot be
pressed till the 'Close' button is pressed by the Polling Officer in-charge at the end of the voting
process in the polling booth. (b) This button is hidden and sealed; this can be broken only at the
counting center in the presence of designated office.

4.5 Benefits

The cost per EVM was ₹5,500 (equivalent to ₹42,000 or US$620 in 2017) at the time the
machines were purchased in 1989–90. The cost was estimated to be ₹10,500 (equivalent
to ₹12,000 or US$180 in 2017) per unit as per an additional order issued in 2014. Even though
the initial investment was heavy, it has since been expected to save costs of production and
printing of crores of ballot papers, their transportation and storage, substantial reduction in the
counting staff and the remuneration paid to them. For each national election, it is estimated that
about 10,000 tonnes of ballot paper is saved. EVMs are easier to transport compared to ballot
boxes as they are lighter, more portable, and come with polypropylene carrying cases. Vote
counting is also faster. In places where illiteracy is a factor, illiterate people find EVMs easier
than ballot paper system. Bogus voting is greatly reduced as the vote is recorded only once. The
unit can store the result in its memory before it is erased manually. The battery is required only
to activate the EVMs at the time of polling and counting and as soon as the polling is over, the
battery can be switched off. The shelf life of Indian EVMs is estimated at 15 years.
4.6 Limitations

A candidate can know how many people from a polling station voted for him. This is a
significant issue particularly if lop-sided votes for/against a candidate are cast in individual
polling stations and the winning candidate might show favoritism or hold grudge on specific
areas. The Election Commission of India has stated that the manufacturers of the EVMs have
developed a Totaliser unit which can connect several balloting units and would display only the
overall results from an Assembly or a Lok Sabha constituency instead of votes from individual
polling stations.
The control units do not electronically transmit their results back to the Election Commission,
even though a simple and unconditionally secure protocol for doing this exists. The Indian
EVMs are purposely designed as stand-alone units to prevent any intrusion during electronic
transmission of results. Instead, the EVMs are collected in counting booths and tallied on the
assigned counting day(s) in the presence of polling agents of the candidates.

4.7 Applications
1.Fast track voting which could be used in small scale elections,like resident welfare
association,”panchayat” level election and other society level elections.
2.It could also be used to conduct opinion polls during annual share holders meeting.
3.It could also be used to conduct general assembly elections in school and colleges to introduce
idea about democracy

4.8 Advantages
1.It is economical.

2.Less manpower required.

3.Time conscious,as less time required for voting and counting.

4.Avoids invalid voting .

5.Saves transportation cost due to its compact size.

6.Convenient on the part of voter.

4.9 Disadvantages
1.Security issues and unequal internet access.

2.We have to use external chip to store the votes.

3.Continuous power supply is required.

4.10 Conclusion
1.This approach allows for the easy development and deployment of applications.For quite some
time,voting equipment vendors have maintained that their systems are secure,and that the closed-
source nature makes tghem even more secure.

2.Infact we believe that an open process would result in more carefull development,as more
scientists,software engineers,political activists,and others who value their democracy would be
paying attention to the quality of the software that is used for their elections.

3.This project can be used for voting since it overcomes all the drawbacks of ordinary voting
machine.
 5.Xilinx Procedure and Waveforms

Using Xilinx Ise A Brief Tutorial:

ISE 13.2i Quick Start Tutorial

The ISE 13.2i Quick Start Tutorial provides Xilinx PLD designers with a quick overview of the
basic design process using ISE 13.2i. After you have completed the tutorial, you will have an
understanding of how to create, verify, and implement a design.

Note: This tutorial is designed for ISE 13.2i on Windows.

This tutorial contains the following sections:

• “Getting Started”

• “Create a New Project”

• “Create an HDL Source”

• “Design Simulation”

• “Create Timing Constraints”

• “Implement Design and Verify Constraints”

• “Reimplement Design and Verify Pin Locations”

• “Download Design to the Spartan™-3 Demo Board”

For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the

Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/

Getting Started

Software Requirements:

To use this tutorial, you must install the following software:

• ISE 13.2i

For more information about installing Xilinx® software, see the ISE Release Notes and

Installation Guide at: http://www.xilinx.com/support/software_manuals.htm.

Hardware Requirements:

To use this tutorial, you must have the following hardware:

• Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board

Starting the ISE Software

To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting:

Start → All Programs → Xilinx ISE →Project Navigator

Note: Your start-up path is set during the installation process and may differ from the one above.

Accessing Help

At any time during the tutorial, you can access online help for additional information

about the ISE software and related tools.

To open Help, do either of the following:

• Press F1 to view Help for the specific tool or function that you have selected or

Highlighted.

• Launch the ISE Help Contents from the Help menu. It contains information about
creating and maintaining your complete design flow in ISE.

Fig4.1: ISE Help Topics

Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3e Startup Kit demo
board.

To create a new project:

1. Select File >New Project... The New Project Wizard appears.

2. Type tutorial in the Project Name field.

3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is
created automatically.

4. Verify that HDL is selected from the Top-Level Source Type list.

5. Click Next to move to the device properties page.

6. Fill in the properties in the table as shown below:

♦ Product Category: All

♦ Family: Spartan3E

♦ Device: XC3S500E

♦ Package: FG320

♦ Speed Grade: -4

♦ Top-Level Module Type: HDL

♦ Synthesis Tool: XST (VHDL/Verilog)

♦ Simulator: ISE Simulator (VHDL/Verilog)

♦ Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields.

When the table is complete, your project properties will look like the following:

Fig4.2: Project Device Properties

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the
end of the next section, your new project will be complete.

Create a Verilog HDL Source

In this section, I will create the a example top-level Verilog HDL file

Creating a Verilog Source

Create the top-level Verilog source file as follows:

1. Click New Source in the New Project dialog box.

2. Select Verilog Module as the source type in the New Source dialog box.

3. Type in the file name counter.

4. Verify that the Add to Project checkbox is selected.

5. Click Next.

6. Declare the ports for the counter design by filling in the port information as shown

below:

Fig4.3: Define Module

7. Click Next, then Finish in the New Source Information dialog box to complete the new source
file template.

8. Click Next, then Next, then Finish.

The source file containing the counter module displays in the Workspace, and the counter
displays in the Sources tab, as shown below:

Fig 4.4: New Project in ISE

Using Language Templates (Verilog)

The next step in creating the new source is to add the behavioral description for counter.

Use a simple counter code example from the ISE Language Templates and customize it for the
counter design.

1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.

2. Open the Language Templates by selecting Edit → Language Templates…

Note: You can tile the Language Templates and the counter file by selecting Window → Tile
Vertically to make them both visible.

3. Using the “+” symbol, browse to the following code example:

Verilog → Synthesis Constructs → Coding Examples → Counter → Binary →

Up/Down Counters → Simple Counter

4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in File
toolbar button. This step copies the template into the counter source file.

5. Close the Language Templates.

Final Editing of the Verilog Source

1. To declare and initialize the register that stores the counter value, modify the

declaration statement in the first line of the template as follows:

replace: reg [<upper>:0] <reg_name>;

with: reg [3:0] count_int = 0;

2. Customize the template for the counter design by replacing the port and signal name

placeholders with the actual ones as follows:

♦ replace all occurrences of <clock> with CLOCK

♦ replace all occurrences of <up_down> with DIRECTION

♦ replace all occurrences of <reg_name> with count_int

3. Add the following line just above the endmodule statement to assign the register value to the
output port:

assign COUNT_OUT = count_int;

4. Save the file by selecting File → Save.

When you are finished, the code for the counter will look like the following:

module counter(CLOCK, DIRECTION, COUNT_OUT);

input CLOCK;

input DIRECTION;

output [3:0] COUNT_OUT;

reg [3:0] count_int = 0;

always @(posedge CLOCK)

if (DIRECTION)

count_int<= count_int + 1;

else

count_int<= count_int - 1;

assign COUNT_OUT = count_int;

endmodule

You have now created the Verilog source for the tutorial project.

Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors and typos.

1. Verify that Synthesis/Implementation is selected from the drop-down list in the

Sources window.

2. Select the counter design source in the Sources window to display the related

processes in the Processes window.

3. Click the “+” next to the Synthesize-XST process to expand the process group.

4. Double-click the Check Syntax process.

Note: You must correct any errors found in your source files. You can check for errors in the
Console tab of the Transcript window. If you continue without valid syntax, you will not be able
to simulate or synthesize your design.

5. Close the HDL file.

Design Simulation
Verifying Functionality using Behavioral Simulation

Create a test bench waveform containing input stimulus you can use to verify the

functionality of the counter module. The test bench waveform is a graphical view of a test bench.

Create the test bench waveform as follows:

1. Select the counter HDL file in the Sources window.

2. Create a new test bench source by selecting Project → New Source.

3. In the New Source Wizard, select Verilog test fixture as the source type, and type
counter_tbwin the File Name field.

4. Click Next.

5. The Associated Source page shows that you are associating the test bench waveform with the
source file counter. Click Next.

6. The Summary page shows that the source will be added to the project, and it displays the
source directory, type and name. Click Finish.
Fig 4.5: Test Bench Waveform

7. Save the waveform.

8. Close the test bench waveform.