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In Depth Tutorials and Information

PROGRAMMING EXTERNAL HARDWARE

INTERRUPTS

SECTION 11.3: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS

The 8051 has two external hardware interrupts. Piri 12 (P3.2) and pin 13 (P3.3) of the 8051, designated as INTO and
INT1, are used as external hardware interrupts. Upon activation of these pins, the 8051 gets interrupted in whatever it is
doing and jumps to the vector table to perform the interrupt service routine. In this section we study these two external
hardware interrupts of the 8051 with some examples.

Figure 11-4. Activation of INTO and INT1

External interrupts INTO and INT1
There are only two external hardware interrupts in the 8051: INTO and INT1. They are located on pins P3.2 and P3.3 of
port 3, respectively. The interrupt vector table locations 0003H and 0013H are set aside for INTO and INT1,
respectively. As mentioned in Section 11.1, they are enabled and disabled using the IE register. How are they activated?
There are two types of activation for the external hardware interrupts: (1) level triggered, and (2) edge triggered. Let’s
look at each one. First, we see how the level-triggered interrupt works.
Level-triggered interrupt

In the level-triggered mode, INTO and INT1 pins are normally high (just like all I/O port pins) and if a low-level signal
is applied to them, it triggers the interrupt. Then the microcontroller stops whatever it is doing and jumps to the interrupt
vector table to service that interrupt. This is called a level-triggered or level-activated interrupt and is the default mode
upon reset of the 8051. The low-level signal at the INT pin must be removed before the execution of the last instruction
of the interrupt service routine, RETI; otherwise, another interrupt will be generated. In other words, if the low-level
interrupt signal is not removed before the ISR is finished it is interpreted as another interrupt and the 8051 jumps to the
vector table to execute the ISR again. Look at Example 11-5.
Example 11-5
Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it should turn on an
LED. The LED is connected to PI .3 and is normally off. When it is turned on it should stay on for a fraction of a
second. As long as the switch is pressed low, the LED should stay on.
Solution:

In this program, the microcontroller,is looping continuously in the HERE loop. Whenever the switch on INT1
(pin P3.3) is activated, the microcontroller gets out of the loop and jumps to vector location 0013H. The ISR for
INT1 turns on the LED, keeps it on for a while, and turns it off before it returns. If by the time it executes the
RETI instruction, the INT1 pin is still low, the microcontroller initiates the interrupt again. Therefore, to end this
problem, the INT1 pin must be brought back to high by the time RETI is executed.

Sampling the low level-triggered interrupt

Pins P3.2 and P3.3 are used for normal I/O unless the INTO and INT1 bits in the IE registers are enabled. After the
hardware interrupts in the IE register are enabled, the controller keeps sampling the INT« pin for a low-level signal once
each machine cycle. According to one manufacturer’s data sheet “the pin must be held in a low state until the start of the
execution of ISR. If the INTn pin is brought back to a logic high before the start of the execution of ISR there will be no
interrupt.” However, upon activation of the interrupt due to the low level, it must be brought back to high before the
execution of RETI. Again, according to one manufacturer’s data sheet, “If the INTw pin is left at a logic low after the
RETI instruction of the ISR, another interrupt will be activated after one instruction is executed.” Therefore, to ensure
the activation of the hardware interrupt at the INTw pin, make sure that the duration of the low-level signal is around 4
machine cycles, but no more. This is due to the fact that the level-triggered interrupt is not latched. Thus the pin must be
held in a low state until the start of the ISR execution.

Figure 11-5. Minimum Duration of the Low Level-Triggered Interrupt (XTAL = 11.0592 MHz)
Edge-triggered interrupts
As stated before, upon reset the 8051 makes INTO and INT1 low-level triggered interrupts. To make them edge-
triggered interrupts, we must program the bits of the TCON register. The TCON register holds, among other bits, the
ITO and IT1 flag bits that determine level- or edge-triggered mode of the hardware interrupts. ITO and IT1 are bits DO
and D2 of the TCON register, respectively. They are also referred to as TCON.O and TCON.2 since the TCON register
is bit-addressable. Upon reset, TCON.O (ITO) and TCON.2 (III) are both Os, meaning that the external hardware
interrupts of INTO and INT1 pins are low-level triggered. By making the TCON.O and TCON.2 bits high with
instructions such as “SETB TCON. 0″ and “SETB TCON. 2″, the external hardware interrupts of INTO and INT1
become edge-triggered. For example, the instruction “SETB CON. 2″ makes INT1 what is called an edge-triggered
interrupt, in which, when a high-to-low signal is applied to pin P3.3, in this case, the controller will be interrupted and
forced to jump to location 0013H in the vector table to service the ISR (assuming that the interrupt bit is enabled in the
IE register).

TF1 TCON.7 Timer 1 overflow flag. Set by hardware when timer/counter 1

overflows. Cleared by hardware as the processor vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn
timer/counter 1 on/off.
TF0 TCON.5 Timer 0 overflow flag. Set by hardware when timer/counter 0
overflows. Cleared by hardware as the processor vectors to the service routine.
TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn
timer/counter 0 on/off.
IE1 TCON.3 External interrupt 1 edge flag. Set by CPU when the
external interrupt edge (H-to-L transition) is detected. Cleared by CPU when the interrupt is
processed. Note: This flag does not latch low-level triggered interrupts.
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to
specify falling edge/low-level triggered external interrupt.
IE0 TCON.1 External interrupt 0 edge flag. Set by CPU when external
interrupt (H-to-L transition) edge is detected. Cleared by CPU when interrupt is processed. Note:
This flag does not latch low-level triggered interrupts.
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify
falling edge/low-level triggered external interrupt.
Figure 11-6. TCON (Timer/Counter) Register (Bit-addressable)
Look at Example 11-6. Notice that the only difference between this program and the program in Example 11-5 is in the
first line of MAIN where the instruction “SETB TCON. 2″ makes INT1 an edge-triggered interrupt. When the falling
edge of the signal is applied to pin INT1, the LED will be turned on momentarily. The LED’s on-state duration depends
on the time delay inside the ISR for nSTTl. To turn on the LED again, another high-to-low pulse must be applied to pin
3.3. This is the opposite of Example 11-5. In Example 11-5, due to the level-triggered nature of the interrupt, as long as
INT1 is kept at a low level, the LED is kept in the on state. But in this example, to turn on the LED again, the INT1
pulse must be brought back high and then forced low to create a falling edge to activate the interrupt.

Example 11-6
Assuming that pin 3.3 (INT1) is connected to a pulse generator, write a program in which the falling edge of the pulse
will send a high to PI.3, which is connected to an LED (or buzzer). In other words, the LED is turned on and off at the
same rate as the pulses are applied to the INT1 pin. This is an edge-triggered version of Example 11-5.

Sampling the edge-triggered interrupt

Before ending this section, we need to answer the question of how often the edge-triggered interrupt is sampled. In
edge-triggered interrupts, the external source must be held high for at least one machine cycle, and then held low for at
least one machine cycle to ensure that the transition is seen by the microcontroller.

The falling edge is latched by the 8051 and is held by the TCON register. The TCON. 1 and TCON.3 bits hold the
latched falling edge of pins INTO and INT1, respectively. TCON.l and TCON.3 are also called IEO and IE1,
respectively, as shown in Figure 11-6. They function as interrupt-in-service flags. When an interrupt-in-service flag is
raised, it indicates to the external world that the interrupt is being serviced and no new interrupt on this INTw pin will
be responded to until this service is finished. This is just like the busy signal you get if calling a telephone number that
is in use. Regarding the ITO and IT1 bits in the TCON register, the following two points must be emphasized.

1. The first point is that when the ISRs are finished (that is, upon execution of
instruction RETI), these bits (TCON.l and TCON.3) are cleared, indicating
that the interrupt is finished and the 8051 is ready to respond to another inter
rupt on that pin. For another interrupt to be recognized, the pin must go back
to a logic high state and be brought back low to be considered an edge-trig
gered interrupt.
2. The second point is that while the interrupt service routine is being executed,
the INT« pin is ignored, no matter how many times it makes a high-to-low
transition. In reality one of the functions of the RETI instruction is to clear the
corresponding bit in the TCON register (TCON. 1 or TCON.3). This informs us
that the service routine is no longer in progress and has finished being serv
iced. For this reason, TCON. 1 and TCON.3 in the TCON register are called
interrupt-in-service flags. The interrupt-in-service flag goes high whenever a
falling edge is detected at the INT pin, and stays high during the entire execu
tion of the ISR. It is only cleared by RETI, the last instruction of the ISR.
Because of this, there is no need for an instruction such as “CLR TCON. 1″
(or “CLR TCON. 3″ for INT1) before the RETI in the ISR associated with the
 hardware interrupt INTO. As we will see in the next section, this is not the case
for the serial interrupt.

Example 11-7
What is the difference between the RET and RETI instructions? Explain why we cannot use RET instead of RETI as
the last instruction of an ISR.
Solution:
Both perform the same actions of popping off the top two bytes of the stack into the program counter, and making the
8051 return to where it left off. However, RETI also performs an additional task of clearing the interrupt-in-service flag,
indicating that the servicing of the interrupt is over and the 8051 now can accept a new interrupt on that pin. If you use
RET instead of RETI as the last instruction of the interrupt service routine, you simply block any new interrupt on that
pin after the first interrupt, since the pin status would indicate that the interrupt is still being serviced. In the cases of
TFO, TF1, TCON.l, and TCON.3, they are cleared by the execution of RETI.
More about the TCON register
Next we look at the TCON register more closely to understand its role in handling interrupts. Figure 11-6 shows
the bits of the TCON register.
ITO and IT1
TCON.O and TCQN.2 are referred to as ITO and IT 1, respectively. These two bits set the low-level or edge-
triggered modes of the external hardware interrupts of the INTO and INT1 pins. They are both 0 upon reset,
which makes them low-level triggered. The programmer can make either of them high to make the external
hardware interrupt edge-triggered. In a given system based on the 8051, once they are set to 0 or 1 they will not
be altered again since the designer has fixed the interrupt as either edge- or level-triggered.

IE0 and IE1

TCON.L and TCON.3 are referred to as IEO and IE1, respectively. These bits are used by the 8051 to keep track of the
edge-triggered interrupt only. In other words, if the ITO and IT1 are 0, meaning that the hardware interrupts are low-
level triggered, IEO and IE1 are not used at all. The IEO and IE1 bits are used by the 8051 only to latch the high-to-low
edge transition on the INTO and INT1 pins. Upon the edge transition pulse on the INT0 (or INT1) pin, the 8051 marks
(sets high) the IE* bit in the TCON register, jumps to the vector in the interrupt vector table, and starts to execute the
ISR. While it is executing the ISR, no H-to-L pulse transition on the INTO (or INT1) is recognized, thereby preventing
any interrupt inside the interrupt. Only the execution of the RETI instruction at the end of the ISR will clear the lEx bit,
indicating that a new H-to-L pulse will activate the interrupt again. From this discussion we can see that the IEO and
IE1 bits are used internally by the 8051 to indicate whether or not an interrupt is in use. In other words, the programmer
is not concerned with these bits since they are solely for internal use.
TRO and TR1
These are the D4 (TCON.4) and D6 (TCON.6) bits of the TCON register. We were introduced to these bits in Chapter 9.
They are used to start or stop timers 0 and 1, respectively. Although we have used syntax such as “SETB TRx” and
“CLR Trx”, we could have used instructions such as “SETB TCON.4″ and “CLR TCON. 4″ since TCON is a bit-
addressable register. TFO and TF1
These are the D5 (TCON.5) and D7 (TCON.7) bits of the TCON register. We were introduced to these bits in Chapter 9.
They are used by timers 0 and 1, respectively, to indicate if the timer has rolled over. Although we have used the syntax
“JNB TFx, target” and “CLR Trx”, we could have used instructions such as “JNB TCON. 5, target” and “CLR TCON.
5″ since TCON is bit-addressable.

Interrupt Programming Code

Activation Code Computer Program

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Previous post: PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT

Related Links
8051 Microcontroller
8051 MICROCONTROLLERS
MICROCONTROLLERS AND EMBEDDED PROCESSORS
OVERVIEW OF THE 8051 FAMILY
8051 ASSEMBLY LANGUAGE PROGRAMMING
 INSIDE THE 8051

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