S05 Bias CKT
S05 Bias CKT
S05 Bias CKT
g m1 (W / L)1
• I out = I ref ⋅ = I ref ⋅
g m2 (W / L) 2
Consideration Factors
- VDD
- Channel Length Modulation
- Transistor Mismatch
0℃
℃
VDD VDD
90℃
℃
M1(Ids)
Negative TC Positive TC
vr0 ZTC
v (Zero Temperature Coefficient)
M1
R1 M1(Vgs)
1. R1 is a conductor which has positive TC
2. M1 has negative TC below ZTC point
(Semiconductor)
3. If we control Vr0 below ZTC point, Vr0 become less
Self Bias Circuit sensitive to temperature due to opposite TC of M1
and R1
starter
ⓐ ⓑ
For Temp.
Compensation pmos diode
Vext
ⓑ
vref
ⓐ
* Temp.
Sensitivity ~
+3300 ppm/C
Schematics
Simulation Results
VDD
Vr0b
Vr0 (a)
Vr0 (b)
(a) (a)
-10C -10C
(b) (b)
Vr0 Current
90C
25C
-10C
0.82V