Automotive Test and Realiability Strategies

Sudhir Borra-0000777923
Email: [email protected]

Abstract— Automotive market is the fast growing market Next is functional safety when the car is power on, there
with increasing demand for memory content. This increase in should be a process performed by the firmware or software
demand for memory has increased the number of semiconductor routines immediately to check for any faults in the system it is
devices used. The increase in semiconductor devices has brought referred to as Power on self-test.
in several challenges and increased the importance of reliability
much more than ever. In this paper we will look into the current The other challenge is to be able to test all the devices with
trends and standards followed by the industry to increase less number of test pins on the board as extra pin will not only
reliability. increase cost the cost of the chip it also increases the
complexity of routing the chip so we need have less testing
Keywords—automotive,reliability,startegies,standards pins so it chip can of low cost. The testing mechanism also
should have hierarchal test integration which allows the system
I. INTRODUCTION to have fast turnaround time. Figure 1 show the challenges
involved in testing automotive integrated circuit.
The consumers today are striving for more functionality in
their cars from having Anti-lock braking system, better
infotainment systems, advanced driver assistant system which
requires scalable integrated development platforms, complete
ecosystem of software, Intellectual properties and design tools
to achieve better productivity or connected automobile which
requires all connected systems used in the car to the cloud to
report, track and other data services.
All these require a lot of hardware and software under the
hood to achieve desired functionality. Hardware means a lot of
semiconductor devices which bring in the challenges such as
supply chain management, power management issues, safety
and security, regulations etc. Software that are required to make
Fig.1 .Challenges of testing a Automotive Integrated Circuit. .
these hardware function such as IP’s, tools to simulate the
functionality of these devices. Increased in functionality means The solution to above challenges is testing standard called
demand for large variety of IP’s which are product proven to ISO 26262 which is an international standard for functional
increase the time to the market ,reliability and increase design safety of electrical and/or electronic systems in production
quality. automobiles defined by International standard for organization.
This certification offers advance fault models, built-in self-test
II. REQUIREMENTS AND TEST CHALLENGES solutions, pin limited compression and SOC test integration so
it offer solution to above challenges with high quality and
A. Requirements for ET&R safety with low cost and turnaround time.
In the design phase we would like to have automated
embedded test and repair solution which has minimal impact to III. AUTOMOTIVE TEST PHASES
power, performance and area. In the early silicon bring up and There are three major test phases in the automotive industry
volume production phase we need clock and process which happens in Early silicon bring up and production stage
monitoring, highest test quality, early debuggable prototype and in field stage of requirements of ET&R the first phase of
with minimized ATE costs. and in the field phase we need testing is production test where in test ,diagnosis and repair all
Power on self–test, periodic in system and mission mode these steps are done during the production of the chip, we have
testing and ECC. another phase called power on phase this testing phase is done
every time the system is powered on in the real working
B. Test challenges for Automotive IC environment i.e. running in system test and repair and final
All these requirements will increase the complexity of phase called mission mode phase in which in system periodic
testing the integrated circuits used in the automotive industry. check and ECC are performed at systematic period of time.
The major challenge is to attain highest possible test quality i.e. Automotive quality levels are defined by ISO/TS 16949
lowest DPPB (Defective Parts Per Billion) it is one of the key standard. This standard is applicable to the entire automotive
metrics used to measure quality in semiconductor devices. supply chain. In this standard the quality standards are highest
for safety critical system. Here we learn how it is applicable to In physical aware test points for logic BIST improve the
Silicon bring up and production stage. The quality that is quality of report by providing high coverage with fewer
desired by top manufacturers is above USL i.e. 3.4 DPPM patterns, simple flow with minimal effort. This has minimal
(defects per million) outside the spec. area impact as it has optimal sharing and re-uses functional
flops.
In physical ware test points for logic BIST are based on
physical design data which uses cluster to optimally group test
points using placement. It reduces congestion and wire lengths
as placement considers slack data and Incremental optimization
for better timing.
In multilevel hierarchal System on chip possess a different
kind of challenge i.e. flat DFT approaches and centralized test
management is expensive in area and time. In this pattern reuse
Fig.2. Show the curve for quality in Different standards. and porting is required and automated test sign of is required.
To attain such higher quality the testing algorithms are Automated test are used to test automotive IP blocks, the
optimized for process nodes. In these algorithms memory patterns are saved and stored such that they can used at any
design and silicon data has been used to model real faults. hierarchy of design. In this way we save a lot of time and
FinFET and planar memories may be differently affected by resources. Random Logic, Memory and IP BIST integration
the same set of faults so programmable background patterns with hierarchical DFT and IEEE 1500 and 1687
and dedicated algorithms are incorporated in this standard it infrastructure enables rapid debug through IEEE
has over 1000 memory fault types. In production testing phase, std 1149.1 TAP.
it has inductive fault models and fault modeling, It can detect In Periodic Self-test safety-critical circuits must check for
FinFET specific defects, also has advanced BIST algorithms errors during their operation to comply with ISO 26262.In this
for providing high test quality and advanced diagnosis testing Logic and memory BIST commonly used. BIST is used
capabilities for fault classification and fault localization. for functional safety, In-system self-test enabled by Multi-core
FinFETs are prone to full and resistive opens/shorts per and redundant systems and Divide-and-conquer BIST with
defect and parameter size and threshold voltage variations. controller. BIST is also used for reliability testing for On-board
FinFET based memories are prone to dynamic faults than debug, for Burn-in, In site stress test and monitoring of
planar memories, they are more stable to process variations. performances drift.
Stress corners such as temperature, voltage, frequency play an With more usage of transistors, scaled voltages, higher
important role in detection for FinFET specific faults. frequency has given rise to the devices being more susceptible
It incoperates interactive failure diagnostics and to soft errors; it is a type of error where a signal or datum is
characterization for faster recovery it has same diagnostic wrong. Errors may be caused by a defect, usually understood
capabilities as tester based solution and advanced fault models either to be a mistake in design or construction, or a broken
for manufacturing test such as IDDQ, static bridging, dynamic component. There are two types of soft errors, chip-level soft
bridging ,cell aware etc. error and system-level soft error. Chip-level soft errors occur
when particles hit the chip, e.g., when the radioactive atoms in
the chip's material decay and release alpha particles into the
IV. INSYSTEM TEST AND REPAIR STRATEGIES chip. Because the alpha particle contains a positive charge and
In system Power on phase it has the ability to run a test and kinetic energy, the particle can hit a memory cell and cause the
repair in the system using the smart mode ,an on chip Central cell to change state to a different value. The atomic reaction in
processing unit enables this in-system test, it also has a i- this example is so tiny that it does not damage the physical
system power on self-test which has logic BIST in it. In fig .3 structure of the chip. System-level soft errors occur when the
you can the logic BIST scheme used in this standard. data being processed is hit with a noise phenomenon, typically
when the data is on a data bus. The computer tries to interpret
the noise as a data bit, which can cause errors in addressing or
processing program code. The bad data bit can even be saved
in memory and cause problems at a later time [3].
So the soft errors can be corrected by using Error
Correcting Codes. This standard has the ability to detect and
correct multi bit errors. This has advanced ECC generation
mechanism with multi robust code support and multi error
correction.
To test what is the effect of soft error, the standard allows
the ECC decoders to inject a small Error injection capability
which will imitate the errors and test the response of the
Fig.3. Logic BIST for Power On Self-test.
system. It has the capability to inject single bit error or multibit REFERENCES
error through the input.
[1] https://www.synopsys.com/cgi-bin/rtl/wpdla/pdfr1.cgi?file=solution-
test-automotive-ics-wp.pdf
[2] https://en.wikipedia.org/wiki/ISO_26262
[3] https://www.iso.org/standard/43464.html
[4] V.D. Agrawal, S.C. Seth, P. Agrawal, “Fault coverage requirement in
production testing of LSI circuits,” IEEE Journal of Solid-State Circuits,
Volume 17, Issue 1, Feb. 1982, pp. 57-61.

Fig.4.Desribes the mechanism used for ECC Error Injection.

The targeted solution of the standard ISO-26262 is

optimized for high performance embedded automotive
applications with integrated hardware safety features like
advanced ECC support ,embedded test and repair, user
programmable test algorithms ,Fault injection and fault
diagnostics and running test algorithm on a range of memory
addresses. Automotive safety integrity enables manufactures to
develop ISO26262 compliant devices.
To achieve ISO26262 for ET&R you need to have a
Trained Functional Safety Manager specific for ET&R,
Generated Safety Manual, Certification Report, Functional
Safety Technical Report and detailed FMEDA spread sheet
(Fault-Mode Report can be used as input to the chip-level
FMEDA report) ET&R and Advanced ECC certification (by
SGS TUV) for use in safety applications needing up to ISO
26262 ASIL D. It also requires qualification of software tool
chained used develop IC and ensure tools do not introduce or
fail to detect errors. The qualification process can be expensive
laborious and time consuming.
Different automotive applications require different type of
architecture for ADAS, infotainment systems or MCU. So
automotive grade IPs reduces risk and accelerates qualification
for automotive SOCs. They are supposed to be compliant with
functional safety of ISO26262 as the goal is to minimize
random hardware failures by defining functional requirement,
applying rigour to the development process and applying
systematic analysis method the standard also requires the
documentation of the entire plan for testing to enhance safety.
There are different phenomenon related to aging of
transistors which pose a huge reliability problem, other
reliability issues are related to schematics electrical parameters
and changes in layout. Because operational reliability of the
automotive integrated circuits is affected by all these
parameters.

CONCLUSION
Automotive ICs have specific design, test, reliability and
safety requirements.so they have to design such that they
accord to Functional and operational safety compliances.
Intellectual property must be designed such that they follow
ISO 26262 functional safety and AEC-Q100 reliability testing
and TS 16949 quality management is very critical.