5 4 3 2 1

Bitland Confidential
D D

M/B Schematics Document

C
Intel Braswell-M Platform C

V1.2

B
2015-04-15 B

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A3 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 1 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

1
 5 4 3 2 1

D D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name Block Diagram
Size Project Name Rev
A3 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 2 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

1
 5 4 3 2 1

BATTERY

7.4V 25WHr CHARGER

+VDC CPU VCORE +VCORE@7A

AC ADAPTER
OZ8782 RT8171B
D Power States D
CPU GXFCORE +VGFX@11A
28V 45W
RT8171B Power Rail On S0 On S3 On S4/S5 On G3

VDDQ
+V_VDDQ_VR@5A
Output power rail
VRTC ON ON ON ON
Input power rail for power transition
DDR_VTT
[email protected]
Input power rail for end IC VCore1/0 ON OFF OFF OFF
uP1740P/Q VGG ON OFF OFF OFF

VDDQ_VTT ON OFF OFF OFF

+5V LDO
[email protected]
+V1.8S ON OFF OFF OFF

+3V LDO
[email protected] +V3.3S ON OFF OFF OFF
C
[email protected]+1.2A +V5S ON OFF OFF OFF C

+5VA
+V1.15S ON OFF OFF OFF
+3VA
[email protected]+1.83A
VDDQ_VR ON ON OFF OFF

RT8205MGQW +V3.3A_PRIME ON ON ON OFF

+V1.8A ON ON ON OFF

1.05A [email protected] +V1.24A ON ON ON OFF

uP1741P +V1.05A ON ON ON OFF

+V3.3A ON ON ON OFF
1.8A LDO
[email protected] [email protected]+0.11A +V5A ON ON ON OFF

B uP0104SSW8 B

1.24A LDO
[email protected] [email protected]
uP0104SSW8

1.15S LDO
+VDDQ_VR@5A [email protected]
uP0104SSW8

[email protected]+1.2A [email protected]
MOS SWITCH
A A
[email protected]+1.83A [email protected]
MOS SWITCH Bitland Information Technology Co.,Ltd.
Page Name Power Block
Size
[email protected] [email protected] A3
Project Name Rev
MOS SWITCH Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 3 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

D D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 4 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

CPU VR
D
EDID0 HDMI D

SM BUS0 Charger

Braswell
EC Battery
I2C 0 Gsensor 0
SM BUS2
I2C 1 Gsensor 1

I2C 2 Touch panel SM BUS2 Thermal

C C

I2C 3 SM BUS1

PS2 Port0

PS2
Touch pad
SMBus block diagram

FST_SPI_CLK
33MHz FST_SPI
32.768KHZ

B B
PCIE_CLK0/1/2_P/N
PCH 100MHz WiFi/LAN/Card Reader

CK_LPC_0_R
19.2MHZ

25MHz EC

CK_DDR0/1_DP/DN
800MHz DDR3L

Clock block diagram

A A

Bitland Information Technology Co.,Ltd.

Page Name Clock block diagram
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 5 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A
Bitland Information Technology Co.,Ltd. A
Page Name Cover Page
Size Project Name Rev
B Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 6 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

sualaptop365.edu.vn
 5 4 3 2 1

+VDIMM 14,18,19,40,41 +V3.3A 10,12,20,24,26..28,33,34,37..44

+V3.3S 8,14,20,23,24,26..28,31,32,34,44 +V1.8A 8..12,14,16,20,23..25,27,31,39,44 ?
CHV_MCP_EDS
U1B
19 M_B_A15 DDR1
M_B_A15 BD5 M_B_DQ[63:0] 19
19 M_B_A[14:0] DDR3_M1_MA_15
? M_B_A14 BD7
18 M_A_A15 CHV_MCP_EDS DDR3_M1_MA_14 BG21 M_B_DQ63
U1A DDR3_M0_DQ_63 M_B_A13 BF10 DDR3_M1_DQ_63
DDR3_M1_MA_13 BH26 M_B_DQ62
M_B_A12 BF6 DDR3_M1_DQ_62
18 M_A_A[14:0] DDR3_M1_MA_12 BJ25 M_B_DQ61
M_A_A15 BD49 M_A_DQ[63:0] 18 M_B_A11 BB5 DDR3_M1_DQ_61
DDR3_M0_MA_15 DDR3_M1_MA_11 BG26 M_B_DQ60
M_A_A14 BD47 M_B_A10 BJ9 DDR3_M1_DQ_60
DDR3_M0_MA_14 BG33 M_A_DQ63 DDR3_M1_MA_10 BG22 M_B_DQ59
M_A_A13 BF44 DDR0 DDR3_M0_DQ_63 M_B_A9 BE2 DDR3_M1_DQ_59
DDR3_M0_MA_13 BH28 M_A_DQ62 DDR3_M1_MA_9 BH20 M_B_DQ58
M_A_A12 BF48 DDR3_M0_DQ_62 M_B_A8 BD10 DDR3_M1_DQ_58
DDR3_M0_MA_12 BJ29 M_A_DQ61 DDR3_M1_MA_8 BG25 M_B_DQ57
M_A_A11 BB49 DDR3_M0_DQ_61 M_B_A7 BE8 DDR3_M1_DQ_57
DDR3_M0_MA_11 BG28 M_A_DQ60 DDR3_M1_MA_7 BJ21 M_B_DQ56
M_A_A10 BJ45 DDR3_M0_DQ_60 M_B_A6 BB8 DDR3_M1_DQ_56
DDR3_M0_MA_10 BG32 M_A_DQ59 DDR3_M1_MA_6
M_A_A9 BE52 DDR3_M0_DQ_59 M_B_A5 BH6
DDR3_M0_MA_9 BH34 M_A_DQ58 DDR3_M1_MA_5 BD26 M_B_DQ55
M_A_A8 BD44 DDR3_M0_DQ_58 M_B_A4 BD12 DDR3_M1_DQ_55
DDR3_M0_MA_8 BG29 M_A_DQ57 DDR3_M1_MA_4 BF24 M_B_DQ54
M_A_A7 BE46 DDR3_M0_DQ_57 M_B_A3 BH7 DDR3_M1_DQ_54
DDR3_M0_MA_7 BJ33 M_A_DQ56 DDR3_M1_MA_3 BA20 M_B_DQ53
D M_A_A6 BB46 DDR3_M0_DQ_56 M_B_A2 BJ6 DDR3_M1_DQ_53 D
DDR3_M0_MA_6 DDR3_M1_MA_2 BD20 M_B_DQ52
M_A_A5 BH48 M_B_A1 BC12 DDR3_M1_DQ_52
DDR3_M0_MA_5 BD28 M_A_DQ55 DDR3_M1_MA_1 BD24 M_B_DQ51
M_A_A4 BD42 DDR3_M0_DQ_55 M_B_A0 BB7 DDR3_M1_DQ_51
DDR3_M0_MA_4 BF30 M_A_DQ54 DDR3_M1_MA_0 BA22 M_B_DQ50
M_A_A3 BH47 DDR3_M0_DQ_54 DDR3_M1_DQ_50
DDR3_M0_MA_3 BA34 M_A_DQ53 BC20 M_B_DQ49
M_A_A2 BJ48 DDR3_M0_DQ_53 BF2 DDR3_M1_DQ_49
DDR3_M0_MA_2 BD34 M_A_DQ52 19 M_B_BS2 DDR3_M1_BS_2 BF20 M_B_DQ48
M_A_A1 BC42 DDR3_M0_DQ_52 AY14 DDR3_M1_DQ_48
DDR3_M0_MA_1 BD30 M_A_DQ51 19 M_B_BS1 DDR3_M1_BS_1
M_A_A0 BB47 DDR3_M0_DQ_51 BH8
DDR3_M0_MA_0 BA32 M_A_DQ50 19 M_B_BS0 DDR3_M1_BS_0 AV22 M_B_DQ47
DDR3_M0_DQ_50 BC34 M_A_DQ49 DDR3_M1_DQ_47 AV20 M_B_DQ46
BF52 DDR3_M0_DQ_49 BG9 DDR3_M1_DQ_46
18 M_A_BS2 DDR3_M0_BS_2 BF34 M_A_DQ48 19 M_B_CAS_N DDR3_M1_CASB BD18 M_B_DQ45
AY40 DDR3_M0_DQ_48 BA14 DDR3_M1_DQ_45
18 M_A_BS1 DDR3_M0_BS_1 19 M_B_RAS_N DDR3_M1_RASB BF18 M_B_DQ44
BH46 BH10 DDR3_M1_DQ_44
18 M_A_BS0 DDR3_M0_BS_0 AV32 M_A_DQ47 19 M_B_WE_N DDR3_M1_WEB AU22 M_B_DQ43
DDR3_M0_DQ_47 AU16 DDR3_M1_DQ_43
AV34 M_A_DQ46 19 M_B_DIM0_CS1_N DDR3_M1_CSB_1 AU20 M_B_DQ42
BG45 DDR3_M0_DQ_46 AY16 DDR3_M1_DQ_42
18 M_A_CAS_N DDR3_M0_CASB BD36 M_A_DQ45 19 M_B_DIM0_CS0_N DDR3_M1_CSB_0 BA18 M_B_DQ41
BA40 DDR3_M0_DQ_45 DDR3_M1_DQ_41
18 M_A_RAS_N DDR3_M0_RASB BF36 M_A_DQ44 BC18 M_B_DQ40
BH44 DDR3_M0_DQ_44 BD16 DDR3_M1_DQ_40
18 M_A_WE_N DDR3_M0_WEB AU32 M_A_DQ43 DDR3_M1_CK_1
AU38 DDR3_M0_DQ_43 BF16
18 M_A_DIM0_CS1_N DDR3_M0_CSB_1 AU34 M_A_DQ42 DDR3_M1_CKB_1 BH16 M_B_DQ39
AY38 DDR3_M0_DQ_42 AY12 DDR3_M1_DQ_39
18 M_A_DIM0_CS0_N DDR3_M0_CSB_0 BA36 M_A_DQ41 19 M_B_DIM0_CKE1 DDR3_M1_CKE_1 BH18 M_B_DQ38
DDR3_M0_DQ_41 BC36 M_A_DQ40 DDR3_M1_DQ_38 BJ13 M_B_DQ37
BD38 DDR3_M0_DQ_40 BD14 DDR3_M1_DQ_37
DDR3_M0_CK_1 19 M_B_DIM0_CK_DDR0_DP DDR3_M1_CK_0 BH12 M_B_DQ36
BF38 BF14 DDR3_M1_DQ_36
DDR3_M0_CKB_1 BH38 M_A_DQ39 19 M_B_DIM0_CK_DDR0_DN DDR3_M1_CKB_0 BJ17 M_B_DQ35
AY42 DDR3_M0_DQ_39 BB10 DDR3_M1_DQ_35
18 M_A_DIM0_CKE1 DDR3_M0_CKE_1 BH36 M_A_DQ38 19 M_B_DIM0_CKE0 DDR3_M1_CKE_0 BG17 M_B_DQ34
DDR3_M0_DQ_38 BJ41 M_A_DQ37 DDR3_M1_DQ_34 BG11 M_B_DQ33
M_A_DIM0_CK_DDR0_DP BD40 DDR3_M0_DQ_37 MB_MON1P AT24 DDR3_M1_DQ_33
18 M_A_DIM0_CK_DDR0_DP DDR3_M0_CK_0 BH42 M_A_DQ36 RSVD1 BG12 M_B_DQ32
M_A_DIM0_CK_DDR0_DN BF40 DDR3_M0_DQ_36 MB_MON1N AU24 DDR3_M1_DQ_32
18 M_A_DIM0_CK_DDR0_DN DDR3_M0_CKB_0 BJ37 M_A_DQ35 RSVD2
BB44 DDR3_M0_DQ_35
18 M_A_DIM0_CKE0 DDR3_M0_CKE_0 BG37 M_A_DQ34 BB3 M_B_DQ31
DDR3_M0_DQ_34 AV18 DDR3_M1_DQ_31
BG43 M_A_DQ33 19 M_B_DIM0_ODT0 DDR3_M1_ODT_0 AW1 M_B_DQ30
MA_MON1P AT30 DDR3_M0_DQ_33 BA16 DDR3_M1_DQ_30
RSVD1 BG42 M_A_DQ32 19 M_B_DIM0_ODT1 DDR3_M1_ODT_1 BC2 M_B_DQ29
MA_MON1N AU30 DDR3_M0_DQ_32 DDR3_M1_DQ_29
RSVD2 AW3 M_B_DQ28
2

c0402 MB_OCAVREF AT26 DDR3_M1_DQ_28

0.1UF/10V,X5R BB51 M_A_DQ31 DDR3_M1_OCAVREF AV3 M_B_DQ27
EMC add C337 18 M_A_DIM0_ODT0
AV36
DDR3_M0_ODT_0
DDR3_M0_DQ_31 AW53 M_A_DQ30 Add R37 for RC filter 0415 MB_ODQVREF AU26
DDR3_M1_ODQVREF
DDR3_M1_DQ_27 BC1 M_B_DQ26
ns BA38 DDR3_M0_DQ_30 DDR3_M1_DQ_26
18 M_A_DIM0_ODT1 DDR3_M0_ODT_1 BC52 M_A_DQ29 AV2 M_B_DQ25
1

C337 DDR3_M0_DQ_29 2 1 BA12 DDR3_M1_DQ_25

AW51 M_A_DQ28 19 MB_DRAMRST_N DDR3_M1_DRAMRSTB BD2 M_B_DQ24
Add R37 for RC filter 0415 MA_OCAVREF AT28
DDR3_M0_OCAVREF
DDR3_M0_DQ_28 AV51 M_A_DQ27 R0402 0_J R61 DDR3_VCCA_PWROK AV26
DDR3_VCCA_PWROK
DDR3_M1_DQ_24
MA_ODQVREF AU28 DDR3_M0_DQ_27
DDR3_M0_ODQVREF BC53 M_A_DQ26 AV12 M_B_DQ23
DDR3_M0_DQ_26 AV52 M_A_DQ25
0.8Ver CRB 182Ohm
GND 182_F 1 R1 2R0402 DRAM_RCOMP1
BA26 DDR3_M1_DQ_23 AP13 M_B_DQ22
2 1 BA42 DDR3_M1_RCOMPPD
18 MA_DRAMRST_N DDR3_M0_DQ_25 BD52 M_A_DQ24 DDR3_M1_DQ_22 AV13 M_B_DQ21
R0402 0_J R37 DDR3_DRAM_S4_PWROKAV28 DDR3_M0_DRAMRSTB BH24
DDR3_M0_DQ_24 19 M_B_DM7 DDR3_M1_DQ_21 AT10 M_B_DQ20
DDR3_DRAM_PWROK DDR3_M1_DM_7

1
AV42 M_A_DQ23 EMC add C336 C336 19 M_B_DM6
BD22
DDR3_M1_DM_6
DDR3_M1_DQ_20 AP14 M_B_DQ19
GND 182_F 1 R2 2 R0402 BA28 DDR3_M0_DQ_23 AP41 M_A_DQ22 0.1UF/10V,X5R 19 M_B_DM5
AY18 DDR3_M1_DQ_19 AT16 M_B_DQ18
M_A_DM[7..0] DDR3_M0_RCOMPPD c0402 BG13 DDR3_M1_DM_5
18 M_A_DM[7..0] DDR3_M0_DQ_22 AV41 M_A_DQ21 19 M_B_DM4 DDR3_M1_DQ_18 AP12 M_B_DQ17
DDR3_M1_DM_4

2
0.8Ver CRB 182Ohm M_A_DM7 BH30 DDR3_M0_DQ_21 ns BA1 DDR3_M1_DQ_17
DDR3_M0_DM_7 AT44 M_A_DQ20 19 M_B_DM3 DDR3_M1_DM_3 AT14 M_B_DQ16
C M_A_DM6 BD32 DDR3_M0_DQ_20 AP10 DDR3_M1_DQ_16 C
DDR3_M0_DM_6 AP40 M_A_DQ19 19 M_B_DM2 DDR3_M1_DM_2
M_A_DM5 AY36 DDR3_M0_DQ_19 AT6
DDR3_M0_DM_5 AT38 M_A_DQ18 19 M_B_DM1 DDR3_M1_DM_1 AV9 M_B_DQ15
M_A_DM4 BG41 DDR3_M0_DQ_18 AP2 DDR3_M1_DQ_15
DDR3_M0_DM_4 AP42 M_A_DQ17 19 M_B_DM0 DDR3_M1_DM_0 AY4 M_B_DQ14
M_A_DM3 BA53 DDR3_M0_DQ_17 DDR3_M1_DQ_14
DDR3_M0_DM_3 AT40 M_A_DQ16 AT4 M_B_DQ13
M_A_DM2 AP44 DDR3_M0_DQ_16 M_B_DQS_P7 BH22 DDR3_M1_DQ_13
DDR3_M0_DM_2 DDR3_M1_DQS_7 AP7 M_B_DQ12
M_A_DM1 AT48 M_B_DQS_N7 BG23 DDR3_M1_DQ_12
DDR3_M0_DM_1 AV45 M_A_DQ15 DDR3_M1_DQSB_7 AV4 M_B_DQ11
M_A_DM0 AP52 DDR3_M0_DQ_15 M_B_DQS_P6 BC24 DDR3_M1_DQ_11
DDR3_M0_DM_0 AY50 M_A_DQ14 DDR3_M1_DQS_6 AY6 M_B_DQ10
DDR3_M0_DQ_14 M_B_DQS_N6 BC22 DDR3_M1_DQ_10
AT50 M_A_DQ13 M_B_DQS_N[7..0] DDR3_M1_DQSB_6 AT7 M_B_DQ9
M_A_DQS_P7 BH32 DDR3_M0_DQ_13 M_B_DQS_P5 AT22 DDR3_M1_DQ_9
M_A_DQS_N[7:0] DDR3_M0_DQS_7 AP47 M_A_DQ12 19 M_B_DQS_N[7..0] DDR3_M1_DQS_5 AP6 M_B_DQ8
M_A_DQS_N7 BG31 DDR3_M0_DQ_12 M_B_DQS_N5 AT20 DDR3_M1_DQ_8
18 M_A_DQS_N[7:0] DDR3_M0_DQSB_7 AV50 M_A_DQ11 DDR3_M1_DQSB_5
M_A_DQS_P6 BC30 DDR3_M0_DQ_11 M_B_DQS_P4 BH14
DDR3_M0_DQS_6 AY48 M_A_DQ10 DDR3_M1_DQS_4 AP3 M_B_DQ7
M_A_DQS_N6 BC32 DDR3_M0_DQ_10 M_B_DQS_N4 BG15 DDR3_M1_DQ_7
DDR3_M0_DQSB_6 AT47 M_A_DQ9 M_B_DQS_P[7..0] DDR3_M1_DQSB_4 AR1 M_B_DQ6
M_A_DQS_P5 AT32 DDR3_M0_DQ_9 M_B_DQS_P3 AY2 DDR3_M1_DQ_6
M_A_DQS_P[7:0] DDR3_M0_DQS_5 AP48 M_A_DQ8 19 M_B_DQS_P[7..0] DDR3_M1_DQS_3 AK2 M_B_DQ5
M_A_DQS_N5 AT34 DDR3_M0_DQ_8 M_B_DQS_N3 BA3 DDR3_M1_DQ_5
18 M_A_DQS_P[7:0] DDR3_M0_DQSB_5 DDR3_M1_DQSB_3 AL1 M_B_DQ4
M_A_DQS_P4 BH40 M_B_DQS_P2 AT12 DDR3_M1_DQ_4
DDR3_M0_DQS_4 AP51 M_A_DQ7 DDR3_M1_DQS_2 AR3 M_B_DQ3
M_A_DQS_N4 BG39 DDR3_M0_DQ_7 M_B_DQS_N2 AT13 DDR3_M1_DQ_3
DDR3_M0_DQSB_4 AR53 M_A_DQ6 DDR3_M1_DQSB_2 AT2 M_B_DQ2
M_A_DQS_P3 AY52 DDR3_M0_DQ_6 M_B_DQS_P1 AV7 DDR3_M1_DQ_2
DDR3_M0_DQS_3 AK52 M_A_DQ5 DDR3_M1_DQS_1 AL3 M_B_DQ1
M_A_DQS_N3 BA51 DDR3_M0_DQ_5 M_B_DQS_N1 AV6 DDR3_M1_DQ_1
DDR3_M0_DQSB_3 AL53 M_A_DQ4 DDR3_M1_DQSB_1 AK3 M_B_DQ0
M_A_DQS_P2 AT42 DDR3_M0_DQ_4 M_B_DQS_P0 AM2 DDR3_M1_DQ_0
DDR3_M0_DQS_2 AR51 M_A_DQ3 DDR3_M1_DQS_0
M_A_DQS_N2 AT41 DDR3_M0_DQ_3 M_B_DQS_N0 AM3
DDR3_M0_DQSB_2 AT52 M_A_DQ2 DDR3_M1_DQSB_0
M_A_DQS_P1 AV47 DDR3_M0_DQ_2
DDR3_M0_DQS_1 AL51 M_A_DQ1
M_A_DQS_N1 AV48 DDR3_M0_DQ_1
DDR3_M0_DQSB_1 AK51 M_A_DQ0 1 OF 13
M_A_DQS_P0 AM52 DDR3_M0_DQ_0
M_A_DQS_N0 AM51 DDR3_M0_DQS_0 CHV_MCP_EDS/BGA
REV = 0.5 ?
DDR3_M0_DQSB_0

CHV_MCP_EDS/BGA
REV = 0.5 1 OF 13 ?
+VDIMM +VDIMM
1

+VDIMM
+VDIMM R6

1
4.7K_F

1
R0402 R5
1

R3 4.7K_F
R4 4.7K_F R0402
2

4.7K_F R0402
R0402

2
MA_ODQVREF_R1 2 MA_ODQVREF R9 1
MB_ODQVREF_R 2MB_ODQVREF

2
R10 0_J R0402 0_J
1

R0402 C3
2

1
MB_OCAVREF_R 1 2 MB_OCAVREF

1
B R13 R7 0_J R0402 R14 B
MA_OCAVREF_R 1 2 MA_OCAVREF 0.1uF/16V,X5R

1
C4
2

R8 R0402 0_J 4.7K_F C0402 4.7K_F

1

R12 C1 0.1uF/16V,X5R
1

C2 R0402 R0402

2
R11 4.7K_F 0.1uF/16V,X5R C0402
GND

2
4.7K_F 0.1uF/16V,X5R R0402 C0402
2

2
2

R0402 C0402 GND

GND

2
GND
GND PLACE TWO 4.7KGND
RESISTORS CLOSE TO CPU PINS ON M_VREF ROUTE THE VREF POWER SIGNALS WITH THICK TRACE
2

PLACE 0.1UF CAP CLOSE TO CPU

PLACE TWO 4.7K RESISTORS CLOSE
GNDTO CPU PINS ON M_VREF ROUTE THE VREF POWER SIGNALS WITH THICK TRACE
GND PLACE TWO 4.7K RESISTORS CLOSE TO CPU PINS ON M_VREF ROUTE THE VREF POWER SIGNALS WITH THICK TRACE
PLACE TWO 4.7K RESISTORS CLOSE TO CPU PINS ON M_VREF ROUTE THE VREF POWER SIGNALS WITH THICK TRACE PLACE 0.1UF CAP CLOSE TO CPU
PLACE 0.1UF CAP CLOSE TO CPU PLACE 0.1UF CAP CLOSE TO CPU

MA_MON1P R6045 1 ns 2 49.9_F R0402 GND

2
R6047
+V1.8A +V3.3A +VDIMM +VDIMM +V3.3S 100.0_F
+V3.3A
R0402
DDR3_DRAM_S4_PWROK ns

1
1

MA_MON1N R6046 1 ns 2 49.9_F R0402 GND

1
Q55A R417
3

R407 L2N7002DW1T1G 1K_F R418 R419

2.2k_J D 2.2k_J 2.2k_J R420 R421
R0402
r0402 r0402 r0402 2.2k_J 2.2k_J MB_MON1P R6042 1 ns 2 49.9_F R0402 GND
2

5 G r0402 r0402
Q33
1

2
Q55B S 10K change to 1K from checklist0.92 1011
6

L2N7002DW1T1G LMBT3904DW1T1G R6044

4

D +VDIMM SOT363 100.0_F

R0402
2 G 4 3 DDR3_VCCA_PWROK
20 SLP_S4_EC_N 44 DDR3_VCCA_PWROK_3P3
S ns

1
1 6 MB_MON1N R6043 1 ns 2 49.9_F R0402
12 PLTRST_N PLT_RST# 20,26,27,32,34 GND
1

+V1.8A
R408 follow CRB0.9 1008wls
1

A A
2.2k_J C284
2

r0402 0.1UF/10V,X5R
2

c0402 PLACE THE RESISTORS AS CLOSE AS POSSIBLE TO SOC,ROUTE THEM AS SINGLE ENDED LINES
2

D16 ns R422 C299

10K_J 0.1UF/10V,X5R
VDDQ_PWRGD 2 1 DDR3_DRAM_S4_PWROK r0402 c0402
20,40,44 VDDQ_PWRGD
2

ns
1

0.37V_30mA_LRB751V-40T1G EMC add C284 0627 Bitland Information Technology Co.,Ltd.

sod323 Page Name Cover Page
EMC add 1029
Size Project Name Rev
1

C164 A2 Braswall-M
0.1UF/10V,X5R 1.0
C0402 Date: Tuesday, June 09, 2015 Sheet 7 of 52

sualaptop365.edu.vn
2

ns PROPERTY NOTE: this document contains information confidential and property to

Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
add 0.1UF FOR EMI 1028 documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3S 7,14,20,23,24,26..28,31,32,34,44
+V1.8A 7,9..12,14,16,20,23..25,27,31,39,44

D D

?
CHV_MCP_EDS
U1C

M44

MCSI and Camera interface

RSVD15 K44
+V1.8A +V1.8A RSVD12
K48
D50 RSVD14 K47
25 DDI0_LANE0_DP C51 DDI0_TXP_0 RSVD13
25 DDI0_LANE0_DN DDI0_TXN_0

1
T44
H49 MCSI_1_CLKP T45
R236 R240
25 DDI0_LANE1_DP H50 DDI0_TXP_1 MCSI_1_CLKN If MIPI*-CSI-1 are not implemented, leave them NC
2.2k_J 2.2k_J 25 DDI0_LANE1_DN DDI0_TXN_1 Y47 form checklist0.92
R0402 R0402 HDMI 25 DDI0_LANE2_DP
F53
DDI0_TXP_2
DDI0 MCSI_1_DP_0
MCSI_1_DN_0
Y48
F52 V45
25 DDI0_LANE2_DN DDI0_TXN_2 MCSI_1_DP_1
2

2
DDI0_CTRL_DATA DDI0_CTRL_CLK V47
G53 MCSI_1_DN_1 V50
25 DDI0_LANE3_DP G52 DDI0_TXP_3 MCSI_1_DP_2 V48
25 DDI0_LANE3_DN DDI0_TXN_3 MCSI_1_DN_2 T41
H47 MCSI_1_DP_3 T42
H46 DDI0_AUXP MCSI_1_DN_3
DDI0_AUXN P50
W51 MCSI_2_CLKP P48
25 DDI0_HPD_Q HV_DDI0_HPD MCSI_2_CLKN
Y51 P47
25 DDI0_CTRL_CLK Y52 HV_DDI0_DDC_SCL MCSI_2_DP_0 P45
+V3.3S +V1.8A 25 DDI0_CTRL_DATA HV_DDI0_DDC_SDA MCSI_2_DN_0 M48
V52 MCSI_2_DP_1 M47
V51 PANEL0_BKLTEN MCSI_2_DN_1
W53 PANEL0_BKLTCTL T50
PANEL0_VDDEN RSVD17
2

1 R0402 2 DDI0_PLLOBS_P F38 T48

DDI0_PLLOBS_P RSVD16
2
R573 R16 402_F DDI0_PLLOBS_N G38
R312 DDI0_PLLOBS P44 R5982 1 150 2 R0402
10K_F MCSI_COMP
10K_F J51
R0402 24 EDP_TX0_DP DDI1_TXP_0
Q50A change to unstuff 1025 H51 AB41
R0402 24 EDP_TX0_DN DDI1_TXN_0 GP_CAMERASB00 AB45
LBSS138DW1T1G
eDP K51 GP_CAMERASB01
1

C sot363 ns DDI1_TXP_1 AB44 C

K52 GP_CAMERASB02
1

DDI1_TXN_1 AC53
G

3 4 eDP_BKLT_EN L53 GP_CAMERASB03 AB51

DDI1
20,24 DDI1_BKLT_EN L51 DDI1_TXP_2 GP_CAMERASB04 AB52
D

DDI1_TXN_2 GP_CAMERASB05 AA51

M52 GP_CAMERASB06
DDI1_TXP_3 AB40
M51 GP_CAMERASB07
DDI1_TXN_3 Y44
GP_CAMERASB08 GP_CAMERASB08 16
24 EDP_AUX_DP M42
DDI1_AUXP Y42
24 EDP_AUX_DN K42 GP_CAMERASB09 GP_CAMERASB09 16
DDI1_AUXN Y41
GP_CAMERASB10 V40
+V1.8A DDI1_HPD_N R51 GP_CAMERASB11 GP_CAMERASB11 16
+V3.3S HV_DDI1_HPD
eDP_BKLT_EN P51
eDP_BKLT_CTRL P52 PANEL1_BKLTEN
PANEL1_BKLTCTL M7
R53 SDMMC1_CLK FLASH_CLK 23
24 DDI1_VDD_R_EN DDI1_PLLOBS_P F47 PANEL1_VDDEN
1

change to unstuff 1024 DDI1_PLLOBS_P P6

1 2 DDI1_PLLOBS_N F49 SDMMC1_CMD FLASH_CMD 23
R570 DDI1_PLLOBS
R20 R0402 402_F M6
R571 10K_F F40 FLASH_D0 23
2.2k_J SDMMC1_D0 M4
R0402 G40 DDI2_TXP_0 FLASH_D1 23
r0402 Q50B SDMMC1_D1 P9
DDI2_TXN_0 FLASH_D2 23
SDMMC1_D2
2

LBSS138DW1T1G ns J40 SDMMC1 P7

DDI2_TXP_1 SDMMC1_D3_CD_B FLASH_D3 23
1
2

sot363 K40 T6
DDI2_TXN_1 MMC1_D4_SD_WE FLASH_D4 23
T7
G

F42 DDI2 MMC1_D5 FLASH_D5 23

6 1 eDP_BKLT_CTRL DDI2_TXP_2 T10
24 DDI1_BKLT_CTRL G42 MMC1_D6 FLASH_D6 23
DDI2_TXN_2 T12
D

MMC1_D7 FLASH_D7 23
D44 T13 MMC1_RCLK 1 TP25 NOTE:MMC1_RCLKFor eMMC 5.0 only. Point to
F44 DDI2_TXP_3 MMC1_RCLK P13 R22 1 100_F 2 R0402 point connection to thecorresponding pin at eMMC
DDI2_TXN_3 SDMMC1_RCOMP device
D48 NOTE:EMMC The RComp pull-down 100 ohm 1% from checklist V0.92
C49 DDI2_AUXP K10
DDI2_AUXN SDMMC2_CLK K9
R441 1 0_J ns 2 R0402 U51 SDMMC2_CMD
HV_DDI2_HPD M12
R442 1 0_J ns 2 R0402 T51 SDMMC2_D0 M10
+V1.8A R443 1 0_J ns 2 R0402 T52 HV_DDI2_DDC_SCL SDMMC2_D1 K7
HV_DDI2_DDC_SDA SDMMC2_D2 K6
SDMMC2
Follow checklist1.2 R441/R442/ B53 SDMMC2_D3_CD_B Secure Digital Card (SD Card)If SD is not implemented,
RSVD6
2

R443 ns 0524V1.3wls A52 F2 leave them NC. from checklist0.92

R15 E52 RSVD3 SDMMC3_CLK D2
D52 RSVD9 SDMMC3_CMD K3
10K_J
B B50 RSVD8 SDMMC3_CD_B B
R0402 RSVD5 NC's
B49 J1
E53 RSVD4 SDMMC3_D0 J3
ns
1

RSVD10 SDMMC3_D1
DDI1_HPD_N L valid C53
A51 RSVD7 SDMMC3_D2
H3
G2
RSVD2 SDMMC3_D3
2

A49
R17 G44 RSVD1 K2
SDMMC3
RSVD11 SDMMC3_1P8_EN L3
100K_J SDMMC3_PWR_EN_B P12 R21 1 2 80.6_F R0402
R0402 SDMMC3_RCOMP
NOTE:SD RComp pull-down 80ohm from checklist V0.92
1

ALL GPIO PU use 1.8A 1020

1 OF 13
CHV_MCP_EDS/BGA
REV = 0.5 ?

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 8 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

sualaptop365.edu.vn
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V1.8A 7,8,10..12,14,16,20,23..25,27,31,39,44

+V1.8S 10,14,20,23,28,31,44

D D

?
CHV_MCP_EDS
U1D

C5 1 2 0.1UF/10V,X5R C0402 C24 C31

34 PCIE_CD_TXP0 PCIE_TXP0 SATA_TXP0 SATA_TXP0 22
1.8S change to 1.8A 1020 Card reader 34 PCIE_CD_TXN0
C6 1 2 0.1UF/10V,X5R C0402 B24
PCIE_TXN0 SATA_TXN0
B30
SATA_TXN0 22 SATA 3.0 HDD
G20 N28
34 PCIE_CD_RXP0 J20 PCIE_RXP0 SATA_RXP0 M28 SATA_RXP0 22
34 PCIE_CD_RXN0 PCIE_RXN0 SATA_RXN0 C29 SATA_RXN0 22
C7 1 2 0.1UF/10V,X5R A25 SATA_TXP1 A29
27 NGFF_TXP1 1 2 0.1UF/10V,X5R C0402 C25 PCIE_TXP1 SATA_TXN1 J28
C8
27 NGFF_TXN1 D20 PCIE_TXN1 SATA_RXP1 K28
NGFF 27 NGFF_RXP1 PCIE_RXP1 SATA_RXN1
+V1.8A F20
27 NGFF_RXN1 PCIE_RXN1 AH3 SATA_LEDN 1 TP27
C9 1 2 0.1UF/10V,X5R B26 SATA_LEDN AH2 SATA_GP0 1 TP28 SATA_GP[0] is multiplexed with ISH_GPIO_12.
26 PCIE_LAN_TXP2 1 2 0.1UF/10V,X5R C0402 C26 PCIE_TXP2 SATA_GP0 AG3 SATA_GP1 1 SATA_GP[1] is multiplexed with SPI3_CS0#
C11 TP29
26 PCIE_LAN_TXN2 PCIE_TXN2 PCIe SATA SATA_GP1 SATA_GP[2] is multiplexed with SATA_DEVSLP[0].
10K_J2 R0402 1 R30 PCIE_CD_CLKREQ0 LAN D22 AG1 SATA_DEVSLP0 1 TP46
26 PCIE_LAN_RXP2 F22 PCIE_RXP2 SATA_GP2 AF3 FLASH_RESET SATA_GP[3] is multiplexed withSATA_DEVSLP[1],
10K_J2 R0402 1 R33 NGFF_PCIE_CLKREQ1 26 PCIE_LAN_RXN2 PCIE_RXN2 SATA_GP3 FLASH_RESET 23 MMC1_RESET_B, SPI3_CS1# From EDS0.92
A27 N30 SATA_OBS_DP 1 R0402 2
10K_J2 R0402 1 R55 PCIE_LAN_CLKREQ2 C27 PCIE_TXP3 SATA_OBSP M30 SATA_OBS_DN R24 402_F
G24 PCIE_TXN3 SATA_OBSN
10K_J2 R0402 1 R56 PCIE_CLKREQ3 J24 PCIE_RXP3 W3 R27 1 R0402 2 10.0_F FAT_SPI_CLK
PCIE_RXN3 FST_SPI_CLK
close to ROM
AM10 V4 R28 1 R0402 2 33.0_J FAT_SPI_CS0_N
34 PCIE_CD_CLKREQ0 PCIE_CLKREQ0B FST_SPI_CS0_B
AM12 V6 FAT_SPI_CS1_N 1 TP49
27 NGFF_PCIE_CLKREQ1 PCIE_CLKREQ1B FST_SPI_CS1_B
C AK14 V7 FAT_SPI_CS2_N 1 TP50 C
26 PCIE_LAN_CLKREQ2 PCIE_CLKREQ2B FST_SPI_CS2_B
PCIE_CLKREQ3 AM14
PCIE_CLKREQ3B V2 R32 1 R0402 210.0_F FAT_SPI_D0
A21 FST_SPI_D0 V3 R34 1 R0402 210.0_F FAT_SPI_D1
34 PCIE_CD_CLKP0 CLK_DIFF_P_0 FAST SPI FST_SPI_D1
C21 U1 R35 1 R0402 210.0_F FAT_SPI_D2
34 PCIE_CD_CLKN0 CLK_DIFF_N_0 FST_SPI_D2
C19 U3 R36 1 R0402 210.0_F FAT_SPI_D3
27 NGFF_REFCLK1_DP CLK_DIFF_P_1 FST_SPI_D3
B20
27 NGFF_REFCLK1_DN CLK_DIFF_N_1
C18 AF13 HDA_RST_N 1 TP51
26 PCIE_LAN_CLKP2 CLK_DIFF_P_2 MF_HDA_RSTB
B18 AD6 HDA_SDI1 R38 75ohm change to 22ohm for sI 0415
26 PCIE_LAN_CLKN2 CLK_DIFF_N_2 MF_HDA_SDI1 +V1.8A
C17 AD9 R38 1 R0402 2 22_J
CLK_DIFF_P_3 MF_HDA_CLK HDA_BIT_CK 28
A17 AD7 1.8S change to 1.8A 1022
C16 CLK_DIFF_N_3 MF_HDA_SDI0 AF12 1 HDA_SDIN 28
R40 75.0_F 2 HDA_SYNC 28
B16 CLK_DIFF_P_4 MF_HDA_SYNC AF14 R41 1 75.0_F 2R0402
CLK_DIFF_N_4 MF_HDA_SDO HDA_SDOUT 28
AB9 R0402
MF_HDA_DOCKENB

1
1 2 PCIE_OBS_DP D26 AB7 HDA_SDI1 1 ns 2 ns 1 2
R42 402_F R0402 PCIE_OBS_DN F26 PCIE_OBSP MF_HDA_DOCKRSTB R39 75.0_F R0402 C0402 CA26 22PF/50V,NPO R199 R198
PCIE_OBSN H4
AUDIO SPKR PCH_HDA_SPKR 28 4.7K_J 4.7K_J
TP38 1 V14
SPI1_CLK R0402 R0402
TP39 1 Y13 AK9 ns
SPI1_CS0_B GP_SSP_2_CLK
delete 33ohm 1010 TP40 1 Y12
SPI1_CS1_B
SPI
GP_SSP_2_FS
AK10 I2S_2_FS
Strap ns

2
TP47 1 V13 AK12 I2S_2_TXD I2S_2_FS follow CRB0.9 1008wls
TP48 1 V12 SPI1_MISO GP_SSP_2_TXD AK13 If audio I2S signals are not implemented, leave them NC
SPI1_MOSI GP_SSP_2_RXD DG 0.95.
I2S_2_TXD
1 OF 13
CHV_MCP_EDS/BGA
REV = 0.5 ?

+V1.8A_SPI
+V1.8A
R83 1 2 0_J R0402

B +V1.8A_SPI +V1.8A_SPI B
2
1

1
R5967 C3768
R5972 3.3K_J 0.1uF/16V,X5R R5977
CS need 100 K PU to +V1P8A_SPI From 20K_J R0402 C0402 20K_J

1
checklist 0.92 3.3K PU from CRB 0.9 R0402
U3
R0402
1

D2D3 PU 20K from CRB0.9 W25Q64FW SSIG

2

2
sop8_1d27_8
FAT_SPI_CS0_N 1 8
FAT_SPI_D1 2 CE# VDD 7 FAT_SPI_D3
FAT_SPI_D2 3 SO/IO1 HOLD#/IO3 6 FAT_SPI_CLK
4 WP#/IO2 SCK 5 FAT_SPI_D0
GND SIO/IO0

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 9 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V1.8A 7..9,11,12,14,16,20,23..25,27,31,39,44 +V1.8S 14,20,23,28,31,44

+V3.3A 7,12,20,24,26..28,33,34,37..44 +V3.3S 7,8,14,20,23,24,26..28,31,32,34,44

2
U1E CHV_MCP_EDS C548 C549
0.1UF/10V,X5R 0.1UF/10V,X5R
c0402 c0402

1
OSCIN P24 ns ns +V1.8A
C10C12 Follow CRB0.9 OSCOUT M22 OSCIN C11 Gsensor_INT0_N R197 2 R0402 1 0_J
OSCOUT RSVD3 Gsensor_INT0 10,31
B10 Gsensor_INT1_N R196 2 R0402 1 0_J
RSVD2 Gsensor_INT1 10,24
2 1 ADD TP follow CRB0.9 wls1008 F12 TP_I2C_RST#_N For Touch panel
GND 1
TP17 J26 RSVD9

1
D c0402 18PF/50V,NPO RSVD13 F10 1 TP1 D
49.9 (1%)PD to GND. from checklist0.92 TP13 1 N26 RSVD8
C10 RSVD17 PIn F10 change to reserved test point 0524V1.3wls R600
1 2 OSCIN R50 1 R0402 2 2.49K_F ICLKICOMP P20
D12
R52 2 R0402 1 49.9_F ICLKRCOMP N20 ICLKICOMP iCLK RESERVED
RSVD5 SoC_EC_INT1# 20 FOR EC 100k_J
R47 0_J R0402 ICLKRCOMP E8 r0402
TP21 1 P26 RSVD7 LID2_N 34

1
RSVD18 C7 Memory_ID1
TP20 1 K26 RSVD4

2
2
3
R51 RSVD14 D6 Memory_ID2
ADD TP follow CRB0.9 wls1008 TP19 1 M26 RSVD6
19.2MHZ 200K_J RSVD16 LID2_N
TP14 1 AH45

PLTFM CLK's
y_4p_smd3225 RSVD1 J12 Memory_ID3
GND R0402 RSVD11
Y3 F7 Memory_ID4
TP7 1 A9 RSVD10
MF_PLT_CLK0 J14
TP8 1 C9 RSVD12
4
1

2
1 2 OSCOUT MF_PLT_CLK1 L13
TP9 1 B8 RSVD15
R48 0_J R0402 The SoC supports up to 6 clocks (PMC_PLT_CLK[5:0]) TP10 1 B7 MF_PLT_CLK2
with a frequency of 19.2 MHz or 25Mhz. From DG 1 B5 MF_PLT_CLK3 AK6 Gsen_SCL_0 R291 1 R0402 2 0_J
2 1 TP11 I2C0_SCL AH7 Gsensor_SCL_0 10,31
GND 1 B4 MF_PLT_CLK4 Gsen_SDA_0 R292 1 R0402 2 0_J
TP12 I2C0_SDA Gsensor_SDA_0 10,31
c0402 18PF/50V,NPO
C181
MF_PLT_CLK5
I2C1_SCL
AF6 Gsen_SCL_1 R281 1 R0402 2 0_J
Gsensor_SCL_1
2 10,24
X Gsensor
AM40 AH6 Gsen_SDA_1 R284 1 R0402 2 0_J
GPIO_DFX0 I2C1_SDA Gsensor_SDA_1 10,24

GPIO_DFX
AM41
AM44 GPIO_DFX1 AF9
AM45 GPIO_DFX2
GPIO_DFX3 I2C
I2C2_SCL
I2C2_SDA
AF7
TP_I2C_2_SCL_N
TP_I2C_2_SDA_N Touch panel
AM47
AK48 GPIO_DFX4 AE4
GPIO_SUS[7:6] These signals are used as AM48 GPIO_DFX5
GPIO_DFX6
I2C3_SCL
I2C3_SDA
AD2
SMB_CLK_SoC
SMB_DAT_SoC
20
20
SOC TO EC
PMC_SUSCLK[3:2], PMC_SUSCLK2 connects with AK41
NFC or Modem? PMC_SUSCLK3 connects with AK42 GPIO_DFX7 AC1
GNSSFrom checklist GPIO_DFX8 I2C4_SCL AD3
GPIO0_SUS AD51 I2C4_SDA
+V1.8A 16 GPIO0_SUS GPIO_SUS0
GPIO1_SUS AD52 AB2 If I2C is not implemented, leave signals NC. From checklist09.2
16 GPIO1_SUS GPIO_SUS1 I2C5_SCL

GPIO_SUS
GPIO2_SUS AH50 AC3
16 GPIO2_SUS GPIO_SUS2 I2C5_SDA
PIN AH48 net GPIO3_SUS change to TP_I2C_INT#_N AH48
TP_I2C_INT#_N 0524V1.3wls 16 TP_I2C_INT#_N GPIO_SUS3
GPIO4_SUS AH51 AA1
16 GPIO4_SUS GPIO_SUS4 I2C6_SCL
1

GPIO5_SUS AH52 AB3

16 GPIO5_SUS GPIO_SUS5 I2C6_SDA
R233 AG51
20 SOC_RUNTIME_SCI_N GPIO_SUS6
4.7K_F AG53 AA3 1 TP22
20 SOC_EXTSMI_N GPIO_SUS7 I2C_NFC_SCL +V1.8A
GPIO9_SUS AF52 Y2 1 TP15
R0402 16 GPIO9_SUS SEC_GPIO_SUS9 I2C_NFC_SDA
PU change to NULL GPIO8_SUS AF51
16 GPIO8_SUS SEC_GPIO_SUS8
ns follow intel opinion 1020 16 GPIO10_SUS
GPIO10_SUS AE51 AM6 R0402 2 R6015 11K_J
SEC_GPIO_SUS10 MF_SMB_CLK
2

GPIO_ALERT Memory_ID0 AC51 AM7 R0402 2 11K_J

GPIO 10 use Rotation_SW# 1023 R60 1 100_F 2 R0402 AH40 SEC_GPIO_SUS11
SMBUS
MF_SMB_DATA AM9 R0402 2
R6016
R6017 11K_J
GPIO0_RCOMP MF_SMB_ALERTB
1

GPIO_ALERT Y3
R234 GPIO_ALERT +V1.8A +V1.8A +V1.8S
C 4.7K_F A 1 K 5% for external pull-up resistor is C
recommended Form checklist 0.92
R0402 1 OF 13
ns CHV_MCP_EDS/BGA

2
REV = 0.5 ?
2

2
R5997 R5998
1K_J 1K_J R6024 R6027
R0402 R0402 1K_J 1K_J
R0402 R0402

1
Q3671A ns ns

1
LBSS138DW1T1G

5
Q3671B sot363
LBSS138DW1T1G

G
2
Gsen_SCL_0 sot363 3 4
Gsensor_SCL_0 10,31
ns

S
Gsen_SDA_0 6 1
Gsensor_SDA_0 10,31

S
ns
+V3.3A
+V1.8A
+V1.8A +V1.8A +V1.8S

Memory_ID1 Memory_ID2 Memory_ID3 Memory_ID4

SDRAM Configuration

2
1

2
R5999 R6000
0(R294) 0(R296) 0(R298) 0(R301) Hynix H5TC4G63AFR-PBA R559 1K_J 1K_J R6036 R6037
Q3674A 3.3k_J R566 R0402 R0402 1K_J 1K_J
LBSS138DW1T1G
r0402 3.3k_J R0402 R0402

2
5
0(R294) 0(R296) 0(R298) 1(R302) Hynix H5TC8G63AMR-PBA Q3674B sot363 r0402

1
ns ns

G
LBSS138DW1T1G Q3672A

1
2
TP_I2C_INT#_N sot363 4 3 TP_I2C_INT# 24 LBSS138DW1T1G

5
Micron MT41K256M16HA-125:E

D
0(R294) 0(R296) 1(R300) 0(R301) TP_I2C_RST#_N 1 6
Q3672B
LBSS138DW1T1G
sot363

G
TP_I2C_RST# 24

2
Gsen_SCL_1 3 4

D
sot363
Gsensor_SCL_1 10,24
0(R294) 0(R296) 1(R300) 1(R302) Micron MT41K512M16TNA-125:E

S
Gsen_SDA_1 6 1 ns Gsensor_SDA_1 10,24

S
0(R294) 1(R297) 0(R298) 0(R301) Elpida EDJ4216EFBG-GN-F
ns
B
0(R294) 1(R297) 0(R298) 1(R302) Elpida EDJ8416E6MB-GN-F B

0(R294) 1(R297) 1(R300) 0(R301) Samsung K4B4G1646Q-HYK0

+V1.8A +V1.8A +V1.8S +V1.8S

0(R294) 1(R297) 1(R300) 1(R302) Samsung K4B8G1646Q-MYK0

1
1

1
1(R295) 0(R296) 0(R298) 0(R301) Hynix H5TC2G63FFR-PBA
R704 R703
R574 R560 2.2k_J 2.2k_J
1(R295) 0(R296) 0(R298) 1(R302) Micron MT41K128M16JT-125K 2.2k_J 2.2k_J r0402 r0402

2
r0402 r0402 ns ns

2
ns ns
1(R295) 0(R296) 1(R300) 0(R301) Samsung K4B2G1646Q-BYK0 Q3673

5
Add memeory_ID 1015wls LMBT3904DW1T1G
SOT363

Gsensor_INT0_N 3 4
Gsensor_INT0 10,31
Gsensor_INT1_N 6 1
Gsensor_INT1 10,24
+V1.8A +V1.8A +V1.8A +V1.8A +V1.8A
+V1.8A +V1.8A +V3.3A
change LS 1024 ns
Memory_ID0 Channel Configuration

2
1

R293 R295 R297 R300 R302

2

1K_J 1K_J 1K_J 1K_J 1K_J

1

1
1(R293) Single R0402
Memory_ID
R0402
Memory_ID
R0402
Memory_ID
R0402
Memory_ID
R0402
Memory_ID
R5995
1K_J
R5996
1K_J
R0402 R0402 R556 R558
2

Q3670A 3.3k_J 3.3k_J

Memory_ID0 LBSS138DW1T1G
r0402 r0402
1

2
5

Memory_ID1 Q3670B sot363

Memory_ID2
G

LBSS138DW1T1G
2

Memory_ID3 TP_I2C_2_SCL_N 4 3
0(R288) Double Memory_ID4
sot363
TP_I2C_2_SCL 24
G

TP_I2C_2_SDA_N 1 6
TP_I2C_2_SDA 24
S

D
1

A A
1

R301
R288 R294 R296 R298 1K_J
1K_J 1K_J 1K_J 1K_J R0402
R0402 R0402 R0402 R0402 Memory_ID Reserved 3.3K vendor suggestion1210
Memory_ID Memory_ID Memory_ID Memory_ID
2
2

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Date: Tuesday, June 09, 2015 Sheet 10 of 52

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5 4 3 2 1
 5 4 3 2 1

+V1.8A 7..10,12,14,16,20,23..25,27,31,39,44

D D

U1F ?
CHV_MCP_EDS
+V1.8A

B48 1 TP16
B32 USB_OTG_ID C42
29 USB3_TXP0 USB3_TXP0 USB_DP0 USB_P0 29
C32 B42 USB3.0 Port
29 USB3_TXN0 USB3_TXN0 USB_DN0 USB_N0 29
USB3.0 PORT F28
29 USB3_RXP0 USB3_RXP0
Debug Port D28 C43
29 USB3_RXN0 USB3_RXN0 USB_DP1 USB_P1 34
B44 BH USB2.0 port
USB_DN1 USB_N1 34

2
All USB 3.0 ports support xHCI debug port functionality. A33
From EDS0.95 C33 USB3_TXP1 C41 R78 R79
USB3_TXN1 USB_DP2 USB_P2 30
F30 A41 USB2.0 charger 10K_F 10K_F
USB3_RXP1 USB_DN2 USB_N2 30
D30
USB3_RXN1 R0402 R0402
C45
USB_DP3 USB_P3 27
C34 A45 Bluetooth
USB3_TXP2 USB_DN3 USB_N3 27

1
Leave the unused USB differential signals as NC B34
form checklist09.2 G32 USB3_TXN2 B40

USB3.0

USB2.0
USB3_RXP2 USB_DP4 USB_CAM_DP 24
J32 C40 USB_OC1
USB3_RXN2 USB_DN4 USB_CAM_DN 24Camera
C35 P16 USB_OC1 USB_OC0_N
A35 USB3_TXP3 USB_OC1_B P14 USB_OC0_N
G34 USB3_TXN3 USB_OC0_B USB_OC0_N 29,34
J34 USB3_RXP3 B46
USB3_RXN3 RSVD3 B47 USB_VBUSSNS_R
1 2 USB3_RCOMP_P D34 USB_VBUSSNS A48 R81 1 R0603 2 113_F
R80 402_F R0402 USB3_RCOMP_N F34 USB3_OBSP USB_RCOMP
USB3_OBSN M36
C37 USB_HSIC_0_STROBE N36
RSVD4 USB_HSIC_0_DATA

HSIC
Make sure this resistor is placed as A37 +V1.8A
close as possible to SoC with minimum DC F36 RSVD1 K38

RESERVED
routing resistance and adequately shielded D36 RSVD7 USB_HSIC_1_STROBE M38 R82 49.9 change to 45.3ohm follow CRB1.5 0418
RSVD6 USB_HSIC_1_DATA

1
from external noise sources. from checklist M34 N38 R82 1 45.3_F 2R0402
M32 RSVD11 USB_HSIC_RCOMP close to SoC from checklist R133
RSVD10 AD10 1
UART1_TXD 20K_J
C C38 AD12 1 TP58 C
RSVD5 UART1_RXD TP53 R0402
B38 AD13 1 BIOS demand 1012
RSVD2 UART1_CTS_B

UART
G36 AD14 1 TP44 ns
RSVD8 UART1_RTS_B

2
J36 TP45 USB_VBUSSNS_R
RSVD9 Y6
N34 UART2_TXD Y7
RSVD12 UART2_RXD

1
P34 V9 USB_VBUSSNS_R need 0ohm PD
RSVD13 UART2_CTS_B V10
UART2_RTS_B R0402 for checklist1.2 0122
0_J
R708
1 OF 13
CHV_MCP_EDS/BGA

2
REV = 0.5 ?

B B

A A

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Date: Tuesday, June 09, 2015 Sheet 11 of 52

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documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V1.8A +V3.3A 7,10,20,24,26..28,33,34,37..44 +V1.05A 13,14,38

+ECVCC 20,21,30,33,36,37 +V1.8A 7..11,14,16,20,23..25,27,31,39,44
+V3.3A_RTC 14,20

2
2

2
D R25 R45 C133/C134 change 15PF to 12PF 0118 D
R18 ns 51_J R43 51_J
51_J 51_J change R45 stuff 1229wls +ECVCC
R0402 R0402 +V3.3A_RTC
R0402 R0402
1 2 BATT3 D1

1
C0402 12PF/50V,NPO RTCBAT with Cable LBAT54CLT1G

1
XDP_H_TDI
XDP_H_TDO BRTCX1
C133
+ 1
SOT23-3

XDP_H_TMS -

2
XDP_H_PREQ_N_BUF 3
Y_4P_SMD7014

3
R230
32.768KHZ

2
10M_J 2
Y4 R5973
R0402

1
XDP_H_TCK 1011-00582 1k_J C3764 C136

2
XDP_H_RST CN3 1UF/16V,X5R 0.1UF/10V,X5R
R0603

1
BRTCX2 85204-02001 C0402 C0402

2
2

cns2_1d25_r_85204 ns

1
R44 R26 U1G ?
CHV_MCP_EDS 3
51_J 51_J 1 2 1
ns C0402 12PF/50V,NPO 2 SPONGE_RTC3

JTAG/ITP
R0402 R0402
XDP_H_TCK AF42 M18 BRTCX1 C134 4 RTCBAT GLUE
XDP_H_TDI AD47 TCK BRTCX1_PAD K18 BRTCX2 C3761
TDI BRTCX2_PAD
1

XDP_H_TDO AF40 F16 BVCCRTC_EXTPAD C0402 2 1 0.1uF/16V,X5R

XDP_H_TMS AD48 TDO BVCCRTC_EXTPAD
XDP_H_RST AB48 TMS D18 SRT_CRST_N

RTC
TRST_B SRTCRST_B G16 R430 1 0_J 2 R0402
COREPWROK COREPWROK 44 +V3.3A_RTC
F18
1 XDP_H_PRDY_N AD45 RSMRST_B J16 PMU_RTEST_N PM_RSMRST_N 20
TP41
XDP_H_PREQ_N_BUF AF41 CX_PRDY_B RTEST_B G18 R0402 2 R64 10K_F1 PIN G18 for 10K pull down follow
PR3 2ns R0402 110K_F M13 CX_PREQ_B RSVD_VSS CRB1.5 0524V1.3wls
GND RSVD5

2
EC AE3 PMU_SUSPWRDNACK c0402 Pull-up PMC_WAKE_PCIE[3:0]# to V1P8A by means of a 10-Kresistor
Debug Card P2 SUSPWRDNACK D14 PMU_SUS_STAT# 0.1UF/10V,X5R FOR EMI 1028 from V0.95 DG
20 L_CLKOUT0 MF_LPC_CLKOUT0 SUS_STAT_B

2
R88 1 R0402 2 22_J Debug_Card R3 C15 WLAN_32K_CLK C281 +V1.8A
27 PCH_CK_JIG MF_LPC_CLKOUT1 PMU_SUSCLK

1
L_CLKRUN_N T3 C12 ns R5969 R5970
20 L_CLKRUN_N LPC_CLKRUNB PMU_SLP_S4_B PM_SLP_S4_N 20
32 TPM_CLKOUT1 R89 1 R0402 2 22_J LPC_FRAME_N P3 B14
PM_SLP_S3_N 20 20K_F 20K_F PMU_BATLOW_N R0402 20K_J 2 1 R316
20,27,32 LPC_FRAME_N LPC_FRAMEB PMU_SLP_S3_B

PMU
AF2 PMU_RSTBTN_N PMU_SUS_STAT# R0402 10K_J 2 1 R317

LPC
PMU_RESETBUTTON_B R0402 R0402
M3 F14 PCIE_WAKE_R_N R0402 10K_J 2 1 R315
20,27,32 LPC_AD0 MF_LPC_AD0 PMU_PLTRST_B PLTRST_N 7
M2 C14 PMU_BATLOW_N PMU_RTEST_N
20,27,32 LPC_AD1 MF_LPC_AD1 PMU_BATLOW_B

1
N3 C13 SRT_CRST_N WLAN_32K_CLK R0402 10K_J 2 1 R542
20,27,32 LPC_AD2 MF_LPC_AD2 PMU_AC_PRESENT AC_PRESENT 20
N1 A13 PM_SLP_S0IX_N 1 TP30 PMU_WAKE_LAN_N R0402 10K_J 2 1 R562
20,27,32 LPC_AD3 MF_LPC_AD3 PMU_SLP_S0IX_B

1
B12 PMU_SLP_LAN_N 1 TP32 C3762 C3763 PMU_RSTBTN_N R0402 10K_J 2 1 R563
R0402 PMU_SLP_LAN_B
C R557 1 2 100_F LPC_RCOMPT4 N16
PCIE_WAKE_R_N 26,27 1UF/16V,X5R 1UF/16V,X5R C
T2 LPC_HVT_RCOMP PMU_WAKE_B M16 C0402 C0402
20 ILB_SERIRQ ILB_SERIRQ PMU_PWRBTN_B PM_PWRBTN_N 20

2
P18 PMU_WAKE_LAN_N +V1.8A
+V1.05A +V1.8A TP24 1 H5 PMU_WAKE_LAN_B

PWM
TP26 1 H7 PWM0 AD42 SVID_CLK Intel recommends to shield SVID_DATA signal

SVID
PWM1 SVID0_CLK by routing it in between the SVID_CLK and

1
AD41 SVID_DATA SVID_ALERT# signals.

Voltage sense
SVID0_DATA
1

AD40 SVID_ALERT_L VC 140226 R348

R543 R541 SVID0_ALERT_B
P28 10K_J
20K_J RSVD6
Reserved

20K_J P30 R0402

Follow CRB0.9 1009wls R0402 RSVD7 AG32 R0402 R129 1 4.7_F 2 VCORE0_SENP 543445
R0402 AF50 CORE_VCC0_SENSE VCORE0_SENP 12,43 ns
ns RSVD4 AJ32 R0402 R130 1 4.7_F 2 VCORE0_SENN COREPWROK PM_RSMRST_N PD 100K form checklist0.92 1011
AF48 CORE_VSS0_SENSE VCORE0_SENN 12,43

2
2
RSVD3 AD29 R0402 R564 1 4.7_F 2 VCORE0_SENP
AF44 CORE_VCC1_SENSE VCORE0_SENP 12,43
2

2
RSVD1 AF27 R0402 R565 1 4.7_F 2 VCORE0_SENN R568
AF45 CORE_VSS1_SENSE VCORE0_SENN 12,43

1
PROCHOT_L RSVD2 AD24 R0402 R537 1 2 0_J VGG_SENP R5971 C138 100K_J AC_PRESENT PMU_SUSPWRDNACK
AD50 DDI_VGG_SENSE VGG_SENP 42

2
PROCHOT_B AD22 R0402 R523 1 2 0_J VGG_SENN 100K_F 1UF/6.3V,X5R
UNCORE_VSS_SENSE2 VGG_SENN 42 R0402

1
AC27 1 TP42 R0402 C0402 PD 10K form checklist0.92 1012 R6048
UNCORE_VSS_SENSE1

2
ns R318 100K_F

1
43 VCORE0_VR_HOT_L R576 1 R0402 2 0_J PROCHOT_L Vcore R sen 100ohm change to 4.7ohm 1029 vendor suggestion 1029 10K_J R0402

1
1 OF 13 R0402
42 VGG_VR_HOT_L R577 1 R0402 2 0_J GND
CHV_MCP_EDS/BGA

1
REV = 0.5 ?

2
+V3.3A +V1.8A ns
2
2

R86 +V1.05A
R319 1K_J
10K_J R0402
R0402
1 1

2
1

R6028 R6029 SVID_DATA 2 Load Design Ru=301ohm,Rss=0~20ohm ,Rs=0ohm from DG1.0

301.0_F 301.0_F
2 3 PROCHOT_L
20 PROCHOT_EC_N R0402 R0402
Q1
1

LMBT3904LT1G
SOT23-3
VCC0VCC1Sense
B B
1 R0402 2 VCC_SVID_DATA R6031 1 R0402 2 10.0_F VCC_VDIO
VCC_VDIO 43
R384 0_J
SVID_DATA 1 R0402 2 VGG_SVID_DATA R6032 1 R0402 2 10.0_F VGG_VDIO
VGG_VDIO 42
Length (<=0.5') R385 0_J

+V1.05A +V1.05A
2

R101 R111
200.0_F 200.0_F 2 Load Design SVID_VCLK Ru=200ohm,Rs=200ohm, from DG1.0
R0402 R0402
1

Length (0.5'~1')
1 R0402 2 VCC_SVID_CLK_R R6022 1 R0402 2 200.0_F VCC_VCLK
R427 0_J VCC_VCLK 43
SVID_CLK 1 R0402 2 VGG_SVID_CLK_R R6023 1 R0402 2 200.0_F VGG_VCLK
R431 0_J VGG_VCLK 42

+V1.05A
2

R355
200.0_F
R0402 SVID_ALERT_N 2 Load Design Ru=200ohm,Rs=0~49.9ohm from DG1.0
1

1 R0402 2 VCC_ALERT_R R6025 1 R0402 2 30.0_J

VCC_ALERT_L VCC_ALERT_L 43
R354 0_J
SVID_ALERT_L 1 R0402 2 VGG_ALERT_R R6026 1 R0402 2 30.0_J
VGG_ALERT_L VGG_ALERT_L 42
Length (<=0.5') R353 0_J

A A

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A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 12 of 52
PROPERTY NOTE: this document contains information confidential and property to

sualaptop365.edu.vn
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VCORE0 43 +V1.15S 41
+VGG 42 +V1.05A 12,14,38

+VNN change to +V1.05A

D
5x 0402 1 F D
3x 0603 22 F
+V1.05A

1
C24 C25 C26
22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
U1H ?
CHV_MCP_EDS C0603 C0603 C0603

2
+VCORE0
3x 0402 4.7 F
2x 0603 22 F UNCORE_VNN_S41
AA18 0805 0ohm change to PJ44 1020
delete C23 C33 for layout 1029
AF36 AA19 GND
AG33 CORE_VCC1_S0IX3 UNCORE_VNN_S42 AA21
CORE_VCC1_S0IX7 UNCORE_VNN_S43
1

1
C27 C28 C29 C30 C31 AG35 AA22 C32 C34 C35
22uF/6.3V,X5R 22uF/6.3V,X5R 4.7uF/6.3V,X5R 4.7uF/6.3V,X5R 4.7uF/6.3V,X5R AG36 CORE_VCC1_S0IX8 UNCORE_VNN_S44 AA24 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
C0603 C0603 C0402 C0402 C0402 AG38 CORE_VCC1_S0IX9 UNCORE_VNN_S45 AA25 C0402 C0402 C0402
CORE_VCC1_S0IX10 UNCORE_VNN_S46
2

2
AJ33 AC18
AJ36 CORE_VCC1_S0IX14 UNCORE_VNN_S47 AC19
AJ38 CORE_VCC1_S0IX15 UNCORE_VNN_S48 AC21
+VCORE0 3x 0402 4.7 F GND CORE_VCC1_S0IX16 UNCORE_VNN_S49
UNCORE_VNN_S410
AC22 GND
AC24
2x 0603 22 F AF30
CORE_VCC1_S0IX2
UNCORE_VNN_S411 AC25 VCCSRANSOCIUN1_OBS 1 2 GND
AG27 UNCORE_VNN_S412 change to NC from 553578 1022
CORE_VCC1_S0IX4 AD25 R440 0_J R0402
AG29 UNCORE_VNN_S413 3x 0402 1 F
1

1
C36 C37 C38 C39 C40 CORE_VCC1_S0IX5 AD27 ns
4.7uF/6.3V,X5R AG30 UNCORE_VNN_S414
22uF/6.3V,X5R 22uF/6.3V,X5R 4.7uF/6.3V,X5R 4.7uF/6.3V,X5R CORE_VCC1_S0IX6
C0603 C0603 C0402 C0402 C0402
AJ27
CORE_VCC1_S0IX11 AA30 2x 0402 1 F +VCCSRAMSOCIUN_1P05 2 1 +V1.05A
AJ29 RSVD1
2

2
CORE_VCC1_S0IX12 V33
AJ30 UNCORE_V1P15_S0IX6 R145 0_J R0805

1
CORE_VCC1_S0IX13 AA32 C41 C42 C43 C44 C45
AF29 UNCORE_V1P15_S0IX1
CORE_VCC1_S0IX1 AA33 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
+VGG GND UNCORE_V1P15_S0IX2 AA35 C0402 C0402 C0402 C0402 C0402
UNCORE_V1P15_S0IX3

2
C AD16 AA36 Place STICHING CAPS IF necessary C
AD18 DDI_VGG_S0IX1 UNCORE_V1P15_S0IX4 AC32
5x 0402 10 F AD19 DDI_VGG_S0IX2
DDI_VGG_S0IX3
UNCORE_V1P15_S0IX5
UNCORE_V1P15_S0IX7
Y30
AF16 Y32 GND +VCCDIGICKSI0_1P05 2 1 +V1.05A
AF18 DDI_VGG_S0IX4 UNCORE_V1P15_S0IX8 Y33
DDI_VGG_S0IX5 UNCORE_V1P15_S0IX9 FB1
1

1
C46 C47 C48 C49 C50 AF19 Y35 C51 ns
DDI_VGG_S0IX6 UNCORE_V1P15_S0IX10 180ohm/100MHZ
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 4.7uF/6.3V,X5R AF21 1UF/6.3V,X5R C52
DDI_VGG_S0IX7 FB0603

iCLK
C0603 C0603 C0603 C0603 C0402 AF22 V19 C0402 1uF/6.3V,X5R
DDI_VGG_S0IX8 ICLK_GND_OFF2
2

2
AJ19 V18 GND
DDI_VGG_S0IX15 ICLK_GND_OFF1 c0402
AG16
AG18 DDI_VGG_S0IX9 AM21
+V1.15S GND AG19 DDI_VGG_S0IX10
DDI_VGG_S0IX11
DDR_V1P05A_G31
DDR_V1P05A_G34
AM33 1x 0402 1 F Back Side Cap to be

1
10UF 0603 change to 4.7uf 0402 for layout 1028 AG21 AM22 C53 C54 C55
placed at outside of package die shadow

DDR
AG22 DDI_VGG_S0IX12 DDR_V1P05A_G32 AN22 1UF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
DDI_VGG_S0IX13 DDR_V1P05A_G35
2x 0603 222 F
2

AG24 AN32 C0402 C0603 C0603

DDI_VGG_S0IX14 DDR_V1P05A_G36

2
R146 AJ21 AM32 +VCCADDR_1P05 1 +V1.05A
AJ22 DDI_VGG_S0IX16 DDR_V1P05A_G33
0_J DDI_VGG_S0IX17 R147 0_J R0805

PCIe
AJ24 V22
R0805 4x 0402 1 F AK24 DDI_VGG_S0IX18 PCIE_V1P05A_G31 V24 +VCCBMPD_MPHY_1P05 1 2
DDI_VGG_S0IX19 PCIE_V1P05A_G32 +V1.05A
2x 0402 1 F R148 0_J R0603
1

+VCCRAM0CPU0SI1_1P15
AK30

1
CORE_V1P15_S0IX1 C56 C57 C64

SATA
AK35 U24
1

C58 C59 C60 C61 C62 C63 CORE_V1P15_S0IX2 SATA_V1P05A_G32 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
AK36 U22
1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R CORE_V1P15_S0IX3 SATA_V1P05A_G31 C0402 C0402 C0402
AM29

2
C0402 C0402 C0402 C0402 C0402 C0402 CORE_V1P15_S0IX4
2

V27
USB3_V1P05A_G32

USB
AK33 U27
R149 1 0_J 2 r0603+VCCFHVCPU0SI0_1P15 AJ35 FUSE_V1P15_S0IX2 USB3_V1P05A_G31 V29 +VCCPADSSICAON_1P05 GND 1 2
+V1.15S FUSE_V1P15_S0IX1 USBSSIC_V1P05A_G3 +V1.05A

1
GND C66 R150 R0603 0_J
AM19

FUSE
B B

1
+V1.15S 2 1 +VCCSRAMGEN_1P15 DDI_V1P15_S0IX2 N18 GND C65 1UF/6.3V,X5R
AK21 FUSE3_V1P05A_G5
DDI_V1P15_S0IX1 U19 1UF/6.3V,X5R C0402
R151 0_J R0805 FUSE_V1P05A_G3

2
C0402

2
1
C70
1

C67 C68 C69 1UF/6.3V,X5R

1 OF 13
1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R C0402
CHV_MCP_EDS/BGA

2
C0402 C0402 C0402 REV = 0.5 ? GND
2

+VCCF1_FUSE 1 2 +V1.05A
+VCC1P05_FUSE R1521 0_J 2
R0603 +V1.05A
R153 0_J R0603

1
GND C71 C72
1UF/6.3V,X5R 1UF/6.3V,X5R
C0402 C0402

2
GND

+V1.05A
CAD NOTE:
+V1.05A
CAD NOTE: PLACE CLOSE TO PIN 1 OF RA
PLACE CLOSE TO PIN 1 OF RA
1

C74 C75 C76

1

C73 C77 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R

22uF/6.3V,X5R 22uF/6.3V,X5R C0603 C0603 C0603
2

C0603 C0603
2

A GND Bitland Information Technology Co.,Ltd. A

GND
Page Name Cover Page
Size Project Name Rev
A3 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 13 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5
sualaptop365.edu.vn 4 3 2 1
 5 4 3 2 1

D D
+VDIMM 7,18,19,40,41 +V1.05A 12,13,38
+V1.8A 7..12,16,20,23..25,27,31,39,44 +V1.24A 39
+V1.8S 10,20,23,28,31,44 +V3.3A_RTC 12,20
+V3.3S 7,8,20,23,24,26..28,31,32,34,44 +V3.3A_PRIME 23,37

+VCCSFRPLLDDR_1P24_1P35
GND C78 1 2 1UF/6.3V,X5R

1
C79 C80 +VCCA_DP_1P24_1P35 C0402 R0603 1 0_J 2 R154
+V1.24A
22uF/6.3V,X5R 1UF/6.3V,X5R ?
C0603 C0402 U1I CHV_MCP_EDS

2
+VCCDPYCSIAON_1P24 R155 1 0_J 2 R0603
GND
+V1.24A change to GND 1015wls
GND 1 2 C83 1 2
AN27 V36 GND C82 GND
+VCCCLKDDR_1P24_1P35 AM25 DDRSFR_VDDQ_G_S4 DDI_VDDQ_G31 Y36 C0402 1UF/6.3V,X5R C0402 1UF/6.3V,X5R
DDR_VDDQ_G_S42 DDI_VDDQ_G32 ns ns

1
C81 C84 BE1
DDR_VDDQ_G_S416 T40
22uF/6.3V,X5R 1UF/6.3V,X5R BE53 MIPI_V1P2A_G32
DDR_VDDQ_G_S419 P40
C0603 C0402 BJ2 MIPI_V1P2A_G31 +VCCSFRICKSI0_1P24_1P35 R1561 0_J 2R0603
DDR_VDDQ_G_S426 +V1.24A

2
BJ3 C85 1 2 1 2 ns
DDR_VDDQ_G_S427 Y27 GND GND C86 C0603
BJ49 ICLK_VSFR_G32 C0402 1UF/6.3V,X5R
DDR_VDDQ_G_S428 Y25 1uF/16V,X5R
BJ5 ICLK_VSFR_G31
GND BH50 DDR_VDDQ_G_S429 +VCCPLL_1P24_1P35 R1571 0_J 2R0603
DDR_VDDQ_G_S425 P38 +V1.24A
BH5 CORE_VSFR_G35 C87 1 2 C88 1 2 1 2 ns
DDR_VDDQ_G_S424 V30 GND GND GND

DDR
BH49 CORE_VSFR_G36 C0402 1UF/6.3V,X5R C0402 1UF/6.3V,X5R C89 C0603
+VCCDDR_1P24_1P35 DDR_VDDQ_G_S423 AC30 1uF/16V,X5R
BH4 PCIE_V1P05A_G31
DDR_VDDQ_G_S422

1
C90 C91 BE3 +VCCCPLLCPU_1P24_1P35 R1581 R0805 2 0_J
DDR_VDDQ_G_S417 +V1.24A
22uF/6.3V,X5R 22uF/6.3V,X5R BG51 C92 1 2 1 2 ns
DDR_VDDQ_G_S421 AF35 GND GND C93 C0603
C C0603 C0603 BG3 CORE_VSFR_G34 C0402 1UF/6.3V,X5R C
DDR_VDDQ_G_S420 AD35

2
BJ51 CORE_VSFR_G32 1uF/16V,X5R
DDR_VDDQ_G_S430 AD38
BJ52 CORE_VSFR_G33
DDR_VDDQ_G_S431 AC36
AY10 CORE_VSFR_G31 +VCCPADHSICAON_1P24 R0603 1 R159 2 0_J +V1.24A change to GND 1015wls
DDR_VDDQ_G_S414 GND
GND AY44 C94 1 2 ns
DDR_VDDQ_G_S415 GND
AV44 M41 +VCCUSBSUS_1P24_1P35 C0402 1UF/6.3V,X5R R0603 1 R160 2 0_J
DDR_VDDQ_G_S413 USBHSIC_V1P2A_G3 +V1.24A
1

1
C95 C97 AV10 U35 1 2 C98 1 2 R160 change footprint 1206 to 0603 wls1229
DDR_VDDQ_G_S410 USB_VDDQ_G32 GND C96 GND
22uF/6.3V,X5R 22uF/6.3V,X5R BE51 V35 C0402 1UF/6.3V,X5R C0402 1UF/6.3V,X5R
DDR_VDDQ_G_S418 USB_VDDQ_G33

USB
C0603 C0603 AV38 H44 +VCCSFRUSB2_1P24_1P35 R0805 1 R161 2 0_J
DDR_VDDQ_G_S412 USB_VDDQ_G31 +V1.24A
2

2
AV16 P41 +VCCPADSSICAON_1P24 R0603 1 R162 2 0_J
DDR_VDDQ_G_S411 USBSSIC_V1P2A_G3 GND
AU36 C0402 C99 1 21UF/6.3V,X5R C100 1 2 C101 1 2 +V1.24A change to GND 1015wls
DDR_VDDQ_G_S49 GND GND GND
AU18 AA29 +VCCUSB2_1P8 ns C0402 1UF/6.3V,X5R C0402 1UF/6.3V,X5R ns 1 2
DDR_VDDQ_G_S48 USB_V1P8A_G3 +V1.8A
GND AN36 C102 1 2 C103 1 2 R0603 R163 0_J
DDR_VDDQ_G_S47 GND GND
AN35 C23 C0402 1UF/6.3V,X5R C0402 1UF/6.3V,X5R
AN19 DDR_VDDQ_G_S46 USB_V3P3A_G32 B22
+VSDIO DDR_VDDQ_G_S45 USB_V3P3A_G31
AN18
DDR_VDDQ_G_S44
1

C104 C105 AM36 +VCCUSB2_3P3 R1651 R0603 2 0_J

DDR_VDDQ_G_S43 C5 +V3.3A_PRIME
1UF/6.3V,X5R 1UF/6.3V,X5R AM18 RTC_V3P3RTC_G52 C106 1 2
DDR_VDDQ_G_S41 B6 GND
C0402 C0402 +VCCPADCF3SI0_1P8_3P3 RTC_V3P3RTC_G51 C0402 1UF/6.3V,X5R +VCCRTC_3P3 R1661 R0603 2 0_J Use V3.3A_RTC not +RTCVCC wls0601

RTC
D4 +V3.3A_RTC
2

E1 RTC_V3P3A_G51 E3 GND C107 1 2

ns R1671 0_J R0603
2 C0402 1 2 GND SDIO_V3P3A_V1P8A_G31 RTC_V3P3A_G52 C0402 1UF/6.3V,X7R
+V3.3A_PRIME GND E2
1 2 C108 1UF/6.3V,X5R SDIO_V3P3A_V1P8A_G32 +VCCRTCSUS_3P3 R1691 R0603 2 0_J
+V3.3S R168 +VCCPADCF1SI0_1P8_3P3 G1 +V3.3A_PRIME
0_J R0603 AH4 SDIO_V3P3A_V1P8A_G33 U16 GND C109 1 2
GND C110 2 1 0.1uF/16V,X5R
R171 change to stuff 1 2 +VCCCFIOAZA_1P80 UNCORE_V1P8A_G32 FUSE_V1P8A_G3 C0402 1UF/6.3V,X7R C0402
+V1.8S AF4
1 2 C111 1 2 1UF/6.3V,X5R H10

FUSE
R171 0_J R0603 UNCORE_V1P8A_G31
R170 change to ns 0118 +V1.8A
nsR170 0_J R0603 C0402
GND Y18
AD33 GPIO_V1P8A_G35
FUSE1_V1P05A_G4 G10 +V1P8_FUSE R1721 R0603 2 0_J
+V1.8A
FUSE0_V1P05A_G3 A3 C112 1 2
AK18 GPIO_V1P8A_G31 GND
1 2 +VCCPADCF2SI0_E_1P80 RSVD_VSS K20 +VCCFHV1_FUSE C0402 1UF/6.3V,X5R R1741 R0603 2 0_J
+V1.8A AF33 GPIO_V1P8A_G33 +V1.05A
RSVD1 M20 C113 1 2
R173 0_J R0603 AK19 GPIO_V1P8A_G32 GND
RSVD2
1

C114 C115 C116 GPIO_V1P8A_G34 C0402 1UF/6.3V,X5R

1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1 TP31
C0402 C0402 C0402
2

1 OF 13
CHV_MCP_EDS/BGA Reserved TP FOR 10K PD follow CRB1.0
REV = 0.5 ?
1 2 +VCCPADCF1SI0_1P80 GND
+V1.8A
R175 0_J R0603
1

C117 C118
1UF/6.3V,X5R 1UF/6.3V,X5R
C0402 C0402
2

B B

GND

CAD NOTE:
PLACE THE RESISTORS ACROSS THE DDR PLANE SPLIT

+VDIMM R176 1 2
+VCCSFRPLLDDR_1P24_1P35
R0805 0_J
+VDIMM R177 1 2
+VCCCLKDDR_1P24_1P35
R0805 0_J

+VDIMM +VCCDDR_1P24_1P35

+V3.3A_PRIME R0603 R1811 2 0_J

+VSDIO
+V3.3S R0603 R1821 2 0_J
ns

R181 change to stuff 1020

A A

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Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 14 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

?
U1L CHV_MCP_EDS
Power-VSS
D D
?
U1KCHV_MCP_EDS AN33 Y24
?
U1J CHV_MCP_EDS P32 VSS2 VSS102 G30
Power-VSS
Power-VSS P27 VSS99 VSS53 G28
AN21 AY9 P22 VSS98 VSS52 G26 U1M
CHV_MCP_EDS
?
AN3 AF38 BG30 VSS5 VSS61 AY28 P19 VSS97 VSS51 G22 Power-VSS
AN29 VSS98 VSS51 AF32 BG27 VSS101 VSS52 AY26 AF24 VSS96 VSS50 G14 F1 W1
AN25 VSS97 VSS50 AF25 BG24 VSS100 VSS51 AY24 N53 VSS1 VSS49 G12 C1 VSS18 VSS57 V44
AN24 VSS96 VSS49 AF10 BG20 VSS99 VSS50 AY22 N51 VSS95 VSS48 F5 TP36 1ORNT_CHK_BH53 BH53 VSS17 VSS56 V42
AN16 VSS95 VSS48 AE9 BG19 VSS98 VSS49 AY20 N32 VSS94 VSS47 F35 BH52 VSS16 VSS55 V41
AN14 VSS94 VSS47 AE8 BG18 VSS97 VSS48 AW35 N24 VSS93 VSS46 F32 BH2 VSS15 VSS54 V38
AN12 VSS93 VSS46 AE6 BG16 VSS96 VSS47 AW27 N22 VSS92 VSS45 F27 BH1 VSS14 VSS53
AN11 VSS92 VSS45 AE53 BG14 VSS95 VSS46 AW19 M9 VSS91 VSS44 F24 BG53 VSS13 V32
AN1 VSS91 VSS44 AE50 BF42 VSS94 VSS45 AM13 VSS90 VSS43 F19 BG1 VSS12 VSS52 V21
AM50 VSS90 VSS43 AE48 BF32 VSS93 VSS4 AK29 K45 VSS42 E51 B52 VSS10 VSS51 V16
AM42 VSS89 VSS42 AE46 BF28 VSS92 VSS3 AK22 M40 VSS77 VSS41 E35 B2 VSS5 VSS50 U9
AM4 VSS88 VSS41 AE45 BF27 VSS91 VSS2 AV40 M35 VSS87 VSS39 E19 VSS4 VSS49 U8
AM38 VSS87 VSS40 AE43 BF26 VSS90 VSS44 AV35 M27 VSS86 VSS38 D42 TP35 1 ORNT_CHK_A6 A6 VSS48 U6
AM35 VSS86 VSS39 AE42 BF22 VSS89 VSS43 AV30 AW13 VSS85 VSS37 D40 A5 VSS2 VSS47 U53
AH44 VSS85 VSS38 AE40 BF12 VSS88 VSS42 AV27 M19 VSS3 VSS36 D38 VSS1 VSS46 U5
AM30 VSS60 VSS37 AE14 BE35 VSS87 VSS41 AV24 M14 VSS84 VSS35 D32 M24 VSS45 U49
AM27 VSS84 VSS36 AE12 BE19 VSS86 VSS40 AV19 L35 VSS83 VSS34 D27 A7 VSSA VSS44 U48
U25 VSS83 VSS35 AE11 C20 VSS85 VSS39 AV14 L27 VSS82 VSS33 D24 BF50 VSS3 VSS43 U46
P10 VSS100 VSS34 AE1 BD53 VSS103 VSS38 AJ18 L19 VSS81 VSS32 D16 BF4 VSS9 VSS42 U45
AM16 VSS99 VSS33 AD44 BG7 VSS84 VSS1 AU53 L1 VSS80 VSS31 D10 BB50 VSS8 VSS41 U43
AD4 VSS81 VSS32 AD36 BD35 VSS102 VSS37 AU51 K50 VSS79 VSS30 J42 VSS7 VSS40 U42
AK7 VSS31 VSS30 AC29 BD27 VSS83 VSS36 AU3 T47 VSS78 VSS65 C47 BB4 VSS39 U40
AK50 VSS80 VSS23 AD32 BD19 VSS82 VSS35 AU1 K4 VSS100 VSS29 C39 VSS6 VSS38 U38
AK47 VSS79 VSS29 AD30 BD1 VSS81 VSS34 AT9 K36 VSS76 VSS28 C36 BG47 VSS37
C AK45 VSS78 VSS28 AD21 BC44 VSS80 VSS33 AT51 K34 VSS75 VSS27 C30 Y9 VSS11 U33 C
AK44 VSS77 VSS27 AC38 BC40 VSS79 VSS32 AT45 K32 VSS74 VSS26 C3 Y50 VSS70 VSS35 U32
AK40 VSS76 VSS26 AC35 BC38 VSS78 VSS31 AT36 K30 VSS73 VSS25 C28 Y45 VSS69 VSS34 U30
AK4 VSS75 VSS25 AC33 BC28 VSS77 VSS30 AT35 K24 VSS72 VSS24 C22 Y40 VSS68 VSS33 U29
AK38 VSS74 VSS24 AC16 BC26 VSS76 VSS29 AT3 K22 VSS71 VSS23 AW41 Y4 VSS67 VSS32
AK32 VSS73 VSS22 AB6 BC16 VSS75 VSS28 AT27 K16 VSS70 VSS4 BJ7 Y38 VSS66 U21
AK27 VSS72 VSS21 AB50 BC14 VSS74 VSS27 AT19 K14 VSS69 VSS22 BJ47 Y29 VSS65 VSS31 U18
AK25 VSS71 VSS20 AB47 BC10 VSS73 VSS26 AT18 K12 VSS68 VSS21 BJ43 Y22 VSS64 VSS30 U36
AM24 VSS70 VSS19 AB42 BB35 VSS72 VSS25 AP9 J53 VSS67 VSS20 BJ39 Y21 VSS63 VSS36 U14
AK16 VSS82 VSS18 AB4 BB27 VSS71 VSS24 AP50 M45 VSS66 VSS19 BJ35 Y19 VSS62 VSS29 U12
AJ53 VSS69 VSS17 AB14 BB19 VSS70 VSS23 AP45 J38 VSS88 VSS18 BJ31 Y16 VSS61 VSS28 U11
AJ51 VSS68 VSS16 AB13 BA35 VSS69 VSS22 AP4 J35 VSS64 VSS17 BJ27 Y14 VSS60 VSS27 T9
AJ3 VSS67 VSS15 AB12 BA30 VSS68 VSS21 AN9 J30 VSS63 VSS16 BJ23 Y10 VSS59 VSS26 P42
AJ25 VSS66 VSS14 AB10 BA27 VSS67 VSS20 AN8 J27 VSS62 VSS15 BJ19 VSS58 VSS23 T14
AJ16 VSS65 VSS13 AA53 BA24 VSS66 VSS19 AN6 J22 VSS61 VSS14 BJ15 P4 VSS25 R1
AJ1 VSS64 VSS12 AA38 BA19 VSS65 VSS18 AN53 J19 VSS60 VSS13 BJ11 L41 VSS22 VSS24
AH9 VSS63 VSS11 AA27 1 2 B36 VSS64 VSS17 AN51 J18 VSS59 VSS12 BG5 P36 VSS19 P35
AH47 VSS62 VSS10 AA16 R439 0_J R0402 B28 VSS63 VSS16 AN5 H8 VSS58 VSS11 BG49 VSS21 VSS20
VSS61 VSS9 VSS62 VSS15 VSS57 VSS10 1 OF 13
AH42 A47 AY7 AN49 E46 BG40
VSS59 VSS8 VSS60 VSS14 VSS40 VSS9 CHV_MCP_EDS/BGA
AH41 A43 AY51 AN48 H35 BG38 REV = 0.5 ?
AH14 VSS58 VSS7 A39 GND AY47 VSS59 VSS13 AN46 H27 VSS56 VSS8 BG36 GND GND
AH13 VSS57 VSS6 A31 AY34 VSS58 VSS12 AN45 H19 VSS55 VSS7 BG35
AH12 VSS56 VSS5 A23 AY32 VSS56 VSS11 AN43 M50 VSS54 VSS6 BG34
AH10 VSS55 VSS4 A19 AY30 VSS55 VSS10 AN42 V25 VSS89 VSS5
AG25 VSS54 VSS3 A15 AY3 VSS54 VSS9 AN40 VSS101
AF47 VSS53 VSS2 A11 AN30 VSS53 VSS8 AN38
VSS52 VSS1 AY45 VSS6 VSS7
VSS57 1 OF 13
1 OF 13 CHV_MCP_EDS/BGA
REV = 0.5 ?
B CHV_MCP_EDS/BGA B
GND REV = 0.5 ? GND GND GND
1 OF 13
GND GND
CHV_MCP_EDS/BGA
REV = 0.5 ?

Bitland Information Technology Co.,Ltd.

A A
Page Name Cover Page
Size Project Name Rev
A3 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 15 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5
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 5 4 3 2 1

+V1.8A 7..12,14,20,23..25,27,31,39,44

+V1.8A

D D

2
1

2
R67 R6007

2
R232 R237 R62 100K_F 10K_F R6008
4.7K_F 4.7K_F R6004 R6006 100K_F 1K_J GPIO5_SUS Q9
R0402 R0402
R0402 R0402 10K_F 10K_F R0402 R0402 L2N7002LT1G
R0402 R0402 ns SOT23-3

3
2

1
ns D

1
GPIO0_SUS 1
GPIO0_SUS 10 EC_OVERRIDE 20
S G
Follow baytrail 1019

2
GPIO1_SUS
GPIO1_SUS 10

GPIO2_SUS
GPIO2_SUS 10 Security Flash Descriptors
0 = Override
TP_I2C_INT#_N
R6006 PIN1 net GPIO3_SUS change to
10
1 = Normal Operation
Pull-up to V1P8A with TP_I2C_INT#_N 0524V1.3wls
4.7K 5% resistor delete PD GPIO4_SUS
GPIO4_SUS 10
Enble DDI0 Port Pull-up to V1P8A with
4.7K 5% resistor
Enble DDI1 Port GPIO5_SUS
GPIO5_SUS 10

GPIO8_SUS
GPIO8_SUS 10

GPIO9_SUS
GPIO9_SUS 10
2

2
2

2
R6003 R77
R6001
10K_F
R6002
10K_F
10K_F 10K_F R238
4.7K_F
R243
4.7K_F
R75
10K_F
change to PU follow intel feedback 1024
R0402 R0402
C 0 = Supply is 1.25V C
1 = Supply is 1.35V R0402 R0402 R0402 R0402 R0402
ns ns ns ns
1

This strap also contains ns ns

1

1
PLL LDO
SPI ROM

+V1.8A
2
2

R6013
R6038 R6021 R6018 10K_F
10K_F 10K_F 10K_F R0402
R0402 R0402 R0402
ns
1

ns ns ns
1

GPIO10_SUS
GPIO10_SUS 10

B B

GP_CAMERASB08 8

GP_CAMERASB09 8

GP_CAMERASB11 8
2
2

R6014
R6039 R6040 R6041 10K_F
100K_F 100K_F 100K_F R0402
R0402 R0402 R0402
ns
1
1

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 16 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A Braswall-M 1.0
A A
Date: Tuesday, June 09, 2015 Sheet 17 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5
sualaptop365.edu.vn
4 3 2 1
 5 4 3 2 1

+VDIMM 7,14,19,40,41

+VTT_DDR 19,40

+VDIMM
D U17 +VDIMM D
M_A_DQ[63:0] 7
U16
M_A_DQ3 E3 B2
M_A_DQS_P[7:0] 7 DQL0 VDD
M_A_DQ1 F7 D9 M_A_DQ21 E3 B2
M_A_DQ6 F2 DQL1 VDD G7 M_A_DQ17 F7 DQL0 VDD D9
M_A_DQS_N[7:0] 7 DQL2 VDD DQL1 VDD
M_A_DQ5 F8 K2 M_A_DQ20 F2 G7
M_A_DQ7 H3 DQL3 VDD K8 M_A_DQ19 F8 DQL2 VDD K2
M_A_DQ0 H8 DQL4 VDD N1 M_A_DQ18 H3 DQL3 VDD K8
M_A_DQ2 G2 DQL5 VDD N9 M_A_DQ16 H8 DQL4 VDD N1
M_A_DQ4 H7 DQL6 VDD R1 M_A_DQ23 G2 DQL5 VDD N9
DQL7 VDD R9 M_A_DQ22 H7 DQL6 VDD R1
M_A_DQ13 D7 VDD DQL7 VDD R9
M_A_DQ11 C3 DQU0 A1 M_A_DQ25 D7 VDD
M_A_DQ9 C8 DQU1 VDDQ A8 M_A_DQ31 C3 DQU0 A1
M_A_DQ10 C2 DQU2 VDDQ C1 M_A_DQ27 C8 DQU1 VDDQ A8
M_A_DQ12 A7 DQU3 VDDQ C9 M_A_DQ29 C2 DQU2 VDDQ C1
M_A_DQ15 A2 DQU4 VDDQ D2 M_A_DQ28 A7 DQU3 VDDQ C9
M_A_DQ8 B8 DQU5 VDDQ E9 M_A_DQ24 A2 DQU4 VDDQ D2
M_A_DQ14 A3 DQU6 VDDQ F1 M_A_DQ30 B8 DQU5 VDDQ E9
DQU7 VDDQ H2 M_A_DQ26 A3 DQU6 VDDQ F1 +VTT_DDR
M_A_DQS_P0 F3 VDDQ H9 DQU7 VDDQ H2
7 M_A_DQS_P0 DQSL VDDQ VDDQ
7 M_A_DQS_N0 M_A_DQS_N0 G3 7 M_A_DQS_P2 M_A_DQS_P2 F3 H9
DQSL M_A_DQS_N2 G3 DQSL VDDQ R472 1 2 80.6_F R0402
7 M_A_DQS_N2 DQSL 7 M_A_A0
7 M_A_DQS_P1 M_A_DQS_P1 C7 H1 +V_VREF_DQ_DIMM0 7 M_A_A1 R444 1 2 80.6_F R0402
DQSU VREFDQ +V_VREF_DQ_DIMM0 18
7 M_A_DQS_N1 M_A_DQS_N1 B7 7 M_A_DQS_P3 M_A_DQS_P3 C7 H1 +V_VREF_DQ_DIMM0 7 M_A_A2 R478 1 2 80.6_F R0402
DQSU DQSU VREFDQ +V_VREF_DQ_DIMM0 18
M8 +V_VREF_CA_DIMM0 7 M_A_DQS_N3 M_A_DQS_N3 B7 7 M_A_A3 R448 1 2 80.6_F R0402
VREFCA +V_VREF_CA_DIMM0 18 DQSU M8 1 2
+V_VREF_CA_DIMM0 7 M_A_A4 R479 80.6_F R0402
E7 L8 VREFCA +V_VREF_CA_DIMM0 18 1 2
7 M_A_DM0 DQA_ZQ1 7 M_A_A5 R455 80.6_F R0402
DML ZQ DQA_ZQ1 18
7 M_A_DM1 D3 7 M_A_DM2 E7 L8 DQA_ZQ2 7 M_A_A6 R452 1 2 80.6_F R0402
DNU J1 D3 DML ZQ DQA_ZQ2 18 1 2
M_A_DIM0_ODT1 7 M_A_DM3 7 M_A_A7 R476 80.6_F R0402
NC0 M_A_DIM0_ODT1 7,18 DNU
7 MA_DRAMRST_N T2 J9 M_A_DIM0_CKE1 J1 M_A_DIM0_ODT1 7 M_A_A8 R470 1 2 80.6_F R0402
RESET NC1 L1 M_A_DIM0_CKE1 7,18 T2 NC0 J9 1 2
M_A_DIM0_CS1_N MA_DRAMRST_N M_A_DIM0_CKE1 7 M_A_A9 R451 80.6_F R0402
NC2 M_A_DIM0_CS1_N 7,18 RESET NC1 M_A_DIM0_CKE1 7,18
7,18 M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DP J7 L9 DQA_ZQ5 L1 M_A_DIM0_CS1_N 7 M_A_A10 R447 1 2 80.6_F R0402
CK NC3 DQA_ZQ5 18 NC2 M_A_DIM0_CS1_N 7,18
7,18 M_A_DIM0_CK_DDR0_DN M_A_DIM0_CK_DDR0_DN K7 M7 M_A_A15 7,18 M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DP J7 L9 DQA_ZQ6 7 M_A_A11 R474 1 2 80.6_F R0402
CK NC4 M_A_A15 7,18 K7 CK NC3 M7 DQA_ZQ6 18 1 2
7,18 M_A_DIM0_CK_DDR0_DN M_A_DIM0_CK_DDR0_DN M_A_A15 7 M_A_A12 R480 80.6_F R0402
K9 CK NC4 M_A_A15 7,18 1 2
7,18 M_A_DIM0_CKE0 M_A_DIM0_CKE0 7 M_A_A13 R467 80.6_F R0402
CKE M_A_DIM0_CKE0 K9 R473 1 2 80.6_F R0402
7,18 M_A_DIM0_CKE0 CKE 7 M_A_A14
7,18 M_A_DIM0_CS0_N M_A_DIM0_CS0_N L2 7,18 M_A_A15 R471 1 2 80.6_F R0402
CS M_A_DIM0_CS0_N L2
7,18 M_A_DIM0_CS0_N CS
7,18 M_A_CAS_N M_A_CAS_N K3 7,18 M_A_DIM0_CKE0 R477 1 2 80.6_F R0402
M_A_RAS_N J3 CAS M_A_CAS_N K3 R468 1 2 80.6_F R0402
7,18 M_A_RAS_N RAS 7,18 M_A_CAS_N CAS 7,18 M_A_DIM0_CKE1
7,18 M_A_WE_N M_A_WE_N L3 A9 7,18 M_A_RAS_N M_A_RAS_N J3
WE VSS B3 M_A_WE_N L3 RAS A9 R481 1 2 80.6_F R0402
VSS 7,18 M_A_WE_N WE VSS 7,18 M_A_DIM0_CS0_N
7,18 M_A_A[14:0] E1 B3 7,18 M_A_DIM0_CS1_N R469 1 2 80.6_F R0402
M_A_A0 N3 VSS G8 VSS E1
A0 VSS 7,18 M_A_A[14:0] VSS
M_A_A1 P7 J2 M_A_A0 N3 G8 7,18 M_A_RAS_N R482 1 2 80.6_F R0402
M_A_A2 P3 A1 VSS J8 M_A_A1 P7 A0 VSS J2 R445 1 2 80.6_F R0402
A2 VSS A1 VSS 7,18 M_A_CAS_N
M_A_A3 N2 M1 M_A_A2 P3 J8 7,18 M_A_WE_N R484 1 2 80.6_F R0402
M_A_A4 P8 A3 VSS M9 M_A_A3 N2 A2 VSS M1
M_A_A5 P2 A4 VSS P1 M_A_A4 P8 A3 VSS M9 R446 1 2 80.6_F R0402
A5 VSS A4 VSS 7,18 M_A_BS0
M_A_A6 R8 P9 M_A_A5 P2 P1 7,18 M_A_BS1 R483 1 2 80.6_F R0402
M_A_A7 R2 A6 VSS T1 M_A_A6 R8 A5 VSS P9 R449 1 2 80.6_F R0402
A7 VSS A6 VSS 7,18 M_A_BS2
M_A_A8 T8 T9 M_A_A7 R2 T1
M_A_A9 R3 A8 VSS M_A_A8 T8 A7 VSS T9
M_A_A10 L7 A9 B1 M_A_A9 R3 A8 VSS R459 1 2 80.6_F R0402
A10/AP VSSQ A9 18 DQA_ZQ1
M_A_A11 R7 B9 M_A_A10 L7 B1 18 DQA_ZQ2 R460 1 2 80.6_F R0402
M_A_A12 N7 A11 VSSQ D1 M_A_A11 R7 A10/AP VSSQ B9 R462 1 2 80.6_F R0402
A12/BC* VSSQ A11 VSSQ 18 DQA_ZQ3
M_A_A13 T3 D8 M_A_A12 N7 D1 18 DQA_ZQ4 R461 1 2 80.6_F R0402
C M_A_A14 T7 A13 VSSQ E2 M_A_A13 T3 A12/BC* VSSQ D8 R463 1 2 80.6_F R0402 C
A14 VSSQ A13 VSSQ 18 DQA_ZQ5
E8 M_A_A14 T7 E2 18 DQA_ZQ6 R464 1 2 80.6_F R0402
M_A_BS0 M2 VSSQ F9 A14 VSSQ E8 R465 1 2 80.6_F R0402
7,18 M_A_BS0 BA0 VSSQ VSSQ 18 DQA_ZQ7
7,18 M_A_BS1 M_A_BS1 N8 G1 7,18 M_A_BS0 M_A_BS0 M2 F9 18 DQA_ZQ8 R466 1 2 80.6_F R0402
M_A_BS2 M3 BA1 VSSQ G9 M_A_BS1 N8 BA0 VSSQ G1
7,18 M_A_BS2 BA2 VSSQ 7,18 M_A_BS1 BA1 VSSQ
7,18 M_A_BS2 M_A_BS2 M3 G9
M_A_DIM0_ODT0 K1 BA2 VSSQ
7,18 M_A_DIM0_ODT0 ODT +VTT_DDR
M_A_DIM0_ODT0 K1
ODT
NT5CB64M16DP-CF 7,18 M_A_DIM0_ODT0 R454 1 2 80.6_F R0402
NT5CB64M16DP-CF 7,18 M_A_DIM0_ODT1 R453 1 2 80.6_F R0402

+VTT_DDR
C387
0.1UF/10V,X5R
+VDIMM C0402
U19 +VDIMM R475 1 2 80.6_F R0402 1 2
7,18 M_A_DIM0_CK_DDR0_DP
U18

2
M_A_DQ46 E3 B2 C361
M_A_DQ45 F7 DQL0 VDD D9 M_A_DQ54 E3 B2 10PF/50V,NPO
M_A_DQ42 F2 DQL1 VDD G7 M_A_DQ53 F7 DQL0 VDD D9 C0402
DQL2 VDD DQL1 VDD

1
M_A_DQ40 F8 K2 M_A_DQ55 F2 G7 7,18 M_A_DIM0_CK_DDR0_DN R456 1 2 80.6_F R0402
M_A_DQ43 H3 DQL3 VDD K8 M_A_DQ49 F8 DQL2 VDD K2
H8 DQL4 VDD N1 H3 DQL3 VDD K8
M_A_DQ41
M_A_DQ47 G2 DQL5 VDD N9
M_A_DQ51
M_A_DQ52 H8 DQL4 VDD N1
Rtt for CAC/CLK = 80 5%
M_A_DQ44 H7 DQL6 VDD R1 M_A_DQ50 G2 DQL5 VDD N9 Ctt = 0.1 F, Cterm = 0.2 pF
DQL7 VDD DQL6 VDD
VDD
R9 M_A_DQ48 H7
DQL7 VDD
R1 From Memor Down DG
M_A_DQ33 D7 R9 +VTT_DDR
M_A_DQ39 C3 DQU0 A1 M_A_DQ59 D7 VDD
M_A_DQ32 C8 DQU1 VDDQ A8 M_A_DQ57 C3 DQU0 A1
M_A_DQ38 C2 DQU2 VDDQ C1 M_A_DQ58 C8 DQU1 VDDQ A8
M_A_DQ37 A7 DQU3 VDDQ C9 M_A_DQ60 C2 DQU2 VDDQ C1
DQU4 VDDQ DQU3 VDDQ

1
M_A_DQ34 A2 D2 M_A_DQ56 A7 C9 C364 C362
M_A_DQ36 B8 DQU5 VDDQ E9 M_A_DQ62 A2 DQU4 VDDQ D2 10UF/6.3V,X5R 10UF/6.3V,X5R
M_A_DQ35 A3 DQU6 VDDQ F1 M_A_DQ63 B8 DQU5 VDDQ E9 C0603 C0603
DQU7 VDDQ DQU6 VDDQ

2
H2 M_A_DQ61 A3 F1 ns
M_A_DQS_P5 F3 VDDQ H9 DQU7 VDDQ H2
7 M_A_DQS_P5 DQSL VDDQ VDDQ
7 M_A_DQS_N5 M_A_DQS_N5 G3 7 M_A_DQS_P6 M_A_DQS_P6 F3 H9
DQSL M_A_DQS_N6 G3 DQSL VDDQ
7 M_A_DQS_N6 DQSL
7 M_A_DQS_P4 M_A_DQS_P4 C7 H1 +V_VREF_DQ_DIMM0
B7 DQSU VREFDQ +V_VREF_DQ_DIMM0 18 C7 H1
7 M_A_DQS_N4 M_A_DQS_N4 7 M_A_DQS_P7 M_A_DQS_P7 +V_VREF_DQ_DIMM0
DQSU DQSU VREFDQ +V_VREF_DQ_DIMM0 18
M8 +V_VREF_CA_DIMM0 7 M_A_DQS_N7 M_A_DQS_N7 B7
VREFCA +V_VREF_CA_DIMM0 18 DQSU

1
M8 +V_VREF_CA_DIMM0 C365 C384 C386 C385 C359 C360
VREFCA +V_VREF_CA_DIMM0 18
7 M_A_DM5 E7 L8 DQA_ZQ3 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
DML ZQ DQA_ZQ3 18
7 M_A_DM4 D3 7 M_A_DM6 E7 L8 DQA_ZQ4 C0402 C0402 C0402 C0402 C0402 C0402
DNU DML ZQ DQA_ZQ4 18

2
J1 M_A_DIM0_ODT1 7 M_A_DM7
D3
MA_DRAMRST_N T2 NC0 J9 M_A_DIM0_CKE1 DNU J1 M_A_DIM0_ODT1
RESET NC1 M_A_DIM0_CKE1 7,18 NC0
L1 M_A_DIM0_CS1_N MA_DRAMRST_N T2 J9 M_A_DIM0_CKE1
NC2 M_A_DIM0_CS1_N 7,18 RESET NC1 M_A_DIM0_CKE1 7,18
7,18 M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DP J7 L9 DQA_ZQ7 L1 M_A_DIM0_CS1_N
K7 CK NC3 M7 DQA_ZQ7 18 J7 NC2 L9 M_A_DIM0_CS1_N 7,18
7,18 M_A_DIM0_CK_DDR0_DN M_A_DIM0_CK_DDR0_DN M_A_A15 7,18 M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DP DQA_ZQ8
CK NC4 M_A_A15 7,18 K7 CK NC3 M7 DQA_ZQ8 18
7,18 M_A_DIM0_CK_DDR0_DN M_A_DIM0_CK_DDR0_DN M_A_A15 Note: Place these Caps near to respective DIMM Pins
CK NC4 M_A_A15 7,18
7,18 M_A_DIM0_CKE0 M_A_DIM0_CKE0 K9
CKE M_A_DIM0_CKE0 K9
7,18 M_A_DIM0_CKE0 CKE
7,18 M_A_DIM0_CS0_N M_A_DIM0_CS0_N L2
CS M_A_DIM0_CS0_N L2
B 7,18 M_A_DIM0_CS0_N CS 18 +V_VREF_DQ_DIMM0 B
7,18 M_A_CAS_N M_A_CAS_N K3
M_A_RAS_N J3 CAS M_A_CAS_N K3
7,18 M_A_RAS_N RAS 7,18 M_A_CAS_N CAS

1
7,18 M_A_WE_N M_A_WE_N L3 A9 7,18 M_A_RAS_N M_A_RAS_N J3 C390 C391 C392 C393
WE VSS B3 M_A_WE_N L3 RAS A9 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
VSS 7,18 M_A_WE_N WE VSS
7,18 M_A_A[14:0] E1 B3 c0402 c0402 c0402 c0402
VSS VSS

2
M_A_A0 N3 G8 7,18 M_A_A[14:0]
E1
M_A_A1 P7 A0 VSS J2 M_A_A0 N3 VSS G8
M_A_A2 P3 A1 VSS J8 M_A_A1 P7 A0 VSS J2
M_A_A3 N2 A2 VSS M1 M_A_A2 P3 A1 VSS J8
M_A_A4 P8 A3 VSS M9 M_A_A3 N2 A2 VSS M1
A4 VSS A3 VSS 18 +V_VREF_CA_DIMM0
M_A_A5 P2 P1 M_A_A4 P8 M9
M_A_A6 R8 A5 VSS P9 M_A_A5 P2 A4 VSS P1
A6 VSS A5 VSS

1
M_A_A7 R2 T1 M_A_A6 R8 P9 C398 C406 C408 C410
M_A_A8 T8 A7 VSS T9 M_A_A7 R2 A6 VSS T1 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
M_A_A9 R3 A8 VSS M_A_A8 T8 A7 VSS T9 c0402 c0402 c0402 c0402
A9 A8 VSS

2
M_A_A10 L7 B1 M_A_A9 R3
M_A_A11 R7 A10/AP VSSQ B9 M_A_A10 L7 A9 B1
M_A_A12 N7 A11 VSSQ D1 M_A_A11 R7 A10/AP VSSQ B9
M_A_A13 T3 A12/BC* VSSQ D8 M_A_A12 N7 A11 VSSQ D1
M_A_A14 T7 A13 VSSQ E2 M_A_A13 T3 A12/BC* VSSQ D8
A14 VSSQ E8 M_A_A14 T7 A13 VSSQ E2
M_A_BS0 M2 VSSQ F9 A14 VSSQ E8
7,18 M_A_BS0 BA0 VSSQ VSSQ +VDIMM +VDIMM
7,18 M_A_BS1 M_A_BS1 N8 G1 7,18 M_A_BS0 M_A_BS0 M2 F9
M_A_BS2 M3 BA1 VSSQ G9 M_A_BS1 N8 BA0 VSSQ G1
7,18 M_A_BS2 BA2 VSSQ 7,18 M_A_BS1 BA1 VSSQ
7,18 M_A_BS2 M_A_BS2 M3 G9
BA2 VSSQ

1
M_A_DIM0_ODT0 K1
ODT M_A_DIM0_ODT0 K1 R485 R487
ODT
4.7K_F 4.7K_F
NT5CB64M16DP-CF R0402 R0402
NT5CB64M16DP-CF

2
+V_VREF_DQ_DIMM0 +V_VREF_CA_DIMM0

1
R488 R489

1
4.7K_F C119 C388 4.7K_F C120 C389
+VDIMM 0.1UF/10V,X5R 10UF/6.3V,X5R 0.1UF/10V,X5R 10UF/6.3V,X5R
+VDIMM R0402 R0402
c0402 C0603 c0402 C0603

2
ns ns

2
1

C413 C414 C415 C416 C418 C417 C419 C421 C173 C147 C170
10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0402 C0402 C0402
2

change filter cap to 0.1uF

divider res change to 4.7K_F
add C217 C248
FOR EMI 0122
1

C172 C171
1000pF/50V,X7R 1000pF/50V,X7R
C0402 C0402
2

2
1

C420 C422 C424 C425 C423 C426 C427 C428

A 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R A
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
2

1UF Cap Place as close to DRAM as possible

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A1 Braswall-M 1.0

sualaptop365.edu.vn
Date: Tuesday, June 09, 2015 Sheet 18 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VDIMM 7,14,18,40,41

+VTT_DDR 18,40

M_B_DQ[63:0] 7

D D

+VDIMM
U72 +VDIMM
U73
M_B_DQ17 E3 B2
M_B_DQ18 F7 DQL0 VDD D9 M_B_DQ8 E3 B2
M_B_DQ22 F2 DQL1 VDD G7 M_B_DQ15 F7 DQL0 VDD D9
M_B_DQ16 F8 DQL2 VDD K2 M_B_DQ12 F2 DQL1 VDD G7
M_B_DQ23 H3 DQL3 VDD K8 M_B_DQ11 F8 DQL2 VDD K2
M_B_DQ21 H8 DQL4 VDD N1 M_B_DQ13 H3 DQL3 VDD K8
M_B_DQ19 G2 DQL5 VDD N9 M_B_DQ10 H8 DQL4 VDD N1
M_B_DQ20 H7 DQL6 VDD R1 M_B_DQ9 G2 DQL5 VDD N9
DQL7 VDD R9 M_B_DQ14 H7 DQL6 VDD R1
M_B_DQ7 D7 VDD DQL7 VDD R9
M_B_DQ1 C3 DQU0 A1 M_B_DQ24 D7 VDD
M_B_DQ2 C8 DQU1 VDDQ A8 M_B_DQ27 C3 DQU0 A1
M_B_DQ5 C2 DQU2 VDDQ C1 M_B_DQ26 C8 DQU1 VDDQ A8
M_B_DQ6 A7 DQU3 VDDQ C9 M_B_DQ28 C2 DQU2 VDDQ C1
M_B_DQ0 A2 DQU4 VDDQ D2 M_B_DQ31 A7 DQU3 VDDQ C9
M_B_DQ3 B8 DQU5 VDDQ E9 M_B_DQ25 A2 DQU4 VDDQ D2
M_B_DQ4 A3 DQU6 VDDQ F1 M_B_DQ29 B8 DQU5 VDDQ E9
DQU7 VDDQ H2 M_B_DQ30 A3 DQU6 VDDQ F1
F3 VDDQ H9 DQU7 VDDQ H2
7 M_B_DQS_P2 G3 DQSL VDDQ F3 VDDQ H9
7 M_B_DQS_N2 DQSL 7 M_B_DQS_P1 G3 DQSL VDDQ
C7 H1 7 M_B_DQS_N1 DQSL
7 M_B_DQS_P0 B7 DQSU VREFDQ +V_VREF_DQ_DIMM1 19 C7 H1
7 M_B_DQS_N0 DQSU 7 M_B_DQS_P3 DQSU VREFDQ +V_VREF_DQ_DIMM1 19
M8 B7
VREFCA +V_VREF_CA_DIMM1 19 7 M_B_DQS_N3 DQSU M8
VREFCA +V_VREF_CA_DIMM1 19 +VTT_DDR
7 M_B_DM2 E7 L8
D3 DML ZQ DQB_ZQ1 19 E7 L8
7 M_B_DM0 DNU 7 M_B_DM1 DML ZQ DQB_ZQ2 19
J1 7 M_B_DM3 D3
NC0 M_B_DIM0_ODT1 7,19 DNU
T2 J9 J1 R507 1 2 80.6_F R0402
7,19 MB_DRAMRST_N RESET NC1 L1 M_B_DIM0_CKE1 7,19 T2 NC0 J9 M_B_DIM0_ODT1 7,19 7 M_B_A0 1 2
R530 80.6_F R0402
J7 NC2 L9 M_B_DIM0_CS1_N 7,19 7,19 MB_DRAMRST_N RESET NC1 L1 M_B_DIM0_CKE1 7,19 7 M_B_A1 1 2
7,19 M_B_DIM0_CK_DDR0_DP R514 80.6_F R0402
CK NC3 DQB_ZQ5 19 NC2 M_B_DIM0_CS1_N 7,19 7 M_B_A2
7,19 M_B_DIM0_CK_DDR0_DN K7 M7 7,19 M_B_DIM0_CK_DDR0_DP J7 L9 R532 1 2 80.6_F R0402
CK NC4 M_B_A15 7,19 CK NC3 DQB_ZQ6 19 7 M_B_A3
7,19 M_B_DIM0_CK_DDR0_DN K7 M7 R515 1 2 80.6_F R0402
K9 CK NC4 M_B_A15 7,19 7 M_B_A4 1 2
R490 80.6_F R0402
7,19 M_B_DIM0_CKE0 CKE K9 7 M_B_A5 R535 1 2 80.6_F R0402
7,19 M_B_DIM0_CKE0 CKE 7 M_B_A6
L2 R512 1 2 80.6_F R0402
7,19 M_B_DIM0_CS0_N CS L2 7 M_B_A7 R502 1 2 80.6_F R0402
K3 7,19 M_B_DIM0_CS0_N CS 7 M_B_A8 R536 1 2 80.6_F R0402
7,19 M_B_CAS_N J3 CAS K3 7 M_B_A9 R533 1 2 80.6_F R0402
7,19 M_B_RAS_N L3 RAS A9 7,19 M_B_CAS_N J3 CAS 7 M_B_A10 R511 1 2 80.6_F R0402
7,19 M_B_WE_N WE VSS B3 7,19 M_B_RAS_N L3 RAS A9 7 M_B_A11 R513 1 2 80.6_F R0402
VSS E1 7,19 M_B_WE_N WE VSS B3 7 M_B_A12 R500 1 2 80.6_F R0402
7,19 M_B_A[14:0] VSS VSS 7 M_B_A13
M_B_A0 N3 G8 7,19 M_B_A[14:0] E1 R506 1 2 80.6_F R0402
M_B_A1 P7 A0 VSS J2 M_B_A0 N3 VSS G8 7 M_B_A14 R504 1 2 80.6_F R0402
M_B_A2 P3 A1 VSS J8 M_B_A1 P7 A0 VSS J2 7,19 M_B_A15
M_B_A3 N2 A2 VSS M1 M_B_A2 P3 A1 VSS J8 R510 1 2 80.6_F R0402
M_B_A4 P8 A3 VSS M9 M_B_A3 N2 A2 VSS M1 7,19 M_B_DIM0_CKE0 R501 1 2 80.6_F R0402
M_B_A5 P2 A4 VSS P1 M_B_A4 P8 A3 VSS M9 7,19 M_B_DIM0_CKE1
M_B_A6 R8 A5 VSS P9 M_B_A5 P2 A4 VSS P1 R517 1 2 80.6_F R0402
M_B_A7 R2 A6 VSS T1 M_B_A6 R8 A5 VSS P9 7,19 M_B_DIM0_CS0_N R503 1 2 80.6_F R0402
M_B_A8 T8 A7 VSS T9 M_B_A7 R2 A6 VSS T1 7,19 M_B_DIM0_CS1_N
M_B_A9 R3 A8 VSS M_B_A8 T8 A7 VSS T9 R518 1 2 80.6_F R0402
M_B_A10 L7 A9 B1 M_B_A9 R3 A8 VSS 7,19 M_B_RAS_N R529 1 2 80.6_F R0402
C M_B_A11 R7 A10/AP VSSQ B9 M_B_A10 L7 A9 B1 7,19 M_B_CAS_N R519 1 2 80.6_F R0402 C
M_B_A12 N7 A11 VSSQ D1 M_B_A11 R7 A10/AP VSSQ B9 7,19 M_B_WE_N
M_B_A13 T3 A12/BC* VSSQ D8 M_B_A12 N7 A11 VSSQ D1 R531 1 2 80.6_F R0402
M_B_A14 T7 A13 VSSQ E2 M_B_A13 T3 A12/BC* VSSQ D8 7,19 M_B_BS0 R516 1 2 80.6_F R0402
A14 VSSQ E8 M_B_A14 T7 A13 VSSQ E2 7,19 M_B_BS1 R534 1 2 80.6_F R0402
M2 VSSQ F9 A14 VSSQ E8 7,19 M_B_BS2
7,19 M_B_BS0 N8 BA0 VSSQ G1 M2 VSSQ F9
7,19 M_B_BS1 M3 BA1 VSSQ G9 7,19 M_B_BS0 N8 BA0 VSSQ G1 R492 1 2 80.6_F R0402
7,19 M_B_BS2 BA2 VSSQ 7,19 M_B_BS1 M3 BA1 VSSQ G9 19 DQB_ZQ1 R491 1 2 80.6_F R0402
K1 7,19 M_B_BS2 BA2 VSSQ 19 DQB_ZQ2 R494 1 2 80.6_F R0402
7,19 M_B_DIM0_ODT0 ODT 19 DQB_ZQ3
7,19 M_B_DIM0_ODT0
K1 R495 1 2 80.6_F R0402
ODT 19 DQB_ZQ4 R496 1 2 80.6_F R0402
NT5CB64M16DP-CF 19 DQB_ZQ5 R497 1 2 80.6_F R0402
NT5CB64M16DP-CF 19 DQB_ZQ6 R498 1 2 80.6_F R0402
19 DQB_ZQ7 R499 1 2 80.6_F R0402
19 DQB_ZQ8

+VTT_DDR

R520 1 2 80.6_F R0402

+VDIMM 7,19 M_B_DIM0_ODT0 R521 1 2 80.6_F R0402
U74 +VDIMM 7,19 M_B_DIM0_ODT1
U75
M_B_DQ37 E3 B2
M_B_DQ39 F7 DQL0 VDD D9 M_B_DQ54 E3 B2
M_B_DQ32 F2 DQL1 VDD G7 M_B_DQ51 F7 DQL0 VDD D9 C429 +VTT_DDR
M_B_DQ35 F8 DQL2 VDD K2 M_B_DQ49 F2 DQL1 VDD G7 0.1UF/10V,X5R
M_B_DQ33 H3 DQL3 VDD K8 M_B_DQ55 F8 DQL2 VDD K2 C0402
M_B_DQ38 H8 DQL4 VDD N1 M_B_DQ53 H3 DQL3 VDD K8 R524 1 2 80.6_F R0402 1 2
DQL5 VDD DQL4 VDD 7,19 M_B_DIM0_CK_DDR0_DP
M_B_DQ36 G2 N9 M_B_DQ50 H8 N1
DQL6 VDD DQL5 VDD

2
M_B_DQ34 H7 R1 M_B_DQ52 G2 N9 C451
DQL7 VDD R9 M_B_DQ48 H7 DQL6 VDD R1 10PF/50V,NPO
M_B_DQ46 D7 VDD DQL7 VDD R9 C0402
DQU0 VDD

1
M_B_DQ44 C3 A1 M_B_DQ57 D7 7,19 M_B_DIM0_CK_DDR0_DN R522 1 2 80.6_F R0402
M_B_DQ43 C8 DQU1 VDDQ A8 M_B_DQ59 C3 DQU0 A1
M_B_DQ41 C2 DQU2 VDDQ C1 M_B_DQ61 C8 DQU1 VDDQ A8
A7 DQU3 VDDQ C9 C2 DQU2 VDDQ C1
M_B_DQ42
M_B_DQ40 A2 DQU4 VDDQ D2
M_B_DQ58
M_B_DQ60 A7 DQU3 VDDQ C9
Rtt for CAC/CLK = 80 5%
M_B_DQ47 B8 DQU5 VDDQ E9 M_B_DQ63 A2 DQU4 VDDQ D2 Ctt = 0.1 F, Cterm = 0.2 pF
DQU6 VDDQ DQU5 VDDQ
M_B_DQ45 A3
DQU7 VDDQ
F1 M_B_DQ62 B8
DQU6 VDDQ
E9 From Memor Down DG
H2 M_B_DQ56 A3 F1
F3 VDDQ H9 DQU7 VDDQ H2
7 M_B_DQS_P4 G3 DQSL VDDQ F3 VDDQ H9 +VTT_DDR
7 M_B_DQS_N4 DQSL 7 M_B_DQS_P6 G3 DQSL VDDQ
C7 H1 7 M_B_DQS_N6 DQSL
7 M_B_DQS_P5 DQSU VREFDQ +V_VREF_DQ_DIMM1 19
B7 C7 H1
7 M_B_DQS_N5 DQSU 7 M_B_DQS_P7 DQSU VREFDQ +V_VREF_DQ_DIMM1 19
M8 B7
VREFCA +V_VREF_CA_DIMM1 19 7 M_B_DQS_N7 DQSU

1
M8 C434 C432
E7 L8 VREFCA +V_VREF_CA_DIMM1 19
7 M_B_DM4 10UF/6.3V,X5R 10UF/6.3V,X5R
DML ZQ DQB_ZQ3 19
7 M_B_DM5 D3 7 M_B_DM6 E7 L8 C0603 C0603
DNU DML ZQ DQB_ZQ4 19

2
J1 7 M_B_DM7 D3 ns
T2 NC0 J9 M_B_DIM0_ODT1 7,19 DNU J1
7,19 MB_DRAMRST_N RESET NC1 L1 M_B_DIM0_CKE1 7,19 T2 NC0 J9 M_B_DIM0_ODT1 7,19
NC2 M_B_DIM0_CS1_N 7,19 7,19 MB_DRAMRST_N RESET NC1 M_B_DIM0_CKE1 7,19
7,19 M_B_DIM0_CK_DDR0_DP J7 L9 L1
K7 CK NC3 M7 DQB_ZQ7 19 J7 NC2 L9 M_B_DIM0_CS1_N 7,19
7,19 M_B_DIM0_CK_DDR0_DN CK NC4 M_B_A15 7,19 7,19 M_B_DIM0_CK_DDR0_DP CK NC3 DQB_ZQ8 19
7,19 M_B_DIM0_CK_DDR0_DN K7 M7
K9 CK NC4 M_B_A15 7,19
7,19 M_B_DIM0_CKE0 CKE

1
B K9 C433 C435 C437 C436 C430 C431 B
7,19 M_B_DIM0_CKE0 CKE
L2 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
7,19 M_B_DIM0_CS0_N CS L2 C0402 C0402 C0402 C0402 C0402 C0402
7,19 M_B_DIM0_CS0_N CS

2
K3
7,19 M_B_CAS_N J3 CAS K3
7,19 M_B_RAS_N L3 RAS A9 7,19 M_B_CAS_N J3 CAS
7,19 M_B_WE_N WE VSS B3 7,19 M_B_RAS_N L3 RAS A9
VSS E1 7,19 M_B_WE_N WE VSS B3
7,19 M_B_A[14:0] VSS VSS
M_B_A0 N3 G8 7,19 M_B_A[14:0] E1
M_B_A1 P7 A0 VSS J2 M_B_A0 N3 VSS G8
M_B_A2 P3 A1 VSS J8 M_B_A1 P7 A0 VSS J2
M_B_A3 N2 A2 VSS M1 M_B_A2 P3 A1 VSS J8
M_B_A4 P8 A3 VSS M9 M_B_A3 N2 A2 VSS M1
M_B_A5 P2 A4 VSS P1 M_B_A4 P8 A3 VSS M9
A5 VSS A4 VSS Note: Place these Caps near to respective DIMM Pins
M_B_A6 R8 P9 M_B_A5 P2 P1
M_B_A7 R2 A6 VSS T1 M_B_A6 R8 A5 VSS P9
A7 VSS A6 VSS 19 +V_VREF_DQ_DIMM1
M_B_A8 T8 T9 M_B_A7 R2 T1
M_B_A9 R3 A8 VSS M_B_A8 T8 A7 VSS T9
A9 A8 VSS

1
M_B_A10 L7 B1 M_B_A9 R3 C440 C441 C442 C446
M_B_A11 R7 A10/AP VSSQ B9 M_B_A10 L7 A9 B1 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
M_B_A12 N7 A11 VSSQ D1 M_B_A11 R7 A10/AP VSSQ B9 c0402 c0402 c0402 c0402
A12/BC* VSSQ A11 VSSQ

2
M_B_A13 T3 D8 M_B_A12 N7 D1
M_B_A14 T7 A13 VSSQ E2 M_B_A13 T3 A12/BC* VSSQ D8
A14 VSSQ E8 M_B_A14 T7 A13 VSSQ E2
M2 VSSQ F9 A14 VSSQ E8
7,19 M_B_BS0 N8 BA0 VSSQ G1 M2 VSSQ F9
7,19 M_B_BS1 BA1 VSSQ 7,19 M_B_BS0 BA0 VSSQ 19 +V_VREF_CA_DIMM1
M3 G9 N8 G1
7,19 M_B_BS2 BA2 VSSQ 7,19 M_B_BS1 M3 BA1 VSSQ G9
7,19 M_B_BS2 BA2 VSSQ

1
7,19 M_B_DIM0_ODT0 K1 C447 C448 C449 C450
ODT K1 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
7,19 M_B_DIM0_ODT0 ODT c0402 c0402 c0402 c0402

2
NT5CB64M16DP-CF
NT5CB64M16DP-CF

+VDIMM +VDIMM

1
R525 R527
4.7K_F 4.7K_F
R0402 R0402
+VDIMM

2
+VDIMM +V_VREF_DQ_DIMM1 +V_VREF_CA_DIMM1
1

1
C956 C957 C958 C959 C960 C961 C962 C963
10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R R526 R528
1

1
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C179 C174 C176 4.7K_F C121 C438 4.7K_F C122 C439
2

1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R 0.1UF/10V,X5R 10UF/6.3V,X5R 0.1UF/10V,X5R 10UF/6.3V,X5R

R0402 R0402
C0402 C0402 C0402 c0402 C0603 c0402 C0603
2

2
ns ns

2
A A

FOR EMI 0122

1

C177 C178
1

C964 C965 C966 C967 C968 C969 C970 C971 1000pF/50V,X7R 1000pF/50V,X7R change filter cap to 0.1uF
1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R C0402 C0402 divider res change to 4.7K_F
2

C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402

add C217 C248
2

1UF Cap Place as close to DRAM as possible

Bitland Information Technology Co.,Ltd.
Page Name Cover Page
Size Project Name Rev
A1 Braswall-M 1.0

sualaptop365.edu.vn
Date: Tuesday, June 09, 2015 Sheet 19 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+ECVCC 12,21,30,33,36,37 +V5S 22,25,28,44

+V3.3A_RTC 12,14 +V3.3A 7,10,12,24,26..28,33,34,37..44
+V3.3S 7,8,14,23,24,26..28,31,32,34,44 +V1.8S 10,14,23,28,31,44
+V1.8A 7..12,14,16,23..25,27,31,39,44

+ECVCC +V1.8S

+ECVCC

2
+ECVCC R679
+V3.3A_RTC 2.2k_J

1
R0402

2
R5873 R5874 ns

G
2
R188 R134 4.7K_J 4.7K_J 2 3 SoC_EC_INT#
10 SoC_EC_INT1#

1
thermal sensor NS 0608V1.3wls 2.2k_J

D
UR3 2.2k_J

S
R0402 R0402
100K_J R0402 R0402 Q42
r0402 ns ns BSS138-7

2
C192 2 1 0.1UF/10V,X5R C0402 SOT23-3
1

1
ECRST# +ECVCC
L16
SMB_CLK2 CLK_SMB ns
SMB_DAT2 DAT_SMB
1

D C340 2 1 +V3.3S D
1UF/6.3V,X5R +V1.8A

1
C0402 C156 C153 C157 C154 C158 C155 C159
2

10UF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 120ohm/100MHZ C0402

C0603 C0402 C0402 C0402 C0402 C0402 FB0603 header4
0.1UF/10V,X5R

2
+ECVCC_L
EC_AVCC

2
ns

2
R687

2
R690 R689 2.2k_J
+V3.3S 2 1 1K_J 1K_J Q3665A R688 R0402 header3
R678 1 2 R0402 0_J R19 U4 add R638&R639 ckj0828 R0402 R0402 LBSS138DW1T1G 2.2k_J

5
10K_J +V3.3A
2 1 IT828E ns ns Q3665B sot363 R0402 ns

1
1

114
121

127

G
R0402 R0402 ns0_J R23 C160 LQFP128_0D4_16X16 LBSS138DW1T1G

11
26
50
92

74

1
3

2
U37 Reserved 3.3A for LPC 0607V1.3wls 0.1UF/10V,X5R 10 SMB_CLK_SoC sot363 4 3 SMB_CLK1

1
+V1.8S +V3.3S 110 R393 1 100_J 2 r0402

D
TXB0101 C0402 CLK_SMB_R ns

VCC

AVCC
VBAT

VSTBY
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
SMCLK0/GPB3 CLK_SMB 36

2
111 R686 1 100_J 2 r0402 1 6
1
sot363
6 SMDAT0/GPB4 115
DAT_SMB_R
DAT_SMB 36 battery/Charge 10 SMB_DAT_SoC SMB_DAT1

D
VCCA VCCB SMCLK1/GPC1
SMB_CLK1 ns ns
116
SM BUS SMDAT1/GPC2
SMB_DAT1
SOC
1

1
C313 2 5 C314 117 SMB_CLK2 ns
GND OE PECI/SMCLK2/GPF6(3) 118 SMB_CLK2 21
0.1UF/10V,X5R
C0402 3 4 SERIRQ
0.1UF/10V,X5R
C0402 SMDAT2/GPF7(3)
SMB_DAT2
SMB_DAT2 21 Thermal
12 ILB_SERIRQ A B SERIRQ 32
2

2
12,27,32 LPC_AD0 10
9 LAD0/GPM0(3) 85
12,27,32 LPC_AD1 LAD1/GPM1(3) PS2CLK0/TMB0/CEC/GPF0 +V1.15S_PWRGD 41,42,44
12,27,32 LPC_AD2
8 86 change Pin 86 to 85
LAD2/GPM2(3) PS2DAT0/TMB1/GPF1 WLAN_EN 27
12,27,32 LPC_AD3 7 87 EC_BLT_OFF_N 24
22 LAD3/GPM3(3) PS2CLK1/DTR0#/GPF2 88 AC_PRESENT_EC
7,26,27,32,34 PLT_RST# LPCRST#/GPD2 PS2DAT1/RTS0#/GPF3
L_CLKOUT0_EC 13 89

PS/2
6 LPCCLK/GPM4(3) PS2CLK2/GPF4 90 TP_SMCLK 34
12,27,32 LPC_FRAME_N LFRAME#/GPM5(3) LPC PS2DAT2/GPF5 TP_SMDAT 34 TPad change PS0 to PS2 1012
17
LPCPD#/GPE6 24
PWM0/GPA0 POWER_LED# 33
12 PROCHOT_EC_N
126 25 VOL1+
SERIRQ 5 GA20/GPB5(3) PWM1/GPA1 28 VOL1-
SMC_EXTSMI_N_R 15 SERIRQ/GPM6(3) PWM2/GPA2 29 +V1.8A +V1.8A +V1.8A +V1.8S
23 ECSMI#/GPD4(3) PWM3/GPA3 30 BEEP_EC 28
SMC_RUNTIME_SCI_N_R
14 ECSCI#/GPD3 PWM PWM4/GPA4 31
Rotation_SW#_N
USE SOC GPIO 1023
21 ECRST# WRST# PWM5/GPA5 CHARGE_LED# 33
SoC_EC_INT# 4 32 BATTERY_LED# 33
KBRST#/GPB6(3) PWM6/SSCK/GPA6

1
16 34
39 +V1.24A_EN_EC PWUREQ#/BBO/SMCLK2ALT/GPC7(3) PWM7/RIG1#/GPA7
USB_STAT_L
USB_STAT_L 30 USB charge 1014

1
R652
44 DELAY_ALL_SYS_PWRGD DELAY_ALL_SYS_PWRGD 119 R304 R650 2.2k_J R651
123 CRX0/GPC0 47 2.2k_J 2.2k_J r0402 2.2k_J
36 OZ8782_STDBY CTX0/TMA0/GPB2(3) TACH0A/GPD6(3)

2
48 PM_PWRBTN_EC r0402 r0402 r0402
TACH1A/TMA1/GPD7(3)

2
106
SPI_ROM_CLK_R 105 SSCE1#/GPG0(Up) 120 Q45
FSCK TMRI0/GPC4(3) ACIN_EC 36

5
GPG6 104 124 SLP_S4_EC_N LMBT3904DW1T1G
103 FDIO3/DSR0#/GPG6 TMRI1/GPC6(3)
SPI_ROM_SDI
FMISO FLASH SOT363
1

2
C163 C352 SPI_ROM_SDO_R 102
0.1UF/10V,X5R 33pF/50V,X5R SPI_ROM_CS# 101 FMOSI 3 4 SMC_EXTSMI_N_R
FSCE# 10 SOC_EXTSMI_N
C0402 c0402 100 125 PWRSW#_R
12 PM_RSMRST_N SSCE0#/GPG2 PWRSW/GPE4(3)
2

1
ns 18 10 SOC_RUNTIME_SCI_N
6 1 SMC_RUNTIME_SCI_N_R
RI1#/GPD0(3) BATT_PRS# 36
WAKE UP 21 RUN_ON 44
RI2#/GPD1
add 0.1UF FOR EMI 1028

1
35 C161
RTS1#/GPE5 Novo_SW# 33

1
112 0.1UF/10V,X5R PC178 PC179
Please do not place any pull-up resistor RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 BT_ON 27

2
TP54 C0402 0.1UF/10V,X5R 0.1UF/10V,X5R
on GPG0, GPG2, and GPG6 (Reserved

2
20MIL c0402 c0402

2
hardware strapping). 109 USB_CTL1 ns FOR ns
EMI 1028
IT8528
TXD/SOUT0/GPB1 USB_CTL1 30

1 1
C 108 C
UART RXD/SIN0/GPB0
USBCHA_EN_EC USBCHA_EN_EC 30 UART Port
KSI0 58 TP55
KSI1 59 KSI0/STB# 20MIL
KSI2 60 KSI1/AFD#
KSI3 61 KSI2/INIT# 84 ALW_ON_R R193 1 2 2.2k_J R0402 +V1.8A +V3.3A
KSI3/SLIN# EGCLK/GPE3 ALW_ON 37
KSI4 62 83
63 KSI4 EGCS#/GPE2 82 SUS_ON 40
KSI5 IBATT IBATT 36
KSI6 64 KSI5 EGAD/GPE1
KSI6

1
R90 1 R0402 2 22_J L_CLKOUT0_EC KSI7 65 56 Caps_LED_R#
12 L_CLKOUT0 KSI7 KSO16/SMOSI/GPC3(3)
1

1
57 USB_CTL2
C219 KSO17/SMISO/GPC5(3) 33 USB_CTL2 30 R700 R699
GINT/CTS0#/GPD5 19 R201 2 R0402 1 0_J +VGG_EN_EC 42 2.2k_J 2.2k_J R698 R612
22PF/50V,NPO L80HLAT/BAO/GPE0 LID2_N_IO 34
2

1
C0402 KSO0 36 20 C346 r0402 r0402 2.2k_J 2.2k_J
KSO0/PD0 L80LLAT/GPE7 LIDIN# Q51

5 2

2
ns KSO1 37 GPIO 0.1UF/10V,X5R r0402 r0402
KSO1/PD1

2
KSO2 38 107 c0402 LMBT3904DW1T1G
KSO2/PD2 FDIO2/DTR1#/SBUSY/GPG1/ID7(Dn) +V1.05A_EN 38

2
KSO3 39 SOT363
40 KSO3/PD3
KSO4/PD4 KBMX
KSO4
KSO5 41 99 add EC_OVERRIDE PIN 1019 12 PM_SLP_S3_N 4 3 SLP_S3_EC_N
42 KSO5/PD5 HMOSI/GPH6/ID6 98 EC_OVERRIDE 16 SLP_S3_EC_N 20,44
KSO6 R816 1 0_J 2 R0402
43 KSO6/PD6 HMISO/GPH5/ID5 97 DDI1_BKLT_EN 8,24 1 6
KSO7 GPIO_TEMP_SCAN_V 12 PM_SLP_S4_N SLP_S4_EC_N
KSO7/PD7 HSCK/GPH4/ID4 SLP_S4_EC_N 7
KSO8 44 96 CHG_SW
KSO9 45 KSO8/ACK# HSCE#/GPH3/ID3 95 CHG_SW 30
KSO9/BUSY CTX1/SOUT1/GPH2/SMDAT3/ID2 ALW_PWRGD 37
KSO10 46 94
KSO11 51 KSO10/PE CRX1/SIN1/SMCLK3/GPH1/ID1 93 PM_CKRUN_EC_N 1 2
KSO11/ERR# CLKRUN#/GPH0/ID0 L_CLKRUN_N 12

2
KSO12 52 ns R194 R0402 0_J
KSO12/SLCT

1
KSO13 53 C191 reserve C191 0417
KSO14 54 KSO13 C0402
55 KSO14
KSO15
KSO15
10PF/50V,NPO Add R63 for touch panel LID 0422

2
66 SLP_S3_EC_N SLP_S3_EC_N 20,44
ADC0/GPI0(3) 67 ALL_SYS_PWRGD
ADC1/GPI1(3) ALL_SYS_PWRGD 44
68 R0402 1 R63 2 0_J
ADC2/GPI2(3) TP_LID# 24

1
69 TEMP_ADC_IN2 C367 add 0.1UF FOR EMI 1028
ADC3/GPI3(3) 70 0.1UF/10V,X5R
ADC4/GPI4(3) VDDQ_PWRGD 7,40,44
32KXCLKI 128 71 GPI5 R0402 1 R113 2 0_J +V1.05A_PWRGD 38 c0402
CK32K/GPJ6(3) ADC5/DCD1#/GPI5(3)

2
1 2 72 ns
CK32KE/GPJ7(3) CLOCK
20MIL TP18 BOARD ID
+ECVCC ADC6/DSR1#/GPI6(3) 73 GPI7 R685 1 2 1K_J r0402 +V1.8A +V1.8A
ADC7/CTS1#/GPI7(3) ADP_ID 36
2

TBD A/D D/A

C554 1000PF/50V,X7R R142
C0402 0_J 76 add 1.15S_EN for debug wls0119
TACH2/HDIO2/GPJ0(3) 77 1.15S_EN 41
R0402 HDIO3/GPJ1(3) HW_POP_MUTE_EC# 28

1
R6841 330_J 2 R0402 78 3.3A_5A_PWRGD 37,38
26 Caps_LED_R# DAC2/TACH0B/GPJ2(3) 79
25 DAC3/TACH1B/GPJ3(3) USB_CTL3 30
1

1
KSI0 80 C315 C280 R306 R691 R692 R693

VCORE
24 KSI1 DAC4/DCD0#/GPJ4(3) 81 USB_SEL 30 0.1UF/10V,X5R 0.1UF/10V,X5R 2.2k_J 2.2k_J 2.2k_J 2.2k_J

AVSS
VSS1

VSS3
VSS4
VSS5
VSS6
VSS7
23 KSI2 DAC5/RIG0#/GPJ5(3) c0402 c0402 r0402 r0402 r0402 r0402
22

2
KSI3
21 KSI4 Q56
20
1
12
27
49
91
113
122

75

5
KSI5 LMBT3904DW1T1G
19 KSI6 SOT363
18 VCORE_C

EC_AGND
KSI7
17 KSO15 3 4 AC_PRESENT_EC
16 12 AC_PRESENT
KSO14
15 KSO13 6 1 PM_PWRBTN_EC
14 12 PM_PWRBTN_N
KSO12
13 KSO11
12
1

1
KSO10 C149 C282
11 KSO9 0.1UF/10V,X5R 0.1UF/10V,X5R
10

2
KSO8 C0402 c0402
9
2

2
B B
8
KSO7 ns
KSO6
7 KSO5
6
28 5
KSO4
KSO3
add 0.1UF FOR EMI 1028
27 4 KSO2
3 KSO1
2 KSO0 +ECVCC
1
KBCON1 +ECVCC +ECVCC
1

88513-2641 change to A10 Keybord conn ckj0814 R592

1
1011-01766 4.7K_J
cns26_0d8_r_50519 r0402 R694 R696
4.7K_J 4.7K_J
r0402 r0402
2

VOL1+ R593 1 2 1K_J VOL1- R695 1 2 1K_J Rotation_SW#_N R697 1 2 1K_J Rotation_SW#
VOL+ 34 VOL- 34 Rotation_SW# 34

2
r0402 r0402 r0402
2

2
C341 C342 C343
0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R
c0402 c0402 c0402
1

1
ns ns ns

+ECVCC
1

R128
+ECVCC 4.7K_J
R0402
+ECVCC R539 change to 470K 0127
1

R0402 PWRSW#_R
470K_F
3

R539
LID Switch D Q29
2

U21 L2N7002LT1G
1 2 1
thermistor circuit change to ns 0604V1.3wls LIDIN# sot23-3
GND

VDD VOUT G S
GPIO_TEMP_SCAN_V
2
1

AH180-WG-7 C180
3
2

sot23-3 0.047UF/10V,X7R
1

R394 C268 D12 C270 c0402 +ECVCC

2

47K_J 0.1UF/10V,X5R ns ESD9B5V-2 100PF/50V,NPO ns U26

R0402 c0402 WBFBP-02C c0402 W25X80AVSS1G CO-LAY
2

ns SOP8_1D27_8 +ECVCC +ECVCC GPG6 R392 1 2 100k_J r0402 ns

1

SPI_ROM_CS# 1 8
PWRSW# 33 CE# VDD
1

TEMP_ADC_IN2 SPI_ROM_SDI_R 2 7 HOLD# GPI5 R681 1 2 100k_J r0402

SO/IO1 HOLD#/IO3

1
+ECVCC SPI_ROM_WP# 3 6 SPI_ROM_CLK
WP#/IO2 SCK
1

C397 4 5 SPI_ROM_SDO R190 GPI7 R683 1 2 100k_J r0402

GND SIO/IO0

1
RT8 0.01UF/25V,X7R GND GND GND GND C208 4.7K_J

1
NTC_47K C0402 Follow MINI BTM 0122 ns C0402 R0402
2

R0402 ns ns R140 0.1UF/10V,X5R

2
1K_J SUS_ON R682 1 2 100k_J r0402
2

2
R0402 R141 U24 ALW_ON R680 1 2 100k_J r0402
22_J SPI_ROM_CS# 1 8
+ECVCC SPI_ROM_SDI1 R0402 2SPI_ROM_SDI_R 2 CS# VCC 7HOLD#
DO/IO1 HOLD#/IO3

2
A SPI_ROM_WP# 3 6SPI_ROM_CLK R138 1 0_J 2 R0402 SPI_ROM_CLK_R A
4 WP#/IO2 CLK 5SPI_ROM_SDO R137 1 22_J 2 R0402 SPI_ROM_SDO_R
GND DI/IO0
2

1
R191 R139 W25X512Kbit

1
8.2K_J 1K_J sop8_1d27_6d0 C148
R0402 +ECVCC 3.3V 5% Lenovo Adapter ID Communication R0402 ns C0402
ns ns
SPI ROM 10PF/50V,NPO

2
R386 100K 5%
1

+ECVCC BOARD ID
L14 1 2 120ohm/100MHZ FB0603 EC_AVCC
Non
AC adapter connection Reserved 170W 135W 90W 65W 45W Reserved
1

R143 Board ID R387 V min V typ V max Phase

100K_J
1

C150 C152 R0402

0.1UF/10V,X5R 1000PF/50V,X7R 0 0 0V 0V 0V REV1.0 ID pin resistor
Open 4640 1910 1000 549 287 118 0(short)
C0402 C0402
(ohm,1%) Bitland Information Technology Co.,Ltd.
2

L9 1 2 120ohm/100MHZ FB0603 EC_AGND 1 8.2K 5% 0.216V 0.250V 0.289V REV1.1

EC detection Page Name Cover Page

voltage <=3.056 <=2.590 <=2.109 <=1.618 <=1.134 <=0.663

2 18K 5% 0.436V 0.503V 0.538V REV1.2 >3.093 >2.626 >2.149 >1.663 >1.172 >0.693 >0.234 <=0.207 Size Project Name Rev
@3.3 VREF A1 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 20 of 52
3 33K 5% 0.712V 0.819V 0.875V REV1.3

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Indication by Non support Non support 170W 135W 90W 65W 45W Non support PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
power manager AC message AC message adapter adapter adapter adapter adapter AC message documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+ECVCC 12,20,30,33,36,37

D D

1
C771
0.1UF/10V,X5R +ECVCC
C0402

2
del the pull resistor 4.7k ohm ckj ns NCT7718W
1010-02048
U58
C772
NCT7718W
msop8_0d65_5d0 1 2
8 1 2200PF/50V,X7R
20 SMB_CLK2 SCLK VDD

3
C0402 Place to hotest area
7 2 ns 1 Q79
20 SMB_DAT2 SDATA D+ LMBT3904LT1G
6 3 SOT23-3
ALERT D-

2
5 4
GND THERM HW_OT# 37
ns
ns
R809 1 2
ECRST# 20
ns
0_J R0402

2
External Thermal Sensor(required for sun)

2
R807
4.7K_J R806
R0402 4.7K_J
thermal sensor circuit change to ns 0604V1.3wls R0402

1
ns
ns
+ECVCC
C C
change power from +3.3s to +ECVCC
10-8

B B

A A

Bitland Information Technology Co.,Ltd.

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Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 21 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

sualaptop365.edu.vn
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V5S 25,28,44

D D

Add CHK2 CHK5 R23 R19 R31 R29 FOR EMC 0415

1011-02183
11
9 SATA_TXP0 C1055 1 2 0.01UF/25V,X7R c0402 SATA_TXP0_C 1
9 SATA_TXN0 C1054 1 2 0.01UF/25V,X7R c0402 SATA_TXN0_C 2
3
9 SATA_RXN0 C1053 1 2 0.01UF/25V,X7R c0402 SATA_RXN0_C 4
9 SATA_RXP0 C1052 1 2 0.01UF/25V,X7R c0402 SATA_RXP0_C 5
6
7
8
1.5A
+V5S
R299 1 2 9 13
0_J 10
R0805 12
1

1
C1057 C1058 C1059 C1056 cons10_0d4_r_50453
10uF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 33PF/50V,NPO 54053-010
C0603 c0402 c0402 c0402 SATA_CONN1
2

2
C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 22 of 52

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Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3A_PRIME 14,37
+V1.8S 10,14,20,28,31,44
+V3.3S 7,8,14,20,24,26..28,31,32,34,44
+V1.8A 7..12,14,16,20,24,25,27,31,39,44

D D

U76B
eMMC-SDIN7DU2-16G

R1 A4
+V1.8S +V1.8A R2 NC_R1 NC_A4 A6
1.8S change to 1.8A wls0118 R3 NC_R2 NC_A6 A9
R5 NC_R3 NC_A9 A11
ns NC_R5 NC_A11
R751 1 R0603 2 0_J R12 B2
U76A R13 NC_R12 NC_B2 B13
eMMC-SDIN7DU2-16G R752 1 R0603 2 0_J EMMC R14 NC_R13 NC_B13 D1
T1 NC_R14 NC_D1 D14
T2 NC_T1 NC_D14 H1
C713 C714
Series 10ohm from checklist 0706wls T3 NC_T2 NC_H1 H2 FLASH_D4_IC
0.1uF/10V,X5R 10uF/6.3V,X5R
R46 1 2 NC_T3 NC_H2
8 FLASH_D0 EMMCFLASH_D0_ICH3 DAT0 VCCQ2
AA5 C0402 C0603 T5
NC_T5
A10pin
8 FLASH_D1 R49 1 10.0_F2R0402 EMMCFLASH_D1_ICH4 AA3 EMMC EMMC T12 H7 FLASH_D7_IC
R53 1 10.0_F2R0402 EMMCFLASH_D2_ICH5 DAT1 VCCQ1 Y4 T13 NC_T12 NC_H7 H8
8 FLASH_D2 DAT2 VCCQ5 +V3.3S NC_T13 NC_H8
8 FLASH_D3 R54 1 10.0_F2R0402 EMMCFLASH_D3_IC J2 W4 T14 H9
R87 1 10.0_F2R0402 EMMCFLASH_D4_IC J3 DAT3 VCCQ4 K6 U1 NC_T14 NC_H9 H10
8 FLASH_D4 DAT4 VCCQ3 NC_U1 NC_H10
8 FLASH_D5 R115 1 10.0_F2R0402 EMMCFLASH_D5_IC J4 U2 H11
R116 1 10.0_F2R0402 EMMCFLASH_D6_IC J5 DAT5 U9 R753 1 R0603 ns 2 0_J U3 NC_U2 NC_H11 H12
8 FLASH_D6 DAT6 VCC4 NC_U3 NC_H12
Series 10ohm from checklist 0707
8 FLASH_D7 R117 1 10.0_F2R0402 EMMCFLASH_D7_IC J6 T10 U6 H13
DAT7 VCC3 N5 NC_U6 NC_H13
10.0_F R0402
VCC2 C715 C716R757 1 R0603 2 0_J
+V3.3A_PRIME
U7
NC_U7 NC_H14
H14
R121 1 2 EMMC FLASH_CMD_ICW5 M6 0.1uF/10V,X5R 10uF/6.3V,X5R EMMC U10 J1 FLASH_D3_IC
8 FLASH_CMD CMD VCC1 NC_U10 NC_J1
10.0_F R0402 C0402 C0603 U12 J7
R118 1 2 FLASH_CLK_IC W6 U8 U13 NC_U12 NC_J7 J8
8 FLASH_CLK EMMC CLK VSS4
EMMC EMMC NC_U13 NC_J8
10.0_F R0402 R10 U14 J9
R119 1 2 FLASH_RESET_IC U5 VSS3 P5 V1 NC_U14 NC_J9 J10
9 FLASH_RESET EMMC RESET VSS2
3.3S change to +V3.3A_PRIME wls0118
NC_V1 NC_J10
10.0_F R0402 M7 V2 J11
VSS1 NC_V2 NC_J11

1
C717 K2 V3 J12
C193 0.1uF/10V,X5R VDDI AA6 V12 NC_V3 NC_J12 J13
VSSQ2 NC_V12 NC_J13
2

MMC1_RESET_N C1060 22PF/50V,NPO C0402 AA4 V13 J14

VSSQ1 NC_V13 NC_J14

2
Reserve 10K PU 0.01UF/25V,X7R EMMC Y5 V14 K1 U9_K2
to V1P8A. Reserve C0402 VSSQ5 NC_V14 NC_K1
c0402 ns Y2 W1 K3
VSSQ4 NC_W1 NC_K3
1

0.01uF (10%) PD K4 W2 K5 FLASH_D5_IC

to GND from Checklist 0706 EMMC VSSQ3 NC_W2 NC_K5
U9_K2 W3 K7
reserve C193 For CLK 0417 W7 NC_W3 NC_K7 K8
Add C1060 from checklist 0706 bga169_0d5_14x14 W8 NC_W7 NC_K8 K9
W9 NC_W8 NC_K9 K10
C 1010-01979 NC_W9 NC_K10
C
EMMC W10 K11
W11 NC_W10 NC_K11 K12
W12 NC_W11 NC_K12 K13
W13 NC_W12 NC_K13 K14
W14 NC_W13 NC_K14 L1
Y1 NC_W14 NC_L1 L2
Y3 NC_Y1 NC_L2 L3
Y6 NC_Y3 NC_L3 L4
Y7 NC_Y6 NC_L4 L12
Y8 NC_Y7 NC_L12 L13
Y9 NC_Y8 NC_L13 L14
Y10 NC_Y9 NC_L14 M1
1.8S change to 1.8A 1022 Y11 NC_Y10 NC_M1 M2
+V1.8A Y12 NC_Y11 NC_M2 M3
Y13 NC_Y12 NC_M3 M5
Y14 NC_Y13 NC_M5 M8
RP1 10K_J ra8_0402 AA1 NC_Y14 NC_M8 M9
1 2 FLASH_D1_IC AA2 NC_AA1 NC_M9 M10
3 4 FLASH_D0_IC AA7 NC_AA2 NC_M10 M12
5 6 FLASH_D4_IC AA8 NC_AA7 NC_M12 M13
7 8 FLASH_D3_IC AA9 NC_AA8 NC_M13 M14
AA10 NC_AA9 NC_M14 N1
ns NC_AA10 NC_N1
RP2 10K_J ra8_0402 AA11 N2
1 2 FLASH_D7_IC AA12 NC_AA11 NC_N2 N3
3 4 FLASH_D6_IC AA13 NC_AA12 NC_N3 N10
5 6 FLASH_D2_IC AA14 NC_AA13 NC_N10 N12
7 8 FLASH_D5_IC AE1 NC_AA14 NC_N12 N13
AE14 NC_AE1 NC_N13 N14
ns NC_AE14 NC_N14
R754 10K_J ns FLASH_CMD AG2 P1
R0402 AG13 NC_AG2 NC_P1 P2
AH4 NC_AG13 NC_P2 P3
R755 10K_J ns FLASH_CLK AH6 NC_AH4 NC_P3 P10
R0402 AH9 NC_AH6 NC_P10 P12
AH11 NC_AH9 NC_P12 P13
R756 10K_J ns FLASH_RESET_IC NC_AH11 NC_P13 P14
R0402 NC_P14

bga169_0d5_14x14
EMMC
B B

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 23 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

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documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VDC 36..38,40,42..44
+V3.3S 7,8,14,20,23,26..28,31,32,34,44
+V3.3A 7,10,12,20,26..28,33,34,37..44
+V1.8A 7..12,14,16,20,23,25,27,31,39,44
+V1.8S 10,14,20,23,28,31,44

AUX Channel

1
D PC15 D
0.1uF/25V,X7R LCD_CN15
C0603 Pitch=0.5mm_40Pin

2
2
cns40_0d5_r_51540
R264
100K_F
1 42
R0402
LVDS_CLK-
Screen backlight +VDC 2
ns LVDS_CLK+ 3

1
4
C212 1 2 0.1UF/10V,X5R C0402 eDP_AUXN_C LVDS_DATA0- eDP_VDD
5
8 EDP_AUX_DN
C213 1 2 0.1UF/10V,X5R C0402 eDP_AUXP_C LVDS_DATA0+
Touch panel power 6
8 EDP_AUX_DP 7
+V3.3A
LVDS_DATA1- 8

2
LVDS_DATA1+ 8 EDP_TX0_DN C251 1 2 0.1UF/10V,X5R C0402 eDP_TXN0_C 9
ns ns

2
R267 C207 C537 8 EDP_TX0_DP C298 1 2 0.1UF/10V,X5R C0402 eDP_TXP0_C 10

1
100K_F LVDS_DATA2- c0402 c0402 4.7UF/6.3V,X5R 0.1UF/10V,X5R 11
R0402 LVDS_DATA2+ 330pF/50V,X7R 330pF/50V,X7R C0603 c0402 eDP_AUXP_C 12

1
C546 C547 eDP_AUXN_C 13
ns

2
CRB v1.0 unstuff 14
1

BKLT_PWM 15
BKLT_ON 16
17
+V3.3S Add 3.3A PU 1024 18
19
10 TP_I2C_2_SCL
20
10 TP_I2C_2_SDA
21
TP_I2C_RST# 22
10 TP_I2C_RST#
TP_I2C_INT# 23
10 TP_I2C_INT# 24
+V3.3A Gsensor_Power

2
C545 C544 GsensorIO1_Power 25
+V1.8A
0.1UF/10V,X5R 0.1UF/10V,X5R 26
c0402 c0402 Gsensor_SCL_1 27
10 Gsensor_SCL_1

1
ns ns Gsensor_SDA_1 28
10 Gsensor_SDA_1

1
C15 C23 29
+V3.3S 0.1UF/10V,X5R 0.1UF/10V,X5R Gsensor_INT1 30
10 Gsensor_INT1
C0402 C0402 CAM_Power 31
+V3.3A

2
32
Backlight control

2
33
+V3.3S +VDMIC

2
R270 C368 C250 34

2
10K_J 0.1UF/10V,X5R 4.7UF/6.3V,X5R C538 USB_CAM_DP 35
C From EC R0402 C0402 C0603 0.1UF/10V,X5R USB_CAM_DN 36 C

1
2 c0402 37
20 EC_BLT_OFF_N

1
DMIC_CLK 38
28 DMIC_CLK
1
3 BKLT_ON DMIC_DAT 39
From SOC 28 DMIC_DAT 40 41
D4
20 TP_LID#
1

1 LBAT54ALT1G C224
8,20 DDI1_BKLT_EN

1
SOT23-3 100PF/50V,NPO C195 C194
C0402 150pF/50V,NPO 150pF/50V,NPO
2

ns C0402 C0402

2
1

R272
100K_J
R0402
2

Gsensor_SCL_1
Gsensor_SDA_1

1
From PCH C145 C33
R274 1 2 0_J R0402 BKLT_PWM 150pF/50V,NPO 150pF/50V,NPO
8 DDI1_BKLT_CTRL
C0402 C0402

2
2

ns ns
1

R275 C225
10K_J 1000PF/50V,X7R
R0402 C0402
2

ns
EMC c169 nc->1000pf FOR EMI 0122
1

USB_CAM_DN
USB_CAM_DN 11
USB_CAM_DP
USB_CAM_DP 11
Q8
Q8 change to use QFN8 footfrint MOS 0420
+V3.3S EMF21P02V
1 dfn8_0d65_3x3 delete colay 0ohm 0605V1.3 wls
2 eDP_VDD
3
B
500mA S 5 R282 1 2 0_J R0805 500mA B

D
2

C190 G
1

1
C229 0.1uF/16V,X5R +V3.3A C231 C232 C233 C234
4

1UF/6.3V,X5R C0402 C230 22UF/6.3V,X5R 4.7uF/6.3V,X5R 0.1UF/10V,X5R 33PF/50V,NPO

1

C0402 +V3.3A 0.1UF/10V,X5R R283 C0805 c0603 C0402 C0402

2

2
2

C0402 75.0_J ns
2

ns R287 R0603 Co_lay

R285 2 1 100K_J 100K_J ns
R0402 R0402
1
2

ns R283 62ohm 0402 change to 75ohm 0603footprint 0418

R0402
1

1K_J R286 10K change to 1K 0524V1.3wls

R286
3

6
1

D D
3

Q11 5 G G 2
8 DDI1_VDD_R_EN R289 2 1 1K_J 1 LMBT3904LT1G S S
R0402 sot23-3 Q14A Q14B
4

1
2

L2N7002DW1T1G L2N7002DW1T1G
2

R290 SOT363 SOT363

100K_J ns ns
R0402
1

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Wednesday, June 17, 2015 Sheet 24 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

HDMI_+5VRUN
+V5S 22,28,44
Follow martini +V1.8A 7..12,14,16,20,23,24,27,31,39,44
+V1.8S 10,14,20,23,28,31,44
1.8S change to 1.8A 1020

1
+V1.8A
D17
LBAT54XV2T1G
sod523

2
R278 2 R0402 1 0_J

2
Q49

2
D R325 +V5S WPM2301-3/TR D
2.2k_J R326 SOT23-3 HDMI_+5VRUN
Q15A R0402 2.2k_J ns
LBSS138DW1T1G R0402 3 2 F4 1 2 16V/0.35A FUSE_1206

S
5
sot363

1
R607 1 2 R0805

G
0_J

G
1

1
4 3 DDC3DATA
8 DDI0_CTRL_DATA

1
S

D
R617 R618 C592

2
HDMI 4.7K_J 4.7K_J 0.1UF/10V,X5R

G
r0402 r0402 C0402

2
3
1 6 DDC3CLK
8 DDI0_CTRL_CLK

2
1

D
Q52
LMBT3904LT1G

1
LBSS138DW1T1G sot23-3

2
sot363
Q15B R616
2.2k_J
r0402 Follow baytrail 1023

2
delete colay 0ohm 0605V1.3 wls
HDMI RECEPTABLE A

C285 0.1UF/10V,X5R 1 2 C0402 JTMDS_D2+ TYPE A

8 DDI0_LANE0_DP
8 DDI0_LANE0_DN C286 0.1UF/10V,X5R 1 2 C0402 JTMDS_D2- JTMDS_D2+ 1
2 D2+
GND
JTMDS_D2- 3
4 D2- 20
JTMDS_D1+
D1+
5
GND
JTMDS_D1- 6 21
D1-
JTMDS_D0+ 7
D0+
8
GND
JTMDS_D0- 9
10 D0-
JTMDS_TXC+
1 2 C0402 11 CK+
C C287 0.1UF/10V,X5R JTMDS_D1+ C
8 DDI0_LANE1_DP GND
C288 0.1UF/10V,X5R 1 2 C0402 JTMDS_D1- JTMDS_TXC- 12
8 DDI0_LANE1_DN CK-
TP37 1 13
CEC
14 22
RSD
DDC3CLK 15
DDC3DATA 16 SCL 23
SDA
17
GND
18
HDMI_+5VRUN +5V
HDMI_DET_HPD 19
HPD

1
2
C381 R433

2
470PF/50V,X7R C293 100K_J
C0402 0.1UF/10V,X5R R0402

1
C0402 HDMI_CN2

1
8 DDI0_LANE2_DP C289 0.1UF/10V,X5R 1 2 C0402 JTMDS_D0+ ABA-HDM-022-K01

2
8 DDI0_LANE2_DN C290 0.1UF/10V,X5R 1 2 C0402 JTMDS_D0- hdmi_hmrbc_akx20c

AddC147 C211For EMC 0115

8 DDI0_LANE3_DP C291 0.1UF/10V,X5R 1 2 C0402 JTMDS_TXC+

8 DDI0_LANE3_DN C292 0.1UF/10V,X5R 1 2 C0402 JTMDS_TXC-

HDMI
D7
619 ohm change to 470ohm follow CRB1.5 0417 ESDA6V8UD D8
B DFN10_0D5_2D5X1D0 ESDA6V8UD B
R338 1 R0402 2 470 JTMDS_D2+ DFN10_0D5_2D5X1D0
R339 1 R0402 2 470 JTMDS_D2- JTMDS_TXC- 1 10 JTMDS_TXC-
JTMDS_D1- 1 10 JTMDS_D1-
R340 1 R0402 2 470 JTMDS_D0+
R341 1 R0402 2 470 JTMDS_D0-
JTMDS_TXC+ 2 9 JTMDS_TXC+
R342 1 R0402 2 470 JTMDS_D1+ JTMDS_D1+ 2 9 JTMDS_D1+
R343 1 R0402 2 470 JTMDS_D1-

R344 1 R0402 2 470 JTMDS_TXC+ 3

R345 1 R0402 2 470 JTMDS_TXC- 3
3

JTMDS_D0+ 4 7 JTMDS_D0+
Q16 D JTMDS_D2+ 4 7 JTMDS_D2+
L2N7002LT1G
sot23-3 1 R346 1 2 0_J R0402
+V5S
S G JTMDS_D0- 5 6 JTMDS_D0-
1

JTMDS_D2- 5 6 JTMDS_D2-
2

R347
100K_J
R0402
ns
2

LD1
DDC3CLK SOT23_6 HDMI_DET_HPD
AZC199-04S

6
+V1.8A
2

1
R428 DDC3DATA
A
10K_J R428 change to stuff SIV CPU A
R0402 validation neet it 0420
1

8 DDI0_HPD_Q
3

sot23-3
D Q2
1

C593 L2N7002LT1G
1 HDMI_DET_HPD
Bitland Information Technology Co.,Ltd.
0.1UF/10V,X5R
C0402 S G Page Name Cover Page
2

Size Project Name Rev

A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 25 of 52

sualaptop365.edu.vn
EMC add C593 0627 PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3A 7,10,12,20,24,27,28,33,34,37..44
+V3.3S 7,8,14,20,23,24,27,28,31,32,34,44

TP108
20MIL
TP107 ictpad_c20
ictpad_c20 TP109
D 20MIL 20MIL D
ictpad_c20

1
1
1
LED1/GPO
R587 1 R0402 2 RSET

VDD33

VDD10
XTAL2
XTAL1
2.49K_F

LED0

LED2
VDD33 U28
60MIL IC Ethernet Controller PCIE 10/100/1000M QFN32 REALTEK RTL8111H-CG SMT RoHS
1010-02414 2 1 c0402 ns

32
31
30
29
28
27
26
25
+V3.3A
qfn32_0d4_4X4 C518 1uF/6.3V,X5R

2
33

AVDD33_2

AVDD10_4

LED1/GPO
LED2(LED1)
RSET

CKXTAL2
CKXTAL1
LED0
GND1

2
C507 C508 C513 C491

2
4.7uF/6.3V,X5R 0.1UF/10V,X5R ns C495 4.7uF/6.3V,X5R 0.1UF/10V,X5R 2 1 c0402

1
c0603 c0402 C514 0.1UF/10V,X5R VDD33 C517 0.1UF/10V,X5R
c0603 C0402

1
ns 4.7uF/6.3V,X5R C0402

1
ns MDI0+ 1 24 REGOUT
c0603 MDIP0 REGOUT(NC) +V3.3S
ns MDI0- 2 23 AVDD33_REG
VDD10 3 MDIN0 VDDREG(DVDD33) 22 VDD10
MDI1+ 4 AVDD10_1 DVDD10_1(NC) 21 PCIE_WAKE#
Cin1 Cin2 Pin11 Pin32 MDI1-
MDI2+
5
6
MDIP1
MDIN1
LANWAKEB
ISOLATEB
20
19
ISOLATEB
LAN_PLT_RST#
R590 1 2 1K_J r0402

MDI2- 7 MDIP2(NC) PERSTB 18 R586 1 2 15K_J R0402

For RTL8111GUL/ RTL8106EUL (SWR mode) MDIN2(NC) HSON
Note: VDD10 8 17
AVDD10_3(NC) HSOP
1. Refer to the RTL8111GUL/ RTL8106EUL Layout Guide
for Cout1, Cout2 selection criteria.
2. Other than Lx, no inductor or bead should be placed
on the path from REGOUT to VDD10 PCIE_WAKE_R_N 12,27

AVDD33_1(NC)
RTL8111H Suoport LDO mode Cin1Cin2 2 1
PLT_RST# 7,20,27,32,34

MDIN3(NC)

REFCLK_N
MDIP3(NC)

REFCLK_P
C1023 C509 can ns vendor suggestion 1029 R0402 0_J R589

CLKREQB
vendor suggest VDD10
add ckj0822

HSIN
HSIP
60MIL
REGOUT

9
10
11
12
13
14
15
16
P30

0.1UF/10V,X5R

0.1UF/10V,X5R

0.1UF/10V,X5R
2

2
MDI3+

C492

C0402

C494

C0402

C490

C0402
C510
C1023 C509 0.1UF/10V,X5R MDI3-
C 0.1UF/10V,X5R 4.7uF/6.3V,X5R VDD33 C
C0402
1

PCIE_RXN0
PCIE_RXP0
c0402 XTAL1
c0603
ns ns <=+/-50ppm, ESR<30ohm
Add RN5 FOR CLK SI debug 0415
2 4 y_4p_smd3225
9 PCIE_LAN_CLKREQ2
3 1 XTAL2
RTL8111GUL&RTL8106EUL do not support LDO Pin3
modePin8 Pin30 9 PCIE_LAN_CLKP2
Y5 25MHZ

2
C0402 C0402
9 PCIE_LAN_CLKN2 22PF/50V,NPO 22PF/50V,NPO
Cin1&Cin2 should be placed on the path from 33VAUX to VDDREG/VDD33 delete colay 0ohm 0605V1.3 wls9
9 PCIE_LAN_TXP2 C295 C296
PCIE_LAN_TXN2

1
C1030 1 2 0.1UF/10V,X5R C0402
9 PCIE_LAN_RXP2 C1031 1 2 0.1UF/10V,X5R C0402
9 PCIE_LAN_RXN2

BIOSPCIE LANEPCIE LAN

Supplier suggest change 18pf to 22pf 0118

U25 RXCT1 R585 1 75_J 2 r0603

MDI3- 2 23 TX3-
MDI3+ 3 TD1+ MX1+ 22 TX3+
1 TD1- MX1- 24 RXCT1 TXCT1 PF1
TCT1 MCT1

1
4 21 TXCT1 P4200SC C485 C515
TCT2 MCT2
2

C479 C480 MDI2- 5 20 TX2- d_smb 1000pF/2KV,X7R 0.1uF/25V,X7R

MDI2+ 6 TD2+ MX2+ 19 TX2+ RXCT2 c1206 C0603
0.1UF/10V,X5R 0.1UF/10V,X5R
TD2- MX2-

2
c0402 c0402 MDI1- 8 17 TX1- ns
TD3+ MX3+
1

1000M LAN ns MDI1+ 9 16 TX1+

7 TD3- MX3- 18 RXCT2 TXCT2
10 TCT3 MCT3 15 TXCT2
MDI0- 11 TCT4 MCT4 14 TX0-
B MDI0+ 12 TD4+ MX4+ 13 TX0+ B
TD4- MX4-
2

C481 C482
0.1UF/10V,X5R 0.1UF/10V,X5R GSC-2410-R
c0402 c0402 transformer24_2d5_18d2x12d9
1

ns ns 1000M LAN
CN14
130470-2
rj45_2rj1656-010111f

OK
1011-02287

11
LD8 LD9
SOT23_6 SOT23_6

NPTH2
MDI0- AZC199-04S MDI1- MDI2- AZC199-04S MDI3-
TX0+ 1 10
1A GND2
4

C486 0.1UF/10V,X5R c0402 TX0- 2

2 1 TX1+ 3 2A
C484 0.1UF/10V,X5R c0402 TX2+ 4 3A
2 1 TX2- 5 4A
C483 0.1UF/10V,X5R c0402 TX1- 6 5A
2 1 TX3+ 7 6A
TX3- 8 7A 9

NPTH1
8A GND1
3

MDI0+ MDI1+ MDI2+ MDI3+

12
GND_RJ45

GND_RJ45

A A

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Date: Tuesday, June 09, 2015 Sheet 26 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3A 7,10,12,20,24,26,28,33,34,37..44
+V3.3S 7,8,14,20,23,24,26,28,31,32,34,44
+V1.8A 7..12,14,16,20,23..25,31,39,44

3.3V is available during the systems stand-by/suspend state to

D D
support wake event processing on the communications card.
WLAN_+3_3V
+V3.3S +V3.3A
ns place near Pin2 Pin72
1 R358 2 0_J
R0805

1
C322

1
C319 C320 C321 0.1UF/10V,X5R C324
10UF/6.3V,X5R 0.1UF/10V,X5R 10UF/6.3V,X5R C0402 C323 10UF/6.3V,X5R

2
C0603 C0402 C0603 0.1UF/10V,X5R C0603

2
C0402

use 3.3S for WLAN 0122

WLAN_+3_3V change to 1.8A 0126

+V1.8A WLAN_+3_3V

1
R569 R572
Q3677A 3.3k_J 3.3k_J
LBSS138DW1T1G
r0402 r0402

2
5
Q3677B sot363
ns 2 1 LAD0

G
LBSS138DW1T1G
12,20,32 LPC_AD0

2
R0402 0_J R207 PCIE_WAKE_R_N sot363 4 3 ns ns PCIE_WAKE_R_N_NGFF
12,26 PCIE_WAKE_R_N
ns 2 1 LAD1

D
12,20,32 LPC_AD1 NGFF_PCIE_CLKREQ1 1 6 NGFF_PCIE_CLKREQ1_N
R0402 0_J R208 9 NGFF_PCIE_CLKREQ1
ns 2 1 LAD2 ns

D
WLAN_+3_3V
12,20,32 LPC_AD2
R0402 0_J R210 Reserved 3.3K vendor suggestion1210
12,20,32 LPC_AD3 ns 2 1 LAD3 WIFI_CN5
R0402 0_J R212 NGFF SlotA-SD KeyE ns
C
12,20,32 LPC_FRAME_N ns 2 1 LFRAME# ngff_conn_80152-2121 C
R0402 0_J R213 Add Level_Shifter 1022
NGFF SlotA-SD
75
74 GND1 73 LFRAME#
72 3.3Vaux3 RESERVED1 71 LAD3
LAD2 70 3.3Vaux2 RESERVED2 69
LAD1 68 RESERVED3 GND2 67
LAD0 66 RESERVED4 Reserved6/PERn1 65 PCH_CK_JIG 12
PLACE near signal devided 64 RESERVED5 Reserved7/PERp1 63
10-15 62 NFC Reset# (MGPIO7)/RESERVED GND3 61
60 NFC I2C IRQ (MGPIO5)/ALERT Reserved8/PETn1 59
58 NFC I2C SM CLK/I2C CLK Reserved9/PETp1 57
56 NFC I2C SM DATA/I2C DATA GND4 55 PCIE_WAKE_R_N_NGFF
20 WLAN_EN W_DISABLE#1(WIFI) PEWake0#
20,27 BT_ON R360 2 2.2k_J 1 R0402 BT_DIABLE 54 53 R0402 R361 1 2 0_J ns NGFF_PCIE_CLKREQ1_N
R362 2 0_J 1 R0402 PCIE_RST#_S 52 Reserved/W_DISABLE#2(BT) CLKRQ0# 51
7,20,26,32,34 PLT_RST# 50 PERST0# GND5 49 NGFF_REFCLK1_DN
48 SUSCLK REFCLKN0 47 NGFF_REFCLK1_DP NGFF_REFCLK1_DN 9
46 COEX1 REFCLKP0 45 NGFF_REFCLK1_DP 9
44 COEX2 GND6 43
COEX3 PERn0 NGFF_RXN1 9 pcie_RXN
42 41 pcie_RXP
40 CLINK_CLK/RESERVED PERp0 39 NGFF_RXP1 9
38 CLINK_DATA/RESERVED GND7 37
36 CLINK_RST/RESERVED PETn0 35 NGFF_TXN1 9
UART RTS PETp0 NGFF_TXP1 9 pcie_TXN
34 33 pcie_TXP
32 UART CTS GND8
WLAN_+3_3V UART Tx

KEY E
2

23
R363 22 SDIO_RST 21
20 UART Rx SDIOWAKE 19
1M_J UART Wake SDIODAT3
18 17
R0402 GND9 SDIODAT2
16 15
ns 14 LED#2 SDIODAT1 13
PCM_OUT SDIODAT0
11

12 11
Q18 10 PCM_IN SDIOCMD 9
G

3 2L2N7002LT1G BT_DIABLE 8 PCM_SYNC SDIOCLK 7

B 20,27 BT_ON 6 PCM_CLK GND10 5 USB_N3 B
sot23-3
D

LED#1 USB_D- USB_N3 11

ns 4 3 USB_P3
3.3Vaux1 USB_D+ USB_P3 11
2 1
3.3Vaux0 GND11

GND12

GND13

P0

P1
76

77

78

79

A A

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A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 27 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3A 7,10,12,20,24,26,27,33,34,37..44
+V3.3S 7,8,14,20,23,24,26,27,31,32,34,44
+V5S 22,25,44
+V1.8S 10,14,20,23,31,44
Global Headset (ALC3240 supported iPhone/Nokia headset, Headphone)

MIC2-VREFO
R664
MIC2-VREFO 1 2 2.2k_J R0402
D Analog D
1 R658 2 2.2k_J R0402

10UF/6.3V,X5R
Digital

2
CA3

1
SLEEVE

C0603 CA5
1uF/6.3V,X5R
SLEEVE 34

2
c0402

1uF/6.3V,X5R

1
+V1.8S RING2

CA2
c0402
CA4
RING2 34

2
10UF/6.3V,X5R

MIC2-VREFO
1
C0603 HPOUT-L
HPOUT-L 34

HPOUT-R

2
HPOUT-L

1
CA6 +5VA HPOUT-R
HPOUT-R 34
2.2UF/6.3V,X5R
c0402 HP-JD_CON
HP-JD_CON 34

2
+V1.8S

30

29

28

27

26

25

24

23

22

21
BA2 1 2 FB0603 ALC3240_AVDD2 UA1
80ohm/100MHZ PCB trace width of SLEEVE &

CBP

CPVEE

HPOUT-R(PORT- I -R)

HPOUT- L(PORT- I - L)

LDO1-CAP
CBN

LINE1-VREFO- L

MIC2- VREFO
CPVDD

VREF

1
CA8 CA10 RING2 are required at least 40
1 2 CA7 10UF/6.3V,X5R vendor chang 3.3S----> 3.3A ckj0826
mil and its length should be as
0.1UF/10V,X5R 0.1UF/10V,X5R C0603
short as possible.

2
c0402 31 c0402
C0603 C0603 CA52 AVSS2 20 +V3.3A
1 2 32 AV DD1
+V5S CA11 LDO2- CAP 19
10UF/6.3V,X5R 10UF/6.3V,X5R
1 2 33 A VSS1 1 2
AVDD2 18 R567 0_J R0402
LINE1- L( PORT-C- L)

1
BA5 1 2 180ohm/100MHZ 34
PVDD1

1
FB0603 17 CA50 CA46
LINE1-R( PORT-C-R)
1

SPK-L+ 35

ALC3240
CA12 0.1UF/10V,X5R 10UF/6.3V,X5R
SPK- OUT- LP

2
1

1
CA15 C325 CA16 10UF/6.3V,X5R CA13 16 c0402 C0603
VD33 STB

2
0.1UF/10V,X5R 10uF 6.3V X5R 10uF/6.3V,X5R C0603 0.1UF/10V,X5R SPK-L- 36
SPK- OUT- LN
2

c0402 C0603 C0603 c0402 15 MIC1-L CA44 1 2 10UF/6.3V,X5RC0603 +V3.3S

MIC2- CAP
2

ns SPK-R- 37 (Include Thermal pad) vendor change 1.8s----> 3.3s 1022WLS

SPK- OUT- RN 14 SLEEVE 100K_J R0402
Add this Filter to avoid other SPK-R+ 38 MIC2-R( PORT-F-R)/ SLEEVE R874 2 1
components/chips be influenced SPK- OUT-RP 13 RING2

GPIO0/DMIC-DATA12
39 MIC2- L( PORT-F- L )/ RING2
qfn40_0d4_5x5
PVDD2 12 RA2 1 2 200K_J HP-JD_CON Analog

GPIO1/DMIC-CLK
1010-02406 R0402
PDB 40 HP / LINE1- JD( JD1)
PDB

SDAT A-OU T
11 Digital

SDA TA- I N
PCBEEP
1

41

LDO3-CAP
CA17 CA18

DVDD- IO
10UF/6.3V,X5R 0.1UF/10V,X5R EPAD

DC DET
BCL K
DVDD
CA19 1 2 0.1UF/10V,X5R c0402 2 RA3 1 10K_J

SYNC
C C0603 c0402 r0402 C
PCH_HDA_SPKR 9
2

CA20 1 2 0.1UF/10V,X5R c0402 2 RA4 1 10K_J r0402

BEEP_EC 20

1
CA23

10

1
100PF/50V,NPO
c0402 RA5 RA6

2
+V3.3S 4.7K_J 4.7K_J

R6041 2
R0402 R0402 place close audio codec
0_J

2
R0402
1

1
CA24

1
CA21 CA22 10UF/6.3V,X5R
+V3.3S 0.1UF/10V,X5R 10UF/6.3V,X5R C0603
2

2
c0402 C0603
Place close to pin 1 2
2

change +V1.8S 0910

vendor suggest ns 0826 R367
1K_J
R0402 +V1.8S
HDA_SYNC 9
ns
1 2
1

1 2 RA26 0_J R0402

20 HW_POP_MUTE_EC#
R370 0_J R0402 R368 1 2 33_J r0402 INTSPK1
HDA_SDIN 9
2

85204-04001
1

R369 C326 cns4_1d25_r_85204

HDA_BIT_CK 9
10K_J 0.1UF/10V,X5R FRH5D28-8R2N 1.6A 1011-00537

1
R0402 c0402 CA25
2

1
6.8PF/50V,NPO CA48 CA47 SPK-R+ RA9 r0603 0_J INT_SPK_R+_CN 1 5
C0402 0.1UF/10V,X5R 4.7uF/6.3V,X5R SPK-R- RA10 r0603 0_J INT_SPK_R-_CN 2
1

2
c0402 C0603 SPK-L+ RA11 r0603 0_J INT_SPK_L+_CN 3

2
SPK-L- INT_SPK_L-_CN 4 6

1 CA28

1 CA29

1 CA30
220PF/50V,NPOCA31
HDA_SDOUT 9 Place close to pin 8 RA12 r0603 0_J

CA25 22PF change to 6.8PF FOR SI 0415 layout note:

220PF/50V,NPO

220PF/50V,NPO

220PF/50V,NPO
1
Demodulation Filter Placement
near Audio Codec
SPK L+ L- R+ R- trace width

2
+V5S DIGITAL BA4
ANALOG +5VA DMIC_CLK 24 Speaker 4 ohm ==> 40 mils
Speaker 8 ohm ==> 20 mils
DMIC_DAT 24 ( s210 speaker impendence=8 ohm)
FB0603 2 1 120ohm/100MHZ

c0402

c0402

c0402

c0402
1

B B
1

RV2 CA32
P3500SC_25-110pF 4.7uF/6.3V,X5R
D_SMB C0603 ns ns ns ns
2

/AZ2015-01H
2

+V3.3A
Moat
In orderns
to prevent the built-in LDO damaged from
over-voltage on +5VSYS or Standby power line, we
1

SLEEVE
suggested using this Voltage suppressing device. R591
vendor chang to Reserved ckj0826 100K_J
R0402
3

RA15 r0603 0_J

D Q19A
2

L2N7002DW1T1G
5 G
ns S
Analog_ground C327
Digital_ground
4
6

1 2
D Q19B ns
0.1UF/10V,X5R L2N7002DW1T1G
HW_POP_MUTE_EC# R372 1 1K_J 2 R0402 2 G
c0402 S
Analog_ground Digital_ground
ns
1
2

CA35
Near AVDD1 and AVDD2 power source input 1uF/6.3V,X5R
c0402 ns
1

ns
RA16 r0603 0_J

Analog_ground Digital_ground

Tied at one point only under

A Codec or near the Codec A

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Date: Tuesday, June 09, 2015 Sheet 28 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
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documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V5A 30,34,37..44

chk1 chk3 FOR EMI SIV 0122

D D

3 2 SSRX0- USB0_5V
11 USB3_RXN0
4 1 SSRX0+
11 USB3_RXP0 QFN5_2D3X2D7 USB30_CN1
CMF-2012-2G45-32T TAR29-9Y1391

5
CHK1 usb_umn109d-9g-55
SSRX0- 5
4 RX-
SSRX0+ 6 PGND 13
USB_P0 3 RX+ GND4 12
7 D+ GND3 11
USB_N0 2 GND GND2 10
USB_P0 SSTX0- 8 D- GND1
11 USB_P0 TX-
USB_N0 1
11 USB_N0 Vbus
SSTX0+ 9
TX+

11 USB3_TXN0 C328 2 1 0.1UF/10V,X5R C0402 3 2 SSTX0-

11 USB3_TXP0 C329 2 1 0.1UF/10V,X5R C0402 4 1 SSTX0+
QFN5_2D3X2D7
CMF-2012-2G45-32T

5
CHK3

C C

Intel recommends each USB3.0 slot be

capable of supplying a minimum of 0.9 A
+V5A USB0_5V

U12
1 8 USB0_5V USB0_5V
2 GND OUT_3 7
3 IN_1 OUT_2 6
IN_2 OUT_1
2

4 5
EN(EN#) OC# USB_OC0_N 11,34

2
R381

1
ns 10K_J uP7534BRA8-15 C330 PC6 C331 C332 R380
r0402 MSOP8_0D65_2D54 0.1UF/10V,X5R 100uF/6.3V,X5R ns 22uF/10V,X5R ns22uF/10V,X5R 20K_J
1

C333 C334 C0402 C1206 C0805 C0805 R0402

1

2
1

0.1uF/16V,X5Rns 10uF/6.3V,X5R
C0402 c0805
C594
0.1UF/10V,X5R
colay
2

1
2

C0402
2

R382
1

10K_J C335 PC6 change 100UF CT to 100uF MLCC 0126

R0402 ns0.1UF/10V,X5R Add for discharge
c0402
1

EMC add C594 1015

B B

D10
ESDA6V8UD
DFN10_0D5_2D5X1D0

SSTX0+ 1 10 SSTX0+ LD3

SOT23_6
USB_P0 AZC199-04S

6
SSTX0- 2 9 SSTX0-

SSRX0+ 4 7SSRX0+

1
USB_N0
SSRX0- 5 6SSRX0-

A A

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Date: Tuesday, June 09, 2015 Sheet 29 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+ECVCC 12,20,21,33,36,37
+5VALW_LDO 37
+V5A 29,34,37..44

USB_P2
11 USB_P2
USB_N2
11 USB_N2

R401 10K_J
1 2
R404
+ECVCC
49.9k_F R0402 USB_OC1_N R0402
D 2 1 ILMI_LO Del MOS D
20,30 CHG_SW R597 23.7K_F R0402 V 140115
1 2 ILMI_HI

USB_STAT_L
With EZ charge, stuff it
20 USB_STAT_L IC to EC

17

16

15

14

13
U29
From IC internal

ILIM_LO

GND_1

FAULT#
PAD

ILIM_HI
USB_CTL3 INPUT3 +V5A_BH +USBPWR_CHA
20 USB_CTL3
1 12 80 mils BA7 1 2 80ohm/100MHz
IN OUT FB0603
USB_N2 2 11 USB_C_N
DM_OUT DM_IN

1
USB_CTL2 INPUT2 C304 C300 C303 C305 CT2
20 USB_CTL2 USB_P2 3 10 USB_C_P 100uF/6.3V,X5R
10uF/6.3V,X5R 1UF/16V,X5R 0.1uF/16V,X5R 10uF/6.3V,X5R
C0603 C0402 DP_OUT DP_IN C0402 C0603 C1206

2
USB_SEL R0402 1 ns 0_J 2R614 USB_SEL_N 4 9 0_J 2 R0402 1R609 USB_STAT_L
USB_CTL1 ILIM_SEL STATUS#
20 USB_CTL1 INPUT1

CTL1

CTL2

CTL3
EN
CT2 change 100UF CT to 100uF MLCC 0126
USB_SEL ILIM_SEL
20 USB_SEL

2 0_J 6

2 0_J 7

2 0_J 8
+ECVCC
Add 1020
USBCHA_EN_EC R596 10K_J
20 USBCHA_EN_EC
2

1 2 USB_STAT_L
R410
+ECVCC

R0402

R0402

R0402
10K_J Add 1020 R0402
R0402

R603

R608

R610
1

1
1

USB_SEL_N

USBCHA_EN

USB_CTL1

USB_CTL2

USB_CTL3
+ECVCC
C C
1

R540
R1 10K_J
R0402 Q47 Q48
ns +5VALW_LDO WPM2301-3/TR +V5A_BH WPM2301-3/TR +V5A
* Enable R1 sot23-3_b sot23-3_b
2

R598 0_J
Disable R2 USBCHA_EN 1 2 USBCHA_EN_EC 2 3 2 3

D
R0402

1 G

1 G
1

1
C539

2
R553 1UF/16V,X5R

1
R2 10K_J R508 C0402 C540

2
1
R0402 100K_J C306 1UF/16V,X5R
ns R0402 0.1uF/16V,X5R C0402

2
+5VALW_LDO C0402
2

2
1
2
R599 1 2 10K_F R0402
R505
10K_F Q3659A USB_5AL_EN
R0402 L2N7002DW1T1G

3
SOT363 D

1
TPS2546 Control Mode (For Adapter) USB_5AL_EN 5 G
S
Q3659B
Input Logic Level Control Mode

4
6
L2N7002DW1T1G
SOT363 D
INPUT1 INPUT2 INPUT3 ILIM_SEL System Status Charging Mode Enable Charging Disable Charging
2 G
20,30 CHG_SW
S
0 1 1 0 S3/S4/S5 DCP(Dedicated Charging Port) S3 S4 S3 S4

1
1 1 1 0 SDP(Standard Downstream Port) USB_STAT(0011) H H/L H L

B B
H
1 1 1 1 S0 CDP(Charging Downstream Port) CHG_SW H H/L L

Note:DCP mode support iPhone 1A, Ipad 2.1A

CHG_EN H H H L

USB_C_P
4

+USBPWR_CHA
1011-02165

1 VBUS 8

USB_C_N USB_C_N 2 D- 7

3 D+ 6
wls0613
LD11 USB_C_P USB_C_P
3

SOT23_6

2
AZC199-04S C693 C694 4 GND 5

USB2.0 port
3.3PF/50V,NPO 3.3PF/50V,NPO
USB_C_N C0402 C0402
1

1
ns ns
USB2.0_CN1
UARD_4K1926
usb_uard2_4k1926

A A

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Date: Tuesday, June 09, 2015 Sheet 30 of 52

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Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V1.8S 10,14,20,23,28,44
+V3.3S 7,8,14,20,23,24,26..28,32,34,44
+V1.8A 7..12,14,16,20,23..25,27,39,44

D D

Bosh G sensor change to 250E no part number 1010wls

VDD_IO

R666
R0402 +V3.3S VDD_IO
Gsensor One
2 1 R575
0_J C502 U41 1 2
0.1uF/10V,X5R BMA250E 0_J
BOSCH

1
C0402 LGA12_0D5_2x2 R0402 C503
BOSCH BOSCH 0.1uF/10V,X5R
R187
3 7 C0402 10K_J
VDDIO VDD
BOSCH r0402
10
11 CSB
PS
BOSCH ns R662

2
6 R0402
Gsensor_SDA_0BOSCH R660 1 0_J 2 R0402 2 INT2 5 2 1 Gsensor_INT0
Gsensor_SCL_0 BOSCH R661 1 0_J 2 R0402 12 SDx INT1 0_J

GNDIO
SCx
BOSCH

GND
SDO
NC
1
4
8
9
Addr

C C
+V1.8A +V1.8S
delete 3.3S 0119wls
+V3.3S
ns
R670 ns2 0_J 1 R0402 4.7uF/6.3V,X5R nsR552
C489 10K_F 2 R554 ns 1 R0402 1 0_J 2
2 1 C0603 R0402
R0402 0_J R705
LSM303D/LIS3DE/LIS3DH/MMA8452Q/FXOS8700CQ/KXCJK-1013

16
15
14
U39 KXCJK-1013
VDD_IO R578 2 0_J 1 R0402

NC4
NC3
VDD
ns
VDD_IO_Kionix 1 13
2 1 C497ns C0402 2 VDDIO NC2 12
C493 C496 10K_F R546 nsR0402 0.1uF/10V,X5R 3 BYP GND3 11 2 R547 1 GSENSOR_INT
NC1 INT1 Gsensor_INT0 10
0.1uF/10V,X5R 0.1uF/10V,X5R 2 1 4 10 0_J
C0402 C0402 R0402 0_J R550 5 SCL GND2 9
GND1 INT2 R0402
ns ns

SDA
SA0
NC
LGA16_0D5_3X3

6
7
8
ns SLAVE ADDRESS:0x19h/0x1Dh

R551
10 Gsensor_SCL_0 VDD_IO_Kionix
1 2R0402
10 Gsensor_SDA_0
0_J
ns

Addr
VDD_IO

2 1
Note:
R0402 0_J R671 The first pin of G-sensor must be
R0402 2 R672 1 ns place on the lower left corner of PCB.
0_J
B B

3D G-Sensor
R671 PIn1 net use Addr 0122

A A

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Date: Tuesday, June 09, 2015 Sheet 31 of 52
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documents or disclosed to others or used for any purpose other than that for which it

sualaptop365.edu.vn
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3S 7,8,14,20,23,24,26..28,31,34,44

D D

+V3.3S +V3.3S_TPM

R675 0_J r0603

2
ns C402 C445
10UF/6.3V,X5R 0.1uF/16V,X5R
C0603 C0402

1
Close to Pin24. Close to Pin19.
ns ns
GND
GND

LPC_AD0
12,20,27 LPC_AD0 LPC_AD1
12,20,27 LPC_AD1 LPC_AD2
12,20,27 LPC_AD2 LPC_AD3
12,20,27 LPC_AD3

LPC_FRAME_N
12,20,27 LPC_FRAME_N
U20
R6051 0_J 2 SERIRQ_N tssop28_0d65_6d4x9d7
20 SERIRQ R0402 Z32H320TC
ns
1 28 ns 2 R676 1 0_J R0402
NC0 LPCPD# 27 +V3.3S_TPM
2 SERIRQ_N
3 NC1 SIRQ 26 LPC_AD0
4 NC2 LAD0 25 1 R673 2 0_J R0402
GND0 GND3 24
ns GND
5
NC3 VDD2 23 +V3.3S_TPM
6 LPC_AD1
7 NC4 LAD1 22 LPC_FRAME_N
vendor suggest Conn to GND 0826 TP56 1 TPM_P8 8 NC5 LFRAME# 21
ns1 R665 2 0_J R0402
NC6 LCLK 20 TPM_CLKOUT1 12
9 LPC_AD2
10 NC7 LAD2 19
+V3.3S_TPM VDD0 VDD1 18 +V3.3S_TPM
11
12 GND1 GND2 17 LPC_AD3
NC8 LAD3 16
2

13 TPM_RST_L 1 R667 2 R0402 0_J

NC9 LRESET# 15 1 PLT_RST# 7,20,26,27,34
R674 14 2 ns
C 0_J NC10 CLKRUN# R677 R0402 0_J C

1
R0402 ns C453 C454
ns add 0 ohm ckj0828 C0402 0.1uF/16V,X5R

2
C452 ns 10PF/50V,NPO C0402
1

2
0.1uF/16V,X5R ns ns
C0402

1
GND ns
Close to Pin10 GND GND GND

GND

B B

A A

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Date: Tuesday, June 09, 2015 Sheet 32 of 52
PROPERTY NOTE: this document contains information confidential and property to

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Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+ECVCC 12,20,21,30,36,37

+V3.3A 7,10,12,20,24,26..28,34,37..44

D D

+ECVCC

2
+V3.3A R509
4.7K_J
R0402 NOVO_SW2
SW 3P
Switch_tp-1117a-ba6325

1
2

3
R549 R548 R584
330_J 330_J 330_J
r0402 r0402 r0402 R31 1 2 1K_J 2 1
20 Novo_SW# r0402
1

1
Power LED Novo SW
VRA13

4
1

1
C807 AZ5725-01F
CHARGE_LED1 BATTERY_LED2 POWER_LED3 0.1UF/10V,X5R R0402 C302

LED on MB

2
BL-HJC36A-TRB AS-F196BP AS-F196BP c0402 0.1UF/10V,X5R

2
led_0603 led_0603 led_0603 ns C0402

Place Charge LED&Battery LED Together

2

2
20 CHARGE_LED# BATTERY_LED# 20 Power_LED# 20
SW DB CONN
1

1
VR18 VR19
AZ5125-01H AZ5125-01H VR21
SOD-523 SOD-523 AZ5125-01H
ns ns SOD-523
2

2
2

c0402 c0402 ns

2
0.1UF/10V,X5R 0.1UF/10V,X5R c0402
C C294 C297 LEDS Button Follow X212
0.1UF/10V,X5R C
1

C307 +ECVCC

1
C307 1000pF change to 0.1UF FOR EMI 0417

2
C294 C297 1000pF change to 0.1UF FOR EMI 0417 R493
4.7K_J
1000pf to 0.1uf For EMC 0115 R0402 POWER_SW1
SW 3P
Switch_tp-1117a-ba6325

3
R29 1 2 1K_J PWRSW_R 2 1
20 PWRSW# r0402 Power SW

1
VRA12

4
1
C806 AZ5725-01F
0.1UF/10V,X5R R0402 C301

2
c0402 0.1UF/10V,X5R

2
ns C0402

B B

A A

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Date: Tuesday, June 09, 2015 Sheet 33 of 52

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Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3S 7,8,14,20,23,24,26..28,31,32,44 +V5A 29,30,37..44

+V1.8A 7..12,14,16,20,23..25,27,31,39,44
+V3.3A 7,10,12,20,24,26..28,33,37..44

D D

Tocuh pad

BMBH PINTBD
+V3.3S
+V3.3S

1
C612
2

2
0.1UF/10V,X5R BM_IO_CN13
R5975 R5974 c0402 Pitch=0.5mm_30Pin

2
10K_J 10K_J 1 37 cns36_0d5_r_88511
2
R0402 R0402 28 SLEEVE
3
28 RING2
GND 4
28 HPOUT-L
1

6 8 5
28 HPOUT-R
TP_SMCLK 5 6
20 TP_SMCLK +V5A 28 HP-JD_CON
TP_SMDAT 4 7
20 TP_SMDAT

2
3 C144 C542 8
2 4.7UF/6.3V,X5R 0.1UF/10V,X5R 9
C 1 7 +V3.3S C0603 c0402 10 C

1
1

C3766 C3767 11
cns6_1d0_r_88513 12
47pF/50V,NPO 47pF/50V,NPO Pitch=1.0mm_6Pin USB_P1 13
11 USB_P1
2

C0402 C0402 TP_CN16 USB_N1 14

11 USB_N1

2
C209 C541 15
GND GND 4.7UF/6.3V,X5R 0.1UF/10V,X5R 16
C0603 c0402 17

1
GND ns ns 18
19
20
21
+V3.3A 11,29 USB_OC0_N
22
20 LID2_N_IO Rotation_SW# 23
20 Rotation_SW# 24
20 VOL-
25
20 VOL+

2
C210 C543 PCIE_CD_CLKREQ0_IO 26
4.7UF/6.3V,X5R 0.1UF/10V,X5R 27
7,20,26,27,32 PLT_RST#
C0603 c0402 28

1
ns ns 29
9 PCIE_CD_TXP0 30
9 PCIE_CD_TXN0 31
32
9 PCIE_CD_RXP0 33
9 PCIE_CD_RXN0 34
35
9 PCIE_CD_CLKP0
36 38
9 PCIE_CD_CLKN0

GND

B B

2 1 LID2_N_IO
10 LID2_N R364 R0402 0_J
ns

reserve LID2 to SOC

+V3.3S

R561
3.3k_J
r0402
2

ns
1

ns
3 2 PCIE_CD_CLKREQ0_IO
9 PCIE_CD_CLKREQ0
A Q3678 A
MMBT2222A-7-F
SOT23
reserve Add Level_Shifter 1022

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Date: Tuesday, June 09, 2015 Sheet 34 of 52

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documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

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A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 35 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

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documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VDC 24,37,38,40,42..44 +ECVCC 12,20,21,30,33,37

C165 C166 C167 C168 C169 change to stuff

FOR EMI 0417

VAD2

1
C165
C0805

C166
C0805

C167
C0805

C168
C0805

C169
C0805
10uF/25V,X5R

10uF/25V,X5R

10uF/25V,X5R

10uF/25V,X5R

10uF/25V,X5R
2

2
D D

+VDC
Colay
System Output
System
Capacitor
Add PC12 PC13 FOR EMI 0118HWL
delete colay Tcap PC12 PC13 0420

1
C0805 C0805 C0805
10uF/25V,X5R 10uF/25V,X5R 10uF/25V,X5R
PC8 PC10 PC11

2
ns
VPF7 1 32V/5A 2 fuse_0603
place near ACIN JACK
10-15
Charger change the direction by yn 0818
Q13
change by gzl 0819
BATT+

AD+ Q20 EMB20N03V L1

PFB7 2 1 100ohm/100MHz,3A fb0603 EMB20N03V dfn8_0d65_3x3 10uH_5.0A 1
1
dfn8_0d65_3x3 1 l_2p_6d6x7d3 2
7 5 AD_IN+ VPF5 1 32V/5A 2 fuse_0603 PFB8 2 1 100ohm/100MHz,3A fb0603 1 2 2 VAD2 2 LX 1 2 1 2 3

10uF/25V,X5R
4 3 3 5
6A S

2
3 R179 S 5 5 S Q31 PR8 D dfn8_0d65_3x3

C0805
1

1
C128
2 PC270 C317 R659 20m_F D D EMB20N03V R91 C0805 0.01_F G EMB20N03V
1

2
6 1 PC275 PC16 PC277 1000PF/50V,X7R 0.1uF/25V,X7R 22K_J R1206 G C151 G dfn8_0d65_3x3 2.2_F 10uF/25V,X5R R1206 Q32

4
2200PF/50V,X7R 1000PF/50V,X7R 4.7uF/25V,X5R c0402 C0603 2 1 10uF/25V,X5R R0603 C130
r0402

2
1
cns5_1d25_r_85204 c0402 c0402 c0805 C127 C0805 4
2

1
Pitch=1.0mm_5P R184 1000pF/50V,X7R

21
2

2
ACIN1 115K_F C0402 C125

S
R0402 R98 R94 2200PF/50V,X7R

1
2
3

2
1M_J 0_J C0402

1
R0402 R0402 R105
ADP_ID 20

2 2
0_J
R0402

1
1

PC3 C129 R180

0.1UF/10V,X5R 0.1UF/10V,X5R 20K_F

1
c0402 c0402 R0402 U14 R99
2

ns C17 30K_J
0.47uF/25V,X7R R0402
C131

1
C0603 LDR 16 10 PMON 1 2
C 1UF/25V,X5R LDR PMON C
C0603 1 2 LX 13 22
LX ICHP

2
D11 change by yn 0818 R383,R386 0ohm change to 100ohm
LBAT54CLT1G HDR 14 23 ICHM FOR SI 0415
HDR ICHM

1
SOT23-3 R92 C13 C14
BATT+ 1 10_J BST 15 12 PB 2.2PF/50V,NPO 2.2PF/50V,NPO
R0603 BST PB
c0402 c0402

2
3 1 2 VAC 24 5
VAC VBATT
2 2 1 VDDP 17 7 r0402 2 100_J 1 R383
D6
LMDL914T1G VDDP OZ8782 SDA DAT_SMB 20,36
sod323 PA 9 6 r0402 2 100_J 1 R386
PA SCL CLK_SMB 20,36
IACM 3 19
IACM ACPRES ACIN_EC 20
4 1
D14 IACP IBATT IBATT 20
1 2 ADOV/STDBY 20 8 COMP
20 OZ8782_STDBY ADOV/STDBY COMP TP57
IBSET 21 2 PROCHOT# 1
R776 LMDL914T1G IBSET PROCHOT TP52

2
sod323 FBV 18 11 PSYS 1

BASE
FBV PSYS

1
R96

2
75K_J OZ8782 C20 R0603
100K_J R0402 R93 C18 47pF/50V,NPO 549.0_F

25

1
1

1
r0402 C21 C140 1 R109 2 100_F 1000pF/50V,X7R C0402

1
0.1UF/10V,X5R 10UF/6.3V,X5R 0_J R102
R0402 C0402

1
C0402 C0603 R0603

2
1

2
ns 1 R110 2

2 1
2
GND_OZ8782 C16 0_J R107
R97 0.1UF/10V,X5R R0603 C22 GND_OZ8782 100K_J

2
39K_F C0402 GND_OZ8782 0.47uF/25V,X7R R0402 GND_OZ8782 +ECVCC
R0402 C0603

1
1 2 R919 r0603 0_J BATT+ change by yn 0818

2
R100 GND_OZ8782

2
C19 200K_J GND_OZ8782
2.2uF/6.3V,X5R R95 R0402
BATT+ C0402 270K_F change by yn 0829

1
chang the order ckj0826 R0402

1
Rev1.3
B B

VMB nsVPF6 1 32V/5A 2 fuse_0603 PFB3 2 1 100ohm/100MHz,3A fb0603 GND_OZ8782 GND_OZ8782

PCB Layout notes VPF4 1 32V/5A 2 fuse_0603 PFB4 2 1 100ohm/100MHz,3A fb0603

6A
1

PC27 PC149 PC148

2200PF/50V,X7R 0.1uF/25V,X7R 0.1uF/25V,X7R
c0402 C0603 C0603
2

9
10 GND1 1
GND2 1 2
2 3 R395 1 100_J 2 r0402
3 4 CLK_SMB 20,36
R396 1 100_J 2 r0402
4 5 DAT_SMB 20,36
PC33 PC34
5 6 5.6PF/50V 5.6PF/50V
6
1

7 c0402 c0402
11 7 8
GND3 8
ns
12 ns
GND4
2

1011-02176
cns8_1d25_r_125022HB
125022HB008M200ZL +ECVCC
BATCON1
1

PR15
Part Reference = PR16 100K_J
1K_J r0402
r0402
2

1 2
BATT_PRS# 20
1

PC17
1000PF/50V,X7R
c0402
2

A A

Bitland Information Technology Co.,Ltd.

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Date: Tuesday, June 09, 2015 Sheet 36 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VDC 24,36,38,40,42..44 +ECVCC 12,20,21,30,33,36

+V3.3A 7,10,12,20,24,26..28,33,34,38..44
+V5A 29,30,34,38..44 +5VALW_LDO 30
+V3.3A_PRIME 14,23

+VDC

CAD NOTE:PC62 place close to pin16

VREF

1
PC150

1
0.1uF/25V,X7R PC96
C0603 1uF/6.3V,X5R

2
c0402

2
+3VALW_LDO +5VALW_LDO

16

3
D D
+VDC
PU3 AGND_51125
PC59 C133 Clolay

VIN

VREF

1
+VDC
C407 C457
SKIPSEL 14 4.7uF/6.3V,X5R 4.7uF/6.3V,X5R
SKIPSEL

2
8 c0603 c0603
VREG3

1
C411 C137 PC153 PC98 PC99

1
1000PF/50V,X7R 10uF/25V,X5R 4.7uF/25V,X5R 4.7uF/25V,X5R 0.1uF/25V,X7R TONSEL 4 PC151 PC67 PC60 C135 C455
c0402 C0805 c0805 c0805 C0603 TONSEL 17 0.1uF/25V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R 1000PF/50V,X7R
VREG5

2
ns C0603 c0805 c0805 C0805 c0402

2
PR34 ns
0_J
+5VBST1 r0603 +5V_BST 22 9 +3V_BST PR35 0_J +3VBST1
VBST1 VBST2

5
PC150 C134 Clolay Q26 r0603
EMB20N03V Q39

D
D
dfn8_0d65_3x3 EMB20N03V
4 +5V_DH 21 10 +3V_DH 4 dfn8_0d65_3x3
+V5A DRVH1 DRVH2

G
6A

2
C458 C459 +V3.3A

S
S
PL4 0.1uF/25V,X7R 0.1uF/25V,X7R PL5
OCP=11A

1
2
3

3
2
1
C0603 C0603

1
1 2 +5V_LX 20 11 +3V_LX 1 2
LL1 LLS

1
4.7uH/5.5A 4.7uH/5.5A

1
l_2p_6d6x7d3 Q38 l_2p_6d6x7d3
PR36 EMB20N03V Q25

D
D
1

1
C412 PC86 1_J dfn8_0d65_3x3 EMB20N03V PR37

1
1000PF/50V,X7R 0.1UF/10V,X5R r0805 4 1 2+5V_DL 19 12 +3V_DL 1 2 4 dfn8_0d65_3x3 1_J + PC152 PC79 C456
DRVL1 DRVL2

1 2
1

1
G
c0402 c0402 + PC154 PC97 PC88 PR38 0_J r0603 PR39 0_J r0603 r0805 PR47 PC94 220uF/6.3V 0.1UF/10V,X5R 1000PF/50V,X7R

G
R0402
2

1 2
220uF/6.3V 1000PF/50V,X7R 13K_F 1000PF/50V,X7R tc7343 c0402 c0402

S
S
20K_F

2
2 tc7343 c0402 1500PF/50V,X7R PC90 r0402 c0402

1
2
3

3
2
1

2
PR51 ns C0402 1500PF/50V,X7R ns

2
C0402

2
24 7
270UF TC3528 change to 220UF TC7343 1229wls 270UF TC3528 change to 220UF TC7343 1229wls
+5VALW_PWM
VO1 VO2

+5V_FB 2 5 +3V_FB
delete 150UF(3528) only use 270uF
VFB1 VFB2

1
1
PR42
R0402 20K_F
13K_F PR151 30K change to 20K 6 +3V_EN
r0402

R555 20K change to 13K 0127qyn ENTRIP2

2
R555
20MIL TP106 1 18
VCLK
2

AGND_51125

1
PR89
AGND_51125 169K_F
r0402

2
+5V_EN +V3.3A
+5V_EN 1 AGND_51125
ENTRIP1
3

C D Q3667A 23 PR86 1 2 10K_J r0402 C

L2N7002DW1T1G PGOOD
5 G sot363

1
S PR87 1 2 0_J r0402
PR88 3.3A_5A_PWRGD 20,38
4

169K_F
+3VALW_LDO r0402
13
EN0

2
2

1
+3V_EN
PR84 R538

GND1
GND
6

100k_J 620K_J +3VALW_LDO +ECVCC

r0402 D Q3667B AGND_51125 r0402
L2N7002DW1T1G RT8205MGQW ns PR81 1 0_J 2 r0402
1

15

25

2
2 G sot363 qfn24_0d5_4x4
S
3

1
AGND_51125 PC62 PC91 PC112
1
1

D PQ18 PC61 0.1UF/10V,X5R 1uF/6.3V,X5R 0.1UF/10V,X5R

L2N7002LT1G 22PF/50V,NPO PR82 1 0_J 2 r0603 c0402 c0402 c0402

2
+3V_+5V_EN_R 1 SOT23-3 C0402 ns
2

G S ns
2

AGND_51125

SKIPSEL
TONSEL

Auto skip mode

OA Auto skip mode PR83 1 2 1K_J r0402

+5VALW_LDO PR75 1 0_J 2 r0402 2 1 VREF +3VALW_LDO 2 1 2 1 VREF +3V_+5V_EN_R D22 2 1 LMDL914T1G ns
ALW_ON 20
PR74 0_J ns PR80 0_J ns PR78 0_J SOD323

2
5V --365K 5V --245K r0402 r0402
3.3V---460K r0402 3.3V---305K PR79

1
0_J PC87
1

PR77 r0402 0.1UF/10V,X5R

0_J ns c0402 D27 1 2 LMDL914T1G
HW_OT# 21

2
r0402 PWM mode SOD323
ns
ns
AGND_51125
thermal sensor circuit change to ns 0608V1.3wls
2 +3VALW_LDO

5V --300K
3.3V---375K

B B

+VDC
1

C380 C379 C378 +VDC

0.1uF/25V,X7R 0.1uF/25V,X7R 0.1uF/25V,X7R
C0603 C0603 C0603
2

+V3.3A

+V3.3A Q34 +V3.3A_PRIME

300mA

2
QM3010K
PR305
1

C373 C374 sot23-3

10K_F
1

0.1uF/25V,X7R 0.1uF/25V,X7R R350 C350 3 2 +V3.3A

S
D

C0603 C0603 0.01UF/25V,X7R R0402

100K_J
2

C0402
G

R0402
2

1
1
2

ALW_PWRGD 20
1

PR308

3
1 B E Q30 51K_J

1
D PQ24 PC269
for emc 0303 C LDTB114ELT1G r0402
L2N7002LT1G 0.1UF/10V,X5R
2

SOT23-3
1 SOT23-3 c0402

3 1
R397

2
G
3

1K_J S
1

D
3+V3.3A_PRIME_ON_N

R352 1 2 33K_J R0402 C372 C371 Q37

2
R0402
10UF/6.3V,X5R 0.1UF/10V,X5R L2N7002LT1G
2

C0603 C0402 +V3.3A_PRIME PR306 1 2 1K_J r0402 1 SOT23-3

1

R387 G S
1

30K_F C363

2
Delete the discharge diode 1015wls 0.1uF/25V,X7R
R0402
C0603
2
1

D Q43
L2N7002LT1G
39 +V1.8A_PWRGD +V3.3A_PRIME_EN 1 sot23-3
G S
2

R426
100K_J
R0402
1

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documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V1.05A 12..14 +V3.3A 7,10,12,20,24,26..28,33,34,37,39..44

+VDC 24,36,37,40,42..44 +V5A 29,30,34,37,39..44
D D

+VDC

1
R185 C162 PC76 PC77 C139
340K_F 0.1uF/25V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R

21

22

23

24

34
R0402 C0603 c0805 c0805 C0805

2
+V5A ns

VIN1

VIN2

VIN3

VIN4

VIN5
7
TON R127

1
+V3.3A PC77 C136 Clolay
27 2 1
30mil
9 BOOT
VCC

1
100K changer to 10k 0916wls 26 C175
NC 2.2_F

1
PC113 0.1uF/25V,X7R
2

1
1UF/6.3V,X5R 25 R0603 C0603
PHASE5

2
1
R186 C123 PR64 C0402 35 +V1.05A
PHASE6

2
10K_J 0.01UF/25V,X7R 10K_F 32 PL11
C0402 GND 20 1 2
r0402 R0402 PHASE4
2

PR55 0.68uh
1

2
19 1_J l_2p_6d6x7d3
PHASE3

1
r0805 PC143 PC109 PC103 PC102 PC93 PC92 PC115

1
10 18 ns 0.1UF/10V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 0.1UF/10V,X5R
CS PHASE2 c0402 C0805 C0805 C0805 C0805 C0805 c0402

2
17 ns
PHASE1

11

2
8 U5 PC108
20 +V1.05A_PWRGD POK uP1741P 4700pF/50V,X7R
C0402

2
C ns C

2 R178 1 2 0_J R0603

100K_J2 R103 1R0402 +V1P0A_EN_N 6 VDDQ
20,37 3.3A_5A_PWRGD EN
ns
1

2
PC107 3
0.1UF/10V,X5R FB R132
2 R104 1 0_J R0402 c0402 178K_F
20 +V1.05A_EN
2

5 28
GND6 GND5 R0402 C126
1 2

1
29 470PF/50V,X7R
GND4 C0402
1
INTREF 31 R5950 1 2 4.02K_F R0402
GND3
1

PC117

1
0.1UF/10V,X5R 33
PGND1

PGND2

PGND3

PGND4

PGND5

PGND6
c0402 GND7 30 PR61
GND2
2

1
4 10K_F PC116
GND1 0.1UF/10V,X5R
R0402
c0402
11

12

13

14

15

16

2
ns

2
B B

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Date: Tuesday, June 09, 2015 Sheet 38 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3A 7,10,12,20,24,26..28,33,34,37,38,40..44 +V5A 29,30,34,37,38,40..44

+V1.24A 14 +V1.8A 7..12,14,16,20,23..25,27,31,44

D D

rsvd C295 C302 EMC request

+V3.3A
+V5A

2
R611 10_J r0402 1003-01048
PR70

1
C466 10K_J C349 C366
1uF/6.3V,X5R r0402 0.1UF/10V,X5R 0.1UF/10V,X5R
c0402 c0402 c0402

2
ns ns

1
4

8
PU15
PR108 2 R0402 10_J +V1.24A_EN_N 2 1 +V1.24A_PWRGD
20 +V1.24A_EN_EC

CTNL

GND
EN PG

1
5 +V1.24A
PR111 NC
700mA

2
100K_J C468 6 +V1.24A
VOUT
R0402 0.1UF/10V,X5R
Clolay c0402

1
7 PC242 PC272 PC262 PC271
FB

2
R6051 0.1UF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1UF/10V,X5R

1
R613 0_J r0603 3 9 11K_F c0402 C0603 C0603 c0402 C347 C348
+V3.3A VIN TGND

2
R0402 ns ns 0.1UF/10V,X5R 0.1UF/10V,X5R
FB4 120ohm/100MHZ c0402 c0402

2
2

1
l0603 ns uP0104SSW8

1
C467 PC231
4.7uF/6.3V,X5R 0.1UF/10V,X5R 0.8v

2
EMC add FB2 0628 c0603 c0402
EMC add C293 C292 0627
R6049
20K_F
R0402

1
C C

rsvd C295 C302 EMC request

+V5A +V3.3A

R581 10_J r0402 1003-01048

2
1

1
C460 PR66 C310 C311
1uF/6.3V,X5R 10K_J 0.1UF/10V,X5R 0.1UF/10V,X5R
c0402 r0402 c0402 c0402

2
ns ns

8
PU11

1
+V1.24A_PWRGD PR106 2 R0402 10_J +V1.8A_EN_N 2 1 R324 2 1 R0402 0_J

CTNL

GND
EN PG +V1.8A_PWRGD 37
1

5 +V1.8A
PR107 NC
700mA
2

100K_J C462 6 +V1.8A

VOUT
R0402 0.1UF/10V,X5R
Clolay c0402
1

1
7 PC213 PC268 PC261 PC267
FB
2

R6020 0.1UF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1UF/10V,X5R

1
R583 0_J r0603 3 9 20K_F c0402 C0603 C0603 c0402 C308 C309
+V3.3A VIN TGND

2
R0402 ns ns 0.1UF/10V,X5R 0.1UF/10V,X5R
2

B FB2 120ohm/100MHZ c0402 c0402 B

2
l0603 ns C461 PC212 uP0104SSW8

1
4.7uF/6.3V,X5R 0.1UF/10V,X5R
0.8v
1

c0603 c0402

2
EMC add FB2 0628
R6019 EMC add C293 C292 0627
16K_F
R0402

A A

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Date: Tuesday, June 09, 2015 Sheet 39 of 52
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

sualaptop365.edu.vn
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VDC 24,36..38,42..44 +V3.3A 7,10,12,20,24,26..28,33,34,37..39,41..44

+VDIMM 7,14,18,19,41 +V5A 29,30,34,37..39,41..44
+VTT_DDR 18,19 +V3.3S 7,8,14,20,23,24,26..28,31,32,34,44

+VDC
D D

1
R59 C124 PC78 PC80 C142
340K_F 0.1uF/25V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R

21

22

23

24

34
R0402 C0603 c0805 c0805 C0805

2
ns

VIN1

VIN2

VIN3

VIN4

VIN5
+V3.3A +V5A 7
TON

1
30mil2 PC99 C137 Clolay
27
R69 1 0_J R0603
9 BOOT
VCC

1
26 C141 +VDIMM
NC

1
PC118 0.1uF/25V,X7R

2
1UF/6.3V,X5R 25 C0603
PHASE5

2
1

1
C143 R68 C0402 35
PHASE6

2
R131 0.01UF/25V,X7R 8.2k_F 32 PL13
C0402 GND 20 1 2
100K_J R0402 PHASE4

2
R0402 0.68uh
19 PR63 l_2p_6d6x7d3
PHASE3

1
1_J PC128 PC155

1
10 18 r0805 PC156 22UF/6.3V,X5R PC126 PC125 PC124 PC121 0.1UF/10V,X5R
CS PHASE2
ns 0.1UF/10V,X5R C0805 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R c0402

2
17 c0402 C0805 C0805 C0805 C0805
PHASE1

2
8 U2 ns
7,20,44 VDDQ_PWRGD POK

1
PC122 uP1740P/Q PC110
0.1UF/10V,X5R 4700pF/50V,X7R
c0402 EMI need 1023 C0402

2
ns
2 R58 1 2 0_J R0603
PR45 2 1 1K_J R0402 uP1740_S5 6 VDDQ
20 SUS_ON S5

2
uP1740_S3 5 3
S3 FB

2
R57
R314 40mil 178K_F

1
100k_J 28 +VDIMM
VTTIN R0402
R0402 R120
C132

1
100K_J PC129
1

1
29 1UF/6.3V,X5R 1 2
R0402 VTT C0402 1000pF/50V,X7R

2
1 C0402
VTTREF

2
C 31 R106 8.2k_F R0402 C
VTTSNS

1
PC119 2 1
0.1UF/10V,X5R 33

PGND1

PGND2

PGND3

PGND4

PGND5

PGND6
VTTGND3

1
c0402 30 PC127
VTTGND2

2
4 PR69 0.1UF/10V,X5R
VTTGND1 c0402
10K_F

2
R0402 ns

11

12

13

14

15

16

2
+VTT_DDR

1
PC120 PC131 PC130
0.1UF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
c0402 C0603 C0603

2
ns

FOR EMI 0127

+VTT_DDR

1
C12 C146 C182 C183 C184
1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R
C0402 C0402 C0402 C0402 C0402

2
PR72 2 0_J 1 R0402 uP1740_S3
41,44 3.3S_1.8S_PWRGD

1
1
B PC114 PR65 B
1uF/6.3V,X5R 1M_J
2 c0402 R0402
ns ns

1
C185 C186 C187 C188 C189
1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R 1000pF/50V,X7R
C0402 C0402 C0402 C0402 C0402

2
+0_75VRUN should ramp down earlier than CPU VDDQ
rail in S3-entry and ramp up after CPU VDDQ rail in S3-exit

A A

Bitland Information Technology Co.,Ltd.

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Date: Tuesday, June 09, 2015 Sheet 40 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3A 7,10,12,20,24,26..28,33,34,37..40,42..44 +V1.15S 13

+V5A 29,30,34,37..40,42..44 +VDIMM 7,14,18,19,40
D D

rsvd C295 C302 EMC request unstuff change to stuff 1028

+V5A +V3.3A

R595 10_J r0402 1003-01048

2
1

1
C463 PR67 C318 C345
add 1.15S_EN for debug wls0119 1uF/6.3V,X5R 10K_J 0.1UF/10V,X5R 0.1UF/10V,X5R
ns c0402 r0402 c0402 c0402

2
R112 2 1 0_J R0402
20 1.15S_EN

8
C PU12 C

1
PR109 2 1 0_J R0402 2 1

CTNL

GND
40,44 3.3S_1.8S_PWRGD EN PG 5 +V1.15S_PWRGD 20,42,44 +V1.15S
NC

1
700mA

2
PR110 C465 6 +V1.15S
100K_J VOUT
0.1UF/10V,X5R
R0402 c0402

1
7 PC281 PC279 PC280
FB

1
R6034 PC278 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1UF/10V,X5R

1
R602 0_J r0603 3 9 10.5K_F 0.1UF/10V,X5R C0603 C0603 c0402 C312 C316
+VDIMM VIN TGND

2
R0402 c0402 ns 0.1UF/10V,X5R 0.1UF/10V,X5R

2
2

1
FB3 120ohm/100MHZ ns c0402 c0402

2
l0603 ns C464 PC276 uP0104SSW8

1
4.7uF/6.3V,X5R 0.1UF/10V,X5R
0.8v

2
c0603 c0402

2
EMC add FB2 0628
R6035 EMC add C293 C292 0627
24K_F
R0402

1
B B

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
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Date: Tuesday, June 09, 2015 Sheet 41 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VGG 13 +V1.05A 12..14,38

+VDC 24,36..38,40,43,44 +V3.3A 7,10,12,20,24,26..28,33,34,37..41,43,44
+V5A 29,30,34,37..41,43,44

D D

+VGG_VCC
+VGG

2
+VDC
PR128
When Vin=12V,Please correct PR150=84.5kPR208=PR265=PR322=73.2K
0_J
R0402 Vin=6-20V
PU13

1
RT8171A

1
2 1 qfn32_4x4_ep +V5A C443
+VREF2

1
PR129 0_J R0402 +V5A +VGG_VCC PC180 PC181 PC182 1000PF/50V,X7R
ns 0.1uF/25V,X7R 10uF/25V,X5R 10uF/25V,X5R C0402

2
C0603 c0805 c0805

2
PR134 1 R0603 2 6 21 VGG_PVCC1 1 2
0_J 2.2_J VCC PVCC PR130 2.2_JR0603
PC183 PC184

5
+VGG_SET2 1 2 SET3_R 1 2VGG_SET3_LL PR132
2.2uF/6.3V,X5R 2.2uF/6.3V,X5R
PR133 1K_F R0402 R0402 V=1508mV, D PQ5
C0603 C0603 EMB12N03V
V=24mV

2
PR135
0_J 25 VGG_UG 1 PR136 2VGG_UG_G 4 G dfn8_0d65_3x3
1 R0402 2 SET3_L 2 1 VGG_SET3_LL 9 UGATE1 S
SETGND2 SET3
0_J IMON Compesation
PR131 432_F R0402 VGG_SET2_ICCMAX 8 R0603 BRASWELL 6W
SET2

1
2
3
1
VGG_SET1_DVID 7 R0402 0.5~1.3V
2.55K VGG_VBOOTSET 29 SET1 22 VGG_BT1 2VGG_BT_RC PR140 +VGG_NTC2P1 NTC_47K2 +VGG_NTC2N Imax:11A
1 2SET2_R 1 PR138 2VGG_SET2_ICCMAX VGG_TSEN 11 Vbootsel BOOT1 OCP :1.5*Imax
TSEN
PR139 2.2_JR0603 10K_J RT =4050 RT1

1
PR137 16.2K R0402 R0402 V=434.9mV, SETGND2
PC185 R0402 +VGG
Follow Kandy mail PR143 0.1uF/25V,X7R
VC 140410 V=86.022mV 0_J C0603 ns PL9

2
R0402 R0402 1 2SET_GND2 30 0.33uH_3.9mohm_20A
C 1 1K 2SET2_L 1 150 2 R0402 SETGND 23 VGG_PH 2 1 C
SETGND2 PHASE1

2
PR141 PR142 l_2p_6d6x7d3

5
PR144 PQ6 PR145

1
PR147 0_J EMB06N03V D 1.0_F PC208
634_F +VDC dfn8_0d65_3x3 22uF/6.3V,X5R
R0402 R0603
1 2SET1_R
1 2 VGG_SET1_DVID ns C0603

2
20 1 PR148 2 VGG_LG_G 4
PR146 82.5K_F R0402 R0402 V=1137mV, PR149 PR150 R tonset=264K_F
LGATE1
VGG_LG G PL9 f wls0610

1 1
1.0_J 806K When VIN=12V 0_J S VGG_PH_RC
PR152 V=1512mV 2 1TON_SET2 1 2TONSET216 R0603 PC186
TONSET

1
2
3
24.3K_F R0603 R0402
GND

+VGG_ISP1

+VGG_ISN1
3300PF/50V,X7R

1
1 2SET1_L
1 2 +V5A PR153 PC187
SETGND2 C0402

2
PR151 169.0_F R0402 R0402 1.0_J 1UF/25V,X5R IBIAS2 10 28 VGG_ISEN1P Difference pair
2 1 C0603 PR155 IBIAS ISEN1P

2
PR154 nsR0603 100K_F PR156
10K_F 1 2 27 VGG_ISEN1N 2 383.0_F 1
1 2VGG_VBOOTSET ISEN1N

RT8171A
R0402 R0402

2
R0402 En:0.7V 680_F C0603

1
VGG_EN 26 4 VGG_VSEN 1 2VGG_SENSE 1 r0402 2 PR160
VRON VSEN 0.47uF/25V,X7R
PR161 PR158 0_J R0402 PR159 383.0_F Close controller IC side

1
10K_F VRON assert after VCC and Vin ready PC189 DRVEN2 18 PC188
DRVEN1 R0402

2
1 2 0.1uF/16V,X5R
SETGND2 +VGG
R0402 C0402 24
DRVEN2

1
2 1 2COMP2_R 1 2
PR165 COMP PR162 0_J R0402 PC190 PR163 68K_F R0402

2
5.6K VGG_PWRGD 17 56pF/50V,NPO
VR_READY

1
1 2VGG_TSEN_R 1 2 VGG_TSEN PR168 VGG_COMP 1 2 1 2 PC191 PR167

1
PR164 100K_F R0402 R0402 200.0_F PR166 10K_F R0402 0.1uF/16V,X5R PC192 100_F
VGG_VCLK 1 2 VCLK2 15 3 VGG_FB C0402 C0402 0.1uF/16V,X5R
VCLK FB R0402

2
1 2
RT =4250 R0402 C0402

2
RT2 NTC_100K R0402 PR169 ns

1
5 VGG_RGND 1 2 VGG_SENSE
CLOSE Hottest MOS 1
0_J
2 13 RGND
VGG_VDIO VDIO2
VDIO 1
PC193
2
680pF/50V,NPO C0603
VSS2_SENSE
Difference pair
R0402
1 2 PR172 PR171 0_J R0402
SETGND2

2
PR170 6.49k_F R0402 0_J

1
VGG_ALERT_L 1 2 ALERT2_L 14 1 PC194 PR174
ALERT# VREF +VREF2
R0402 0.1uF/16V,X5R 100_F

1
1 2 PR175 PC195 C0402
+V3.3A R0402

2
PR173 10K_F R0402 75.0_F 0.47uF/16V,X7R ns
VGG_VR_HOT_N 1 2 VR_HOT2_L 12 31 IMON21 2 C0603
VR_HOT# IMON

1
1

PC196 R0402 OD,Active low PR176 4.12K R0402

IMON2_R0
Thermal_PAD
B 0.1uF/16V,X5R B
C0402
2

ns 32 19
NC PGND 1 2IMON2_R1 1 2
PR177 3.01K R0402 PR178 5.6K R0402

1
Vout 0.5-1.3V

33
PR179
6.49K Vin 12V/20V
R0402
+VGG_NTC2P
Switch Freq 800KHz
colay 0605V1.3 for power Follow Kandy mail

2
IMON2_R2 VC 140410 +VGG_NTC2N
+VGG ocp 1.38*Imax

1
Pls check 1pcs 820uF 7mohm Polymer whether can pass spec VR12.1 MLCC_Iripple 10uF/1A,47uF/2.8A
PR183
VGG_VCLK
12 VGG_VCLK 3.6K Choke size 0.33uH/10x10mm
1

Length (0.5'~1) R0402

1

1
VGG_VDIO T + PEC5 T + PEC6 T + PEC7 T + PEC8 T + PEC9
12 VGG_VDIO
270uF/2V
PC7
22uF/6.3V,X5R 270uF/2V
PC9
22uF/6.3V,X5R 270uF/2V
PC12
22uF/6.3V,X5R 270uF/2V
PC13
22uF/6.3V,X5R 270uF/2V
PC14 PC197
22uF/6.3V,X5R22uF/6.3V,X5R
PC198
22uF/6.3V,X5R
PC199
22uF/6.3V,X5R
PC200
22uF/6.3V,X5R Choke Idc/Isat 20A/30A

2
VGG_ALERT_L
12 VGG_ALERT_L
TC3528_1 C0603 TC3528_1 C0603 TC3528_1 C0603 TC3528_1 C0603 TC3528_1 C0603 C0603 C0603 C0603 C0603
Choke DCR Mean:3.73m
2

2
ns ns ns ns ns 1 2
+VREF2
VGG_VR_HOT_N
12 VGG_VR_HOT_L
PR184 499 R0402
Cin CAP 47uF+2*10uF
Add PEC8PEC9 1020 Cout CAP 330uF+10*22uF
VGG_SENSE
12 VGG_SENP Cout CAP_ESR 9m
VSS2_SENSE
12 VGG_SENN LIR 0.2-0.3

VGG_PWRGD
43 VGG_PWRGD
Add 1 22uf follow Vendor
+VGG VC 140303

PR157
0_J
1

1
1 2 VGG_EN PC201 PC202 PC203 PC204 PC205 PC206 PC207 PC209 PC210 PC211
20,41,44 +V1.15S_PWRGD
R0402 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
ns C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
2

2
A A

PR240 1 2 1K_J r0402

20 +VGG_EN_EC
+VGG
22UF 0805 change to 22UF 0603 1020
Bitland Information Technology Co.,Ltd.
1

PC243 PC245 PC244

22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R Page Name Cover Page
C0603 C0603 C0603
2

Size Project Name Rev

A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 42 of 52

sualaptop365.edu.vn Add PC243 PC245 PC244 1020 PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+VCORE0 13 +V1.05A 12..14,38

+VDC 24,36..38,40,42,44 +V3.3A 7,10,12,20,24,26..28,33,34,37..42,44
+V5A 29,30,34,37..42,44

+VCORE0
+VCORE0_VCC0
D D

2
PR185
0_J +VDC
R0402
1 PR186
0_J
2 1
R0402
+VREF0
PU14 Vin=12-20V
ns +VCORE0_VCC0 RT8171A

1
+V5A qfn32_4x4_ep +V5A C409 PC214 PC215 PC216
PR192 PR188 1000PF/50V,X7R 0.1uF/25V,X7R 10uF/25V,X5R 10uF/25V,X5R
39.2K_F 432_F C0402 C0603 c0805 c0805

2
1 2 1
V0_SET3L 2VCORE0_SET3_LL R0603
+VCORE0_SET R0402 R0402 1 2 6 21 VCORE0_PVCC1 1 2
VCC PVCC
V=1299mV, PR191 2.2_JR0603
PC218
2.2_J

5
PR189 PR193 PC217 PR187
V=824mV

1
221.0_F 13.7K_F 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R D PQ8
2 1 2
V0_SET3R 1 C0603 EMB12N03V
SETGND0 C0603

2
R0402 R0402

2
PR195 PR190 25 VCORE0_UG 1 PR182 2VCORE0_UG_G 4 G dfn8_0d65_3x3
24.3K 4.99K VCORE0_SET3_LL 9 UGATE1 R0603 0_J S
1 2V0_SET2L
1 2VCORE0_SET2_ICCMAX VCORE0_SET2_ICCMAX 8 SET3 IMON Compesation
SET2 BRASWELL 6W

1
2
3
1
7 R0402
R0402 R0402 V=109mV, VCORE0_SET1_DVID
VCORE0_VBOOTSET 29 SET1 22 1
VCORE0_BT 2VCORE0_BT_RC VCORE0_NTC1P
0.5~1.3V
1 NTC_47K2VCORE0_NTC1NImax:7A
R0603 PR197
PR199 V=86.07mV VCORE0_TSEN 11 Vbootsel BOOT1 2.2_J RT3 OCP :1.5*Imax
10K_J
PR198 TSEN RT =4050

1
1.1K_F PR196 PC219 R0402
2 0_J 1V0_SET2R 1 2 SETGND0 0.1uF/25V,X7R L15
SETGND0 PR200 +VCORE0
R0402 R0402 0_J C0603 ns 1uH/11A

2
1 2SET_GND0 30 SETGND
l_2p_6d6x7d3 colay 0605V1.3 for power
PR203 PR204 23 1 2
R0402 PHASE1

1
82.5K_F 634_F

2
1 2V0_SET1L
1 2VCORE0_SET1_DVID PR201
D PQ7

1
+VDC
R0402 R0402 V=1137mV, 0_J EMB06N03V
PR202

1
T + PEC12 PC4 + T PEC10 PC2
PR208 PR209 V=1512mV R0402
ns dfn8_0d65_3x3 1.0_F
270uF/2V 22uF/6.3V,X5R 270uF/2V 22uF/6.3V,X5R
R0603
169.0_F 24.3K_F PR206 PR207 20 VCORE0_LG_G4 G TC3528_1 C0603 TC3528_1 C0603
R tonset=232K_F LGATE1

2
1 2V0_SET1R
1 2 1.0_J 470K When VIN=12V S ns ns
SETGND0

1 1
R0402 R0402 2 1TON_SET0 1 2 1 2TONSET016
TONSET

1
2
3
C R0603 R0402 R0402
GND PC221 C

+VCORE0_ISP1

+VCORE0_ISN1
1
PR211 +V5A PR210 PC220 PR236 3300PF/50V,X7R
270K
10K_F 1.0_J 1UF/25V,X5R 1 2 10
IBIAS0 28 VCORE0_ISEN1P
IBIAS ISEN1P C0402 Difference pair

2
1 2 VCORE0_VBOOTSET 2 1 C0603 R0402

2
R0402 R0603 100K_F PR213
ns PR212 27 VCORE0_ISEN1N 487
ISEN1N 2 1

RT8171A
PR217 PR214 PC222 1UF change to 0.47UF FOR power 0420

1
10K_F 0_J r0402 R0402
1 2 En:0.7V26 4 1 2VCORE0_SENSE 1 680_F 2
VCORE0_EN VCORE0_VSEN PR216
SETGND0 VRON VSEN C0603

1
R0402 R0402 PR215 487 0.47uF/25V,X7R Close controller IC side

1
PC223 18
DRVEN1 R0402 PC222
PR220 PR221 0.1uF/16V,X5R DRVEN0

2
100K_F 5.6K C0402 24 0_J 68K_F +VCORE0
DRVEN2

2
1 2VCORE0_TSEN_R 1 2VCORE0_TSEN 2 1 PR218 2COMP0_R 1 PR219 2
R0402 RT4 R0402 COMP R0402 R0402

1
NTC_100K VCORE0_PWRGD 17 47pF/50V,NPO 10K_F PC225

2
1 2 VR_READY VCORE0_COMP1 2 1 2
RT =4250 0_J PC224
PR222
R0402
0.1uF/16V,X5R
C0402
PR223

1
PC226 100_F

2
VCORE0_VCLK 1 2 VCLK0 15 3
CLOSE Hottest MOS R0402
PR226
PR224
R0402 VCLK FB VCORE0_FB
C0402 0.1uF/16V,X5R R0402
PC227 C0402
6.49k_F

2
1 2 0_J 5
390pF/50V,NPO ns

1
SETGND0 PR225 RGND 1 2 VCORE0_SENSE
R0402 VCORE0_VDIO 1 2 VDIO0 13 0_J
R0402 VDIO VCORE0_RGND 1 PR227 2
C0603
VSS0_SENSE Difference pair
R0402

2
0_J
PR228

1
1
VCORE0_ALERT_L 2 ALERT0_L 14 1 PC228 PR230
ALERT# VREF +VREF0
PR229 R0402 0.1uF/16V,X5R 100_F

1
10K_F PR232 PC229 C0402 R0402

2
1 2 75.0_F 1.6K 0.47uF/16V,X7R ns
+V3.3A PR231 2
R0402 1
VCORE0_VR_HOT_N VR_HOT0_L 12 31 IMON01 2 C0603
VR_HOT# IMON

1
1

PC230 R0402 R0402

OD,Active low

Thermal_PAD
0.1uF/16V,X5R

IMON0_R0
C0402
2

ns 32 19 PR234
NC PGND 1K 6.49K
1 PR233 2IMON0_R1 1 2
R0402 R0402

1
33
PR235
5.6K
B B
R0402
VCORE0_NTC1P

2
IMON0_R2 VCORE0_NTC1N
colay 0605V1.3 for power

1
Length (0.5'~1)
VCORE0_VCLK +VCORE0 Add PEC12 PEC11 1020
12 VCC_VCLK
PR237
Vout 0.5-1.3V
VCORE0_VDIO
Pls check 1pcs 820uF 7mohm Polymer whether can pass spec VR12.1 1.37K
12 VCC_VDIO R0402
PR239 Vin 12V/20V
VCORE0_ALERT_L
12 VCC_ALERT_L
825
Switch Freq 800KHz

2
1

1 2
+VREF0
1

VCORE0_VR_HOT_N T + PEC11 1
12 VCORE0_VR_HOT_L
PC5
22uF/6.3V,X5R 270uF/2V
PC234
22uF/6.3V,X5R
PC232 PC233
22uF/6.3V,X5R 22uF/6.3V,X5R
R0402
ocp 1.5*Imax
C0603 TC3528_1 C0603 C0603 C0603
MLCC_Iripple 10uF/1A,47uF/2.8A
2

ns
VCORE0_SENSE
12 VCORE0_SENP Choke size 1uH/7.3x6.8mm
VSS0_SENSE +VCORE0
12 VCORE0_SENN Choke Idc/Isat 11A/22A
Add 1 22uf follow Vendor
VC 140303 Choke DCR 10m
1

1
VCORE0_PWRGD
44 VCORE0_PWRGD
PC235
22uF/6.3V,X5R
PC236 PC237
22uF/6.3V,X5R 22uF/6.3V,X5R
PC238
22uF/6.3V,X5R
PC239
22uF/6.3V,X5R
PC240
22uF/6.3V,X5R
PC241
22uF/6.3V,X5R Cin CAP 47uF+2*10uF
C0603 C0603 C0603 C0603 C0603 C0603 C0603
Cout CAP 330uF+5*22uF
2

2
1 2 680_F r0402 VCORE0_EN
42 VGG_PWRGD
PR241
Cout CAP_ESR 9m
LIR 0.2-0.3
22UF use 0603 Footprint 1020

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 43 of 52

sualaptop365.edu.vn
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

+V3.3S 7,8,14,20,23,24,26..28,31,32,34,44 +VDIMM 7,14,18,19,40,41

+V3.3A 7,10,12,20,24,26..28,33,34,37..44 +VDC 24,36..38,40,42,43
+V1.8A 7..12,14,16,20,23..25,27,31,39 +V3.3A 7,10,12,20,24,26..28,33,34,37..44
+V5A 29,30,34,37..43 +V3.3S 7,8,14,20,23,24,26..28,31,32,34,44 +V3.3S
+V5S 22,25,28 +V1.8S 10,14,20,23,28,31

1
R412
change use DFN8 footprint MOS 0417 10K_J
r0402
+V3.3A +V3.3S

2
+V5A ns
Q23 +V5S
QM3003M3 2A Q3666
EMF21P02V
1 dfn8_0d65_3x3
D 2 1 dfn8_0d65_3x3 PR181 1 2 1K_J r0402 D
3 2 43 VCORE0_PWRGD
S 5 3

1
change PMOS
D S 5

1
R328 C356 G D

1
100K_F 0.1uF/16V,X5R C358 C357 R359 G PR180 1 2 1K_J r0402 ns 2 1
20,41,42 +V1.15S_PWRGD ALL_SYS_PWRGD 20

1
R0402 C0402 10UF/6.3V,X5R 0.1UF/10V,X5R 100K_F C353 R0402 0_J R413

4
1
C0603 C0402 R0402 C354 0.1UF/10V,X5R

1
0.1UF/10V,X5R C355 C0402 timing sequence change 0119wls
2

2
C0402 ns10UF/6.3V,X5R

1
C0805 D24 2 1 LMDL914T1G SOD323

2
PR365

V5S_ON_N
100k_J

1V3.3S_ON_N
r0402
ns

2
2
20 SLP_S3_EC_N

2
+V5S 3
R400 PD3
4.7K_J R398 1 LBAT54ALT1G
7,20,40 VDDQ_PWRGD
R0402 1K_F SOT23-3
R0402

1
C595 C605 C606
1

0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R

2
C0402 C0402 C0402

2
3

D Q22 +V3.3A
L2N7002LT1G
1 2RUN_DISCHAGE#_L 1 sot23-3
20 RUN_ON G
R402 1K_J R0402 S
2

1
C370
2

R403 +V3.3S 0.1UF/10V,X5R

100K_J c0402

2
R0402

3
1

5
D Q21 C597 C608 C609 ALL_SYS_PWRGD 1 ns
L2N7002LT1G 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 4
1 sot23-3 C0402 C0402 C0402 2 DDR3_VCCA_PWROK_3P3 7
20 DELAY_ALL_SYS_PWRGD

2
G S U15

3
C 74AHC1G08GW C

2
sot353 1 2
COREPWROK 12
R414 0_J R0402

U15 change to ns,R416 change to stuff 0604V1.3wls

+VDC
R416 1 0_J 2 R0402

+V1.8A Q40 +V1.8S

QM3010K 300mA
2

sot23-3 +V3.3A
1

R351 C351 3 2
Add PR60 PU 0118

S
D
100K_J 0.01UF/25V,X7R

2
C0402

G
R0402
2

PR60

1
2

10K_F
1

+V3.3A R0402
1 B E Q36
C LDTB114ELT1G
3.3S_1.8S_PWRGD 40,41

1
2

2
SOT23-3
R405
3

1K_J PR125

3
R0402 R371 1 2 33K_J R0402 C377 C376 51K_J

1
10UF/6.3V,X5R 0.1UF/10V,X5R r0402 D PQ15 PC177
2

C0603 C0402 L2N7002LT1G 0.1UF/10V,X5R

1

1
R406 1 SOT23-3 c0402

2
1
30K_F C375 +V3.3S G S

3
R0402 0.1uF/25V,X7R

2
2 C0603 C
PR126 1 2 1K_J r0402 1 B
1

E
3

Q27
D Q46 LMBT3904LT1G

2
L2N7002LT1G SOT23-3
RUN_DISCHAGE#_L 1 sot23-3
G S
B B
2

+V1.8S

2
C
PR127 1 2 680_F r0402 1 B R409
E 0_J
Q28 R0402
LMBT3904LT1G ns

2
SOT23-3

1
+V5S +V3.3S
+V1.8S
2

+VDC
2

R435 R327
330_J 330_J R349
2

r0603 r0603 330_J

R329 r0603
510K_J
3 1

6 1

R0402 Q61B
6 1

L2N7002DW1T1G Q62B
D D L2N7002DW1T1G
1

D
5 G 2 G
S S 2 G
3

Q61A S
4

D R434 L2N7002DW1T1G
1

200K_F sot363
RUN_DISCHAGE#_L 5 G
R0402
S
Q62A
4

L2N7002DW1T1G
sot363

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 44 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name Cover Page
Size Project Name Rev
A2 Braswall-M 1.0
Date: Tuesday, June 09, 2015 Sheet 45 of 52

sualaptop365.edu.vn PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 5 4 3 2 1

D D

Gsensor Two

+V3.3S_DB1 +V1P8S_DB1

VDD_IO_DB BOSCH
U44 R644 1 0_J 2 R0402
C520 BMA250E

1
0.1uF/10V,X5R LGA12_0D5_2x2 BOSCH C511
C0402 0.1uF/10V,X5R R183
BOSCH 3 7 C0402 10K_J
VDDIO VDD
BOSCH r0402
10
11 CSB
DB1_GND
PS
ns

2
BOSCH 6 DB1_GND
Gsensor_SDA_1_DB R647 1 0_J 2 R0402 2 INT2 5 Gsensor_INT1_DB
Gsensor_SCL_1_DB R645 1 0_J 2 R0402 12 SDx INT1
SCx

GNDIO
BOSCH

GND
SDO
NC
change the P/N from 1011-00916 to 1011-01986 ckj0911

1
4
8
9
BOSCH
+V1P8S_DB1 +V3.3S_DB1 CN12
Addr_1_DB 50376-00601-001
CNS6_0D6_R_50376
DB1_GND 1 7
2
3
Gsensor_SCL_1_DB 4
Gsensor_SDA_1_DB 5
Gsensor_INT1_DB 6 8

+V3.3S_DB1
+V1P8S_DB1+V3.3S_DB1 R718 ns 0R R0402
ns R719
R630 2 0_J 1 R0402 C512 4.7uF/6.3V,X5R 1 0_J 2
C0603 R0402
2 1 DB1_GND ns ns DB1_GND

VDD_IO_DB
R0402 0_J R646
LSM303D/LIS3DE/LIS3DH/MMA8452Q/FXOS8700CQ/KXCJK-1013

16
15
14
BOSCH U43
KXCJK-1013 1010-01810

VDD
NC4
NC3
C506 1 13
2 R638 1ns VDDIO NC2
ns 2 BYP GND3
12 DB1_GND
C 0_J 3 11 Gsen_INT1_DB 2 R717 1Gsensor_INT1_DB C
C516 C519 2 R642 1 4 NC1 INT1 10 0_J
R0402
0.1uF/10V,X5R 0.1uF/10V,X5R 0_J0.1uF/10V,X5R 5 SCL GND2 9 R0402
C0402 C0402 C0402 GND1 INT2
R0402 DB1_GND ns

SDA
SA0
BOSCH BOSCH ns

NC
ns LGA16_0D5_3X3

6
7
8
SLAVE ADDRESS:0x19h/0x1Dh
DB1_GND DB1_GND

Gsensor_SCL_1_DB R639 VDD_IO_DB

1 0_J 2R0402
Gsensor_SDA_1_DB
Note:
ns The first pin of G-sensor must be

Addr_1_DB
+V1P8S_DB1 place on the lower left corner of PCB.

R0402 2 R640 1ns 3D G-Sensor

0_J

2 1
R0402 0_J R641
BOSCH
DB1_GND

B B

A A

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 5 4 3 2 1

D D

C C

B B

A A

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Date: Tuesday, June 09, 2015 Sheet 47 of 52
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 5 4 3 2 1

H1
HOLE H7 H8
hole_2d5_8d0 HOLE HOLE
hole_2d5_8d0 hole_2d5_8d0

D D

1
H6
HOLE
CPU_BOSS1 hole_2d5_6d5_3
HOLE
hole_np_4d1

For Thermal

1
H2
HOLE

1
hole_2d5_8d0_1 CPU_BOSS3
CPU_BOSS2 HOLE
HOLE hole_np_4d1
hole_np_4d1
1

1
C C

1
H5
HOLE
HOLE_2D5_6D5_2

H4
H3 HOLE
HOLE hole_2d5_8d0
HOLE_2D5_6D5_2

1
1
1
PCB1 PCB2

MK1 MK2 MK3

1 1 1
MB MB 1 1 1
FMARKS FMARKS FMARKS
fmarks fmarks fmarks
ns ns ns
B B
BM5334 BM5334
PCB PN PCB PN MK6
MK4 MK5
1
SW 1 SW 2 W HITE BARCODE1 1 1 1
1 1 FMARKS
FMARKS FMARKS fmarks
fmarks fmarks ns
ns ns

MK8
MK7
EC code BIOS code W HITE 1
BIOS PN EC PN 1301-02021 1 1
1 FMARKS
FMARKS fmarks
fmarks ns
ns

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A3 Braswall-M 1.0
Date: W ednesday, June 17, 2015 Sheet 48 of 52
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documents or disclosed to others or used for any purpose other than that for which it
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 5 4 3 2 1

2A 2B +ECVCC
+5VALW_LDO
1B
BATT+
8A 8B 9A 9B
PD1 V3.3A\V5A_PWRGD V1.05A_PWRGD
D
1A charger IC +VDC +V1.05A D

AD+ 7A 7B
ALW_ON
ALW Power +V5A
+V3A
ACIN_EC 4A
14A 12B 10A 10B +V1.35A_PWRGD
8A 8B 9A 9B V1.05A_PWRGD +V1.24A
V3.3A\V5A_PWRGD

6A 6B
3A 3B ECRST#
ALW_ON
5A AC_PRESENT
5A AC_PRESENT
PMU_AC_PRESENT 10A 10B+V1.15A_PWRGD 11A 11B +V1.8A_PWRGD
4A ACIN_EC 18A 17B PMC_SUSPWRDNACK +V1.8A
PMC_SUSPWRDNACK
8A 8B V3.3A\V5A_PWRGD
11A 11B+V1.8A_PWRGD+V3.3A_PRIME 12A 12B +V3.3A_PRIME
11A 11B +V1.8A & 14A14B ALW_PWRGD
15A 15B PM_RSMRST_N
15A 15B PM_RSMRST_N RSMRST_B
14A 14B ALW_PWRGD
17A 5B 18= 16B 12A 12B+V3.3A_PRIME_EN
19A 18B PM_PWRBTN_N PMU_RSTBTN_B PMU_SLP_S4_B PM_SLP_S4_N
+V3.3A_PRIME
18A 17B PMC_SUSPWRDNACK EC PMC_SUSPWRDNACK_EC
Braswell-M
C 8528 SoC C

Isense_SYSN
17A 5B 19
16A 4B PWRSW# PM_PWRBTN_N
20.5 DDR3_DRAM_PWROK DDR3_DRAM_PWROK PMC_SLP_S3_B
21 PM_SLP_S3_N
SUS_ON
VDIMM 20 VDDQ_PWRGD
20.5 DDR3_DRAM_PWROK
34 (VDDQ)
18 PM_SLP_S4_N
19 SUS_ON
PM_SLP_S0IX_N

PMU_SLP_S0IX_B
19
21 PM_SLP_S3_N
22 RUN_ON
PM_SLP_S0IX_N

29 30 22
ALL_SYS_PWRGD DELAY_ALL_SYS_PWRGD 31 DDR3_VCCA_PWROK
RUN_ON
+V5S
25 26 DDR3_VCCA_PWROK
1.8S/1.5S_PWRGD 1.15S_EN 31.5 COREPWROK
COREPWROK PMU_PLTRST_B
32 PLTRST_N 34.5PLT_RST#
27 +V1.15S_PWRGD
28 +VGG_EN_EC
22 RUN_ON
30.5 ALL_SYS_PWRGD
31 DELAY_ALL_SYS_PWRGD +V3.3S

22 +V3.3S
23 RUN_ON
+V1.8S 25
24 +V1.8S & 1.8S/1.5S_PWRGD

31 DELAY_ALL_SYS_PWRGD 32 32.5COREPWROK
30 ALL_SYS_PWRGD
& DDR3_VCCA_PWROK

B
25 1.8S/1.5S_PWRGD
B

27 +V1.15S_PWRGD
26 +1.15S
1.15S_EN

27 +V1.15S_PWRGD
29 VGG_PWRGD
28 VGG
+VGG_EN_EC

29 VGG_PWRGD
30 VCORE0_PWRGD
30.5 ALL_SYS_PWRGD
Vcore0

A A

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Power On/Off Sequence Specification(Adapter Mode) G3-S5-S4-S3-S0

T8 >60us
PLTRST_B TO SOC
T7 >1mS
SUS_STAT#
T6b >99mS
COREPWROK TO SOC
D D

PLTRST_N
DDR3_VCCA_PWROK_3P3 Power IC To SOC
+V_VDDQ_VTT
ALL_SYS_PWRGD Input EC & SOC
SLP_S3_EC_N Input EC

+V_VDDQ_VTT EC TO Power IC
RUN_ON EC Output

Vcore0/1 VGG IC TO Vcore IC

DDR3_VCCA_PWROK_3P3
+VGG EC output
COREPWROK
+V1.15S
+V1.15S/+V1.8S/+V5S/+V3.3S/
3.3S_1.8S_PWRGD
Input EC
Ttype=3~4mS PMU_SLP_S4_N
RUN_ON EC output
EC Output
T5 >26uS SUS_ON
PM_SLP_S3_N SB to EC
+VDIMM
+VDIMM
EC Output
C ALW_ON C

Ttype=1~2mS
SUS_ON EC output +V1.05A/+V1.24A/+V1.8A/+V3.3A_PRIME/+V3.3A/+V5A

PM_SLP_S4_N SB to EC

S0 S0 S3/S4/S5 S5 G3
TB_min>=16mS TB_min>=0mS:5mS
PM_PWRBTN_N EC to SB TD_type=50ms
Tmin>=0mS
TA_min>=5mS:97mS
TC_Min>=100ms:155mS
PWRSW#_R External Power Botton TO EC
Tmin>=0mS Press Power Button

T2 >10uS
PM_RSMRST_N EC to SB

ALW_PWRGD Input EC

+V3.3A_PRIME +V1.8A IC Output

B
+V1.8A +V1.24A IC Output B

+V1.24A EC Output

+V1.05A EC Output

3.3A_5A_PWRGD Input EC

+V5A/+V3.3A

Ttype=1~2mS:1mS
ALW_ON EC output

AC_PRESENT EC To SB

ACIN_EC Charger IC TO EC

EC_RST_N

+3VALW_LDO/+ECVCC

A
+VDC A

RTCRST# T1
>9mS

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Date: Tuesday, June 09, 2015 Sheet 50 of 52

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Power On/Off Sequence Specification(Battery Mode) G3-S5-S4-S3-S0

T8 >60us
PLTRST_B TO SOC
E E

T7 >1mS
SUS_STAT#
T6b >99mS
COREPWROK TO SOC

DDR3_VCCA_PWROK_3P3 Power IC To SOC

ALL_SYS_PWRGD Input EC & SOC

+V_VDDQ_VTT EC TO Power IC

Vcore0/1 VGG IC TO Vcore IC

+VGG EC output

+V1.15S
D D

3.3S_1.8S_PWRGD

RUN_ON EC output
Ttype=3~4mS
PM_SLP_S3_N SB to EC

+VDIMM

SUS_ON EC output
Ttype=1~2mS

PM_SLP_S4_N SB to EC

PM_RSMRST_N EC to SB
C C

PM_PWRBTN_N EC to SB Tmin>=0mS
TA_min>=5mS:97mS
TC_Min>=100ms:155mS
PWRSW#_R External Power Botton TO EC
Press Power Button

ALW_PWRGD Input EC

+V3.3A_PRIME +V1.8A IC Output

+V1.8A +V1.24A IC Output

+V1.24A EC Output
B B
+V1.05A EC Output

3.3A_5A_PWRGD Input EC

+V5A/+V3.3A

Ttype=1~2mS:1mS
ALW_ON EC output

EC_RST_N

+3VALW_LDO/+ECVCC

+VDC

RTCRST# T1
>9mS
A A
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G3 G3 S5 S3/S4/S5 S0 S0 Date: Tuesday, June 09, 2015 Sheet 51 of 52
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 5 4 3 2 1

Change History
D Version Notes Date D

V1.0 Initial release 2014.10.11

V1.1 SIV

C C

V1.2 SIT

B V1.3 SVT B

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Date: Tuesday, June 09, 2015 Sheet 52 of 52
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