DAC and ADC

Sample and Hold Circuit

Sample and Hold Circuit
Sample and Hold Circuit
Sample and Hold Circuit
Digital-to-Analog Converter (DAC)
Specifications
Digital-to-Analog Converter (DAC)
A block diagram of a DAC can be seen in the above figure
Here an N-bit digital word is mapped into a single analog
voltage.

where vOUT is the analog voltage output,

VREF is the reference voltage, and
F is the fraction defined by the input word, D, that is N
bits wide.
The number of input combinations represented by the
input word D is related to the number of bits in the word
by
Number of input combinations = 2N
Digital-to-Analog Converter (DAC)
If the input is an N-bit word, then the value of
the fraction, F, can be determined by,

if a 3-bit DAC is being used, the input, D, is 100

=410 and VREF is 5 V, then the value of F is

the analog voltage that appears at the output

becomes,
 Digital-to-Analog Converter (DAC)

This maximum analog

output voltage that can be
generated is known as
full-scale voltage, VFS and
can be generalized to any
N-bit DAC as
Digital-to-Analog Converter (DAC)
The least significant bit (LSB) refers to the
rightmost bit in the digital input word. The LSB
defines the smallest possible change in the
analog output voltage. The LSB will always be
denoted as Do. One LSB can be defined as
 DAC-Problems
Find the number of input combinations, values
for 1 LSB, the percentage accuracy, and the
full-scale voltage generated for a 3-bit, 8-bit,
and 16-bit DAC, assuming that VREF = 5 V.
 Differential Nonlinearity
Non ideal components cause the analog increments to
differ from their ideal values. The difference between
the ideal and non ideal values is known as differential
nonlinearity, or DNL and is defined as

DNLn = Actual increment height of transition n - Ideal increment height.

where n is the number corresponding to the digital

input transition.
The DNL specification measures how well a DAC can
generate uniform analog LSB multiples at its output.
 DNL EXAMPLE
Determine the DNL for the 3-bit non ideal DAC whose transfer
curve is shown in Fig. Assume that V REF = 5 V.
 DNL EXAMPLE
The actual increment heights are labelled with respect
to the ideal increment height, which is 1 LSB
There is no increment corresponding to 000, since it is
desirable to have zero output voltage with a
The increment height corresponding to 001, however,
is equal to the corresponding height of the ideal case
digital input code of 000, therefore, DNL1 = O.
Similarly, DNL2 is also zero since the increment
associated with the transition at 010 is equal to the
ideal height.
 DNL EXAMPLE
Notice that the 011 increment, however, is
not equal to the ideal curve but is 1.5 times
the ideal height
 DNL EXAMPLE
If we were to plot the value of DNL (in LSBs)
versus the input digital code, would result as
shown below.
 Integral Nonlinearity
Another important static characteristic of DACs is
called integral nonlinearity (INL).
Defined as the difference between the data
converter output values and a reference straight
line drawn through the first and last output
values.
INL defines the linearity of the overall transfer
curve and can be described as

INL =Output value for input code n - Output value of the reference line at that point
Integral Nonlinearity
 Integral Nonlinearity
Determine the INL for the non ideal 3-bit DAC shown in Fig.
28.14. Assume that VREF =5 V.
 Integral Nonlinearity
First, a reference line is drawn through the first and
last output values. The INL is zero for every code in
which the output value lies on the reference line;
therefore, INL2=INL4 =INL6 =INL7 =O.
Only outputs corresponding to 001, 011, and 101 do
not lie on the reference.
Both the 001 and the 011 transitions occur 0.5 LSB
higher than the straight-line values; therefore, INL1 =
INL3 = 0.5 LSB.
By the same reasoning, INL5 =- 0.75 LSB.
The INL plot for the nonideal 3-bit DAC can be seen in
Fig below.
Integral Nonlinearity
 Offset
The analog output should be 0 V for D = O. However, an offset exists if the
analog output voltage is not equal to zero.
 Gain Error
A gain error exists if the slope of the best-fit
line through the transfer curve is different
from the slope of the best-fit line for the ideal
case.
Gain error =Ideal slope - Actual slope
Gain Error
 Latency and SNR
Latency
This specification defines the total time from the
moment that the input digital word changes to
the time the analog output value has settled to
within a specified tolerance.
Signal-to-Noise Ratio (SNR)
Signal-to-noise (SNR) is defined as the ratio of the
signal power to the noise at the analog output.
 Dynamic Range
Dynamic Range
Dynamic range is defined as the ratio of the
largest output signal over the smallest output
signal.
DAC Architectures
Resistor String
 Resistor String
Advantages
Output is always monotonic.
Disadvantages
Always connected with 2N-1 Switches are off and one
switch is on.
For large resolution large parasitic capacitance at
output node which results in slow conversion speeds.
Hence the binary switch arrangement is shown in the
figure, where N switches are OFF and N switches are
ON, Thus increasing the conversion speed.
Balance between area and power dissipation.
 Resistor String example
Design a 3-bit resistor string ladder using a
binary switch array. Assume that VREF = 5 V
and that the maximum power dissipation of
the converter is to be 5 mW. Determine the
value of the analog voltage for each of the
possible digital input codes.
 Resistor String example
The power dissipation will determine the
current flowing through the resistor string by

Since a 3-bit converter will have eight

resistors, the value of R is
Resistor String example
Resistor String example
Mismatch Errors Related to the
Resistor String DAC
 Mismatch Errors Related to the
Resistor String DAC
The value of the voltage at the tap associated
with the i-th resistor should ideally be
 Mismatch Errors Related to the
Resistor String DAC
Including the mismatch, the actual value of
the i-th voltage will be the sum of all the
resistances up to and including resistor i,
divided by the sum of all the resistances in the
string. This can be represented by
 Integral Nonlinearity of the Resistor
String DAC
Integral nonlinearity (INL) is defined as the
difference between the actual and ideal
switching points, or
 Integral Nonlinearity of the Resistor
String DAC
If the resistors on a string were known to have 2% matching, then
Rk would be constrained to the bounds of

Worst case INL would be

Differential Nonlinearity of the
Worst-Case Resistor String DAC
 R-2R Ladder Networks
This has fewer resistors.
Alternating values of R and 2R.
The digital input determines whether each
resistor is switched to ground or to the
inverting input of opamp.
Each node is related to Vref, by a binary
weighted relationship caused by voltage
division of the ladder network.
R-2R Ladder Networks
 R-2R Ladder Networks
The output voltage depends on the current flowing
through feedback resistor.

Where the iTOT is the sum of currents selected by the digital input given by.

Where Dk bit is the k-th bit of the input word

with a value that is either a 1 or 0.
 R-2R Ladder Networks
Requires matching .
Switch resistance must be negligible or drop will occur which leads to error.
To eliminate this problem we can use dummy switch as shown below.
 R-2R Ladder Networks
Design a 3-bit DAC using a R-2R architecture
with R =1 k, RF =2 k , and VREF = 5 V.
Assume that the resistances of the switches
are negligible. Determine the value of iTOT for
each digital input and the corresponding
output voltage, vOUT
R-2R Ladder Networks
R-2R Ladder Networks
 Cyclic DAC
It uses simple components to perform conversion
such as summer, amplifier, S/H circuit.
A summer adds Vref or ground to the feedback
signal depending on the input bits.
An amplifier with a gain of 0.5 feeds the output
voltage back to the summer such that the output
at the end of each cycle depends on the value of
the output during the cycle before.
Input bits must be read serially.
N cycles required for each conversion.
Cyclic DAC
 Cyclic DAC
The accuracy of this converter is dependent on
several factors.
The gain of the 0.5 amplifier needs to be highly
accurate and is usually generated with passive
capacitors.
Summer and sample hold should also be N bit
accurate.
Since this converter uses a pseudo sampled data
approach, implementing this architecture using
switched capacitors is relatively easy.
 Cyclic DAC
Show the value of the output voltage at the
end of each cycle for a 6-bit cyclic DAC with an
input value of D5 D4 D3 D2 D1 D0= 1 1 0 1 0 1.
Assume that VREF= 5 V.
Cyclic DAC
 Pipeline DAC
Cyclic DAC takes N clock cycles per N bit conversion.
Cyclic convertors are extended to N stages rather than the
recycling the output back.
The extension of the cyclic converter is called pipeline DAC.
The signal is passed down the pipeline and each stage
works on one conversion, the previous stage can begin
processing another.
Conversion takes place at every clock cycle.
It takes N clock cycle delay.
Fast
Amplifier gain must be accurate for high resolution.
Trade off between speed and chip area.
 Pipeline DAC
If the input bit is 1, add vref to the output of
the previous stage, divide by two, and pass
the value to the next stage.
If the input bit is 0, simply divide the output of
the previous stage and pass the value to the
next stage.
Pipeline DAC
 Pipeline DAC
Find the output voltage for a 3-bit pipeline
DAC for three cases: DA = 001, DB =110, and
D; = 101 and show that the conversion time to
perform all three conversions is five clock
cycles using the pipeline approach. Assume
that VREF = 5 V.
Pipeline DAC
 Current Steering
Uses current through out the conversion.
Set of current sources, each having a unit value of
current I.
For a 3 bit DAC, it requires 7 current sources.
The output current Itot has a range of

Since there are 2N-1 current sources, the digital

input will be in the form of thermometer code.
Thermometer encoder is used.
Current Steering
 Current Steering
Binary weighted current sources.
Requires only N current sources of various
sizes .
Input code can be binary number.
Advantage
No output buffers are used to drive load, High
speed applications.
Disadvantage
Glitch while switching
Current Steering
 Current Steering
Construct a table showing the thermometer
code necessary to generate the output shown
in Fig. for a 3-bit current steering DAC using
unit current sources.
Current Steering
 Mismatch Errors Related to Current
Steering DACs
Analysis of the mismatch associated with the
current sources is similar to the resistor string
analysis. It is assumed that each current
source in Fig. is

where I is the ideal value of the current and k

is the error due to mismatch.
 Mismatch Errors Related to Current
Steering DACs
If it is again assumed that the IK terms sum
to zero and that one-half of the current
sources contain the maximum positive
mismatch, Imax, and the other half contains
the maximum negative mismatch, Imax,,
then the worst-case condition will occur at
midscale with the actual output current being
 INL Related to Current Steering DACs
INL is simply the actual output current minus
the ideal, the worst-case INL will be

The term, I Ilmax, lNL represents the

maximum current source mismatch error that
will keep the INL less than 0.5 LSB.
Each current source represents the value of 1
LSB; therefore, 0.5 LSB is equal to 0.5 I.
 INL Related to Current Steering DACs
0.5 I results in the value for I I lmax,lNL

Above equation illustrates the difficulty of

using this architecture at high resolutions. If
the value of I is set to be 5 micro A, and the N
is desired to be 12 bits, then the value of I I
lmax,lNL becomes
 INL Related to Current Steering DACs
which means that each of the 5 micro A
current sources must lie between the bounds
of,

to achieve a worst-case INL, which is within

0.5 LSB error.
DNL Related to Current Steering DACs
The DNL is easily obtained since the step
height in the transfer curve is equivalent to
the value of the ideal current source, I.
The maximum difference between any two
adjacent values of output current will be
simply the value of the single source, Ik ,
which contains the largest mismatch error for
which the DNL will be less than 0.5 LSB,
I I lmax,DNL:
DNL Related to Current Steering DACs

Therefore, the DNL is simply

Equating the maximum DNL to the value of

1/2 LSB,
 Mismatch errors of Binary-weighted
current sources
It will be assumed that the current source
corresponding to the MSB (DN-1) has a
maximum positive mismatch error value and
the remainder of the bits (D0 to DN-2 ) contain
a maximum negative mismatch error, so that
the sum of all the errors equals zero.
Therefore, the INL is
 Mismatch errors of Binary-weighted
current sources
The DNL is slightly different because of the
binary weighting of the current sources. One
cannot add a single current source with each
incremental increase in the digital input code.
However, the worst-case condition for
binary-weighted arrays tends to occur at
midscale when the code transitions from
011111....111 to 100000....000.
The worst-case DNL at this point is
 Mismatch errors of Binary-weighted
current sources
It can be written as,

and setting this value equal to 0.5 LSB and

solving for Imax,
 Charge Scaling DACs
A very popular DAC architecture used in CMOS
technology is the charge scaling DAC. Shown in
Fig. a parallel array of binary-weighted capacitors,
totalling 2NC, is connected to an op-amp.
The value, C, is a unit capacitance of any value.
After initially being discharged, the digital signal
switches each capacitor to either VREF or ground,
causing the output voltage, vOUT, to be a function
of the voltage division between the capacitors.
Charge Scaling DACs
 Charge Scaling DACs
Since the capacitor array totals 2NC, if the MSB
is high and the remaining bits are low, then a
voltage divider occurs between the MSB
capacitor and the rest of the array. The analog
output voltage, VOUT, becomes

which confirms the fact that the MSB changes

the output of a DAC by 0.5 VREF
 Charge Scaling DACs
Figure below shows the equivalent circuit
under this condition. The ratio between vOUT
and VREF due to each capacitor can be
generalized to

where it is assumed that the k-th bit, Dk , is 1

and all other bits are zero. Superposition can
then be used to find the value of vOUT for any
digital input word by
Charge Scaling DACs
 Charge Scaling DACs
One limitation of this architecture is the existence
of a parasitic capacitance at the top plate of the
capacitor array due to the op-amp.
This will prohibit its use as a high-resolution data
converter.
A better implementation would include the use of
a parasitic insensitive, switched-capacitor
integrator as the driving circuit.
However, the capacitor array itself is the critical
component of this data converter and is used in
charge redistribution ADCs.
 Charge Scaling DACs
Design a 3-bit charge scaling DAC and find the
value of the output voltage for D2 D1 D0= 010
and 101. Assume that VREF=5 V and C =0.5 pF.
 Charge Scaling DACs

For D= 010

For D=101
 Layout Considerations for a
Binary-Weighted Capacitor Array
 Charge Scaling DACs
The Split Array
The charge scaling architecture is very popular
among CMOS designers because of its simplicity
and relatively good accuracy.
 Charge Scaling DACs
The output is taken off a different node and
an additional attenuation capacitor is used to
separate the array into a LSB array and a MSB
array.
Note that the LSB, Do, now corresponds to the
leftmost switch and that the MSB, D5
corresponds to the rightmost switch. The value
of the attenuation capacitor can be found by
 Charge Scaling DACs
where the sum of the MSB array is equal to
the sum of LSB capacitor array minus C.
The value of the attenuation capacitor should
be such that the series combination of the
attenuation capacitor and the LSB array,
assuming all bits are zero, is equal to C.
 Charge Scaling DACs
Using the 6-bit charge scaling DAC shown in
Fig. 29.15, (a) show that the output voltage
will be 0.5 VREF if (a) D5D4D3D2D1D0=
100000 and (b) the output will be 1/64 VREF if
D5D4D3D2D1D0 = 000001.
Charge Scaling DACs
Charge Scaling DACs
ADC
Analog-to-Digital Converter (ADC)

Number of quantization levels =2N

Analog-to-Digital Converter (ADC)
 Quantization Error
Since the analog input is an infinite valued
quantity and the output is a discrete value, an
error will be produced as a result of the
quantization. This error, known as
quantization error,
Qe is defined as the difference between the actual
analog input and the value of the output
(staircase) given in voltage. It is calculated as
 Quantization Error
where the value of the staircase output,
Vstaircase can be calculated by

where D is the value of the digital output code

and VLSB is the value of 1 LSB in volts
 Differential Nonlinearity
Differential nonlinearity for an ADC is similar
to that defined for a DAC. However, for the
ADC, DNL is the difference between the actual
code width of a nonideal converter and the
ideal case.
DNL = Actual step width - Ideal step width
 DNL Example
Using figure below calculate the differential
nonlinearity of the 3-bit ADC. Assume that
VREF = 5 V. Draw the quantization error, Qe in
units of LSBs.
DNL Example
 DNL Example
The DNL of the converter can be calculated by
examining the step width of each digital output
code.
Since the ideal step width of the 000 transition is
0.5 LSB, then DNL0 = 0.
Also note that the step widths associated with 001
and 100 are equal to 1 LSB; therefore, both DNL1
and DNL4 are zero.
However, the remaining values code widths are
not equal to the ideal value but can be calculated
as
DNL Example
 Missing Codes
It is of interest to note the consequences of having a DNL that is equal to
-1 LSB.
 Integral Nonlinearity
Integral nonlinearity (INL) is defined similarly
to that for a DAC. Again, a "best-fit straight
line is drawn through the end points of the
first and last code transition, with INL being
defined as the difference between the data
converter code transition points and the
straight line with all other errors set to zero.
 INL Example
Determine the INL for the ADC whose transfer
curve is illustrated in Fig. Assume that VREF =
5 V. Draw the quantization error, Qe, in units
of LSBs
INL Example
 INL Example
By inspection, it can be seen that all of the
transition points occur on the best-fit line
except for the transitions associated with code
011 and 110. Therefore,

The INL corresponding to the remaining codes

can be calculated as
INL Example
Offset and Gain Error
 Signal-to-Noise Ratio
Signal-to-noise (SNR) ratios of ADCs represent
the value of the largest RMS input signal into
the converter over the RMS value of the noise.
ADC Architectures
 Flash Converters
Flash or parallel converters have the highest speed of ADC.
They utilize one comparator per quantization level (2N- 1) and
2N resistors.
The reference voltage is divided into 2N values, each of which
is fed into a comparator.
The input voltage is compared with each reference value and
results in a thermometer code at the output of the
comparators.
A thermometer code will exhibit all zeros for each resistor
level if the value of VIN is less than the value on the resistor
string, and ones if V IN is greater than or equal to voltage on
the resistor string.
 Flash Converters
A simple 2N - l:N digital thermometer decoder circuit converts the
compared data into an N-bit digital word.
The advantage of this converter is the speed with which one
conversion can take place.
Each clock pulse generates an output digital word.
The advantage of having high speed, however, is counterbalanced by
the doubling of area with each bit of increased resolution.

For example, an 8-bit converter requires 255 comparators, but a 9-bit

ADC requires 511! Flash converters have traditionally been limited to
8-bit resolution with conversion speeds of 10 - 40 Ms/s using CMOS
technology.
The disadvantages of the Flash ADC are the area and power
requirements of the 2N - 1 comparators. The speed is limited by the
switching of the comparators and the digital logic.
Flash Converters
 Example
Design a 3-bit Flash converter, listing the
values of the voltages at each resistor tap, and
draw the transfer curve for vin = 0 to 5 V.
Assume VREF = 5 V. Construct a table listing
the values of the thermometer code and the
output of the decoder for vin =1.5, 3.0, and
4.5 V.
Example
 Example
The 3-bit converter can be seen in Fig. above,
Since the values of all the resistors are equal, the voltage of
each resistor tap, Vj , will be Vj =VREF (i/8) where i is the
number of the resistor in the string for i =1 to 7.
V1= 0.625 V, V2 = 1.25 V, V3 = 1.875 V, V4 = 2.5 V,
V5 = 3.125, V6 = 3.75 V, V7 = 4.375 V.
Therefore, when vin first becomes equal or greater than
each of these values, a transition will occur in the transfer
curve.
The transfer curve can be seen in Fig. below. The
quantization levels and their corresponding thermometer
codes can be summarized as seen in Fig.
Example
Example
 Example
When vin =1.5 V, only comparators CI and C2 will
have outputs of 1, since both VI and V2 are less
than 1.5 V. The remaining comparator outputs will
be 0 since V3 through V8 will be greater than 1.5
V, thus generating the thermometer code,
0000011. The encoder must then convert this into
a 3-bit digital word, resulting in 010. The same
reasoning can be used to construct the data
shown in Fig.below It should be obvious that if the
polarity of the comparators were reversed, the
thermometer code would be inverted.
Example
 Accuracy Issues for the Flash ADC
Accuracy is dependent on the matching of the
resistor string and the input offset voltage of
the comparators.
An ideal comparator should switch at the
point at which the two inputs, v+ and v-, are
the same potential.
The offset voltage Vos prohibits this from
occurring as the comparator output switches
state as follows:
 Accuracy Issues for the Flash ADC

the voltage on the i-th tap of the resistor string was found
to be

where Vi, ideal is the voltage at the i-th tap if all the
resistors had an ideal value of R. The term, Rk is the value
of the resistance error (difference from ideal) due to the
mismatch. Note that for the resistor string DAC, the sum of
the mismatch terms plays an important factor in the overall
voltage at each tap.
 Accuracy Issues for the Flash ADC
The switching point for the i-th comparator,
Vsw,i' then becomes

where Vos,i is the input referred offset voltage

of the i-th comparator. The INL for the
converter can then be described as
 Accuracy Issues for the Flash ADC
which becomes

The worst-case INL will occur at the middle of

the string. Including the offset voltage, the
maximum INL will be
 Accuracy Issues for the Flash ADC
which can be rewritten as

where it is assumed that the maximum positive mismatch

occurs in all the resistors in the lower half of the string and
the maximum negative mismatch occurs in the upper half
(or vice versa) and that the comparator at the i-th tap
contains the maximum offset voltage, lVos|,lmax, Notice
that the offset contributes directly to the maximum value
for the INL This explains another limitation to using Flash
converters at high resolutions. The offset voltage alone can
make the INL greater than 0.5 LSB.
 Accuracy Issues for the Flash ADC
Using the definition of DNL,

The maximum DNL will occur assuming R; is at

its maximum, Vos,i is at its maximum positive
value, and Vos,i is at its maximum negative
voltage. Thus,
 The Two-Step Flash ADC
Another type of Flash converter is called the
two-step Flash converter or a parallel,
feed-forward ADC.
The converter is separated into two complete
Flash ADCs with feed-forward circuitry.
The first converter generates a rough estimate
of the value of the input, and the second
converter performs a fine conversion.
 The Two-Step Flash ADC
The advantages of this architecture are that the
number of comparators is greatly reduced from
that of the Flash converter from 2N - 1
comparators to 2(2N/2 - 1) comparators.
For example, an 8-bit Flash converter requires 255
comparators, while the two-step Flash requires
only 30.
The tradeoff is that the conversion process takes
two steps instead of one, with the speed limited
by the bandwidth and settling time required by
the residue amplifier and the summer.
 The Two-Step Flash ADC
The conversion process is as follows:
After the input is sampled, the most significant bits
(MSBs) are converted by the first Flash ADC.
The result is then converted back to an analog voltage
with the DAC and subtracted with the original input.
The result of the subtraction, known as the residue, is
then multiplied by 2N/2 and input into the second ADC.
The multiplication not only allows the two ADCs to be
identical, but also increases the quantum level of the
signal input into the second ADC.
The second ADC produces the least significant bits
through a Flash conversion
The Two-Step Flash ADC
The Two-Step Flash ADC
 Example
Assume that the two-step ADC has four bits of
resolution. Make a table listing the MSBs, V1'
V2, V3 , and the LSBs for V1N = 2, 4, 9, and 15
V assuming that VREF = 16 V. It uses two 2-bit
flash converter
 Example
Since VREF was conveniently made 16 V, each LSB
will be 1 V.
If vin =2 V, the output of the first 2-bit Flash
converter will be 00 since VREF = 16 V and each
resistor drops 4 V.
The output of the 2-bit DAC, V1 will therefore be
0, resulting in V2 =2 V. The multiplication of V2 by
the 4 results in V3 =8 V. The thermometer code
from the second Flash converter will be 0011,
which results in 10 as the LSBs.
Example
 The Pipeline ADC
The pipeline ADC is an N-step converter, with
1-bit being converted per stage.
Able to achieve high resolution (10-13 bits) at
relatively fast speeds, the pipeline ADC
consists of N stages connected in series
Each stage contains a 1-bit ADC (a
comparator), a sample-and-hold, a summer,
and a gain of two amplifier.
 The Pipeline ADC
Each stage of the converter performs the
following operation:
After the input signal has been sampled, compared it
to Vref/2. The output of each comparator is the bit
conversion for that stage.
If vin > vref/2(comparator output is 1), vref/2 is
subtracted from the held signal and pass the result to
the amplifier. If Vin < vref/2 (comparator output is 0),
then pass the original input signal to the amplifier. The
output of each stage in the converter is referred to as
the residue.
Multiply the result of the summation by 2 and pass
the result to the sample-and-hold of the next stage.
The Pipeline ADC
 The Pipeline ADC
A main advantage of the pipeline converter is its high
throughput. After an initial delay of N clock cycles, one
conversion will be completed per clock cycle. While the
residue of the first stage is being operated on by the second
stage, the first stage is free to operate on the next samples.
Each stage operates on the residue passed down from the
previous stage, thereby allowing for fast conversions.
The disadvantage is having the initial N clock cycle delay
before the first digital output appears. The severity of this
disadvantage is, of course, dependent on the application.
A slight error in the first stage propagates through the
converter and results in a much larger error at the end of
the conversion.
 Example
Assume the pipeline converter is a 3-bit
converter. Analyze the conversion process by
making a table of the following variables: D2,
D1 Do, V2, V1 for vin = 2, 3, and 4.5 V. Assume
that VREF = 5 V. Where V3 is the residue
voltage out of the first stage and V2 is the
residue voltage out of the second stage.
 Example
The output of the first comparator, D2 = 0,
since V IN < 2.5 V. Since D2 = 0, V3 = 2(2) =4 V.
Passing this voltage down the pipeline, since
V3 >2.5 V, D1 =1 and V2 becomes

The LSB, Do =1, since V2 > 2.5 V, and the

digital output corresponding to VIN = 2 V, is
D2D1D0 = 011. The actual digital outputs are
simply the comparator outputs
Example
Example
Accuracy Issues Related to the Pipeline
Converter
The 1-bit per stage ADC can be analyzed by
examining the switching point of each
comparator for the ideal and nonideal case.
Assuming all the components are ideal, let
Vin1 represents the value of the input voltage
when the first comparator switches. This
occurs when
Accuracy Issues Related to the Pipeline
Converter
The positive input voltage on the second
comparator, vp2 can be written in terms of the
previous stage, or

where DN-1 is the MSB output from the first

comparator and is either a I or a 0. The second
comparator switches when vo2 = VREF . The
value of vin at this point, denoted as Vin,2
Accuracy Issues Related to the Pipeline
Converter
We can write the value of the voltage on the
positive input of the third comparator in terms
of the previous two stages as

and the third comparator will switch when vo3

= VREF, which corresponds to the point at
which vin becomes
Accuracy Issues Related to the Pipeline
Converter
If we have N stages the equation can be
written as.
Accuracy Issues Related to the Pipeline
Converter
The positive input to the first nonideal
comparator, Vp1' will include the offset from
the first sample-and-hold, such that

Now the first comparator will not switch until

the voltage on the positive input overcomes
the comparator offset as well. This occurs
when
 Accuracy Issues Related to the Pipeline
Converter
solving for the value of the input voltage when
the switching occurs for the first comparator
yields

The input to the second comparator, Vp2' can

be written as
Accuracy Issues Related to the Pipeline
Converter
and the value of input voltage at the point
which the second comparator switches occurs
when

we can write the value of the input voltage

that causes the third comparator to switch as
Accuracy Issues Related to the Pipeline
Converter
which can be generalized to the N-th
switching point as
 INL Issues
The INL can be calculated by subtracting
switching point between the nonideal and
ideal case, for the first stage

The second stage INL is

the INL for the N-th stage is

 INL Issues
The worst-case addition of the offsets must be
less than LSB to keep the ADC N-bit
accurate.
The second stage is more dependent on the
gain of the residue amplifier
 DNL
The DNL can be found by calculating the
difference between the worst-case switching
points and subtracting the ideal value for an
LSB. The DNL is

Assuming DNLis 0 and all other bits 1

 Integrating ADCs
Another type of ADC performs the conversion by
integrating the input signal and correlating the
integration time with a digital counter. Known as
single- and dual-slope ADCs.
These types of converters are used in
high-resolution applications but have relatively
slow conversions.
However, they are very inexpensive to produce
and are commonly found in slow-speed,
cost-conscious applications.
 Single-Slope Architecture
A counter determines the number of clock
pulses that are required before the integrated
value of a reference voltage is equal to the
sampled input signal.
The number of clock pulses is proportional to
the actual value of the input, and the output
of the counter is the actual digital
representation of the analog voltage.
 Single-Slope Architecture
Since the reference is a DC voltage, the output of the
integrator should start at zero and linearly increase with a
slope that is dependent on the gain of the integrator.
Notice that the reference voltage is defined as negative so
that the output of the inverting integrator is positive.
At the time when the output of the integrator surpasses the
value of the SIH output, the comparator switches states,
thus triggering the control logic to latch the value of the
counter.
The control logic also resets the system for the next sample.
Single-Slope Architecture
Single-Slope Architecture
 Single-Slope Architecture
If the input voltage is very small, the conversion
time is very short, since the counter has to
increment only a few times before the
comparator latches the data.
However, if the input voltage is at its full-scale
value, the counter must increment to its
maximum value of 2N clock cycles.
Thus, the clock frequency must be many times
faster than the bandwidth of the input signal.
The conversion time, tc is dependent on the value
of the input signal and can be described as
 Single-Slope Architecture
where TCLK is the period of the clock. The
sampling rate is inversely proportional to the
conversion time and can be written as
 Accuracy issues
The voltage across the integrating capacitor,
Vc

Where tc is the conversion time.

 Dual-Slope Architecture
Here, two integrations are performed, one on the input
signal and one on VREF. The input voltage in this case is
assumed to be negative, so that the output of the inverting
integrator results in a positive slope during the first
integration.
The first integration is of fixed length, dictated by the
counter, in which the sample-and-held signal is integrated,
resulting in the first slope.
After the counter overflows and is reset, the reference
voltage is connected to the input of the integrator. Since vin
was negative and the reference voltage is positive, the
inverting integrator output will begin discharging back
down to zero at a constant slope.
A counter again measures the amount of time for the
integrator to discharge, thus generating the digital output.
Dual-Slope Architecture
Dual-Slope Architecture
 Dual-Slope Architecture
The first integration period continues until the
beginning of the eighth (23) clock pulse, which
corresponds to the counter's overflow bit.
Note that the integrator's output corresponding to VB
is twice the value of the output corresponding to VA.
Thus, it requires twice as many clock pulses for the
integrator to discharge back to zero from VB than from
VA.
The output of the counter at tA is three or 011, while
the counter output at tB is twice that value or six (110)
and the quantization is complete.
 Dual-Slope Architecture
Notice that the first slope varies according to
the value of the input signal, while the second
slope, dependent only on VREF , is constant.
Similiarly, the time required to generate the
first slope is constant, since it is limited by the
size of the counter.
However, the discharging period is variable
and results in the digital representation of the
input voltage.
 Accuracy Issues Related to the
Dual-Slope ADC
The first integration period requires a full 2N clock
cycle and cannot be decreased, because the second
integration might require the full 2N clock cycles to
discharge if the maximum value of V in is being
converted.
However, the dual slope is the preferred architecture
because the same integrator and clock are used to
produce both slopes.
Therefore, any nonidealities will essentially be
canceled.
For example, assuming that the S/H is ideal, the gain
of the integrator at the end of the first integration
period, T1, becomes
 The Successive Approximation ADC
An N-bit register controls the timing of the
conversion where N is the resolution of the ADC.
Vin is sampled and compared to the output of the
DAC.
The comparator output controls the direction of
the binary search, and the output of the
successive approximation register (SAR) is the
actual digital conversion.
The successive approximation algorithm is as
follows.
The Successive Approximation ADC
The Successive Approximation ADC
The Successive Approximation ADC
The Successive Approximation ADC
 Example
Perform the operation of a 3-bit successive
approximation ADC with VREF = 8. Make a
table that consists of D2D1D0, B2B1B0, VOUT
(the output from the DAC) and the comparator
output, which shows the binary search
algorithm of the converter for VIN =5.5 V and
2.5 V.
Example
The Charge-Redistribution Successive
Approximation ADC
 The Charge-Redistribution Successive
Approximation ADC
This converter samples the input signal and
then performs binary search based on the
amount of charge present in the capacitor of
the DAC.
A comparator has been replaced with unity
gain buffer.
The conversion process begins by discharging
the capacitor array, via reset switch.
 Once the reset switch is closed, the
comparator acts as a unity gain buffer. Thus,
the capacitor array charges to the offset
voltage of the comparator.
Figure shows the equivalent circuit
 The reset switch is then opened, and the
bottom plates of each capacitor in the array
are switched to ground, so that the voltage
appearing at the top plate of the array is now
Vos Vin
 The conversion process begins by switching the
bottom plate of the MSB capacitor to VREF .
If the output of the comparator is high, the
bottom plate of the MSB capacitor remains
connected to VREF
If the comparator output is low, the bottom plate
of the MSB is connected back to ground.
The output of the comparator is DN-1.
The voltage at the top of the capacitor array,is
now
The next largest capacitor is tested in the same manner. The voltage at the top
plate of the capacitor after the second capacitor is tested becomes
 The conversion process continues on with the
remaining capacitors so that the voltage on the
top plate of the array, VTop, converges to the
value of the offset voltage, Vos (within the
resolution of the converter), or

The initial charge stored on the capacitor array is

now redistributed onto only those capacitors that
have their bottom plates connected to VREF