Verilog HDL

HDLs
Hardware Description Languages
Widely used in logic design
Verilog and VHDL

Describe hardware using code

Document logic functions
Simulate logic before building
Synthesize code into gates and layout
Requires a library of standard cells
 Taste of Verilog

Module name Module ports

module Add_half ( sum, c_out, a, b );
input a, b;
Declaration of port
output sum, c_out; modes

wire c_out_bar; Declaration of internal

signal
Instantiation of primitive
xor (sum, a, b); gates

nand (c_out_bar, a, b); a

b sum
not (c_out, c_out_bar);
c_out_bar
endmodule
Verilog keywords c_out
 Behavioral Description
module Add_half ( sum, c_out, a, b );
input a, b;
output sum, c_out; a sum
reg sum, c_out; Add_half
always @ ( a or b ) b c_out
begin
sum = a ^ b; // Exclusive or
c_out = a & b; // And
end
endmodule
 Example of Flip-flop

module Flip_flop ( q, data_in, clk, rst );

rst
input data_in, clk, rst;
data_in q
output q;
reg q; clk

always @ ( posedge clk ) Declaration of synchronous behavior

begin
if ( rst == 1) q = 0;
Procedural statement
else q = data_in;
end
endmodule
 Gate Delay
and
and(yout,
(yout,x1,
x1,x2);
x2); ////default,
default,zero
zerogate
gatedelay
delay
and
and#3
#3(yout,
(yout,x1,
x1,x2);
x2); ////33units
unitsdelay
delayforforall
alltransitions
transitions
and
and#(2,3)
#(2,3)G1(yout,
G1(yout,x1,
x1,x2);
x2); ////rising,
rising,falling
fallingdelay
delay
and
and#(2,3)
#(2,3)G1(yout,
G1(yout,x1,
x1,x2),
x2),G2(yout2,
G2(yout2,x3, x3,x4);
x4);
////Multiple
Multipleinstances
instances
a_buffer
a_buffer#(3,5,2)
#(3,5,2)(yout,
(yout,x);
x); ////UDP,
UDP,rise,
rise,fall,
fall,turnoff
turnoff
bufif1
bufif1#(3:4:5,
#(3:4:5,6:7:9,
6:7:9,5:7:8)
5:7:8)(yout,
(yout,xin,xin,enable);
enable);
////min:typ:max
min:typ:max//rise, rise,fall,
fall,turnoff
turnoff

Simulators simulate with only one of min, typ and max delay values
Selection is made through compiler directives or user interfaces
Default delay is typ delay
 Time Scales
Time scale directive: timescale <time_unit>/<time_precision>
time_unit -> physical unit of measure, time scale of delay
time_precision -> time resolution/minimum step size during
simulation
time_unit time_precision

Unit/precision Delay Simulator time Delay value in

specification step simulation
1ns / 100ps #4 0.1ns 4.0ns
100ns / ns #4 1ns 400ns
10ns / 100ps #4.629 0.1ns 46.3ns
 Net Delay

wire
wire#2
#2y_tran;
y_tran;
and
and#3
#3(y_tran,
(y_tran,x1,
x1,x2);
x2); x1
buf
buf#1
#1(buf_out,
(buf_out,y_tran);
y_tran); 2 4 6 8 10
and
and#3
#3(y_inertial,
(y_inertial,x1,
x1,x2);
x2);
x2
2 4 6 8 10

y_inertial
2 4 6 8 10
x1 y_tran buf_out
y_tran
x2
2 4 6 8 10
y_inertial
buf_out
2 4 6 8 10
 Structural vs. Behavioral Descriptions

module my_module();

assign ; // continuous assignment
and (); // instantiation of primitive
adder_16 M(); // instantiation of module

always @() Structural, no order

begin end

initial Behavior, in order in each procedure

begin end
endmodule
 Behavioral Statements

initial
initial|| always
always
single_statement;
single_statement; || initial
Activated from tsim = 0
begin
begin
Executed once
block_of_statements;
block_of_statements; Initialize a simulation
end
end
always
Activated from tsim = 0
Executed cyclically
Continue till simulation
terminates
 Example of Behavioral Statement

module
moduleclock1
clock1((clk
clk););
parameter
parameterhalf_cycle
half_cycle==50;
50;
parameter
parametermax_time
max_time==1000;
1000;
output
outputclk;
clk; clk
reg
regclk;
clk;
initial
initial
clk
clk==0;0;
always
always 50 100 150 200 tsim
begin
begin
#half_cycle
#half_cycleclkclk==~clk;
~clk;
end
end
initial
initial
#max_time
#max_time$finish;
$finish;
endmodule
endmodule
 Assignment
Continuous assignment
Values are assigned to net variables due to some
input variable changes
assign =

Procedural assignment
Values are assigned to register variables when
certain statement is executed in a behavioral
description
Procedural assignment, =
Procedural continuous assignment, assign =
[deassign]
Non-blocking assignment, <=
 Procedural Continuous Assignment
Continuous assignment establishes static binding for
net variables

Procedural continuous assignment (PCA) establishes

dynamic binding for variables
assign deassign for register variables only
 assign deassign PCA
Binding takes effect module
moduleflop flop((q,q,qbar,
qbar,preset,
preset,
when PCA statement is clear,
clear,clock,
clock,data
data););
executed
assign
assignqbar qbar==~q; ~q;
initial
initial
Can be overridden by qq==0; 0;
another PCA statement always
always@ @((negedge
negedgeclk clk))
qq==data;
data;
always
always@ @((clear
clearororpreset
preset))
deassign is optional
begin
begin
ifif((!preset
!preset))assign
assignqq==1;1;
assign takes control, else
elseifif((!clear
!clear))assign
assignqq==0;0;
deassign release else
elsedeassign
deassignq; q;
end
control end
endmodule
endmodule
 Example of assign
module
module mux4_PCA(a,
mux4_PCA(a, b, b, c,
c, d,
d, select,
select, y_out);
y_out);
input
input a,
a, b,
b, c,
c, d;
d; input
input [1:0]
[1:0] select;
select;
output
output y_out;
y_out; regreg y_out;
y_out;

always
always @(select)
@(select) y_out changes with a;
begin
begin
ifif (select
(select ==
== 0)0) assign
assign y_out=a;
y_out=a;
else
else ifif (select
(select ==
== 1)
1) assign
assign y_out=b;
y_out=b;
else
else ifif (select
(select ==
== 2)
2) assign
assign y_out=c;
y_out=c;
else
else ifif (select
(select ==
== 3)
3) assign
assign y_out=d;
y_out=d;
else
else assign
assign y_out=1bx;
y_out=1bx;
end
end

endmodule
endmodule
 Alternative
module
module mux4_PCA(a,
mux4_PCA(a, b, b, c,
c, d,
d, select,
select, y_out);
y_out);
input
input a,
a, b,
b, c,
c, d;
d; input
input [1:0]
[1:0] select;
select;
output
output y_out;
y_out; regreg y_out;
y_out;

always
always @(select
@(select oror aa or
or bb or
or cc or
or d)
d)
begin
begin Value of a is assigned to
ifif (select
(select ==
== 0)0) y_out=a;
y_out=a; y_out at this time
else
else ifif (select
(select ==
== 1) 1) y_out=b;
y_out=b;
else
else ifif (select
(select ==
== 2) 2) y_out=c;
y_out=c;
else
else ifif (select
(select ==
== 3) 3) y_out=d;
y_out=d;
else
else y_out=1bx;
y_out=1bx;
end
end

endmodule
endmodule
 Blocking and Non-blocking Assignment

initial Blocking assignment =

begin Statement order matters
a = 1; A statement has to be executed
b = 0; before next statement
a = b; // a = 0;
b = a; // b = 0;
end
Non-blocking assignment <=
initial
begin Concurrent assignment
a = 1; If there are multiple non-
b = 0; blocking assignments to same
a <= b; // a = 0; variable in same behavior, latter
b <= a; // b = 1;
overwrites previous
end
 Delay Control Operator (#)
initial
initial
begin
begin
#0
#0 in1
in1==0;
0;in2
in2== 1;
1;
#10
#10 in3
in3== 1;
1;
#40
#40 in4
in4== 0;
0; in5
in5==1;
1;
#60
#60in3
in3==0;0;
end
end

#5
#5A=B
A=B A=#5
A=#5BB ??
??
 Event Control Operator (@)
Event -> identifier or expression
@@((eventA
eventAor
oreventB
eventB))begin
begin
When @ is reached
@@((eventC
eventC))begin
begin Activity flow is suspended
The event is monitored
end
end Other processes keep going
end
end
posedge: 0->1, 0->x, x->1
negedge: 1->0, 1->x, x->0
 The wait Construct
module
modulemodA
modA();
(); Activity flow is
suspended if expression
always
always is false
begin
begin
It resumes when the
wait
wait((enable
enable))ra
ra==rb;
rb; expression is true

end
end
endmodule
Other processes keep
endmodule
going
Intra-assignment Delay: Blocking Assignment

////BB==00at
attime
time00 If timing control operator(#,@)
////BB==11at
attime
time44 on LHS
Blocking delay
#5#5AA==B;B; ////AA==11
CC==D; RHS evaluated at (#,@)
D;
Assignment at (#,@)
AA==#5 #5B;
B; ////AA==00
CC==D; D;
If timing control operator(#,@)

AA==@(enable)
@(enable)B; B; on RHS
CC==D; D; Intra-assignment delay
RHS evaluated immediately
AA==@(named_event)
@(named_event)B; B;
C= Assignment at (#,@)
C=D;D;

 Indeterminate Assignment
module
modulemulti_assign();
multi_assign(); Multiple assignments
reg
rega,a,b,b,c,c,d;
initial
d; are made to same
initialbegin
begin
#5 variable in different
#5aa==1; 1;bb==0;
0;end
end
always
always@ @((posedge
posedgeaa))begin
begin
behaviors
cc==a;a;
end
end
always
Value depends on
always@ @((posedge
posedgeaa))begin
begin
cc==b;b; code order or vendor
end
end specifications
always
always@ @((posedge
posedgeaa))begin
begin
dd==b; b;
end
end
Similar to race-
always
always@ @((posedge
posedgeaa))begin
begin conditions in
dd==a; a; hardware
end
end
endmodule
endmodule
 Activity Flow Control ( if else )
ifif((AA==
==BB)) PP==d;
d; Syntax: if ( expression )
ifif((BB<<CC);); statement [ else statement ]
ifif((aa>=
>=bb))
begin
begin
Value of expression

end
end 0, x or z => false
Non-zero number => true
ifif((AA<<BB)) PP==d;
d;
else
elsePP==k;k;

ifif((AA>>BB)) PP==d;d;
else
elseifif((AA<<BB))PP==k;
k;
else
elsePP==Q; Q;
 Conditional Operator ( ? : )

always
always@@(( posedge
posedgeclock
clock ))
yout
yout== ((sel
sel)) ??aa++bb::aab;
b;

Conditional operator can be applied in

either continuous assignments

or behavioral descriptions
 The case Statement
module
modulemux4mux4((a,a,b,b,c,c,d,
d,select,
select,yout
yout);); Case items are examined in
input
input a,a,b,
b,c,c,d;
d; order
input
input[1:0]
[1:0] select;
select;
output
outputyout;
yout; Exact match between case
reg
regyout;
yout; expression and case item
always
always@( @(aaor orbbororccor
orddor
orselect
select))
begin
begin casez treats z as dont
case
case((select
select)) cares
0:
0:yout
yout==a; a;
1:
1:yout
yout==b; b; casex treats both x and
2:
2:yout
yout==c; c; z as dont cares
3:
3:yout
yout==d; d;
default
defaultyout
yout==1`bx;
1`bx;
endcase
endcase
endmodule
endmodule
 The repeat Loop

word_address
word_address==0;
0;
repeat
repeat((memory_size
memory_size))
begin
begin
memory
memory[word_address]
[word_address]==0;
0;
word_address
word_address==word_address
word_address++1;
1;
end
end

 The for Loop

reg
reg[15:0]
[15:0]regA;
regA;
integer
integerk;k;

for
for((kk==4;
4;k;
k;kk==kk11))
begin Loop variables have to be either
begin
integer or reg
regA
regA[[k+10
k+10]]==0;
0;
regA
regA[[k+2
k+2]]==1;
1;
end
end

 The while Loop

begin
begincnt1s
cnt1s Loop activities suspend external activities
reg
reg[7:0]
[7:0]tmp;
tmp;
cnt module
modulesthsth((externalSig
externalSig););
cnt==0;
0;
tmp input
inputexternalSig;
externalSig;
tmp==regA;
regA;
while
while((tmp
tmp))
begin always
always
begin
cnt begin
begin
cnt ==cnt
cnt++tmp[0];
tmp[0];
tmp while
while((externalSig
externalSig););
tmp==tmp
tmp>>>>1;
1;
end end
end
end
end endmodule
endmodule
end
 The disable Statement

begin
begin
kk==0; 0;
for
for((kk==0;0;kk<=
<=15;
15;kk==kk++11))
ifif((word[
word[kk]]==
==11))disable
disable;;
end
end

Terminate prematurely in a block of procedural statements

 The forever Loop
parameter
parameterhalf_cycle
half_cycle==50;
50;

initial
initial
begin
begin::clock_loop
clock_loop
clock
clock==0; 0;
forever
forever
begin
begin
#half_cycle
#half_cycleclock
clock==1;
1;
#half_cycle
#half_cycleclock
clock==0;
0;
end
end
end
end

initial
initial
#350
#350disable
disableclock_loop;
clock_loop;
 Task
module
modulebit_counter
bit_counter(data,
(data,count);
count);
input
input[7:0]
[7:0]data;
data;
output
output[3:0]
[3:0]count;
count;reg
reg[3:0]
[3:0]count;
count;

always
always@(data)
@(data)t(data,
t(data,count);
count);

task
taskt;
t;
input
input[7:0]
[7:0]a;a;output
output[3:0]
[3:0]c;
c;reg
reg[3:0]
[3:0]c;
c;
reg
reg[7:0]
[7:0]tmp;
tmp;
begin
begincc==0; 0;tmp
tmp==a;
a;
while
while(tmp)
(tmp)
begin
begin
cc==cc++tmp[0];
tmp[0];
tmp
tmp==tmptmp>>
>>1; 1;
end
end
end
end
endtask
endtask
endmodule
endmodule
 Function
module
moduleword_aligner
word_aligner(w_in,
(w_in,w_out);
w_out);
input
input[7:0]
[7:0]w_in;
w_in;
output
output[7:0]
[7:0]w_out;
w_out;

assign
assignw_out
w_out==align
align(w_in);
(w_in);

function
function[7:0][7:0]align;
align;
input
input[7:0]
[7:0]word;
word;
begin
begin
align
align==word;
word;
ifif(align
(align!=
!=0)
0)
while
while(align[7]
(align[7]==
==0)0)
align
align==align
align<<
<<1;
1;
end
end
endfunction
endfunction
endmodule
endmodule
 Switch Level NAND Gate
module
modulenand_2
nand_2((Y,Y,A,
A,BB);); Vdd
output
outputY;
Y;
input
inputA,
A,B;
B;
A B
supply0
supply0GND;
GND; Y
supply1
supply1PWR;
PWR;
wire
wirew;
w; A

pmos
pmos((Y,Y,PWR,
PWR,AA););
pmos
pmos((Y,Y,PWR,
PWR,BB);); B
nmos
nmos((Y,Y,w,
w,AA););
nmos
nmos((w,
w,GND,
GND,BB););
endmodule
endmodule
 Assign Drive Strengths
nand
nand((pull1,
pull1,strong0
strong0))G1(
G1(Y,
Y,A,
A,BB););
wire
wire((pull0,
pull0,weak1
weak1))A_wire
A_wire==net1
net1||||net2;
net2;
assign
assign((pull1,
pull1,weak0
weak0))A_net
A_net==reg_b;
reg_b;

Drive strength is specified through an unordered pair

one value from { supply0, strong0, pull0, weak0 , highz0 }
the other from { supply1, strong1, pull1, weak1, highz1 }

Only scalar nets may receive strength assignment

Latch Resulted from Unspecified Input State

module
modulemyMux(
myMux(y,y,selA,
selA,selB,
selB,a,a,bb););
b
input
inputselA,
selA,selB,
selB,a,
a,b;
b;
output selA
outputy;
y; en
reg
regy;
y; selB y

selA
always
always@ @((selA
selAororselB
selBor
oraaor
orbb)) latch
case selB
case(({selA,
{selA,selB}
selB}))
2b10: a
2b10:yy==a;
a;
2b01:
2b01:yy==b;
b;
endcase
endcase
endmodule
endmodule
 Synthesis of Loops
repeat, for, while, forever

Depends on
Venders
Timing control
Data dependencies

A loop is static or data-independent if the number of

iterations can by determined by the complier before
simulation
Static Loops without Internal Timing Controls >
Combinational Logic
module
modulecount1sA
count1sA((bit_cnt, bit_cnt,data,
data,clk,
clk,rst
rst););
parameter
parameterdata_width
data_width==4; 4; parameter
parametercnt_width
cnt_width==3;
3;
output
output[cnt_width-1:0]
[cnt_width-1:0]bit_cnt; bit_cnt;
input
input[data_width-1:0]
[data_width-1:0]data; data; input
inputclk,
clk,rst;
rst;
reg
reg[cnt_width-1:0]
[cnt_width-1:0]cnt, cnt,bit_cnt,
bit_cnt,i;i;reg
reg[data_width-1:0]
[data_width-1:0]
tmp;
tmp;
always
always@ @((posedge
posedgeclk clk))
ifif((rst
rst))begin
begincnt cnt==0;0;bit_cnt
bit_cnt==0; 0;end
end
else
elsebegin
begincnt cnt==0; 0;tmp
tmp==data;
data;
for
for((i i==0; 0;i i<<data_width;
data_width;i i==i i++11))
begin
begin
ifif((tmp[0]
tmp[0]))cnt cnt==cnt
cnt++1;1;
tmp
tmp==tmp tmp>>>>1;1;end
end
bit_cnt
bit_cnt==cnt; cnt;
end
end
endmodule
endmodule
 Static Loops with Internal Timing
Controls > Sequential Logic
module
modulecount1sB
count1sB((bit_cnt,
bit_cnt,data,
data,clk,
clk,rst
rst););
parameter
parameterdata_width
data_width==4; 4; parameter
parametercnt_width
cnt_width==3;
3;
output
output[cnt_width-1:0]
[cnt_width-1:0]bit_cnt;
bit_cnt;
input[data_width-1:0]
input[data_width-1:0]data; data; input
inputclk,
clk,rst;
rst;
reg
reg[cnt_width-1:0]
[cnt_width-1:0]cnt, cnt,bit_cnt,
bit_cnt,i;i;reg
reg[data_width-1:0]
[data_width-1:0]
tmp;
tmp;
always
always@ @((posedge
posedgeclk clk))
ifif((rst
rst))begin
begincnt
cnt==0;0;bit_cnt
bit_cnt==0; 0;end
end
else
elsebegin
begin
cnt
cnt==0; 0;tmp
tmp==data;
data;
for
for((ii==0;
0;ii<<data_width;
data_width;ii==ii++11))
@@((posedge
posedgeclk clk))
begin
beginifif((tmp[0]
tmp[0]))cntcnt==cnt
cnt++1; 1;
tmp
tmp==tmptmp>> >>1;1;end
end
bit_cnt
bit_cnt==cnt;
cnt;
end
end
endmodule
endmodule
Non-Static Loops without Internal Timing Controls >
Not Synthesizable
module
modulecount1sC
count1sC((bit_cnt,
bit_cnt,data,
data,clk,
clk,rst
rst););
parameter
parameterdata_width
data_width==4; 4; parameter
parametercnt_width
cnt_width==3;
3;
output
output[cnt_width-1:0]
[cnt_width-1:0]bit_cnt;
bit_cnt;
input
input[data_width-1:0]
[data_width-1:0]data; data; input
inputclk,
clk,rst;
rst;
reg
reg[cnt_width-1:0]
[cnt_width-1:0]cnt, cnt,bit_cnt,
bit_cnt,i;i;reg
reg[data_width-1:0]
[data_width-1:0]tmp;
tmp;
always
always@ @((posedge
posedgeclkclk))
ifif((rst
rst))begin
begincnt
cnt==0;0;bit_cnt
bit_cnt==0; 0;end
end
else
elsebegin
begin
cnt
cnt==0; 0;tmp
tmp==data;
data;
for
for((i i==0;
0;tmp;
tmp;i i==i i++11))
begin
beginifif((tmp[0]
tmp[0]))cntcnt==cnt
cnt++1; 1;
tmp
tmp==tmptmp>>>>1; 1;end
end
bit_cnt
bit_cnt==cnt;cnt;
end
end
endmodule
endmodule
 Non-Static Loops with Internal Timing
Controls > Sequential Logic
module
modulecount1sD
count1sD((bit_cnt,
bit_cnt,data,
data,clk,
clk,rst
rst););
parameter
parameterdata_width
data_width==4; 4; parameter
parametercnt_width
cnt_width==3;
3;
output
output[cnt_width-1:0]
[cnt_width-1:0]bit_cnt;
bit_cnt;
input
input[data_width-1:0]
[data_width-1:0]data; data; input
inputclk,
clk,rst;
rst;
reg
reg[cnt_width-1:0]
[cnt_width-1:0]cnt, cnt,bit_cnt,
bit_cnt,i;i;reg
reg[data_width-1:0]
[data_width-1:0]tmp;
tmp;
always
always@ @((posedge
posedgeclk clk))
ifif((rst
rst))begin
begincntcnt==0;0;bit_cnt
bit_cnt==0; 0;end
end
else
elsebegin:
begin:bit_counter
bit_counter
cnt
cnt==0; 0;tmp
tmp==data;
data;
while
while((tmptmp))
@@((posedge
posedgeclk clk))begin
begin
ifif((rst
rst))begin
begincnt
cnt==0;
0;disable
disablebit_counter;
bit_counter;end
end
else
elsebegin
begincnt
cnt==cnt
cnt++tmp[0];
tmp[0];tmp tmp==tmp
tmp>>
>>1;1;end
end
bit_cnt
bit_cnt==cnt;cnt;
end
end
end
end
endmodule
endmodule