Memory

Organization

This lecture was originally

prepared by betiglu; a great
friend and colleague. RIP
Memory Classification

Characteristics for classification of memory types:

Location: processor, internal (main), external (secondary
or auxiliary)

Capacity: word size, number of words

Unit transfer: word, block

Access mode: sequential, direct, random, associative

Performance: access time (latency), cycle time, transfer
rate

Physical type: semiconductor, magnetic, optical

Physical characteristics: volatile | non volatile, erasable |
non erasable

Memory Organization 2
Memory Hierarchy

A memory hierarchy can be visualized based on
three characteristics: capacity, access time and
cost.

Memory Organization 3
Memory Hierarchy
EXERCISE
Place the following memory elements according to their
proximity to CPU.
Main Memory
Magnetic disk

CPU
Registers

Cache Memory Magnetic tape

Cache memory: very high speed memory used for increasing

speed of a processor by holding most heavily used program and
data.

Auxiliary memory: mainly for backup storage (permanently) for
program and data that are not presently used by CPU.

Memory Organization 4
Main Memory

ROM: Permanent storage, needed for bootstrap loader
(initial program)

RAM: Temporary storage, random access

RAM Technology

Semiconductor

Two Types of RAM

Static RAM (SRAM)

Short read/write cycle

Faster

Cache

Dynamic RAM (DRAM)

Reduced power

Large Storage

Main Memory

Memory Organization 5
Memory Chip
CS1
CS1
CS2
8 CS2
128 X 8 8
RD 128 X 8
WR
Add
Add
7 7
ROM
RAM

CS1 CS2 RD WR Function Data bus State

0 0 X X Inhibit High-impedance
0 1 X X Inhibit High-impedance
1 0 0 0 Inhibit High-impedance
1 0 0 1 Write Input Data
1 0 1 X Read Output Data
1 1 X X Inhibit High-impedance

Memory Organization 6
Memory Address Map

Example

512 byte of RAM (4 - 128X8)

512 byte of ROM (1 - 512X8)

Address bus 12 bits
Address Bus
Hexadecimal Component
9 8 7 6 5 4 3 2 1 0
- - 0 0 0 X X X X X X X 000-07F RAM 0
- - 0 0 1 X X X X X X X 080-0FF RAM 1
- - 0 1 0 X X X X X X X 100-17F RAM 2
- - 0 1 1 X X X X X X X 180-1FF RAM 3
- - 1 X X X X X X X X X 200-37F ROM

Memory Connection to CPU

RD and WR for the RAM

RD for ROM

Memory Organization 7
Memory to CPU Connection

Memory Organization 8
Memory Organization 9
Designing Memory Unit
EXERCISE 1

Suppose that you have 256x8bit memory chips
as building blocks. Show your design to build the
following memory units.

1024x8bit memory CS1
CS2

256x16bit memory 8
256X 8

1024x16bit memory. RD
WR
Add
8
RAM

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EXERCISE 2

A system requires a 1kword memory where each
kword is 16bits. Out of these, the first 512words
are required to be on RAM and the rest on ROM.
But the only memory chips that you have in store
are 128x16bit RAM chips and 512x8bit ROM
chips. Show how you will integrate and connect
the chips to the CPU.

Memory Organization 11
Memory Organization 12
Cache Memory

Provides fast access with large size (as compared to
registers)

Locality of Reference: refers to a phenomenon that the
references to memory of a program being confined
within few localized areas in memory.

Why Locality of Reference

Loops

Subroutines

Table Lookups

Arrays

Active portions of the program and data are

stored in a small and fast memory called Cache
Memory.
Memory Organization 13
Cache Memory
CPU Cache Memory

OPERATION

The CPU looks for the item in the cache;

If the item is available there, it is fetched or written.

Otherwise the item is fetched from memory. The block
containing the item is also copied to cache.

Cache Performance: measured in hit ratio.

Hit means the required item is found in cache.
numberof hits
hit ratio =
numberof hits + numberof miss
Memory Organization 14
Cache Memory

Cache performance is affected by

Cache size

Speed of cache memory

Cache replacement algorithm

Random

FIFO (First In First Out)

LRU (Least Recently Used)

LFU (Least Frequently Used)

Mapping transformation of data from main memory
to cache.

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Cache Memory

Types of Mapping

Associative

Direct

Set-associative

Memory Organization 16

Associative Mapping

Argument register = 24bits

Associative mapping

Address = 24bits

Data = 32bits

Cache word length

24 + 32 = 56bits

Memory Organization 17

Direct Mapping

Single Word Transfer
Memory address

16MW 24bits

Cache address

64KW 16bits

Tag

24 - 16 = 8bits

Cache word length

8 + 32 = 40bits

Memory Organization 18

Direct Mapping
64words per block

Block Transfer

Tag

24 - 16 = 8bits

Index

Word

64words

6bits

Block

16-6 = 10bits

210 blocks

Memory Organization 19

Set-Associative Mapping
K=2

Tag

24 - 16 = 8bits

Data

32bits

Cache word length

2(8 + 32) = 80bits

K = 2 set of words

Memory Organization 20
Characteristics of Cache design

Cache design is characterized by:

Mapping Function

Replacement Algorithms

Write Policy

Writing Through

Update cache and memory simultaneously

Write Back

Update cache

Memory is updated when cache is flushed

Number of Caches

Memory Organization 21
Others Types of
Memory
Auxiliary Memory

Secondary Storage

I/O device

Magnetic Disks

Hard Disk

Floppy Disk

Magnetic Tapes

Plastic coated with
magnetic recording
material
Magnetic Disk Structure

Memory Organization 23
Magnetic Disk (HDD)

Data from disk to memory or from memory to disk are
translated in blocks.

To transfer a disk block, given its address the disk controller
first locates the sector containing the block.

The time taken from the moment an instruction of data reading
from disk is issued to the time the data appear in memory is
known as disk latency.

The major components of the latency of the disk are:

Seek Time: time taken for read/write head to locate the proper
track (cylinder). Typical range for seek time is 7 to 10 millisecond.

Rotational Latency (Delay): time taken to locate the sector
containing the first desired block. Typical rotational latency is 1
cycle per 10 milliseconds.

Transfer Time: time to transfer data to the memory

Memory Organization 24
Virtual Memory

Virtual memory is used to simulate large
memory space available by the use of the
auxiliary memory

Two spaces

Address Space

Set of addresses for the virtual address used by a
programmer

Memory Space

Set of physical address (location in main memory)

Memory Organization 25
 Virtual Memory

Program 1
Data 1,1
Program 1
Data 1,2

Data 1,1
Program 2
Data 2,1
Data 2,2
Memory Space
Address Space M=32K
N=1024K

20 bits of address is used

Requires Mapping of the virtual address into physical address

Memory Organization 26
Address Mapping using Pages

Random Access

The address space are grouped into pages.

The memory space are grouped into blocks.
Page 0
Page 1
Page 2

Block 0
Block 1
Page 6 Block 2
Page 7 Block 3
Address Space Memory Space
N=8K M=4K

Memory Organization 27
 Address Mapping using Pages

The virtual address represents

Page number (index in the address space)

Line Number (address within block)

Every Page has two field

Block number

Presence bit

If presence bit is 1

Block in the main memory

Block number from the page and line number from the virtual
address gives physical address

If presence bit is 0

Block not in memory, need to I/O transfer

Memory Organization 28
 Address Mapping using Pages

0 1 0 Line Number

0
I
n 1 1 1 Block 0
d 0 1 1 Block 1
e 0
Block 2
x 0 0 1 Line Number
Block 3
1 1 1
1 0 1
0
0 1 1

Memory Organization 29
Associative Memory
 Associative Memory or Content Addressable Memory (CAM)

A memory unit accessible by content of the data

Suitable for parallel search
Argument Register (AR)

Key Register (K)

Example
Input
Associative Memory A 101 111100
Array and logic M
Read K 111 000000
mXn
Write Word 1 100 111100 
Output Word 2 101 000011 

Match Logic:
(A Fij + A j Fij + K j );
n
Mi = j i = 1, 2 ,3 ... m
j =1

Memory Organization 30
Associative Memory Page Table

0 1 0 Line Number

1 1 1 0 0 Block 0
Block 1
0 0 1 1 1 Block 2
0 1 0 0 1 0 1 Line Number
Block 3
1 0 1 0 0
1 1 0 1 0

Memory Organization 31
Memory Management
Memory Management

Software

Operating System

The main memory is divided into two parts for

Operating System (resident memory)

Programs

Even distribution of I/O and Processor programs in main
memory

Swapping

Partitioning

Fixed Size

Variable Size  Compaction

Paging

Virtual Memory

Memory Organization 33
Memory Management Hardware

Basic Components of Memory Management
hardware

Dynamic Storage Allocation

Segmented Page Mapping

Sharing Common Programs

Used for multiprograming

Protection of Information

Prevent unauthorized access

Prevent unwanted interaction

Memory Organization 34
Segmented Page Mapping

Programs and data are divided into logical parts known
as Segments.

Segments are generated by the programmer or the OS

Subroutines (procedure), Array of data, User programs,

The address generated by the segments are referred to as
Logical Address.

The memory management hardware is then maps the
logical addresses into physical addresses.

Logical address is partitioned into:

Segment, Page, Word

Physical address is partitioned into:

Block, Word

Memory Organization 35
Logical to Physical address Mapping

Logical Address
Segment Page Word

Segment Table Page Table

Block Word
Physical Address

Memory Organization 36
Associative Memory Translation Look- Look-aside
Buffer (TLB)

Helps to minimize memory access for most
recently referenced table entries.
Argument Register

Segment Page Block

Memory Organization 37
Example

Logical vs. Physical Address

Memory Organization 38
 Example

Memory Address Assignment

Memory Organization 39
 Example

Segment and page table mapping

Memory Organization 40
 Example

Associative Memory Translation Look-aside Buffer (TLB)

Memory Organization 41
Memory Protection

The segment filed is partitioned into

Base Address

Length

Protection

Memory Organization 42
 Memory Protection

The protection information is set by the master
control program of the operating system

Full Control (Read and Write privileged)

Read Only (Write protection)

Execute Only (Program protection)

System Only (Operating System Protection)

Memory Organization 43