THY Ibd 8

3412 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
12, DECEMBER 2010
TABLE I as the ac ground and current return path shared by several signal
TSV G EOMETRICAL PARAMETERS BASED ON ITRS08 [33]
TSVs. In a simple situation, one VDD TSV, one GND TSV, and
one signal TSV with the inverters (driver and load) on different
substrates form a circuit network, as shown in Fig. 12. The
parallel admittance network and serial impedance network of
the 3-TSV system are illustrated and verified in Fig. 12(a)(d).
The parameters in the 3-TSV system can be obtained from the
TSV pairs. In particular, in the network of parallel admittance,
the capacitance C1 is still the same as that illustrated in Fig. 5(a)
and can be expressed as in (9); while the admittance Y2,VS ,
Y2,SG , and Y2,VG can be obtained from
1

1 1
Y2 (d = d0 ) = Y2,VS + Y2,SG + Y2,VG
1
1 1 (32)
below 100 GHz, while the difference decreases as the frequency
Y2 (d = 2d 0 ) = Y 2,VG + Y + Y
2,VS 2,SG
increases. Furthermore, as expected, the resistance of W TSV Y2,VS = Y2,SG
is the highest. The resistances of SWCNTs (all metallic) and
MWCNTs are the lowest at the lower and higher frequencies, where Y2 is a function of the center-to-center distance (d) of
respectively. The inductances of Cu, W, SWCNT, and MWCNT a TSV pair, given in (10). For the TSV pair of VDD signal or
TSVs are almost identical, since it is the outer inductance rather signalGND, d = d0 . For that of VDD GND, d = 2d0 . In the
than inner inductance that dominates. network of serial impedance

ZV = ZS = ZG = Z(d = d0 )/2
(33)
V. S CALING A NALYSIS OF TSVs jMVG = [Z(d = d0 ) Z(d = 2d0 )] /2
The International Technology Roadmap for Semiconductors where Z is a function of d of a TSV pair, given in (23);
(ITRS) [33] provides scaling predictions for TSV geometries and jMVG is the mutual impedance (for a low-conductivity
(Table I). As technology scales, both the radius and pitch of substrate, as discussed in this paper, the real part of jMVG
TSVs reduce, while the substrate thickness (determining the can be ignored). Incorporating these networks into the inverter-
TSV height) remains same. based driverreceiver circuit [Fig. 12(e)], the performance
From Table I and the analytical models presented (delay, rise/fall time, etc.) can be analyzed.
earlier, the RLCG of a TSV pair (per unit TSV height) is The performance of Cu-, W-, SWCNT-bundle, and MWCNT-
computed, and the results are shown in Fig. 11. As technology bundle-based TSVs at 22-nm technology node is compared for
scales, C, G, and L do not change very much because the different driver sizes (Fig. 13). As the inverter size increases, the
geometrical parameters scale nearly proportionally; R increases delay and rise times of the signal voltage decrease, as expected.
a lot at 1 GHz, as well as at 100 GHz. This is due to the On the other hand, the delay does not quite depend on the TSV
decreasing area and perimeter of the TSV cross section. From material, although there is a significant difference in resistance
the resistance perspective, MWCNT is worse than Cu at 1 GHz and some difference in inductance among those materials. This
[Fig. 11(c)]. Although MWCNTs have advantages over Cu at result is different from long-horizontal-wire analysis, where
higher frequencies, the benefits diminish as technology scales metal resistance dramatically affects the performance since it
[Fig. 11(d)]. This is not in conflict with Fig. 10(a), because the is mostly RC dominated.
geometrical dimension of the TSVs in Fig. 11 is much smaller: By changing the values of either C, G, R, or L, the sensitivity
a smaller radius results in a lower skin effect in Cu, while a to the RLCG parameters of the circuit performance can be
shorter height implies a higher effective resistivity of MWCNT obtained [Fig. 14(a) and (b)]. The figure indicates that the
due to the quantum contact resistance [34]. Furthermore, the capacitance is the most important parameter, because a 5% error
total inductance of MWCNT becomes apparently greater than in capacitance leads to up to 2.4% error in the delay and 2.6%
that of other materials, because a smaller cross-sectional area error in the rise time of the signal voltage. On the other hand,
indicates a greater ratio of kinetic inductance to total inductance for any reasonable inverter sizes (below 300 times the minimum
[21], [22]. On the other hand, the SWCNT bundle (all metallic) size), the resistance is the least important parameter, because a
maintains its advantage over Cu, since their electrical MFP is 20% error in resistance only leads to up to 0.17% error in the
much smaller than the TSV height. delay and 0.35% error in the rise time of the signal voltage.
The importance of conductance and inductance is somewhere
in between. This is a clear indication of the short-transmission-
VI. E LECTRICAL P ERFORMANCE OF TSVs
line behavior of the signal propagation. In other words, for the
The 3-D ICs require both power/ground and signal TSVs typical TSV sizes, the attenuation would not be a big concern
to communicate with the components on different substrates. (G is not as important as C, while R is not as important as
The power/ground TSVs and horizontal wires are usually pe- L). On the other hand, at least for digital applications with
riodically placed, forming the power/ground grid [35]. For reasonable driver sizes, our compact RLCG model is sufficient
performance analysis, each power/ground TSV can be treated for performance analysis, since it has good accuracy for CG

THY Ibd 8

Uploaded by

Copyright:

Available Formats

THY Ibd 8

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

THY Ibd 8

Uploaded by

Copyright:

Available Formats

3412 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.

12, DECEMBER 2010

You might also like