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    Design of AES Encryption and Decryption Algorithm With 128-Bits Key Length

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    saikumar
    The document describes the design of an AES encryption and decryption algorithm with a 128-bit key length. It discusses AES, a symmetric block cipher used to encrypt plaintext into ciphertext. The algorithm operates on blocks of 128 bits using cipher functions including substitution, shifting, mixing and adding a round key for encryption. For decryption, inverse cipher functions are applied. The AES encryption and decryption modules are designed using VHDL and synthesized on an FPGA, operating at a maximum frequency of 18.970 MHz.

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    Design of AES Encryption and Decryption Algorithm With 128-Bits Key Length

    Uploaded by

    saikumar
    37 views7 pages
    The document describes the design of an AES encryption and decryption algorithm with a 128-bit key length. It discusses AES, a symmetric block cipher used to encrypt plaintext into ciphertext. The algorithm operates on blocks of 128 bits using cipher functions including substitution, shifting, mixing and adding a round key for encryption. For decryption, inverse cipher functions are applied. The AES encryption and decryption modules are designed using VHDL and synthesized on an FPGA, operating at a maximum frequency of 18.970 MHz.

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    The document describes the design of an AES encryption and decryption algorithm with a 128-bit key length. It discusses AES, a symmetric block cipher used to encrypt plaintext into ciphertext. The algorithm operates on blocks of 128 bits using cipher functions including substitution, shifting, mixing and adding a round key for encryption. For decryption, inverse cipher functions are applied. The AES encryption and decryption modules are designed using VHDL and synthesized on an FPGA, operating at a maximum frequency of 18.970 MHz.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    37 views7 pages

    Design of AES Encryption and Decryption Algorithm With 128-Bits Key Length

    Uploaded by

    saikumar
    The document describes the design of an AES encryption and decryption algorithm with a 128-bit key length. It discusses AES, a symmetric block cipher used to encrypt plaintext into ciphertext. The algorithm operates on blocks of 128 bits using cipher functions including substitution, shifting, mixing and adding a round key for encryption. For decryption, inverse cipher functions are applied. The AES encryption and decryption modules are designed using VHDL and synthesized on an FPGA, operating at a maximum frequency of 18.970 MHz.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 7

    Design of AES Encryption and Decryption Algorithm with 128-bits Key Length

    ABSTRACT
    In todays world most of the communication is done using electronic media. Data
    Security plays a vital role in such communication. Hence, there is a need to protect data from
    malicious attacks. Cryptography is the science of secret codes, enabling the confidentiality of
    communication through an insecure channel. It protects against unauthorized parties by
    preventing unauthorized alteration of use. Generally speaking, it uses a cryptographic system to
    transform a plaintext into a cipher text, using most of the time a key.

    Advanced Encryption Standard (AES), also known as Rijndael, is an encryption standard


    used for securing information. AES was published by NIST (National Institute of Standards and
    Technology). AES is a block cipher algorithm that has been analyzed extensively and is now
    used widely. AES is a symmetric block cipher that is intended to replace DES as the approved
    standard for a wide range of applications. The block cipher Rijnddael was designed by Dr. Joan
    Daemen and Dr. Vincent Rijmen and the name of the algorithm is a combination of the names of
    its two creators. Rijndael is very secure and has no known weakness. Rijndael is conventional
    (symmetric key) system and is relatively simple cipher in many respects. It takes an input block
    of a certain size, usually 128, and produces a corresponding output block of the same size. The
    transformation requires a second input, which is the secret key. It is important to know that the
    secret key.

    In this work, both encryption and decryption will be carried out with the key length of
    128 bits, that is, both AES encrypter and the AES decrypter were integrated. Hence the input
    block and secret key will be provided for encryption and the cipher block and same secret key
    will be provided to the decryption to get the proper block as output. All the transformations of
    both Encryption and Decryption will be developed using VHDL language and will be verified
    with the help of its simulation result.

    The AES Encryption and Decryption is synthesized on FPGA family of Virtex-2 using
    Xilinx ISE tool and hence the design operates at a maximum clock frequency of 18.970 MHz
    with a minimum period of 52.716ns.

    Department of ECE,VJIT
    Design of AES Encryption and Decryption Algorithm with 128-bits Key Length

    INDEX
    CONTENTS PAGE NUMBER

    ABSTRACT

    ACKNOWLEDGEMENT

    LIST OF FIGURES

    Chapter 1: INTRODUCTION

    1.1.1 WHAT IS CRYPTOGRAPHY 1

    1.1.2 HOW DOES CRYPTOGRAPHY WORK 3

    1.1.3 THE PURPOSE OF CRYPTOGRAPHY 3

    1.2 METHODS OF ENCRYPTION 4

    1.2.1 SYMMETRIC CRYPTOGRAPHY 5

    1.2.2 ASYMMETRIC CRYPTOGRAPHY 8

    1.3 TYPES OF CRYPTOGRAPHIC ALGORITHMS 11

    1.4 INTRODUCTION TO AES 12

    1.4.1 BLOCK CIPHER 13

    1.5 APPLICATION 14

    CHAPTER 2 : LITERATURE

    Department of ECE,VJIT
    Design of AES Encryption and Decryption Algorithm with 128-bits Key Length

    2.1 INTRODUCTION TO AES 15


    2.2 TERMINOLOGIES 15
    2.3 ALGORITHM PARAMETERS 16
    2.4 AES ALGORITHM 17
    2.4.1 SPECIFICATION 17
    2.4.2 DESCRIPTION 18
    2.5 ENCRYPTION
    2.5.1 AES CIPHER FUNCTIONS 20
    2.5.1.1 AddRoundKey Transformation 21
    2.5.1.2 SubBytes Transformation 22
    2.5.1.3 ShiftRows Transformation 23
    2.5.1.4 MixColumns Transformation 24
    2.5.2 KEY EXPANSION 26
    2.6 DECRYPTION
    2.6.1 AES INVERSE CIPHER FUNCTIONS 29
    2.6.1.1 Inverse of the AddRoundKey Transformation 30
    2.6.1.2 InvSubBytes Transformation 30
    2.6.1.3 InvShiftRows Transformation 30
    2.6.1.4 InvMixColumns Transformation 31
    INTRODUCTION TO FPGA 32
    CHAPTER 3 : SOFTWARE ANALYSIS
    3.1 AES 34
    3.2 IMPLEMENTATION REQUIREMENTS 34
    3.3 NOTATION AND CONVENTIONS 35
    3.4 MATHEMATICAL PRELIMINARIES 37

    Department of ECE,VJIT
    Design of AES Encryption and Decryption Algorithm with 128-bits Key Length

    3.5 GENERAL IMPLEMENTATION FLOW 38


    3.6 IMPLEMENTATION 39
    CHAPTER 4 : RESULT
    4.1 SIMULATION RESULTS 43
    4.2 SYNTHESIS RESULT OF FPGA 53
    CONCLUSION AND FUTURE SCOPE 56
    BIBILOGRAPHY 57
    APPENDIX CODE 58

    Department of ECE,VJIT
    Design of AES Encryption and Decryption Algorithm with 128-bits Key Length

    LIST OF FIGURES
    FIGURE NUMBER PAGE NUMBER

    1.1 Encryption and decryption 1


    1.2 Using symmetric algorithms, the sender and receiver use 6
    the same key for encryption and decryption functions.

    1.3 Asymmetric cryptosystem 8

    1.4 Type of security service that will be provided. 10

    1.5 Three types of cryptographic algorithms 12

    1.6 Overall Representations of Encryption and Decryption 12

    2.1 Top Level Block Diagram of AES Algorithm 18


    2.2 Block Diagram for AES Round and AES Last Round 21
    2.6 AddRoundKey Operation 22
    2.3 SubBytes Operation of the State 23
    2.4 ShiftRows Operation of the State 24
    2.5 MixColumns operates on the State column-by-column 26
    2.7 InvShiftRows Operation of the State 31

    Department of ECE,VJIT
    Design of AES Encryption and Decryption Algorithm with 128-bits Key Length

    3.1 State Array Input and Output 36


    3.2 General Implementation Flow Diagram 38
    4.1.1 Simulation Result of AES Encryption and Decryption for Set-1 Inputs 44
    4.1.2 Simulation Result of AES Encryption and Decryption for Set-2 Inputs 45
    4.1.3 Simulation Result of Encryption with Internal Operation for Set-1 Inputs 46
    4.1.4 Simulation Result of Decryption with Internal Operation for Set-1 Inputs 48
    4.1.5 Simulation Result of Encryption with Internal Operation for Set-2 Inputs 49
    4.1.6 Simulation Result of Decryption with Internal Operation for Set-2 Inputs 49
    4.1.7Simulation Result of Encryption for Set-1 Inputs 50
    4.1.8 Simulation Result of Decryption for Set-1 Inputs 51
    4.1.9 Simulation Result of Encryption for Set-2 Inputs 52
    4.1.10Simulation Result of Decryption for Set-2 Inputs 52
    4.11 RTL Schematic 53

    Department of ECE,VJIT
    Design of AES Encryption and Decryption Algorithm with 128-bits Key Length

    Department of ECE,VJIT

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