Quanta Ze7 r1b Schematics

1 2 3 4 5 6 7 8
ZE7 Block Diagram (Intel Cedar Trail-M Platform) 01
CLK Gen.
DDI0
Cedarview-M SLG8LV631V P2
HDMI 1.3a 400 / 640MHz
HDMI CONN
A P17 DC(3.5W) & DC(6.5W) A
(32nm)
DDR III,800/1066 MT/s UNBUFFERED
DDI1 Micro-FCBGA8 DDRIII SODIMM
1366x768 (22x22mm) Channel A RC-B/F
CLK2/3, H=4 P4
LVDS 18bit,SC
LVDS/eDP CONN 0ohm 1366x768
P18
DAC
1920x1200
VGA CONN P5~9
P18
B
x2 DMI Gen1 B
PCIE Gen1
0
RTL8105TA-VC-CG
P22 Tigerpoint (NM10)
3 5 1.5W
Mini card2
P25 vFBGA
(360 balls,17x17mm)
RJ45 CONN HD AUDIO I/F Audio CODEC MIC In Jack
P22 1 Mini card1 7 Realtek 271X P20 Analog MIC
2 P25
Speaker Header (2W) P20
RTS5209-GR
MM-SIM CARD 4
CARDREADER
P25
P26
USB interface 6
5 IN1 CARDREADER module
P19 0 SATA II I/F Mobile 2.5" HDD
C C
SD3.0, MS, MS PRO, P24
xD, MMC P26
3
USB PORT
0 1 2
Left P21 USB 2.0
P10~15
USB PORT USB PORT CCD

Right Down P21 Right Up P18
P21
EC Nuvoton NPCE791L
P27
D
BATTERY CHAGER Discharge/+1.8V/
DDR 1.5VSUS Keyboard Touch Pad SPI Flash Charger PWM FAN D
P29 P32 +3.3V_PRIME P34

P19 P19 P27 P29 P6
Thermal Protection
SYSTEM
P30
+1.05V P35
5V/3V PCU P33
CPU Core Quanta Computer Inc.

Gfx Core PROJECT : ZE7
P31 Size Document Number Rev
Block Diagram 1B
Date: Wednesday, November 02, 2011 Sheet 1 of 40

1 2 3 4 5 6 7 8
5 4 3 2 1
CLK GEN (CLK) 02

+3V VDD_CLK_3.3V VDD_CLK_1.5V +1.5V
R219 1 2 2.2/J_6 L27

PBY160808T-301Y-N/2A/300ohm_6
L32
C225 C277 C224 <20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress
PBY160808T-301Y-N/2A/300ohm_6
D D
.1U/10V_4 .1U/10V_4 10U/10V_8
C285 C278 C254 C242
Place close to L32 Place close to L27
10U/10V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4
0.1uF near every power pin
U12
0.1uF near every power pin
5 VDD_REF_3.3 VDD_CORE_1.5 23
9 VDD_PCI_3.3 VDD_CORE_1.5 45
<20100803_Sam> Reserve 0ohm to connect to CK505, 10Kohm pull up is required.
VDD_IO can be ranging from 1.05V to 3.3V. 14 VDD_48M_3.3
36 PM_STPPCI#_R R251 *0/J_4
+1.05V PCI_STOP# PM_STPPCI# [13]
30 42 PM_STPCPU#_R R229 *0/J_4 PM_STPCPU# [13] From SB
VDD_SRC_IO_1.05 CPU_STOP#
VDD_CLKIO_1.05V 35 53
VDD_SRC_IO_1.05 CPU_0 CLK_MCH_BCLK [6]
CPU_0# 52 CLK_MCH_BCLK# [6] To CPU (Host CLK) 100 MHz
L28 48
PBY160808T-301Y-N/2A/300ohm_6 VDD_CPU_IO_1.05
R221 *0/short_6 CPU_1 50 CLK_DDR3_REFCLK [8]
CPU_1# 49 CLK_DDR3_REFCLK# [8] To CPU (DDR3 IO CLK) 100 MHz
1
Place close to L28 C228 C229 C249 C253 2
NC
44
NC SRC_1/CPU_ITP CLK_PCIE_LANP [22]
C 13 NC SRC_1/CPU_ITP# 43 CLK_PCIE_LANN [22] To LAN (LAN) 100 MHz C
10U/10V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 54 NC
SRC_2 41 CLK_PCIE_MNC_P [25]

CG_XOUT 3 40 To Mini Card 2 (3G/Wimax) 100 MHz <20101109> Place R235/ R241/ R248/ R254 close to U13
XTAL_OUT SRC_2# CLK_PCIE_MNC_N [25]
CG_XIN 4
C238 XTAL_IN
0.1uF near every power pin SRC_3 38 CLK_PCIE_MPC_P [25]
33P/50V_4 CG_XIN 37 To Mini Card 1 (WLAN) 100 MHz
SRC_3# CLK_PCIE_MPC_N [25]
SMBDT1 7 SDA
2
Y2 14.318MHZ [4,13,25] SMBDT1 SMBCK1 8 SCL SRC_4 34 CLK_PCIE_DMIP [5]

[4,13,25] SMBCK1
Load Capacitance=20p SRC_4# 33 CLK_PCIE_DMIN [5] To CPU (DMI CLK) 100 MHz
C236 FSB 15 32 CLK_PCIE_MMC_P [26]
1
33P/50V_4 CG_XOUT USB48_1/FSB SRC_5

SRC_5# 31 CLK_PCIE_MMC_N [26] To Card Reader (MMC) 100 MHz
R312 33/J_4 USB_48M 17
[10] CLKUSB_48 USB48_2
SRC_6 28 CLK_PCIE_ICH [10]
SRC_6# 27 CLK_PCIE_ICH# [10] To SB (DMI CLK) 100 MHz
<Layout note> R293 33/J_4 FSC 6
[13] 14M_ICH REF/FSC
18 DREFCLK_R R299 *0/J_4
Crystal place within 500mil of CK505 DOT96/SRC7 DREFCLK#_R R300 *0/J_4
DREFCLK [5]
DOT96#/SRC7# 19 DREFCLK# [5] To CPU (PLL CLK) 96 MHz
R296 22/J_4 ITP_EN 10
[12] PCLK_ICH PCIF/ITP_EN
R304 22/J_4 20 <20110110> DPL_REFSSCCLK is used to drive internal
+3V [27] LCLK_EC LCD_CLK DREFSSCLK [5]
R291 33/J_4 33M_SEL 11 21 To CPU (DPLSS CLK) 100 MHz registers and logics of the display interface and therefore
[25] PCLK_DEBUG 25MHz/PCI_2/SEL_33MHz LCD_CLK# DREFSSCLK# [5]
26
needs to be present at all times.
SATA CLK_PCIE_SATA [11]
12 VSS_PCI SATA# 25 CLK_PCIE_SATA# [11] To SB (SATA CLK) 100 MHz
R311 16
*20K/J_4 22
VSS_48M <20100819> Add 475ohm resistors to prevent current leakage
B VSS_LCD CLKREQ_LAN#_R R204 475/F_4 Control SRC_1 Register B5b6 for CLKREQ_A#
B
24 VSS_SATA CLKREQ_A# 47 CLKREQ_LAN# [22]
39 46 CLKREQ_MPC#_R R199 475/F_4 0 = SRC1, 1=SRC2
VSS_SRC CLKREQ_B# CLKREQ_MPC# [25]
51 29 CLKREQ_MMC#_R R284 475/F_4 Control SRC_3 Register B5b4 for CLKREQ_B#
VSS_CPU CLKREQ_C# CLKREQ_MMC# [26]
56 0 = SRC3, 1=SRC4
VSS_REF HWPG Control SRC_5 Register B5b3 for CLKREQ_C#
CKPWRGD/PD# 55 HWPG [13,16,27]
R310 57 0 = SRC5, 1=SRC6
Thermal Pad
*100K_4 <20110110> CFG input hardware strapping to allocate PLL assignment. C357
SLG8LV631V *0.1U/10V_4
<20110221> Reserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes
LOW = Both CPU and SRC clock drive from PLL3 will change to 25MHz after flash BIOS and restart in first time issue.
HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3.
Contains 100k pull-down resistor.
+3V
FSC FSB Frequency <EMI>
0 0 133MHz PM_STPPCI#_R R250 10K/J_4
0 1 166MHz USB_48M C280 *10P/50V_4
R313 *10K/J_4
1 1 200MHz PM_STPCPU#_R R230 10K/J_4
+3V
1 = Pin 43/44 as CPU_ITP 1 0 100MHz <20100720_Sam> Keep 100MHz as default. ITP_EN C259 *10P/50V_4
A R306 10K/J_4 ITP_EN 0 = Pin 43/44 as SRC_1 A
CLKREQ_MPC#_R R213 10K/J_4
FSB C279 *10P/50V_4
R301 10K/J_4 R289 10K/J_4 R317 *10K/J_4 CLKREQ_MMC#_R R279 10K/J_4

+3V +3V +3V
FSC C245 *10P/50V_4
R295 *10K/J_4 33M_SEL 1 = Pin 11 as 33MHz FSC FSB Quanta Computer Inc.
0= Pin 11 as 25MHz R259 *10K/J_4 R318 10K/J_4 CLKREQ_LAN#_R R212 10K/J_4
33M_SEL C266 *10P/50V_4
PROJECT : ZE7
Size Document Number Rev
1B
CLOCK GENERATOR
5 4 3 2 1
5 4 3 2 1
03
D D
C C
B B
A A
Quanta Computer Inc.

PROJECT : ZE7
1B
Reserved
5 4 3 2 1
5 4 3 2 1
DDR_STD(DDR) DIMM0 H=4mm 04

+1.5VSUS
2.48A JDIM1B
JDIM1A M_A_DQ[63:0] [8]
[8] M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ0 76 48
M_A_A1 A0 DQ0 M_A_DQ1 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ4 88 60
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
D
86 A7 DQ7 18 99 VDD9 VSS24 66 D
Populate rules: populate M_A_A8 89 21 M_A_DQ8 100 71
SODIMM1 first M_A_A9 A8 DQ8 M_A_DQ9 VDD10 VSS25
85 A9 DQ9 23 105 VDD11 VSS26 72
Strictly follow the mapping M_A_A10 107 33 M_A_DQ10 106 127
PC2100 DDR3 SDRAM SO-DIMM

M_A_A11 A10/AP DQ10 M_A_DQ11 VDD12 VSS27
between clock/control signal 84 35 111 128
groups and SODIMMs, as 83 22 112 133
M_A_A13 A12/BC# DQ12 M_A_DQ13 +3V VDD14 VSS29
well as SMB address. Other 119 24 117 134
configurations/mappings will 80 A14 DQ14 34 118 VDD16 VSS31 138
not M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ16 VDD17 VSS32
PC2100 DDR3 SDRAM SO-DIMM

be supported by MRC DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ17 C179 C178 145
[8] M_A_BS0 BA0 DQ17 VSS34
108 51 M_A_DQ18 199 150
[8] M_A_BS1 BA1 DQ18 VDDSPD VSS35
79 53 M_A_DQ19 .1U/10V_4 .1U/10V_4 151
[8] M_A_BS2 BA2 DQ19 VSS36
114 40 M_A_DQ20 77 155
[8] M_CS#2 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
[8] M_CS#3 S1# DQ21 NC2 VSS38
M_A_DQ22
+3V DESIGN NOTE: [8] M_CLK2 101 CK0 DQ22 50 125 NCTEST VSS39 161
103 52 M_A_DQ23 162
[8] M_CLK2# CK0# DQ23 VSS40
ADDRESS-(A2)H [8] M_CLK3 102 57 M_A_DQ24 198 167
CK1 DQ24 M_A_DQ25 EVENT# VSS41
[8] M_CLK3# 104 CK1# DQ25 59 [8] DDR3_DRAMRST# 30 RESET# VSS42 168
73 67 M_A_DQ26 172
[8] M_CKE2 CKE0 DQ26 VSS43
R150 74 69 M_A_DQ27 173
[8] M_CKE3 CKE1 DQ27 VSS44
10K/J_4 115 56 M_A_DQ28 +SMDDR_VREF_DQ0 1 178
[8] M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF_DIMM 126 179
[8] M_A_RAS# RAS# DQ29 VREF_CA VSS46
113 68 M_A_DQ30 184
[8] M_A_WE# W E# DQ30 VSS47
DIMM1_SA0 197 70 M_A_DQ31 185
DIMM1_SA1 SA0 DQ31 M_A_DQ32 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
SMBCK1 202 131 M_A_DQ33 3 190
[2,13,25] SMBCK1 SCL DQ33 VSS2 VSS50
SMBDT1 200 141 M_A_DQ34 8 195
(204P)
[2,13,25] SMBDT1 SDA DQ34 VSS3 VSS51
143 M_A_DQ35 9 196
R151 R170 DQ35 M_A_DQ36 VSS4 VSS52
[8] M_ODT2 116 ODT0 DQ36 130 13 VSS5
C *10K/J_4 10K/J_4 120 132 M_A_DQ37 14 C
[8] M_ODT3 ODT1 DQ37 VSS6
[8] M_A_DM[7:0] 140 M_A_DQ38 19
M_A_DM0 DQ38 M_A_DQ39 VSS7 +0.75V_DDR_VTT
11 DM0 DQ39 142 20 VSS8
M_A_DM1 28 147 M_A_DQ40 25
M_A_DM2 DM1 DQ40 M_A_DQ41 VSS9
46 149 26 203
(204P)
M_A_DM3 DM2 DQ41 M_A_DQ42 VSS10 VTT1
63 DM3 DQ42 157 31 VSS11 VTT2 204
M_A_DM4 136 159 M_A_DQ43 32
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ45 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ47
[8] M_A_DQS[7:0] DQ47
M_A_DQS0 12 163 M_A_DQ48
M_A_DQS1 DQS0 DQ48 M_A_DQ49 DDR3-DIMM0_H=4_STD
29 DQS1 DQ49 165
M_A_DQS2 47 175 M_A_DQ50
M_A_DQS3 DQS2 DQ50 M_A_DQ51
64 DQS3 DQ51 177
M_A_DQS4 137 164 M_A_DQ52
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54
[8] M_A_DQS#[7:0] 188 DQS7 DQ55 176
M_A_DQS#0 10 181 M_A_DQ56 <Layout note>
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183 PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON
M_A_DQS#2 45 191 M_A_DQ58 DDR_VREF_CA
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
M_A_DQS#6 169 192 M_A_DQ62 +1.5VSUS R198 *0/J_4 +SMDDR_VREF +SMDDR_VREF
186 DQS#7 DQ63 194
R191 1K/F_4 +SMDDR_VREF_DIMM_R +SMDDR_VREF_DIMM

DDR3-DIMM0_H=4_STD R205 0/J_4
B B
C194 C205
R208
.1U/10V_4 1K/F_4 0.1U/50V_6
<Layout note>
PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_DQ
<20100827> Add by DG request
Place these Caps near DIMM0 +1.5VSUS R149 *0/J_4 +SMDDR_VREF +SMDDR_VREF
+0.75V_DDR_VTT
R148 1K/F_4 +SMDDR_VREF_DQ0_R +SMDDR_VREF_DQ0

R146 0/J_4
C172 C200 C190 C185 C176
+1.5VSUS C160 C166
10U/6.3V_6 *10U/6.3V_6 *10U/6.3V_6 1U/6.3V_4 1U/6.3V_4 R147
.1U/10V_4 1K/F_4 0.1U/50V_6
C171 C169 C193 C163 C168 C198 C199 C197 C196 + C203
.1U/10V_4 .1U/10V_4 .1U/10V_4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 *330U/2V_7343
LAYOUT NOTE: PLACE CAPS
A NEAR DIMM-0 A
+0.75V_DDR_VTT
+1.5VSUS
+SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM
C175 C184
C191 C162 C173 C164 C165 C161 C192 C189
C170 C167 C216 C214 1U/6.3V_4 1U/6.3V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
.1U/10V_4 2.2U/6.3V_6 .1U/10V_4 2.2U/6.3V_6 PROJECT : ZE7
1B
DDRIII SO-DIMM-0
5 4 3 2 1
5 4 3 2 1
Cedar View (CPU) R397 *1K/J_4 +3V

05
U24C R398 *1K/J_4
CEDARVIEW
D14 CRT_HSYNC [18]
REV = 1.10 CRT_HSYNC
CRT_VSYNC C14 CRT_VSYNC [18]
HDMI: 7.5", 4 via, 1.65 Gbps [17] DDI0_HDMI_SCL H25

DDI0_DDC_SCL
[17] DDI0_HDMI_SDA J22 B12 CRT_R [18]
Level Shifter For HDMI DDI0_DDC_SDA CRT_RED
B11 CRT_G [18]
VGA
T33 DDI0_AUXP CRT_GREEN
C8 C11 CRT_B [18]
T31 DDI0_AUXN DDI0_AUXP CRT_BLUE
B8
DDI0_AUXN
D12 LAYOUT NOTE: PLACE THESE 3 RESISTORS
DDI
HDMI_DDI0_HPD# CRT_IRTN CRT_IREF R408 681/F_6 R414 R413 R415
[17] HDMI_DDI0_HPD# H22 DDI0_HPD CRT_IREF A13 CLOSE TO PIN
150/F_4 150/F_4 150/F_4
D TX2_HDMI+ C66 .1U/10V_4 DDI0_TX2_DP D
[17] TX2_HDMI+ G2 E29 CRT_DDC_SDA [18]
TX2_HDMI- C67 .1U/10V_4 DDI0_TX2_DN DDI0_TXP0 CRT_DDC_DATA
[17] TX2_HDMI- G3 DDI0_TXN0 CRT_DDC_CLK E27 CRT_DDC_SCL [18]
TX1_HDMI+ C61 .1U/10V_4 DDI0_TX1_DP F3 <20110110> DPL_REFSSCCLK is used to drive internal
[17] TX1_HDMI+ DDI0_TXP1
TX1_HDMI- C68 .1U/10V_4 DDI0_TX1_DN F2 F17
[17] TX1_HDMI-
TX0_HDMI+ C43 .1U/10V_4 DDI0_TX0_DP DDI0_TXN1 DPL_REFSSCCLKP DREFSSCLK [2] registers and logics of the display interface and therefore
[17] TX0_HDMI+ D4 E17 DREFSSCLK# [2]
TX0_HDMI- C44 .1U/10V_4 DDI0_TX0_DN C3
DDI0_TXP2 DPL_REFSSCCLKN needs to be present at all times.
[17] TX0_HDMI- DDI0_TXN2
TX3_HDMI+ C41 .1U/10V_4 DDI0_TX3_DP B7 B9 DREFCLK_R1 R406 *0/J_4
[17] TX3_HDMI+ DDI0_TXP3 DPL_REFCLKP DREFCLK [2]
TX3_HDMI- C42 .1U/10V_4 DDI0_TX3_DN A7 A9 DREFCLK#_R1 R405 *0/J_4
[17] TX3_HDMI- DDI0_TXN3 DPL_REFCLKN DREFCLK# [2]
T3 H_RSVD_TP_H15 H15 R52 *2.2K/J_4 +3V <20100818_Jerry> If you implement XDP, you need the PU 2.2K
T9 H_RSVD_TP_J15 RSVD_TP_H15 R48 *2.2K/J_4
J15 RSVD_TP_J15
F28 T51
R68 *2.2K/J_4 DDI1_DDC_SCL LVDS_CTRL_CLK
eDP: 7", 3 via, 2.7Gbps +3V
R62 *[email protected]/J_4 DDI1_DDC_SDA
F25
DDI1_DDC_SCL LVDS_CTRL_DATA
E24 T52
G27
DDI1_DDC_SDA
G24 LCD_CLK [18]
DDI1_AUX_DP LVDS_DDC_CLK
[18] DDI1_AUX_DP D10 H24 LCD_DATA [18]
DDI1_AUX_DN DDI1_AUXP LVDS_DDC_DATA
[18] DDI1_AUX_DN C10 DDI1_AUXN <20110610> Remove PU resistor for Intel update.
LVDS_IBG E10 LIBG 2.37K/F_4 R61 <20110630> Stuff R38/ R39 PU resistor. Intel will fixed EDID issue by VGA driver and vbios
[18] DDI1_HPD# DDI1_HPD# D26 F10
DDI1_HPD LVDS_VBG
LVDS
DDI1_TX0_DP E11 H2 R426 *0/short_6
[18] DDI1_TX0_DP DDI1_TXP0 LVDS_VREFH R39 2.2K/J_4 LCD_CLK
DDI1_TX0_DN F11 H3 R428 *0/short_6 +3V
[18] DDI1_TX0_DN DDI1_TXN0 LVDS_VREFL
DDI1_TX1_DP J11
[18] DDI1_TX1_DP DDI1_TXP1 R38 2.2K/J_4 LCD_DATA
DDI1_TX1_DN H11 G10
[18] DDI1_TX1_DN DDI1_TXN1 LVDS_TXP0 TXLOUT0+ [18]
DDI1_TX2_DP F13 H10
+1.5V [18] DDI1_TX2_DP DDI1_TXP2 LVDS_TXN0 TXLOUT0- [18] <EMI>
DDI1_TX2_DN E13 F8
[18] DDI1_TX2_DN DDI1_TXN2 LVDS_TXP1 TXLOUT1+ [18] C50 C51
DDI1_TX3_DP J13 E8
[18] DDI1_TX3_DP DDI1_TXP3 LVDS_TXN1 TXLOUT1- [18]
DDI1_TX3_DN K13 H7
[18] DDI1_TX3_DN DDI1_TXN3 LVDS_TXP2 TXLOUT2+ [18] *220P/50V_4 *220P/50V_4
H8 TXLOUT2- [18]
T11 H_RSVD_TP_H17 LVDS_TXN2
J17 RSVD_TP_J17 LVDS_TXP3 G5
R32 C55 1U/6.3V_4 T7 H_RSVD_TP_J17 H17 G6
0/J_6 RSVD_TP_H17 LVDS_TXN3
BREF1.8V E15 H4
BREF18V LVDS_CLKP TXLCLKOUT+ [18]
R45 7.5K/F_4 EXT_BANDGAP F15 J4
BREFREXT LVDS_CLKN TXLCLKOUT- [18]
H21
IHDA
<20101125_Colt> Please follow PDG, we will [13] ACZ_BITCLK_CPU AZIL_BCLK R58 2.2K/J_4 CRT_DDC_SDA
F22 G22 +3V
C doing BOM stuff changing in next version CRB [13] ACZ_SYNC_CPU AZIL_SYNC PANEL_BKLTCTL INT_LVDS_PWM [18] C
E25 LBKLT_EN R56 2.2K/J_4 CRT_DDC_SCL
33/J_4 ACZ_SDINO_R PANEL_BKLTEN
[13] ACZ_SDINO R42 E22 F29 INT_LVDS_DIGON_Q
AZIL_SDI PANEL_VDDEN R65
[13] ACZ_SDOUT_CPU F21
AZIL_SDO
*10K/J_4
<EMI>
C58 C65
[13] ACZ_RST#_CPU E21 AZIL_RST# 3 OF 6
*220P/50V_4 *220P/50V_4
CDV_22MM_REV1P10
LCD Panel Power (LDS) U24A
CEDARVIEW
REV = 1.10
[10] DMI_TXP0 L3 K6 DMI_RXP0 [10]
+3V DMI_RXP0 DMI_TXP0
[10] DMI_TXN0 L2 K5 DMI_RXN0 [10]
C329 .1U/10V_4 DMI_RXN0 DMI_TXN0
[10] DMI_TXP1 M3 L5 DMI_RXP1 [10]
DMI_RXP1 DMI_TXP1
[10] DMI_TXN1 M2 L6
DMI
DMI_RXN1 DMI_TXN1 DMI_RXN1 [10]
U20 [10] DMI_TXP2 N2 L9
DMI_RXP2 DMI_TXP2 DMI_RXP2 [10]
5
[10] DMI_TXN2 N1 DMI_RXN2 DMI_TXN2 L8 DMI_RXN2 [10]

ECPWROK 2 TC7SH08FU [10] DMI_TXP3 P2 N5
DMI_RXP3 DMI_TXP3 DMI_RXP3 [10]
4 INT_LVDS_DIGON [18] [10] DMI_TXN3 P3 N6 DMI_RXN3 [10]
INT_LVDS_DIGON_Q DMI_RXN3 DMI_TXN3
1
[2] CLK_PCIE_DMIP N9 R8
DMI_REFCLKP RSVD_TP_R8
[2] CLK_PCIE_DMIN N8 R7
3
R360 DMI_REFCLKN RSVD_TP_R7 DMI_REF1.5V_R 7.5K/F_4

DMI_REF1.5V T2 T1 R445 DMI_REF1.5V
DMI_REF1P5 DMI_RCOMP
100K_4 <20101109> Add DMI_REF1.5V to follow CRB v0.7
+1.5V R450 *0/short_4
1 OF 6
R355 *0/J_4
CDV_22MM_REV1P10
B C354 B
1U/10V_4
<20101109> Add C354 to follow CRB v0.7
LCD Panel Backlight (LDS) For HDMI deep color mode support THERMAL SENSOR (THM)
<20110414> Unstuff Thermal Sensor and related circuit.
(HDM)
+3V <20100727_Sam> Customer must to use 27MHz due to
C48 .1U/10V_4
accuracy concerns(<1000ppm) from Intel silicon
U2 perspective.
<20110414> Pull up at EC side
5
ECPWROK 2 TC7SH08FU LAYOUT NOTE: PLACE CLOSE TO PIN +3V

[8,13,16,27] ECPWROK
LBKLT_EN 1
4 INT_LVDS_BLON [18]
R114 * *0/J_4
2ND_MBCLK [27]
DREFCLK_R1
DREFCLK#_R1 * R115 THERMAL_SCL
* 1
U5
5 THERMAL_SDA R119 * *0/J_4
3
SCL SDA 2ND_MBDATA [27]

R53 *2K/F_4
2 +3V
100K_4 R409 R410 GND C148 C154
0/J_4 0/J_4 [6,13,27] THERM_ALERT# R111* *0/J_4 THERM_ALERT#_1 3
ALERT# VDD
4 *0.1U/16V_4 *0.1U/16V_4
R51 *0/J_4
Y3 2nd source: BG627000289 (ZYG)
*NCT7717U
* C155 * C156
*0.1U/16V_4 *4.7U/6.3V_6
ALERT# Pull Up Value Alert temperature point
27MHz/+-20PPM_20PF
2K ohm 75 degree
R385 1M/J_4
7.5K ohm 90 degree
C334 C335
A 10.5K ohm 100 degree A
33P/50V_4 33P/50V_4
14K ohm 105 degree
18.7K ohm 110 degree

PROJECT : ZE7
1B
Cedarview DMI/Display
5 4 3 2 1
5 4 3 2 1
Cedar View (CPU) 06

U24D
CEDARVIEW
REV = 1.10
L26 RSVD_L26 SMI# B18 H_SMI# [11]

R74 2.2K/J_4 L27 C22 H_NMI [11]
R71 2.2K/J_4 RSVD_L27 NMI/LINT1 R386 *0/short_4
K28 RSVD_K28 RSVD_C18 C18 H_A20M# [11]
K25 RSVD_K25 STPCLK# D22 H_STPCLK# [11]
ICH
D J28 RSVD_J28 D
K26 RSVD_K26
K27 RSVD_K27
<20100811_Jerry>can be NC but please reserve 2.2K pull H27 RSVD_H27
low as CRB. can be removed later depends on CRB K30 RSVD_K30
L29
validation status. L30
RSVD_L29
C21
RSVD_L30 DPRSTP# ICH_DPRSTP# [13]
K29 RSVD_K29 DPLSLP# B21 H_DPSLP# [13]
<20101019>Stuff R74 R71 for using 0xFFFE_0000 J31
RSVD_J31 CPUSLP#
B22 CPUSLP# [11]
as Punit microbase address H30 RSVD_H30
INIT# A23 H_INIT# [11]
D20 H_INTR [11]
INTR/LINT0 +1.05V
HV_GPIO_RCOMP K24 B20 H_THRMTRIP#
MV_GPIO_RCOMP HV_GPIO_RCOMP THERMTRIP#
K23 L11
MV_GPIO_RCOMP RSVD_L11
<20100811_Jerry>please use 100+/-5% as in PDG.
R381
R72 R69 100/J_4
49.9/F_4 49.9/F_4 C20 H_FERR#_R R400 *0/short_4 H_FERR# [11]
PBE#
A19 H_PROCHOT_R# R377 *0/short_4
PROCHOT# H_PROCHOT# [31]
D23 H_PW RGD
PWRGOOD H_PW RGD [13,16]
G30 PLTRST# PLTRST# [13,16,22,25,26,27]
RESET#
DBR# E30 XDP_DBRESET_N_CDV R33 1K/J_4 +1.8V
+3V
H29 H_BPM4_PRDY# H_BPM4_PRDY# R442 *51/J_4

PRDY# T43
G29 H_BPM5_PREQ#
PREQ# T44 H_BPM5_PREQ# R443 51/J_4
J19 CLK_MCH_BCLK
CPU
HPLL_REFCLK_P CLK_MCH_BCLK [2] Host CLK 100/133 MHz C268
K19 CLK_MCH_BCLK# CLK_MCH_BCLK# [2]
C HPLL_REFCLK C
.1U/10V_4
RSVD_E19 E19 +1.05V
RSVD_F19 F19
R399 R416
75/J_4 110/F_4
XDP_TCLK C25 B16

T45 TCLK SVID_ALERT# VR_SVID_ALERT# [31]
XDP_TDI C24 D18
T46 TDI SVID_CLK VR_SVID_CLK [31]
XDP_TDO B25 C16
T47 TDO SVID_DATA VR_SVID_DATA [31]
XDP_TMS D24
T48 TMS
XDP_TRST# B24
T49 TRST#
R5
RSVD_R5
R6 RSVD_R6
+1.05V W25
RSVD_W25
W26 K21
RSVD_W26 RSVD_K21
XDP_TDI R449 51/J_4 N24 L22
RSVD_N24 RSVD_L22
XDP_TDO R459 51/J_4 N25 RSVD_N25 RSVD_L24 L24
XDP_TMS R470 51/J_4
XDP_TCLK R446 51/J_4

XDP_TRST# R448 51/J_4
CDV_22MM_REV1P10
4 OF 6
B B
125 Degree Protection(CPU) CPU FAN CTRL(THM)

+1.05V
+3V +5V +3V +5V

3
Q2
2N7002K
IMVP_PW RGD 2
[27,31] IMVP_PW RGD R509 R507 R512
R505 *0/short_6 C365 0.1U/16V_4
10K/J_4 10K/J_4 10K/J_4
R514 *0/J_4
CN18
1
[5,13,27] THERM_ALERT#
+5V_FANVCC
FANSIG [27] 4 6
2
FANSIG 3 5
R17 2
CPUFAN# 1 3 FAN_PW M_CN
1K/J_4 [27] CPUFAN# 1
Q43 METR3904-G
EC PWM SIGNAL FAN CONN
Shutdown System Power Immediately
2
Q1
From CPU H_THRMTRIP# 1 3 SYS_SHDN# [30,35]
METR3904-G
A To System Power A
For EMI
R16 *0/short_4
PM_THRMTRIP# [11]
FAN_PW M_CN FANSIG
To Tiger Point
C368
*220P/50V_6
C372
*220P/50V_6
PROJECT : ZE7
1B
Cedarview Miscellaneous
Date: W ednesday, November 02, 2011 Sheet 6 of 40
5 4 3 2 1
1 2 3 4 5 6 7 8
Cedar View PLL Power

Cedar View (CPU) Default stuff 1.5VPLL, Intel verify whether 07
1.05VPLL is ok or not
LAYOUT NOTE: place close to VCCADDR pin 1.1V (0.75V~1.18V)
U24E
V_1.05_CORE_RSENSE R112 *1.5VPLL@0/short_6
CEDARVIEW
5.95A +1.5V
REV = 1.10 +VCC_CORE
C352 C120 C141 AA14 P18 VCCSFRMPL_1.5 L18
VCCADDR_1 VCC_CPU_01 +1.05V
*22U/6.3V_8 1U/10V_4 *1U/10V_4 AA16 P19 1U/10V_4 *1U/10V_4 22U/6.3V_8 22U/6.3V_8 *1.05VPLL@10uH/100mA_8
VCCADDR_2 VCC_CPU_02
W16 P21
VCCADDR_3 VCC_CPU_03 C126 C100 C105 C118 C101 C125 C106 C103 C112 C134 C142
W18 P28
A VCCADDR_4 VCC_CPU_04 *10U/6.3V_8
A
P29 1U/10V_4
V_1.05_CORE_EAST VCC_CPU_05
<20101126_Colt> Please follow PDG to C92 *1U/10V_4 N30
VCCRAMXXX_1 VCC_CPU_06
P30
placehold the 0805 capacitor N31 R22
C116 1U/10V_4 V_1.05_CORE_RSENSE VCCRAMXXX_2 VCC_CPU_07 1U/10V_4 *1U/10V_4 *1U/10V_4 22U/6.3V_8 22U/6.3V_8
V4 R23
VCCRAMXXX_3 VCC_CPU_08 R29 *1.5VPLL@0/short_6
R24 +1.5V
V_1.05_VCCDDR VCC_CPU_09
W8 R25
VCCACKDDR_1 VCC_CPU_10
W9 R26
VCCACKDDR_2 VCC_CPU_11 VCCADP0_1.5
LAYOUT NOTE: PLACE
DDR
R27 L3 +1.05V
CPU
C129 C130 C128 V_1.05_VCCDDR VCC_CPU_12 *1.05VPLL@10uH/100mA_8
W11 T19 ONE 1U CAP ON BOT LAYER
*1U/10V_4 1U/10V_4 1U/10V_4 VCCADLLDDR_1 VCC_CPU_13
W13 T21
VCCADLLDDR_2 VCC_CPU_14 C52 C28
T29
VCCCKDDR_VSM VCC_CPU_15 *10U/6.3V_8
AJ6 T30 1U/10V_4
VCCCKDDR_1 VCC_CPU_16
AK6 T31
VCCCKDDR_2 VCC_CPU_17
[8] VCCDDRAON_1.5 U22
VCC_CPU_18
AH14 U23
V_SM_1 VCC_CPU_19
AH19 U24
R134 *0/short_8 VCCDDRAON_1.5 V_SM_2 VCC_CPU_20 R36 *1.5VPLL@0/short_6
+1.5VSUS AK23 U25 +1.5V
V_SM_3 VCC_CPU_21
AK5 U26
C149 C153 C146 C152 V_SM_4 VCC_CPU_22
AL11 U27
V_SM_5 VCC_CPU_23
For Deep Standby AL16
V_SM_6 VCC_CPU_24
V18 VCCADP1_1.5 L4 +1.05V
2.2U/6.3V_6 2.2U/6.3V_6 2.2U/6.3V_6 2.2U/6.3V_6 AL21 V19 *1.05VPLL@10uH/100mA_8
V_SM_7 VCC_CPU_25
AG31 V21
V_SM_8 VCC_CPU_26 C53 C29
V28 1.05V (0.76V~1.05V)
R419 *0/short_6 VCCADP_1.05 VCC_CPU_27 *10U/6.3V_8
+1.05V B5 V29 1U/10V_4
VCCADP_1 VCC_CPU_28
C6 V30 1.98A
VCCADP_2 VCC_CPU_29
C56 1U/10V_4 D6
VCCADP_3
LAYOUT NOTE: PLACE
R77 *0/short_6 VCCGFX
+1.05V TWO CAPS ON BOT LAYER
R54 *0/J_6 VCCADP0_1.5 K17
VCCADP0_SFR
POWER
C83 VCCADP1_1.5 L18 N11
1U/10V_4 VCCADP1_SFR VCC_GFX_01
B N13 B
C82 *0.1U/10V_4 V_1.05_CORE_EAST L19
VCCAGPIO_LV
VCC_GFX_02
VCC_GFX_03
P11 C95 C98 C117 C94 C115 Cedar View LVDS Power
R31 *0/short_6 VCCAGPIO_1.5 L16 P13
+1.5V VCCAGPIO_REF VCC_GFX_04
R46 *0/short_6 VCCAGPIO_1.8 N18 R10 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 22U/6.3V_8
+1.8V VCCAGPIO_DIO VCC_GFX_05
R9 BOM structure
C93 1U/10V_4 R55 *0/short_6 VCCAGPIO_3.3 VCC_GFX_06
+3.3V_PRIME D30 T11
VCCAGPIO_1 VCC_GFX_07
D31
VCCAGPIO_2 VCC_GFX_08
T13 w/LVDS: stuff R436/ C345/ L38/ C75
C59 2.2U/6.3V_6 VCCADAC_1.8 U10 w/EDP: unstuff R436/ C75
R384 0.2A/600ohm_6 VCC_GFX_09
+1.8V B13 V11
VCCADAC VCC_GFX_10 C60 1U/10V_4 change L38/ C345 to 0ohm
V13
C336 22U/6.3V_8 VCCALVDS_1.8 VCC_GFX_11
H5
VCCDLVDS_1.8 VCCALVDS VCCADMI_1.05 R423 *0/short_6
J1 B4 +1.05V
<20100830> Add Farrite bead for VCCDAC low pass filterC337 *47U/6.3V_8 VCCDLVDS VCCADMI_1
DMI
C5 C88 1U/10V_4
VCCADMI_2
A4
C91 1U/10V_4 V_1.05_CORE_EAST L21 VCCADMI_3 VCCADMI_1.5 R456 *0/short_6 +1.8V
K4 +1.5V
VCCDIO VCCADMI_PLLSFR VCCDLVDS_1.8
R47 *0/short_6 VCCAZILAON_3.3 B29 V16 V_1.05_CORE_RSENSE
+3.3V_PRIME VCCAZILAON_1 VCCFHV_1
A30 T16
C54 2.2U/6.3V_6 VCCAZILAON_2 VCCFHV_2
VCCSFRMPL_1.5 AA18 V14 VCCALVDS_1.8 [email protected]/300mA_6 L38 R436 LVDS@0/J_6
V_1.05_CORE_RSENSE R94 *0/short_6 VCCDMPL_1.05 VCCSFRMPL VCCFHV_3
PLL
AA11
VCCDMPL
M28 CPUVCC_SENSE [31]
VCCPLLCPU0_1.05 VCC_CPUSENSE C75 C345
B27 M30 CPUVSS_SENSE [31]
C139 VCCPLLCPU1_1.05 VCCPLLCPU0 VSS_CPUSENSE [email protected]/6.3V_6
C29 BOM@1U/10V_4
*2.2U/6.3V_4 VCCPLLCPU1_1
B30 U8 GTVCC_SENSE [31]
VCCPLLCPU1_2 VCC_GFXSENSE
U7 GTVSS_SENSE [31]
VCCAHPLL_1.05 VSS_GFXSENSE
B26
VCCAHPLL
<20101125_Colt> Please follow PDG, we will doing BOM N16 V_1.8_RSENSE
VCCTHRM_1 R437 *0/short_6
stuff changing in next version CRB K2 +1.8V
VCCTHRM_2
C C
C350
*1U/10V_4
VCCPLLCPU0_1.05 R40 *0/J_6 VCCPLLCPU1_1.05
LAYOUT NOTE: OVERLAP RESISTOR AND INDUCTOR

+1.5VSUS
2nd source: CV01001MN32 VCCCKDDR_VSM R489 *0/short_8
C359
C362
+1.05V 1U/6.3V_4 10U/6.3V_8
VCCPLLCPU0_1.05 10uH/100mA_8 L6
<2010/9/27>Reserve 0805 footprint for farrite bead
CV01001MN16 due to co-layout issue.
C31 C40
5 OF 6 4.7u/6.3V_6 1U/10V_4
CDV_22MM_REV1P10 <20101125_Colt> Please follow PDG, we will doing BOM
+1.05V stuff changing in next version CRB
VCCPLLCPU1_1.05 10uH/100mA_8 L11
<20101125_Colt> Please follow PDG, we will doing BOM V_1.05_VCCDDR R89 *0/short_6 +1.05V
stuff changing in next version CRB C45 C46
D 4.7u/6.3V_6 1U/10V_4 D
V_1.05_CORE_RSENSE R440 *0/short_6
+1.05V
VCCAHPLL_1.05 10uH/100mA_8 L10
C32 C49 Quanta Computer Inc.

4.7u/6.3V_6 1U/10V_4
PROJECT : ZE7
1B
CedarView Power
1 2 3 4 5 6 7 8
5 4 3 2 1
Cedar View (CPU) U24B 08

M_A_DQ[63:0] [4]
CEDARVIEW
[4] M_A_A[15:0]
M_A_A0 AK14 Y30 M_A_DQ0
M_A_A1 DDR3_MA0 DDR3_DQ0 M_A_DQ1
AK16 DDR3_MA1 DDR3_DQ1 Y29
M_A_A2 AJ14 REV = 1.10 AC30 M_A_DQ2
AJ16 DDR3_MA3 DDR3_DQ3 AC31
M_A_A4 AK18 W 31 M_A_DQ4
AH18 DDR3_MA5 DDR3_DQ5 W 28
M_A_A6 AJ18 AB28 M_A_DQ6
AK20 DDR3_MA7 DDR3_DQ7 AB30
M_A_A8 AJ20 AA24 M_A_DQ8
D
AH20 DDR3_MA9 DDR3_DQ9 AA22 D
M_A_A10 AJ12 AE27 M_A_DQ10
AK21 DDR3_MA11 DDR3_DQ11 AE26
M_A_A12 AJ21 AB27 M_A_DQ12
AJ8 DDR3_MA13 DDR3_DQ13 AA25
M_A_A14 AH22 AD25 M_A_DQ14
AJ22 DDR3_MA15 DDR3_DQ15 AD27
AD29 M_A_DQ16
M_A_WE# DDR3_DQ16 M_A_DQ17
[4] M_A_WE# AH10 DDR3_W E# DDR3_DQ17 AE29
[4] M_A_CAS# M_A_CAS# AJ10 AJ30 M_A_DQ18
M_A_RAS# DDR3_CAS# DDR3_DQ18 M_A_DQ19
<Layout note> [4] M_A_RAS# AJ11 DDR3_RAS# DDR3_DQ19 AK29
AD28 M_A_DQ20
PLACE RESISTORS AND CAP CLOSE TO CPU DDR_VREF PIN M_A_BS0 AK12
DDR3_DQ20
AD30 M_A_DQ21
[4] M_A_BS0 DDR3_BS0 DDR3_DQ21
M_A_BS1 AH13 AG30 M_A_DQ22
[4] M_A_BS1 DDR3_BS1 DDR3_DQ22
M_A_BS2 AK22 AJ29 M_A_DQ23
R482 1K/F_4 [4] M_A_BS2 DDR3_BS2 DDR3_DQ23
[7] VCCDDRAON_1.5 AE24 M_A_DQ24
DDR3_DQ24 M_A_DQ25
AH12 DDR3_CS#0 DDR3_DQ25 AG24
AH8 AD22 M_A_DQ26
R492 *0/J_4 R483 *0/short_4 M_CS#2 DDR3_CS#1 DDR3_DQ26 M_A_DQ27
+SMDDR_VREF [4] M_CS#2 AK11 DDR3_CS#2 DDR3_DQ27 AC21
M_CS#3 AK8 AG27 M_A_DQ28
[4] M_CS#3 DDR3_CS#3 DDR3_DQ28
AG25 M_A_DQ29
R493 DDR3_DQ29 M_A_DQ30
AH23 DDR3_CKE0 DDR3_DQ30 AG21
1K/F_4 C360 AJ24 AE21 M_A_DQ31
M_CKE2 DDR3_CKE1 DDR3_DQ31 M_A_DQ32
0.1U/16V_4 [4] M_CKE2 AK24 DDR3_CKE2 DDR3_DQ32 AD13
M_CKE3 AH24 AD11 M_A_DQ33
[4] M_CKE3 DDR3_CKE3 DDR3_DQ33
AG8 M_A_DQ34
DDR3_DQ34 M_A_DQ35
AK10 DDR3_ODT0 DDR3_DQ35 AG7
AK7 AG13 M_A_DQ36
M_ODT2 DDR3_ODT1 DDR3_DQ36 M_A_DQ37
[4] M_ODT2 AL9 DDR3_ODT2 DDR3_DQ37 AE13
M_ODT3 AJ7 AD10 M_A_DQ38
[4] M_ODT3 DDR3_ODT3 DDR3_DQ38
C AF8 M_A_DQ39 C
DDR3_DQ39 M_A_DQ40
AG15 DDR3_CK0 DDR3_DQ40 AH2
AF15 AG3 M_A_DQ41
DDR3_CK#0 DDR3_DQ41 M_A_DQ42
AF17 DDR3_CK1 DDR3_DQ42 AD2
AG17 AD3 M_A_DQ43
M_CLK2 DDR3_CK#1 DDR3_DQ43 M_A_DQ44
<20100810_Jerry> Please refer to Cedar Trail CPET HW section(#454349), [4] M_CLK2 AD17 DDR3_CK2 DDR3_DQ44 AH4
it is to implement Deep Standby. And please waiting the whitepaper for implementation detail. M_CLK2# AC17 AK3 M_A_DQ45
[4] M_CLK2# DDR3_CK#2 DDR3_DQ45
M_CLK3 AC15 AE2 M_A_DQ46
[4] M_CLK3 DDR3_CK3 DDR3_DQ46
M_CLK3# AD15 AD4 M_A_DQ47
[4] M_CLK3# DDR3_CK#3 DDR3_DQ47
AD7 M_A_DQ48
DDR3_DQ48 M_A_DQ49
DDR3_DQ49 AD6
* DDR3_DRAMRST#_R AK25 DDR3_DRAMRST# DDR3_DQ50
DDR3_DQ51
AA6
AB5
M_A_DQ50
M_A_DQ51
DDR_VREF AJ27 AE8 M_A_DQ52
DDR3_VREF DDR3_DQ52 M_A_DQ53
AL28 DDR3_VREF_NCTF DDR3_DQ53 AE5
AB9 M_A_DQ54
DDR3_DQ54 M_A_DQ55
[2] CLK_DDR3_REFCLK AC19 DDR3_REFP DDR3_DQ55 AA8
AB19 AB2 M_A_DQ56
<20100817_Jerry>DELAY_VR_PWRGOOD on CDV should be connected to the XDP_PWRGOOD [2] CLK_DDR3_REFCLK# DDR3_REFN DDR3_DQ56
AB4 M_A_DQ57
because the SV folks expressed a preference on using PWROK over PWRGOOD for CDV. DDR3_DQ57
W4 M_A_DQ58
This has changed from PNV to CDV. DDR3_DQ58
DDRAM_PWROK AA5 V3 M_A_DQ59
DELAY_VR_PWRGD_CDV DDR3_DRAM_PW ROK 1.5V DDR3_DQ59 M_A_DQ60
T53 W7 DDR3_VCCA_PW ROK 1.5V DDR3_DQ60 AC2
AB3 M_A_DQ61
R99 121/F_4 M_ODTPU DDR3_DQ61 M_A_DQ62
[5,13,16,27] ECPWROK AJ26 DDR3_ODTPU DDR3_DQ62 Y2
M_CMDPU AJ25 W1 M_A_DQ63
R98 M_DQPU DDR3_CMDPU DDR3_DQ63
AK27 DDR3_DQPU M_A_DQS[7:0] [4]
AA30 M_A_DQS0
100/F_4 DDR3_DQS0 M_A_DQS1
AB11 RSVD_TP_AB11 DDR3_DQS1 AB24
<20110520>Change 12.1K to 121ohm to follow CRBv1.5 R485 R488 C361 R484 AB13 AF30 M_A_DQS2
RSVD_TP_AB13 DDR3_DQS2 M_A_DQS3
B
AF19 RSVD_TP_AF19 DDR3_DQS3 AE22 B
<20110520>Change 10K to 100ohm to follow CRBv1.5 274/F_4 22.6/F_4 *0.01U/25V_4 33.2/F_4 AG19 AG10 M_A_DQS4
RSVD_TP_AG19 DDR3_DQS4 M_A_DQS5
DDR3_DQS5 AF4
DDR3 AB6 M_A_DQS6
DDR3_DQS6 M_A_DQS7
DDR3_DQS7 Y3 M_A_DQS#[7:0] [4]
[4] M_A_DM[7:0]
<20100811_Jerry> R485 please follow CRB schematic. (274ohm) M_A_DM0 Y28 AA31 M_A_DQS#0
M_A_DM1 DDR3_DM0 DDR3_DQS#0 M_A_DQS#1
AB26 DDR3_DM1 DDR3_DQS#1 AB25
M_A_DM2 AE30 AF29 M_A_DQS#2
AB21 DDR3_DM3 DDR3_DQS#3 AF22
M_A_DM4 AG11 AF10 M_A_DQS#4
AG2 DDR3_DM5 DDR3_DQS#5 AF3
M_A_DM6 AB8 AB7 M_A_DQS#6
AA3 DDR3_DM7 DDR3_DQS#7 AA2
CDV_22MM_REV1P10
DRAM Reset (CPU) 2 OF 6
<20110727>Connect DDRAM_PWROK between CDV and RT8207L to meet JEDEC timing spec
+1.5VSUS
<20110520>Need to confirm with Intel if <20110607>Keep original design first for DRAMRST# +1.5VSUS
we need to add series 100ohm resistor
<20110707_Nick> Please un-stuff 1K pull up VCCDDRAON_1.5
R538
A
*1K/F_4 R100 A
10K/J_4
R537 *0/short_4 DDR3_DRAMRST#_NS R539 *0/short_4 DDR3_DRAMRST#_R
[4] DDR3_DRAMRST#
C159 DDRAM_PWROK
<20110607>Keep original design first for DRAMRST# [27,32] DDRAM_PWROK
R474
0.1U/16V_4
<20110707_Nick> Please stuff 100K pull down
R97
<20110727> Add C159 to suppress glitch
100K/J_4
*0/J_4
C388
*1U/10V_6
<20110727> Reserve C388 for RC delay PROJECT : ZE7
1B
CedarView DDR
5 4 3 2 1
1
09
Cedar View (CPU)
U24F
A11 VSS
CEDARVIEW
VSS H19
A16 H26
VSS VSS
A21 H28
VSS REV = 1.10 VSS
A25 H6
VSS VSS
AA1 J10
VSS VSS
AA10 J2
VSS VSS
AA13 VSS VSS J21
AA19 VSS VSS J30
AA21 VSS VSS K11
AA23 VSS VSS K15
AA26 VSS VSS K3
AA27 VSS VSS K7
AA29 K8
VSS VSS
AA7 VSS VSS K9
AA9 L1
VSS VSS
AB15 VSS VSS L10
AB17 VSS VSS L13
AB23 VSS VSS L23
AB29 L25
VSS VSS
AC1 L31
VSS VSS
AC10 L7
VSS VSS
AC11 M29
VSS VSS
GND
AC13 M4
VSS VSS
AC22 N10
VSS VSS
AC28 N14
VSS VSS
AC4 N19
VSS VSS
AD19 N21
VSS VSS
AD21 N22
VSS VSS
AD24 VSS VSS N23
AD26 VSS VSS N26
AD5 N27
VSS VSS
AD8 N28
VSS VSS
AE1 N4
VSS VSS
AE10 N7
VSS VSS
AE11 P14
VSS VSS
AE15 VSS VSS P16
AE17 VSS VSS P4
AE19 VSS VSS T14
AE3 T18
VSS VSS
AE31 T3
VSS VSS
AF11 VSS VSS U5
AF13 VSS VSS U6
AF21 VSS VSS U9
AF24 V2
VSS VSS
AF28 W10
VSS VSS
AF7 W14
VSS VSS
AG22 W19
VSS VSS
AG5 VSS VSS W2
AH26 W21
VSS VSS
AH28 W22
VSS VSS
AH6 VSS VSS W23
AH9 W24
VSS VSS
AJ2 W27
VSS VSS
AJ3 W30
VSS VSS
AK13 W5
VSS VSS
AK19 W6
A VSS VSS A
AK28 Y4
VSS VSS
AK9
VSS
AL13
VSS
AL19 A27
VSS VSS
AL23 A29
VSS VSS
AL25 A3
VSS VSS
AL7 AH1
VSS VSS
B10 AJ1
VSS VSS
B14 AJ31
VSS VSS
B19 AK1
VSS VSS
B23 AK2
VSS VSS
C12 AK30
VSS VSS
C26 AK31
VSS VSS
C30 VSS VSS AL2
C7 AL29
VSS VSS
D19 VSS VSS AL3
D28 VSS VSS AL30
D8 AL5
VSS VSS
D9 B2
VSS VSS
E2 B3
VSS VSS
E5 B31
VSS VSS
E7 VSS VSS C1
F24 C2
VSS VSS
F4 C31
VSS VSS
G1 E1
VSS VSS
G11 VSS
G13 VSS
G15 VSS VSS_CDVDET L14
G17 D13
VSS VSSA_CRTDAC
G19
VSS
G21
VSS
G31
VSS
G8
VSS
H13 VSS
6 OF 6
CDV_22MM_REV1P10

PROJECT : ZE7
1B
CedarView GND/ Deep Standby
1
1
10
Tiger Point (CLG)
U22B TGP
[5] DMI_RXN0 R23 DMI0RXN USBP0N H7 USBP0- [21]

[5] DMI_RXP0
C96 .1U/10V_4 DMI_TXN0_C
R24
P21
DMI0RXP USBP0P H6
H3
USBP0+ [21] SYSTEM (Right Down)
[5] DMI_TXN0 DMI0TXN USBP1N USBP1- [21]
C90 .1U/10V_4 DMI_TXP0_C
[5]
[5]
DMI_TXP0
DMI_RXN1
P20
T21
DMI0TXP USBP1P H2
J2
USBP1+ [21] SYSTEM (Right Up)
DMI1RXN USBP2N USBP2- [18]
T20 J3
[5] DMI_RXP1
C113 .1U/10V_4 DMI_TXN1_C T24
DMI1RXP USBP2P
K6
USBP2+ [18] CCD
DMI
C104 .1U/10V_4 DMI_TXP1_C T25 K5
[5]
[5]
DMI_TXP1
DMI_RXN2 R81 *0/J_4 DMI_RXN2_R T19
DMI1TXP USBP3P
K1
USBP3+ [21] SYSTEM (Left/ USB Charger)
DMI2RXN USBP4N USBP4- [25]
R80 *0/J_4 DMI_RXP2_R
[5] DMI_RXP2
C110 *.1U/10V_4 DMI_TXN2_C
T18
U23
DMI2RXP USBP4P K2
L2
USBP4+ [25] SIM
<20110222> ES2 CPU DMI will C122 *.1U/10V_4 DMI_TXP2_C
[5] DMI_TXP2
R88 *0/J_4 DMI_RXN3_R
U24
V21
DMI2TXP USBP5P L3
M6
USBP5+ [25] 3G
change from x4 to x2 [5] DMI_RXN3
R86 *0/J_4 DMI_RXP3_R DMI3RXN USBP6N USBP6- [19]
[5] DMI_RXP3
C124 *.1U/10V_4 DMI_TXN3_C
V20
V24
DMI3RXP USBP6P M5
N1
USBP6+ [19] BT
C132 *.1U/10V_4 DMI_TXP3_C V23 N2
[5] DMI_TXP3 DMI3TXP USBP7P USBP7+ [25] WLAN +3V_S5
USB
D4 USBOC#R_1 R435 *0/short_4 USBOC#R [21,27] USBOC#R_1 R433 8.2K/J_4
OC0# USBOC#R_1 USBOC#L_1 R429 8.2K/J_4
[22] PCIE_RXN0 K21 PERN1 OC1# C5
[22] PCIE_RXP0 K22 D3 USBOC# USBOC# R432 1K/F_4
C63 .1U/10V_4 PCIE_TXN0_CJ23 PERP1 OC2# USBOC#L_1 R427 *0/short_4
LAN [22] PCIE_TXN0
C71 .1U/10V_4 PCIE_TXP0_CJ24 PETN1 OC3# D2
E5 USBOC#
USBOC#L [21,27] CRB ties unused OC pins together with 1k ohm
[22] PCIE_TXP0 PETP1 OC4#
[25] PCIE_RXN1 M18 E6 USBOC#
PERN2 OC5#/GPIO29 USBOC#
[25] PCIE_RXP1 M19 PERP2 OC6#/GPIO30 C2
C343 .1U/10V_4 PCIE_TXN1_C K24 C3 USBOC#
WLAN [25] PCIE_TXN1
C344 .1U/10V_4 PCIE_TXP1_C K25 PETN2 OC7#/GPIO31
[25] PCIE_TXP1 PETP2
[26] PCIE_RXN2 L23 <Layout note>
PERN3
[26] PCIE_RXP2 L24 PERP3 Close to pin within 200mil ; keep away from CLK/High speed signals
C87 .1U/10V_4 PCIE_TXN2_C L22
Card Reader [26] PCIE_TXN2 PETN3 USBRBIAS G2
PCI-E
C80 .1U/10V_4 PCIE_TXP2_C M21 G3 USBRBIAS R438 22.6/F_4
[26] PCIE_TXP2 PETP3 USBRBIAS#
[25] PCIE_RXN3 P17 PERN4
[25] PCIE_RXP3 P18 PERP4
C347 *.1U/10V_4 PCIE_TXN3_C N25
Media Processor [25] PCIE_TXN3
C346 *.1U/10V_4 PCIE_TXP3_C N24 PETN4
[25] PCIE_TXP3 PETP4
CLK48 F4 CLKUSB_48 CLKUSB_48 [2]
A A
<20110630> No support PCI-e in 3G card EMI

R66
*10/F_4
<Layout note>
Close to pin within 500mil
R425 24.9/F_4 DMI_COMP H24
+1.5V DMI_ZCOMP
J22 C81
DMI_IRCOMP *10P/50V_4
[2] CLK_PCIE_ICH# W23 DMI_CLKN
[2] CLK_PCIE_ICH W24 DMI_CLKP
2
Tiger Point

PROJECT : ZE7
1B
Tiger Point DMI/PCIE/USB
1
5 4 3 2 1
Tiger Point (CLG) 11
D
<Layout note> D
Close to pin within 200mil
Follow CRB [12,13,14] VCC3_VCC3
U22C TGP
SERIRQ R96 4.7K/J_4
R12 AE6 SATA_RXN0 [24] KBRST# R117 10K/J_4
RSVD03 SATA0RXN
AE20 AD6
AD17
RSVD04 SATA0RXP
AC7
SATA_RXP0 [24] SATA HDD
RSVD05 SATA0TXN SATA_TXN0 [24]
AC15
RSVD06 SATA0TXP
AD7 SATA_TXP0 [24] <20100811_Jerry> Please follow CRB schematic (8.2K)
AD18 AE8 +3V
RSVD07 SATA1RXN
Y12 AD8
RSVD08 SATA1RXP GA20 R95 8.2K/J_4
AA10 AD9
RSVD09 SATA1TXN PCH_GPIO36 R103 *10K/J_4
AA12 RSVD10 SATA1TXP AC9 <20100811_Jerry>CDV doesn't support A20M,
Y10
SATA
RSVD11 please follow CRB to have a 1K pull up at the moment. +1.05V

AD15
RSVD12
W10 RSVD13 <20110516>Reserve 1K PU to +1.05V for C6-state
V12 H_A20M# R109 1K/J_4
RSVD14
AE21 CPUSLP#_R R532 *1K/J_4
C AE18
RSVD15 <20100813_Jerry> Update for the IGNNE#, please no C
RSVD16 stuff the resister and follow CRB's circuit first.
AD19 RSVD17
U12
RSVD18
AD4 <Layout note> <20110607_C-stage> Stuff 1K to follow CRB V1.5 H_IGNNE# R105 1K/J_4
SATA_CLKN CLK_PCIE_SATA# [2] Close to pin within 500mil
AC17 AC4 CLK_PCIE_SATA [2]
RSVD19 SATA_CLKP
AB13
RSVD20 SATARBIAS# R466 24.9/F_4
AC13 RSVD21 SATARBIAS# AD11
AB15 AC11
RSVD22 SATARBIAS SATALED#
Y14 AD25 SATALED# [24]
RSVD23 SATALED#
AB16 R102 10K/J_4
RSVD24 +3V
AE24 RSVD25
AE23
RSVD26
AA14 U16 GA20 GA20 [27]

RSVD27 A20GATE
V14 Y20 H_A20M# H_A20M# [6] <20100811_Jerry>you can follow PDG for the pull up
RSVD28 A20M#
CPUSLP# Y21 CPUSLP#_R R533 0/J_4
CPUSLP# [6] resistor value and tolerance requirement. CRB is more
Y18 H_IGNNE#
IGNNE# strictly.
AD21 <Layout note>
B INIT3_3V# B
AD16 RSVD29 INIT# AC25 H_INIT# H_INIT# [6] R110 60.4/F_4 Close to pin
AB11 AB24 H_INTR +1.05V
HOST
RSVD30 INTR H_INTR [6]

AB10 Y22 H_FERR# H_FERR# [6]
PCH_GPIO36 RSVD31 FERR#
AD23 GPIO36 NMI T17 H_NMI H_NMI [6]
AC21 KBRST# KBRST# [27]
RCIN# +1.05V
AA16 SERIRQ SERIRQ [27]
SERIRQ
AA21 H_SMI# H_SMI# [6] <20100811_Jerry>for Thermtrip#, please use 60 ohms+/-5% pull up.
SMI#
STPCLK# V18 H_STPCLK# H_STPCLK# [6]
AA20 PM_THRMTRIP#
THERMTRIP# R104
60.4/F_4 <Layout note>
Close to pin within 1"
3
PM_THRMTRIP# [6]
Tiger Point
A A

PROJECT : ZE7
1B
Tiger Point Sata/Host
5 4 3 2 1
5 4 3 2 1

U22A TGP
A5 B22 PCI_INTB# RP3 1 2 8.2K_8P4R

PAR AD0 +3V
PCI_DEVSEL# B15 D18 PCI_IRDY# 3 4
DEVSEL# AD1 PCI_INTG#
D PCI CLK 33MHz
[2] PCLK_ICH
T32
J12 PCICLK AD2 C17
PCI_INTE#
5 6 D
A23 PCIRST# AD3 C18 7 8
PCI_IRDY# B7 B17
IRDY# AD4 PCI_LOCK# RP2
C22 C19 1 2 8.2K_8P4R
EMI PCI_SERR# B11
PME#
SERR#
AD5
AD6 B18 PCI_INTD# 3 4
+3V
R73 PCI_STOP# F14 B19 PCI_TRDY# 5 6
*33/J_4 PCI_LOCK# STOP# AD7 PCI_PERR#
A8 PLOCK# AD8 D16 7 8
PCI_TRDY# A10 PCI D15
PCI_PERR# TRDY# AD9 PCI_DEVSEL#RP1
D10 PERR# AD10 A13 1 2 8.2K_8P4R +3V
PCI_FRAME# A16 E14 PCI_FRAME# 3 4
C99 FRAME# AD11 PCI_REQ1#
AD12 H14 5 6
*10P/50V_4 L14 PCI_REQ2# 7 8
AD13
AD14 J14
T13 A18 E10
T4 GNT1# AD15 PCI_INTA# RP4
E16 GNT2# AD16 C11 1 2 8.2K_8P4R +3V
E12 PCI_INTC# 3 4
PCI_REQ1# AD17 PCI_INTF#
G16 REQ1# AD18 B9 5 6
PCI_REQ2# A20 B13 PCI_INTH# 7 8
REQ2# AD19
AD20 L12
AD21 B8
PCH_GPIO48 G14 A3 PCI_STOP# R392 8.2K/J_4
GPIO48/ STRAP1# AD22 +3V
PCH_GPIO17 A2 B5 PCI_SERR# R391 8.2K/J_4
C PCH_GPIO22 C15 GPIO17/ STRAP2# AD23 EC_SCI# R41 10K/J_4 C
GPIO22 AD24 A6
[27] EC_SCI# EC_SCI# C9 G12
GPIO1 AD25
AD26 H12
AD27 C8
D9 R30 *1K/J_4 PCH_GPIO48 R35 *1K/J_4 +3V
PCI_INTA# AD28 R424 *1K/J_4 PCH_GPIO17 R421 *1K/J_4
B2 PIRQA# AD29 C7
PCI_INTB# D7 C1
PCI_INTC# PIRQB# AD30 R389 *8.2K/J_4 PCH_GPIO22 R388 8.2K/J_4
B3 PIRQC# AD31 B1 +3V
PCI_INTD# H10
PCI_INTE# PIRQD#
E8 PIRQE#/GPIO2
PCI_INTF# D6
PCI_INTG# PIRQF#/GPIO3
H8 PIRQG#/GPIO4 C/BE0# H16
PCI_INTH# F8 M15 <20101104> Reserve R389(PCH_GPIO22 PD) for 27MHz or 96MHz choosing, need vBIOS support
PIRQH#/GPIO5 C/BE1#
C/BE2# C13 Pull up --> for 27MHz
T34 PCH_A16WP D11 L16
R70 10K/J_4 K9
STRAP0# C/BE3# Pull down --> for 96MHz
[11,13,14] VCC3_VCC3 RSVD01
R43 8.2K/J_4 M13
+3V RSVD02
1
Tiger Point
B B
<20090601(A1A)_Checklist Rev0.7>
Strap1#/strap2#: signals have weak
internal pull-ups
ICH Boot BIOS select

PCH_GPIO17 PCH_GPIO48 Description
(INT PU) (INT PU) Boot BIOS Location IRQ
PIRQA USB UHCI Controller #1, #4
0 1 SPI
1 0 PCI PIRQB AC'97 Codec; option for SMBUS
1 1 LPC (CURRENTLY USE)
PIRQC USB UH Controller #3; SATA/IDE Native Mode
A16 SWAP Override strap PIRQD USB UHCI Controller #2
PIRQE Internal LAN; Option for SCI, TCO, HPET#0,1,2

PCH_A16WP Low = A16 swap override enabled
(INT PU) High = Default PIRQF Option for SCI, TCO, HPET#0,1,2
A A
PIRQG Option for SCI, TCO, HPET#0,1,2
PIRQH USB EHCI Controller; Option for SCI, TCO, HPET#0,1,2 Quanta Computer Inc.
PCI_GNT#2 Internal PU
PROJECT : ZE7
Should not be PD Size Document Number Rev
1B
TigerPoint PCI
5 4 3 2 1
5 4 3 2 1

+3V_S5
PCLK_SMB R378 8.2K/J_4

U22D TGP PDAT_SMB R383 8.2K/J_4
PM_BATLOW# R402 8.2K/J_4
T18 AA5 T15 BM_BUSY# DNBSWON# R431 *10K/J_4
LDRQ1#/GPIO23 BM_BUSY#/GPIO0
R90 33/J_4 ACZ_BITCLK_AUDIO_R [25,27] LAD0 V6 W16 PCH_GPIO6 T20 EC_SMI# R49 10K/J_4
LAD0/FWH0 GPIO6
LPC
[20] ACZ_BITCLK_CODEC
R93 90.9/F_4 [25,27] LAD1 AA6 W14 PCH_GPIO7 T19 SYS_RST# R375 10K/J_4
[5] ACZ_BITCLK_CPU Y5
LAD1/FWH1 GPIO7
K18 PCH_GPIO8
<20101105> GPIO12 for A3-test CLKREQ setting SMBALERT# R379 10K/J_4
[25,27] LAD2 LAD2/FWH2 GPIO8
[25,27] LAD3 W8 H19 PCH_GPIO9 GPIO12 Command: For CLK Gen Byte5 CLKREQ# strap SMB_LINK_ALERT# R394 10K/J_4
LAD3/FWH3 GPIO9
2011/4/28 For EMI Sam request C136 T21 Y8 M17 EC_SMI# EC_SMI# [27] Pull-high: 0x58 -> SRC2/4/6 PCIE_WAKE# R404 10K/J_4
LDRQ0# GPIO10
*30P/50V_4 [25,27] LFRAME# Y4 A24 PCH_GPIO12 Pull-low: 0x00 -> SRC1/3/5 SMLINK1 R418 10K/J_4
LFRAME# GPIO12
D GPIO13 C23 PCH_GPIO13 SMLINK0 R420 10K/J_4 D
ACZ_BITCLK_AUDIO_R P6 P5 PCH_GPIO14 <20101108> GPIO13 for A3-test LAN chip selection ICH_RI# R422 10K/J_4
ACZ_RST#_AUDIO_R HDA_BIT_CLK GPIO14
U2 E24 PCH_GPIO15 Pull-high -> for Atheros LAN AR8158 PCH_GPIO14 R28 10K/J_4
AUDIO
HDA_RST# GPIO15
[5] ACZ_SDINO W2 AB20 PM_DPRSLPVR T38 PCH_GPIO15 R403 10K/J_4
V2
HDA_SDI0 DPRSLPVR
Y16 Pull-down -> for Realtek LAN RTL8105TA-VC-CG PCH_GPIO9 R380 10K/J_4
[20] ACZ_SDIN1 HDA_SDIN1 STP_PCI# PM_STPPCI# [2]
P8 AB19 <20110607> PU to +3V_S5 for GPIO12/13 no use to PCH_GPIO8 R393 10K/J_4
HDA_SDIN2 STP_CPU# PM_STPCPU# [2]
ACZ_SDOUT_AUDIO_R AA1 R3 PCH_GPIO24 PCH_GPIO12 R407 10K/J_4
R452 33/J_4 ACZ_RST#_AUDIO_R
ACZ_SYNC_AUDIO_R HDA_SDOUT GPIO24 T35 follow checklist v1.0
[20] ACZ_RST#_CODEC
R454 90.9/F_4 Y1 C24 DMI_AC_ENABLE PCH_GPIO13 R382 10K/J_4
14M_ICH HDA_SYNC GPIO25
[5] ACZ_RST#_CPU
[2] 14M_ICH AA3 CLK14 GPIO26 D19 PCH_GPIO26 T8
GPIO27 D20 PCH_GPIO27 T10
U3 F22 PCH_GPIO28
EPROM
EE_CS GPIO28 T6
R461 33/J_4 ACZ_SDOUT_AUDIO_R AE2 AC19 CLKRUN# CLKRUN# [27]
EE_DIN CLKRUN#
[20] ACZ_SDOUT_CODEC
R472 90.9/F_4 T6 U14 PCH_GPIO33 T15 Follow CRB [11,12,14] VCC3_VCC3
EE_DOUT GPIO33
[5] ACZ_SDOUT_CPU <20090529(A1A)_Checklist Rev0.7> V3 AC1 BOARDID0
EE_SHCLK GPIO34
If integrated LAN is not used AC23 BOARDID1
GPIO38
R451 33/J_4 ACZ_SYNC_AUDIO_R T4 AC24 BOARDID2 MCH_SYNC# R471 1K/F_4
[20] ACZ_SYNC_CODEC LAN_RST# tie it to GND. P7
LAN_CLK GPIO39 CLKRUN# R464 8.2K/J_4
R468 90.9/F_4 LANR_STSYNC
[5] ACZ_SYNC_CPU B23 AB22 H_PWRGD H_PWRGD [6,16]
BM_BUSY# R467 10K/J_4
C348 6P/50V_4 AA2
LAN_RST# CPUPWRGD/GPIO49 Stuff -> Unuse thermal sensor THERM_ALERT# R465 10K/J_4
LAN
LAN_RXD0 Unstuff -> Use thermal sensor
AD1 LAN_RXD1 THRM# AB17 THERM_ALERT# THERM_ALERT# [5,6,27]
<20110516_DGv1.5> AC2 V16 HWPG HWPG [2,16,27]
LAN_RXD2 VRMPWRGD
MISC
Change ACZ BITCLK/RST/SDOUT/SYNC to CPU RES from 33ohm to 90.9ohm R434 W3 AC18 MCH_SYNC# DMI_AC_ENABLE R401 1K/J_4
32.768KHz,+-20PPM LAN_TXD0 MCH_SYNC#
10M/J_4 T7 E21 DNBSWON# DNBSWON# [16,27]
Y4 LAN_TXD1 PWRBTN#
U4 H23 ICH_RI# TPT_PWROK R495 10K/J_4
LAN_TXD2 RI#
G22 T5
1
RTC_X1 W4 SUS_STAT#/LPCPD#
D22 SUSCLK EC_RSMRST# R460 10K/J_4
RTC
RTCX1 SUSCLK SUSCLK [27]
C349 6P/50V_4 RTC_X2 V5 G18 SYS_RST#
RTCRST# RTCX2 SYS_RESET#
T5 G23 PLT_RST#
RTCRST# PLTRSTB
WAKE# C25 PCIE_WAKE# PCIE_WAKE# [22,25]
SMBALERT# E20 T8 SM_INTRUDER# VCCRTC
PCLK_SMB SMBALERT#/GPIO11 INTRUDER#
H18 SMBCLK PWROK U10 TPT_PWROK TPT_PWROK [16]
SMB
PDAT_SMB E23 AC3 EC_RSMRST# EC_RSMRST# [16,27] SM_INTRUDER# R473 1M/F_6
SMB_LINK_ALERT# SMBDATA RSMRST#
H21 SMLALERT# INTVRMEN AD3 ICH_INTVRMEN
SMLINK0 F25 J16 SPKR [20] ICH_INTVRMEN R458 332K/F_4
SMLINK1 SMLINK0 SPKR
F24
SMLINK1
H20 SUSB# SUSB# [16,27]
SLP_S3#
T36 R2 E25 SUSC# SUSC# [16,27]
SPI_MISO SLP_S4#
C T37 T1 F21 T12 C
SPI_MOSI SLP_S5#
SPI
T14 M8 R107 *56/F_4 +1.05V
SPI_CS#
T17 P9 B25 PM_BATLOW#
SPI_CLK BATLOW#
T16 R4 SPI_ARB DPRSTP# AB23 ICH_DPRSTP_R# R108 *0/short_4 ICH_DPRSTP# [6]
DPSLP# AA18 H_DPSLP# H_DPSLP# [6]
RSVD31 F20
Tiger Point
TPT Power OK (CLG) Platform Reset (CLG)

+3V
+3V C338 *0.1U/10V_4
U21
5
C144 0.1U/10V_4
PLT_RST# 2 *TC7SH08FU
U4 <20110426 (G1A)> 4 PLTRST# [6,16,22,25,26,27]
5
Add 0.1uF CAP to prevent PWROK glitch issue 1

HWPG 2 TC7SH08FU
4 TPT_PWROK
3
[5,8,16,27] ECPWROK 1 R395
B B
C143 100K_4
3
0.1U/10V_4
R417 0/J_4
R101 *0/J_4
RTC (RTC) Clock GEN I2C Level Shift Mother Board ID (CLG)
+3VPCU VCCRTC
D16 C222
+3V ACZ_SDOUT ACZ_SYNC
+3V
(INT PD) (INT PD) Description
CH500H-40 1U/10V_6
D15 R211 R374 0 0 * 4 x 1s

VCCRTC_3 RTCRST# R513 *0/J_4 RTCRST#_EC [27] 8.2K/J_4
2
PCH: +3V_S5 CLK GEN: +3V R92 R462 R457

CH500H-40 20K/F_6 G1 *10K/J_4 *10K/J_4 *10K/J_4 1 0 Reserved
1
C223 [25] PCLK_SMB 3 1 SMBCK1 [2,4,25]

R254 1U/10V_6 0 1 Reserved
1K/J_4 *SHORT_PAD 2N7002K BOARDID0
2
Q38 BOARDID1
BOARDID2 1 1 1 x 4s(1 port/4 lanes)
+5V_S5
20MIL 20MIL R87 R463 R469
+3V
10K/J_4 10K/J_4 10K/J_4 INTVRMEN
A VCCRTC_4 1 3 VCCRTC_1 R218 2K/F_4 VCCRTC_2 R217 2K/F_4 A
Enable internal VccSus1_5 VRM
Q27 1
METR3904-G (default)
2
R216 R376 <20110428 (G1A)>

8.2K/J_4 Stuff 10K PD resistors from ZE7 A2-stage 0 Disable
2
68.1K/F_4 PCH: +3V_S5 CLK GEN: +3V

1
3 1 SMBDT1 [2,4,25]
[25] PDAT_SMB
ML1220 Coin type

R215 2N7002K Quanta Computer Inc.
Q37
CN5 AHL03001406 Maxell (HML) 18mAH 150K/F_4
PROJECT : ZE7
RTC SOCKET
AHL03001424 FDK (SAY) 15mAH
2

AHL03017100 Panasonic (MAT) 17mAH 1B
TPT ACZ/GPIO/RTC
5 4 3 2 1
1
14
Tiger Point (CLG)
D36 RB500V-40
+3V
<Layout note>
VCC5_VCC5REF R390 100/F_4
Place 0402 caps close to ball +5V
Place 0603/0805 caps close to ICH C333 1U/10V_4
D4 RB500V-40
+3V_S5
TGP
R37 10/F_4
+5V_S5
U22E RVCC5_VCC5REF_SUS
6mA F12 C351 .1U/10V_4

VCC5REF
VCC1.5_SATAPLL L19 *0/short_6
+1.5V
10mA F5 C133 .1U/10V_4
VCC5REF_SUS
45mA Y6 C358 .1U/10V_4 C147
VCCSATAPLL C355 .01U/25V_4 10U/10V_8
6uA VCCRTC AE3 VCCRTC
24mA Y25 VCC1.5_VCCDMIPLL L20 *0/short_6
VCCDMIPLL +1.5V
C151 .01U/25V_4
10mA VCCUSBPLL F6
C150
*4.7U/6.3V_6
14mA W18 VCCP_VCC1_05

V_CPU_IO
1.422A AA8 VCC1.5_VCC1.5 R120 *0/short_6

VCC1_5_1 +1.5V
M9 C127 .1U/10V_4
VCC1_5_2 C84 .1U/10V_4
VCC1_5_3 M20
A N22 C76 1U/6.3V_4 A
VCC1_5_4 C72 1U/6.3V_4
C157 4.7U/10V_8
POWER
0.955A J10 VCCP_VCC1_05 R106 *0/short_6

VCC1_05_1 +1.05V
K17 C119 1U/6.3V_4
VCC1_05_2 C102 1U/6.3V_4
VCC1_05_3 P15
V10 C137 4.7U/10V_8
VCC1_05_4
0.216A H25 VCC3_VCC3 R503 *0/short_6 +3.3V_PRIME

VCC3_3_1 C135 1U/6.3V_4
VCC3_3_2 AD13
F10 C64 1U/6.3V_4
VCC3_3_3 VCC3_VCC3 [11,12,13]
G10 C74 1U/6.3V_4
VCC3_3_4 C107 .1U/10V_4
VCC3_3_5 R10
T9 C121 .1U/10V_4
VCC3_3_6
0.092A F18 RVCC3_VCCSUS3 R430 *0/short_6 +3V_S5

VCCSUS3_3_1 C97 1U/6.3V_4
VCCSUS3_3_2 N4
K7 C70 1U/6.3V_4
VCCSUS3_3_3 C57 .1U/10V_4
VCCSUS3_3_4 F1
C69 *10U/10V_8
LAYOUT NOTE: place 10U CAP close to pin F18

5
Tiger Point
PROJECT : ZE7
1B
TigerPoint Power
1
1
15
Tiger Point (CLG)
U1LB
U22F TGP
VSS01 A1
VSS02 A25
VSS03 B6
VSS04 B10
VSS05 B16
VSS06 B20
VSS07 B24
VSS08 E18
VSS09 F16
VSS10 G4
VSS11 G8
VSS12 H1
VSS13 H4
VSS14 H5
VSS15 K4
VSS16 K8
VSS17 K11
VSS18 K19
VSS19 K20
VSS20 L4
VSS21 M7
VSS22 M11
VSS23 N3
VSS24 N12
VSS25 N13
VSS26 N14
VSS27 N23
VSS28 P11
VSS29 P13
VSS30 P19
VSS31 R14
VSS32 R22
VSS33 T2
VSS34 T22
VSS35 V1
A V7 A
VSS36
VSS37 V8
VSS38 V19
VSS39 V22
VSS40 V25
VSS41 W12
VSS42 W22
VSS43 Y2
VSS44 Y24
VSS45 AB4
VSS46 AB6
VSS47 AB7
VSS48 AB8
VSS49 AC8
VSS50 AD2
VSS51 AD10
VSS52 AD20
VSS53 AD24
VSS54 AE1
VSS55 AE10
VSS56 AE25
VSS57 G24
VSS58 AE13
VSS59 F2
RSVD32 AE16
Tiger Point

PROJECT : ZE7
1B
TigerPoint GND
1
5 4 3 2 1
Power Sequence Connector 30pin (CPU) 16
CN17
D D
1 2 NBSWON#
NBSWON# [24,27]
S5_ON 3 4 +5V_S5
[27,30,35] S5_ON
+3V_S5 5 6 EC_RSMRST#
EC_RSMRST# [13,27]
DNBSWON# 7 8 SUSC#
[13,27] DNBSWON# SUSC# [13,27]
SUSB# 9 10 SUSON
[13,27] SUSB# SUSON [27,32,34]
+1.5VSUS 11 12 MAINON
MAINON [27,32,33,34]
+5V 13 14 +1.5V
+1.05V 15 16 HWPG_1.05V
HWPG_1.05V [31,33,34]
+3.3V_PRIME_ON 17 18 +VCC_CORE
[27,31,34] +3.3V_PRIME_ON
+3.3V_PRIME 19 20 +1.8V
HWPG 21 22 ECPWROK
[2,13,27] HWPG ECPWROK [5,8,13,27]
TPT_PWROK 23 24 H_PWRGD
[13] TPT_PWROK H_PWRGD [6,13]
PLTRST# 25 26
[6,13,22,25,26,27] PLTRST#
27 28
29 30
31 32
*30pin POWER SEQ CONN
C C
1 GND 11 +1.5VSUS 21 HWPG

2 NBSWON# 12 MAINON 22 ECPWROK
3 S5_ON 13 +5V 23 TPT_PWROK
4 +5V_S5 14 +1.5V 24 H_PWRGD
5 +3V_S5 15 +1.05V 25 PLTRST#
6 RSMRST# 16 HWPG_1.05V 26 RESERVE
7 DNBSWON# 17 VRON 27 RESERVE
8 SUSC# 18 +VCC_CORE 28 RESERVE
9 SUSB# 19 +3.3V_PRIME 29 RESERVE
10 SUSON 20 +1.8V 30 RESERVE
B B
A A

PROJECT : ZE7
1B
Cedarview XDP
5 4 3 2 1
5 4 3 2 1
17
HDMI (HDM)
Level Shifter motherboard topology for max data rate of 1.65Gb/s

<20101209> Change to DFHS19FR015 by ME design change
Close to HDMI connector
CN16
+3V HDMITX2P_MOS R200 620/F_4 TX2_HDMI+ +3V HDMITX0P_MOS R181 620/F_4 TX0_HDMI+ SHELL1 20
TX2_HDMI+
3
[5] TX2_HDMI+ 1 D2+
R195 620/F_4 TX2_HDMI- R177 620/F_4 TX0_HDMI- 2 D2 Shield
D TX2_HDMI- D
[5] TX2_HDMI- 3 D2-
TX1_HDMI+ 4
2 2 [5] TX1_HDMI+ D1+
5 D1 Shield
TX1_HDMI- 6
Q24 Q18 [5] TX1_HDMI- D1-
TX0_HDMI+ 7
2N7002K 2N7002K [5] TX0_HDMI+ D0+
8 D0 Shield
TX0_HDMI-
1
1
R233 100K/J_4 R190 100K/J_4 [5] TX0_HDMI- 9 D0- GND 23
<20100115(B2A)> TX3_HDMI+ 10
[5] TX3_HDMI+ CK+
11 22
Add fuse to meet IEC 60950-1 TX3_HDMI- 12
CK Shield GND
HDMITX2N_MOS HDMITX0N_MOS [5] TX3_HDMI- CK-
2nd certificationand.
3
3
13 CE Remote
14 NC
HDMI_DDC_CLK 15
HDMI_DDC_DATA DDC CLK
16 DDC DATA
2 2 F2 17 GND
+5V 2 1 +5V_HDMI 18
Q25 Q19 +5V
HDMI_HPD 19
2N7002K 2N7002K HP DET
1.1A 8V POLY(SMD1206P110TFT) 21
C367 SHELL2
1
1
R245 100K/J_4 R192 100K/J_4
0.22U/6.3V_4 HDMI connector
R142
+3V +3V 1M/F_6
HDMITX1P_MOS R189 620/F_4 TX1_HDMI+ HDMITX3P_MOS R174 620/F_4 TX3_HDMI+
3
3
R185 620/F_4 TX1_HDMI- R171 620/F_4 TX3_HDMI-
<20101001> Change from 100K to 1M ohm (follow DG0.7)
2 2
Q22 Q16
2N7002K 2N7002K
1
1
C R209 100K/J_4 R176 100K/J_4 C
HDMITX1N_MOS HDMITX3N_MOS +3V

3
3
2 2 R126
10K/J_4
Q23 Q17
2N7002K 2N7002K
HDMI_DDI0_HPD#
[5] HDMI_DDI0_HPD#
1
3
R515 100K/J_4 R180 100K/J_4
2 HDMI_HPD
Q7
2N7002K
R138
1
*100K_4
EMI reserve for HDMI (EMC) ESD Protect (HDM)

B SDVO I2C Control (HDM) <20100909_Jennifer> Change R500/ R502
from 1.5k to 2.2k to follow CRB.
B
Close to HDMI Connector Close to HDMI Connector
+3V U6
R500 2.2K/J_4 D39 RB500V-40 +5V HDMI_DDC_DATA 1 10 HDMI_DDC_DATA
R534 2.2K/J_4 TX2_HDMI+ HDMI_DDC_CLK 1 10 HDMI_DDC_CLK
2 2 9 9
3 GND_3/8
2
R196 4 7
*100/F_4 HDMI_HPD 4 7 HDMI_HPD
The DDC signals are rated at 5V at connector. The 5 5 6 6
1 3 HDMI_DDC_CLK_L L22 BLM18AG601_6 HDMI_DDC_CLK passgate can also be used to protect against TX2_HDMI-
[5] DDI0_HDMI_SCL
*RClamp0524P
Q13 back-power TX1_HDMI+
2N7002K when computer is OFF but the display is ON and still U7
+3V R502 2.2K/J_4 D41 RB500V-40 C180 pulled up to 5 V. R187 TX0_HDMI+ 1 10 TX0_HDMI+
+5V 1 10
*0.1u/10V_4 *100/F_4 TX0_HDMI- 2 9 TX0_HDMI-
R535 2.2K/J_4 TX1_HDMI- 2 9
3 GND_3/8
TX3_HDMI+ 4 7 TX3_HDMI+
4 7
2
TX0_HDMI+ TX3_HDMI- 5 6 TX3_HDMI-

5 6
1 3 HDMI_DDC_DATA_L L23 BLM18AG601_6 HDMI_DDC_DATA R179 *RClamp0524P
[5] DDI0_HDMI_SDA
*100/F_4
Q14 TX0_HDMI- U9
2N7002K C183 TX2_HDMI+ 1 10 TX2_HDMI+
TX3_HDMI+ TX2_HDMI- 1 10 TX2_HDMI-
*0.1u/10V_4 2 2 9 9
3 GND_3/8
R173 TX1_HDMI+ 4 7 TX1_HDMI+
*100/F_4 TX1_HDMI- 4 7 TX1_HDMI-
5 5 6 6
TX3_HDMI-
*RClamp0524P
A A

PROJECT : ZE7
1B
HDMI
5 4 3 2 1
5 4 3 2 1
HALL IC (HSR) LCD POWER SWITCH (LDS) CAMERA POWER (CCD) 0.15A 18
Irush=1.5A
+3V CCD_POWER
AVG=0.24A
+3VPCU R91 *100K_4 <EMI>
R19 *0/short_4
LCDVCC R344 *0/short_6 CCD_POWER
LCDVCC_1 R349 *0/short_8 USBP2-_R

R536 [10] USBP2-
USBP2+_R C309 4.7U/10V_8
+
47/F_6 [10] USBP2+
D44 *VPORT_6 D7 *VPORT_6 C319 C324 C327 C318 C310 C308 1000P/50V_4
2 1 1 2 LID# 1 2 R20 *0/short_4
.1U/10V_4 *2.2U/6.3V_6 .1U/10V_4 .01U/16V_4 4.7u/10V_8 C312 *0.1U/10V_4
<G1A>
D +3V Change C138 from 4.7U to 1U D
3
MR1
C138
1U/10V_6
APX9132H AI-TRG LCD MODULE (LDS)
R113 20mA*24pcs=480mA
10K_4 VIN R13 0/J_6
+3V
C18 C19
D8 RB500V-40 R345 *EDP@0/J_8 R359 LVDS@0/J_4 TXLOUT1_R+_EDP_AUXP
LID# [27] [5] TXLOUT1+ 4.7U/25V_8 0.1U/50V_6 CN1
R358 LVDS@0/J_4 TXLOUT1_R-_EDP_AUXN
[5] TXLOUT1- V_BLIGHT 1
U19 1
+3V C328 DDI1_AUX_DP C326 *[email protected]/16V_4 TXLOUT1_R+_EDP_AUXP 2 2
[5] DDI1_AUX_DP LCDVCC 3
4.7U/6.3V_6 6 1 DDI1_AUX_DN C325 *[email protected]/16V_4 TXLOUT1_R-_EDP_AUXN 3
IN OUT [5] DDI1_AUX_DN 4
4
DISPON 4 2 Refer to INTEL DG co-layout IVO panel : 21.W/5V=0.42A +3V 5
5
IN GND CCD_POWER CCD_POWER 6
R26 0/J_6 +5V_LCD 6
R350 0/J_4 +5V 7
[5] INT_LVDS_DIGON 3 5 7
ON/OFF GND
3
R118 8 8
10K_4 9 9
C22 C21 USBP2-_R 10
R354 IC(5P) G5243AT11U R348 LVDS@0/J_4 TXLOUT2_R+_EDPTX0+ 10
[5] TXLOUT2+ USBP2+_R 11
2 BL# 100K/J_4 R347 LVDS@0/J_4 TXLOUT2_R-_EDPTX0- *[email protected]/25V_8 *[email protected]/50V_6 11
[5] TXLOUT2- 12
Q4 12
DISPON 13
DDI1_TX0_DP C314 *[email protected]/16V_4 TXLOUT2_R+_EDPTX0+ 13
[5] DDI1_TX0_DP LCD_VADJ
3
2N7002K DDI1_TX0_DN C313 *[email protected]/16V_4 TXLOUT2_R-_EDPTX0- 14

[5] DDI1_TX0_DN 14
15
TXLOUT2_R-_EDPTX0-_R1 15
1
16
Refer to INTEL DG co-layout TXLOUT2_R+_EDPTX0+_R1 16
2 Reserve for IVO panel 17
17
INT_LVDS_BLON [5] 18
Q6 18
TXLOUT1_R-_EDP_AUXN_R1 19
TXLOUT1_R+_EDP_AUXP_R1 19
2N7002K R131 20
20
R352 LVDS@0/J_4 TXLOUT0_R+_EDPTX1+ 21 21
TXLOUT0_R-_EDPTX1-_R1
1
[5] TXLOUT0+ 22
100K_4 R353 LVDS@0/J_4 TXLOUT0_R-_EDPTX1- 22
[5] TXLOUT0- TXLOUT0_R+_EDPTX1+_R1
3
23 23
DDI1_TX1_DP C315 *[email protected]/16V_4 TXLOUT0_R+_EDPTX1+ 24 24
[5] DDI1_TX1_DP TXLCLKOUT-_R_EDPTX2-_R1 25
2 DDI1_TX1_DN C316 *[email protected]/16V_4 TXLOUT0_R-_EDPTX1- 25
EC_FPBACK# [27] [5] DDI1_TX1_DN TXLCLKOUT+_R_EDPTX2+_R1 26
26
Q5 27 31
Refer to INTEL DG co-layout LCD_CLK_R_EDPTX3+ 28
27 31
32
C DTC144EUA 28 32 C
LCD_DATA_R_EDPTX3-
1
29 33
+3V_EDP_HPD 29 33
30 34
30 34
LCD CONN
R357 LVDS@0/J_4 TXLCLKOUT+_R_EDPTX2+
[5] TXLCLKOUT+
R356 LVDS@0/J_4 TXLCLKOUT-_R_EDPTX2-
[5] TXLCLKOUT-
DDI1_TX2_DP C323 *[email protected]/16V_4 TXLCLKOUT+_R_EDPTX2+
[5] DDI1_TX2_DP <C-test> Chang to DFHS30FR048 for SMT ME Peter request
DDI1_TX2_DN C322 *[email protected]/16V_4 TXLCLKOUT-_R_EDPTX2-
[5] DDI1_TX2_DN
Refer to INTEL DG co-layout
Single-ended 50ohm
R371 LVDS@0/J_4 LCD_CLK_R_EDPTX3+ Trace Impedance use
[5] LCD_CLK
R370 LVDS@0/J_4 LCD_DATA_R_EDPTX3-
[5] LCD_DATA single-ended 50ohm and differential 90ohm
CRT(CRT) [5] DDI1_TX3_DP
[5] DDI1_TX3_DN
DDI1_TX3_DP
DDI1_TX3_DN
C332
C331
*[email protected]/16V_4
*[email protected]/16V_4
LCD_CLK_R_EDPTX3+
LCD_DATA_R_EDPTX3-
Differential 90ohm Refer to INTEL DG co-layout
<20100115(B2A)>
Add F1(fuse) to meet IEC 60950-1 2nd certificationand. eDP (LDS)
C38 .1U/10V_4 +3V +3V
F1
2 1 CRTVDD5
+5V
1.1A 8V POLY(SMD1206P110TFT) R365 R23
<Layout note> *EDP@100K_4 *EDP@1K/J_4
PLACE inductances 90 DEGREE FROM EACH OTHER
R27 *EDP@0/J_4
[5] DDI1_HPD#
B TXLOUT1_R-_EDP_AUXN B
3
TXLOUT1_R+_EDP_AUXP
R366 2 DDI1_HPD
CN10 *EDP@100K_4 Q3
16
*EDP@2N7002K
R25
6 *EDP@100K/J_4
1
L14 PBY160808T-220Y-N CRT_R1 1 11 CRT_11 T2
[5] CRT_R
7
L15 PBY160808T-220Y-N CRT_G1 2 12 CRT_SDA DDI1_HPD R21 *EDP@0/J_4 +3V_EDP_HPD
[5] CRT_G
8 R22 LVDS@0/J_4 +3V_EDP_HPD
+3V
L13 PBY160808T-220Y-N CRT_B1 3 13 CRTHSYNC
[5] CRT_B
9
4 14 CRTVSYNC
R85 R84 R83 C114 C109 C108 C77 C78 C79 10
5 15 CRT_SCL
150/F_4 150/F_4 150/F_4 *10P/50V_4 *10P/50V_4 *10P/50V_4 4.7P/50V_4 4.7P/50V_4 4.7P/50V_4 R59 0/J_4 LCD_VADJ
[5] INT_LVDS_PWM
R373 *0/short_4
CRT CONN R60 *0/J_4
17
[27] CONTRAST
TXLOUT1_R+_EDP_AUXP TXLOUT1_R+_EDP_AUXP_R1 C39 *0.1U/10V_4
2nd source: 4.7P(+-0.25P) CH-4706TB01 TXLOUT1_R-_EDP_AUXN TXLOUT1_R-_EDP_AUXN_R1
R372 *0/short_4
R362 *0/short_4
TXLOUT2_R+_EDPTX0+ TXLOUT2_R+_EDPTX0+_R1
+3V
<Layout note> TXLOUT2_R-_EDPTX0- TXLOUT2_R-_EDPTX0-_R1
Close to CONN
C35
.1U/10V_4 U3 R361 *0/short_4
CRTVDD5 1 16 CRT_VSYNC1 R76 47/F_4 VSYNC_R L17 0/J_6 CRTVSYNC
VCC_SYNC SYNC_OUT2 CRT_HSYNC1 R75 47/F_4 HSYNC_R L16 0/J_6 CRTHSYNC R364 *0/short_4
A SYNC_OUT1 14 A
7 VCC_DDC
C47 0.22U/25V_6 CRT_BYP 8 C37 *10P/50V_4 CRTVDD5
BYP CRTVDD5 TXLOUT0_R-_EDPTX1- TXLOUT0_R-_EDPTX1-_R1
SYNC_IN2 15 CRT_VSYNC [5]
2 13 C131 *100P/50V_4 CRTVSYNC TXLOUT0_R+_EDPTX1+ TXLOUT0_R+_EDPTX1+_R1
+3V VCC_VIDEO SYNC_IN1 CRT_HSYNC [5]
C123 *100P/50V_4 CRTHSYNC
C36 CRT_R1 3 10 R79 R78 R363 *0/short_4
VIDEO_1 DDC_IN1 CRT_DDC_SCL [5]
.1U/10V_4 CRT_G1 4 11 2.2K/J_4 2.2K/J_4 C85 *100P/50V_4 CRT_SCL
VIDEO_2 DDC_IN2 CRT_DDC_SDA [5]
CRT_B1 5 R368 *0/short_4
VIDEO_3 CRT_SCL C86 *100P/50V_4 CRT_SDA
9
6 GND
DDC_OUT1
DDC_OUT2 12 CRT_SDA
TXLCLKOUT+_R_EDPTX2+ TXLCLKOUT+_R_EDPTX2+_R1
IP4772_Rout=10ohm Pull up at CPU side TXLCLKOUT-_R_EDPTX2- TXLCLKOUT-_R_EDPTX2-_R1
PROJECT : ZE7
R367 *0/short_4 1B
CRT/LVDS/EDP
5 4 3 2 1
5 4 3 2 1
<20110214(E1A)>
KEYBOARD (KBC) Change CP1~CP6 footprint from BLUETOOTH (BTM) 19
8p4r-0402-smt to 8P4R, for SMT open issue.
<EMI>
CN2
1 MX7 MX7 7 8
MX7 [27]
2 MX6 MX6 5 6
MX6 [27] CP4
3 MX5 MX5 3 4
D MX5 [27] *220P_8P4R D
4 MY0 MY0 1 2
MY0 [27] Q33
5 MY1 MY1 7 8
MY1 [27]
6 MY2 MY2 5 6 CN7
MY2 [27] CP1 61mA BT_POWER
7 MX4 MX4 3 4 +3V 1 3
MX4 [27] *220P_8P4R 5
8 MY3 MY3 1 2
MY3 [27] 4 6
9 MY4 MY4 7 8 C283 BT@AO3413
MY4 [27] [10] USBP6+ 3
10 MY5 MY5 5 6
MY5 [27] CP3 [10] USBP6-
2
MY6 MY6 *[email protected]/10V_4 BT_LED 2 7
11 MY6 [27] 3 4 *220P_8P4R 1
12 MY7 MY7 1 2 + T30
MY7 [27]
13 MY8 MY8 7 8 R282 C246 C248 BT@BT_CONN
MY8 [27]
14 MX3 MX3 5 6 [email protected]/25V_6 BT@1000p/50V_4
MX3 [27] CP2 [25,27] BT_POWERON#
15 MY9 MY9 3 4
MY9 [27] *220P_8P4R
16 MX2 MX2 1 2 BT@10K/J_4
MX2 [27]
17 MX1 MX1 7 8
MX1 [27]
18 MY10 MY10 5 6 C270
MY10 [27] CP6
19 MY11 MY11 3 4 *BT@1000p/50V_4
MY11 [27] *220P_8P4R
20 MX0 MX0 1 2
MX0 [27]
21 MY12 MY12 7 8
MY12 [27]
22 MY13 MY13 5 6
MY13 [27] CP5
23 MY14 MY14 3 4
MY14 [27] *220P_8P4R
24 MY15 MY15 1 2
MY15 [27]
0603 size
C 25 C
26
KB CONN
TOUCH PAD (TPD)

Left Button
+5V_TP
SW2 3mA
3 1 TP_L# +5V_TP +5V
4 2
1
5
6 TP switch D43 <EMI>
CN3 R24 R18
*14V/38V/100P_4
4.7K/J_4 4.7K/J_4 L9 3A/120ohm_8
2
B B
1 TP_R# CX121T30001:3A/120ohm_8
2 <EMI>
TP_L#
3 TPDATA_CN L8 0.4A/120ohm_6
4 TPDATA [27]
TPCLK_CN L7 0.4A/120ohm_6
7 5 TPCLK [27]
+5V_TP C30
8 6 CX08T121000:0.4A/120ohm_6
CX121T04000:0.4A/120ohm_6 .1U/10V_4
TP_CONN
C34 C33
10P/50V_4 10P/50V_4 Right Button

SW3
3 1 TP_R#
4 2
1
5
6 TP switch D42
*14V/38V/100P_4
2
A A

PROJECT : ZE7
1B
KB/BT/TP/LED/Power Connector
5 4 3 2 1
5 4 3 2 1
HPR
Codec ALC271X (ADO) HPL EARPHONE (AMP) 20
MIC1-VREFO-L
MIC2-VREFO
MIC1-VREFO-R
MIC2-VREFO R244
ADOGND 2.2K/J_4
Place near codec MIC2_R2 2.2U/6.3V_6 C240
INT_AMIC-VREFO C208 10U/6.3V_6 ADOGND MIC2_L2 2.2U/6.3V_6 C244 1K/J_4 R243 COMBO_MIC
C206
1
+
2.2U/6.3V_6 Place next to pin 27 <20100917> Add 22k PD by FAE R236 D37
suggestion for discharing 22K/F_4 *14V/38V/100P_4
D D
2
C209 + C212 C210
C213 ADOGND
2.2U/6.3V_6 0.1U/10V_4 *10U/6.3V_6 +5VA
+5VA + MIC2-JD#
ADOGND ADOGND
2.2U/6.3V_6
3
Q26
C217 C207
2SK3018
10U/6.3V_6 .1U/10V_4
36
35
34
33
32
31
30
29
28
27
26
25
U11 C227 C219
2 22K/F_4 R235
.1U/10V_4 10U/6.3V_6
CBP
CPVEE
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
LDO-CAP
AVSS1
AVDD1
CBN
HP-OUT-R
MIC1-VREFO-R
VREF
ADOGND ADOGND
ANALOG
Place next to pin 38 C231
1
Spilt by AGND 37
AVSS2 LINE1-R
24 ADOGND
*10U/6.3V_8
Place next to pin 25
38 23
AVDD2 LINE1-L
R220 *0/short_6 +5VPVDD1 39 22 MIC1_R1
+5V PVDD1 MIC1-R ADOGND
L_SPK+ 40 21 MIC1_L1 Normal Open Jack
C230 C220 C221 C226 SPK-L+ MIC1-L
L_SPK- 41 20
Placement near Audio Codec CN15
4.7U/6.3V_6.1U/10V_4 4.7U/6.3V_6 .1U/10V_4 SPK-L- MONO-OUT
3
42 19 R226 20K/F_4 ADOGND 6
PVSS1 JDREF HPL R172 47/F_4 HPL-1 L21 0_6 HPL_SYS 1
43
PVSS2
ALC271X-VB3-GR Sense-B
18 SENSEB R232 20K/F_4 MIC2-JD#
HPR HPR-1 HPR_SYS
AMIC2_INT R497 47/F_4 L39 0_6 2
Place next to pin 39 R_SPK- 44 17 MIC2_R2 4
SPK-R- MIC2-R HP_JD#
C204 <20110428> Add 1n PD to AGND for amic 5
R_SPK+ MIC2_L2 R496 R152 C363 C174
1
45 16 UNIVERSAL JACK
SPK-R+ MIC2-L
1
Spilt by PGND noise depressing by FAE Vic suggestion 010030FR006G119ZR
+5VPVDD2 LIN2_INT_R1 C237 1n/50V_4 2200P/50V_4
+5V R268 *0/short_6 46 15 1u/16V_6 *1K/J_4 *1K/J_4 2200P/50V_4 D11
PVDD2 LINE2-R D38 D40 *14V/38V/100P_4
GPIO0/DMIC-DATA
EAPD# GPIO1/DMIC-CLK LIN2_INT_L1 C239
2
47 14 1u/16V_6 *14V/38V/100P_4 *14V/38V/100P_4
2
SPDIFO2/EAPD LINE2-L ADOGND
C234 C258 C247 C243 Spilt by DGND
SENSEA R249 39.2K/F_4 HP_JD#
SDATA-OUT
48 13
4.7U/6.3V_6.1U/10V_4 4.7U/6.3V_6 .1U/10V_4 SPDIFO Sense A
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
49 R257 20K/F_4 MIC1_JD# ADOGND ADOGND ADOGND ADOGND
DVDD1
DVSS2
PGND
SYNC
ANALOG <20101103> Add EC PWM control
PD#
for beep sound volumn control

C C
Place next to pin 46 ALC271X-VB3-GR
1
10
11
12
PCBEEP dont coupling any signals if possible
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion
1.6Vrms R273 47K/J_4
+3V R283 *0/short_6 +AZA_VDD
PCBEEP_C C260 1U/10V_6 BEEP_1 R274 47K/J_4
PCBEEP
SPKR
[27]
[13]
MIC (AMP)
C264 R267
C256 C263 4.7K/J_4 If either HDA device io power use +1.5V,
.1U/10V_4 4.7U/6.3V_6 100P/50V_4 all device IO power change to +1.5V
MIC1-VREFO-R
MIC1-VREFO-L
Place next to pin 1
+AZA_VDD_R R266 *0/short_6 +AZA_VDD
DMIC_DAT
T54 DMIC_CLK R453 R178
T55 4.7K/F_4 4.7K/F_4
C252 C265
PD# ACZ_RST#_CODEC [13] Normal Open Jack

.1U/10V_4 4.7U/6.3V_6
0V : Power down Class D SPK amplifier ACZ_SYNC_CODEC [13] CN13
5V : Power up Class D SPK amplifier 3
ACZ_SDIN1_R R265 33/J_4
ACZ_SDIN1 [13] 6
Place next to pin 9 MIC1_L1 C356 4.7u/6.3V_6 MIC1_L2 R455 1K/F_4 MIC1_L3 R447 0_6 MIC1_L 1
ACZ_SDOUT_CODEC [13]
MIC1_R1 C218 4.7u/6.3V_6 MIC1_R2 R202 1K/F_4 MIC1_R3 R183 0_6 MIC1_R 2
4
ACZ_BITCLK_CODEC [13] MIC1_JD# MIC1_JD# 5
UNIVERSAL JACK
C257 *22P/50V_4
1
010030FR006G119ZR
D12 C187 C353 C201
*VPORT_6 Near CN13 *470p/50V_4 *470p/50V_4 *0.1u/16V_6
2
B ADOGND ADOGND B
Power (ADO) Internal Speaker (AMP) GND Internal Analog MIC (AMP)
Demodulation Filter
+5V Place close to Codec +5VA
DIGITAL ANALOG <20110811> For analog mic ESD protection using

L25 0/J_8
<20101115> Change to 10K by codec FAE suggestion
40mil for each signal R520 *0/J_6
R501 0/J_6 INT_AMIC-VREFO 10K/J_4 R140
CN4
CN6 AMIC2_INT AMIC2_INT_R
R_SPK+ R_SPK+_1 1K/J_4 R130
R297 *0/short_6 1
R_SPK- R290 *0/short_6 R_SPK-_1 4
2
3
1
Mute (ADO) L_SPK-
L_SPK+
R272
R242
*0/short_6
*0/short_6
L_SPK-_1
L_SPK+_1 2
1
R439
R261
R188
*0/J_6
*0/J_6
*0/J_6 C158 D9
INT_MIC
R-L-SPEAKERS R225 *0/J_6 *22P-50V_4 TVS/6pF_4
2
C275 C269 C261 C241 R175 *0/J_6
*68p/50V_6 *68p/50V_6 *68p/50V_6 *68p/50V_6 R184 *0/J_6
R441 *0/J_6
A R168 *0/J_6 ADOGND ADOGND ADOGND A
+5V <20101115> Change to 10K by codec FAE suggestion <20110706> Stuff TVS BC040201Z00 for ESD solution
R511 *Short_6
R203 0/J_6
R444 0/J_6
R285
*10K/J_4 C195 1000P/50V_4

C251 1000P/50V_4
PD# D25 RB500V-40 ACZ_RST#_CODEC
D24 RB500V-40 EAPD# ADOGND Quanta Computer Inc.

D23 RB500V-40
PROJECT : ZE7
AMP_MUTE# [27]
1B
ALC271X / AMP / SPK
5 4 3 2 1
5 4 3 2 1
USB Left (USB) 21
+5VPCU
D D
C380
U25 2A
1U/6.3V_4
IC(8P)G547E2P81U
2 8 5VUSB_1
IN1 OUT3
3 7 <Layout note>
IN2 OUT2
6 Close to CONN
USB_EN# 4
OUT1 <Layout note>3528 type H=1.9mm C377
EN + C379
1
GND <2nd Source> CH71001M687
5 .1U/10V_4
OC# USBOC#L [10,27]
100U/6.3V_3528 Left
R248 *0/short_4 CN21
G547E2P81U: Enable: Low Active /2.5A
1 6
Follow ZH9 USBP3-_CN VDD GND6
[10] USBP3- 2 5
USBP3+_CN D- GND5
[10] USBP3+ 3
D+
4 7
GND1 GND7
8
1
R253 *0/short_4 GND8
D20 D18 USB_CONN
*5V/30V/0.2P_4 *5V/30V/0.2P_4
2
C C
USB Right (USB)
+5VPCU
+3VPCU C111
4.7u/10V_6 U23 2A
R82 IC(8P)G547E2P81U
*10K/J_4 2 8 5VUSB_0
IN1 OUT3
3 7
IN2 OUT2 <Layout note>
6
USB_EN# 4 OUT1 + C26 Close to CONN C24
[27] USB_EN# EN
1
GND 220u/6.3V_7343 0.1u/10V_4
5 USBOC#R [10,27]
OC#
Right up
R15 *0/short_4
CN9
1 6
[10] USBP1- USBP1-_CN VDD GND6
2 5
G547E2P81U: Enable: Low Active /2.5A [10] USBP1+ USBP1+_CN 3
D- GND5
D+
Follow ZH9 4 7
GND1 GND7
1
R14 *0/short_4 8
GND8
D2 D3
USB_CONN
B *5V/30V/0.2p_4 *5V/30V/0.2p_4 B
2
<Layout note>
Close to CONN C73
+ C89
0.1u/10V_4 Right down
*100u/6.3V_3528
R50 *0/short_4 CN12
1 6
USBP0-_CN VDD GND6
[10] USBP0- 2 5
USBP0+_CN D- GND5
[10] USBP0+ 3
D+
4 7
GND1 GND7
8
1
1
R44 *0/short_4 GND8
D5 D6 USB_CONN
*5V/30V/0.2p_4 *5V/30V/0.2p_4
2
A A

PROJECT : ZE7
D3E
USB Port
5 4 3 2 1
5 4 3 2 1
LAN (LAN) 22
+3V_S5 +3V_LAN VDD10 R1 *0/short_4 EVDD10
1
R351 *0/short_6
Close To IC C6 C5 Close To IC Pin 13.
C1 C16 C2 1U/10V_4 0.1U/16V_4
2
1
Close to IC 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4
C304 C307 C320 C317
0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 *4.7U/10V/8
2
D D
R2 *0/short_4 CTRL12
Close To IC Pin 31.

C3
0.1U/16V_4
<20110510> Change from 27P to 33P by vendor's measure report.
C7 33P/50V_4 25MCLKX1 +3V_LAN

LAN_ACTLED#
25MCLKX2
CTRL12 GPO R6 1K/J_4 +3V_LAN CLKREQ_LAN#_R1 R342 *10K/J_4
1
R3 2.49K/F_4 RSET LAN_LINKLED#

Y1 PCIE_WAKE# R7 *10K/J_4
25MHz-LAN
EEDI/SDA R9 10K/J_4
32
31
30
29
28
27
26
25
2
U1
EECS/SCL R8 10K/J_4
CTRL12
CKXTAL2
CKXTAL1
VDD3
RSET
LEDPIN/SPICSB
EESKPIN/LED1/TCLK/SPISCK
GPOUTPIN
C4 33P/50V_4 33 GND
34 GND
35
GND
36 GND
1 24 EEDI/SDA
+3V_LAN HV EEDIPIN/TDI/SPISI/SDA
TX0P 2 23 LED3/EEDO T1
TX0N MDIP0 EEDOPIN/LED3/SPISO EECS/SCL
Pull-Up at CLK Gen side 3 MDIN0 EECSPIN/TCS/SCL 22 Int. PU in SB
TX1P 4 21 VDD10
TX1N MDIP1 VDD1 PCIE_WAKE#
5 20 PCIE_WAKE# [13,25]
C MDIN1 LANWAKEBPIN C
6 NC VDD3 19 +3V_LAN
VDD10 7 18 ISOLATE# R11 1K/J_4 +3V
R343 *0/short_4 CLKREQ_LAN#_R1 VDD1 ISOLATEBPIN R10 15K/J_4
[2] CLKREQ_LAN# 8 17
CLKREQBPIN PERSTBPIN
RTL8105TA-VC-CG
REFCLK_N
REFCLK_P
37 R12 *0/short_4
GND PLTRST# [6,13,16,25,26,27]
GNDTX
38
VDDTX
GND
1
HSON
HSOP
HSIN
39
HSIP
GND
GND
GND
GND C17
*4.7U/10V/8
2
40
41
42
9
10
11
12
13
14
15
16
[10] PCIE_TXP0
[10] PCIE_TXN0
[2] CLK_PCIE_LANP
[2] CLK_PCIE_LANN
EVDD10
C8 .1U/10V_4 PCIE_RXP0_LAN
[10] PCIE_RXP0
C14 .1U/10V_4 PCIE_RXN0_LAN
[10] PCIE_RXN0
For Rural
TRANSFORMER (LAN) RJ45 Connector (LAN)
B B
CN8
U17 U15 LAN_LINKLED# R346 *510/J_6 11
TX0P R335 0/J_4 TX0P_R X-TX0P G-
TX0N R336 0/J_4 TX0N_R
1
2
1 8
8
7 X-TX0N
1
2
1 8
8
7 C311
+3V_LAN 12
G+ GREEN
TX1P R338 0/J_4 TX1P_R 2 7 X-TX1P 2 7
3 6 3 6
TX1N R337 0/J_4 TX1N_R 3 6 X-TX1N 3 6 *0.1U/50V_8 TERM9
4 5 4 5 8
4 5 4 5 NC4/3-
*UCLAMP2512T.TCT *UCLAMP2512T.TCT 7 NC/3+
X-TX1N 6
RX-/1-
TERM9 5
NC2/2-
For Rural, stuff 0/J_4 (CS00002JB38)
For Rural, use 1/F_4 (CS-1002FB23) U16 For Normal, unstuff 0/J_4 (CS00002JB38) 4
NC1/2+
For Normal, use 0/J_4 (CS00002JB38) X-TX1P 3
TX1N_R X-TX1N RX+/1+
8 9
TX1P_R TD- TX- X-TX1P X-TX0N
7 10 2
TD+ TX+ TERM0 TX-/0-
6 11
CT CT X-TX0P
5 NC NC 12 1 TX+/0+
4 13 14
NC NC GND
3 CT CT 14 GND 13
TX0N_R 2 15 X-TX0N LAN_ACTLED# R334 *510/J_6 9
TX0P_R RD- RX- X-TX0P R339 *0/J_4 A-
1
RD+ RX+
16
C299
+3V_LAN 10
A+ AMBER
2
NS0014 LF_Bothhand R340 R341 *0.1U/50V_8 RJ45-CONN

D35
C303 C302 C300 C301 C306 75/F_8 75/F_8
*10P/50V_4 *10P/50V_4 *10P/50V_4 *10P/50V_4 0.01U/25V_4
A *P3100SBLRP A
The value should be <20110105> Will add RJ45 connector without LED type by inner document
1
0.01uF-0.4uF DFTJ08FR221 (FOX)

DFTJ08FR222 (AEC)
TERM9
Reserve for EMI request
C305 Quanta Computer Inc.

1000P/3KV_1808
PROJECT : ZE7
1B
LAN RTL8105TA-VC-CG
5 4 3 2 1
5 4 3 2 1
23
Stitching Capacitor (CLG)
For RF Request
D D
+1.05V
C145 C27
1000P/50V_4 1000P/50V_4
For CRT R/G/B Signals

VIN
C140
1U/25V_6
C C
B B
A A

PROJECT : ZE7
1B
Stitching Cap
5 4 3 2 1
5 4 3 2 1
2.5" SATA HDD (HDD) 24
D D
CN11
1
2 SATA_TXP0_C1 C340 0.01u/16V_4 SATA_TXP0 SATA_TXP0 [11]
3 SATA_TXN0_C1 C339 0.01u/16V_4 SATA_TXN0 SATA_TXN0 [11]
4
5 SATA_RXN0_C1 C342 0.01u/16V_4 SATA_RXN0
SATA_RXN0 [11]
6 SATA_RXP0_C1 C341 0.01u/16V_4 SATA_RXP0
SATA_RXP0 [11]
7
8
9
14 10
15 11 1A
16 12 5V_SATA1 R369 *0/short_8 +5V
17 13
+
C25 C23 C20 C330
MAIN_SATA
0.1U/10V_4 *0.1U/10V_4 4.7U/10V_8 *100U/6.3V_3528
C C
LED/SW (UIF)
<20110223> In S5 and battery only mode, +3V
+3V_S5 D31 1 2 *5.5V/25V/410P_4 EC will turn off PWRLED#/SUSLED# while EC is idle. PWR indicator
LED3 LED1
PWR LED 3 2 R330 33/J_4 PWRLED# [27] 2 1 R333 51/J_4
1 R331 220/F_4 LED_BLUE_TOP

SUS LED LED_AMBER/BLUE
SUSLED# [27]
D32 1 2 *5.5V/25V/410P_4
B B
+3VPCU D33 1 2 *5.5V/25V/410P_4
LED2
PWR button SW1
FULL LED 3 2 R327 33/J_4 BATLED0# [27]

3
4
2
1
NBSWON#
NBSWON# [16,27]
R328 220/F_4 5
1
1
CHG LED LED_AMBER/BLUE
BATLED1# [27] 6
Power Switch
D1
D34 *5.5V/25V/410P_4
1 2 *5.5V/25V/410P_4
2
<20110530> Change from +3V to +5V Due to there is the
internal series resister in 3G/WLAN module, cause the forward voltage of LED4 is too small
D28 1 2 *[email protected]/25V/410P_4
+5V
LED4
3G LED 3 2 R325 3G@150/F_4
3G_MINI_LED# [25]
1 R326 470/J_4
WLAN LED LED_AMBER/BLUE
WLAN_LED# [25]
D29 1 2 *5.5V/25V/410P_4
A SATALED# [11] A
<20090609(A1A)_Checklist Rev1.0>
*BSS84
Need the buffer for LED driving
2
+5V Q36
LED5 capability since the IOL is 6mA only.
HDD LED 3 1 R329 *330/J_4 1 3
*LED_BULE_SIDE
D30 1 2 *5.5V/25V/410P_4
PROJECT : ZE7
<20101229> Unstuff HDD LED 1B
SATA HDD/LED/SW
5 4 3 2 1
5 4 3 2 1
Mini Card 1 (MPC) Turn off WLAN LED when 3G module is on

+1.5V_Mini1_VDD
+3V_Mini1_VDD 25
+3V_Mini1_VDD
+3V_Mini1_VDD
4
2
+3V_Mini1_VDD RF_LED_ON R308 *0/short_4 3G_MINI_LED#
CN22 RN1
R528 *0/J_4 51 52 R302
[19,27] BT_POWERON# Reserved +3.3V
49 50 Q30 *4.7K_4P2R
2
PLTRST# R529 0/J_4 Reserved GND 4.7K/J_4 2N7002K Q32
47 48
Reserved +1.5V
2
R526 0/J_4 45 46 *2N7002E
3
1
[2] PCLK_DEBUG Reserved LED_WPAN#
43 44 WLAN_LED1# 1 3
GND LED_WLAN# WLAN_LED# [24]
41 42 WIMAX_LED# R525 *0/short_4 3 1 WL_SMDATA
+3.3Vaux LED_WWAN# [2,4,13] SMBDT1
39 40
+3.3Vaux GND
37 38 USBP7+ [10]
GND USB_D+ R314 *0/J_4
D 35 36 USBP7- [10] D
GND USB_D-
[10] PCIE_TXP1 33 34
PETp0 GND WL_SMDATA
[10] PCIE_TXN1 31 32
PETn0 SMB_DATA WL_SMCLK
29 30
GND SMB_CLK +3V_Mini1_VDD
27 28
GND +1.5V
[10] PCIE_RXP1 25 26
PERp0 GND Q29
[10] PCIE_RXN1 23 24
PERn0 +3.3Vaux
2
21 22 PLTRST#_2 R521 *0/short_4 *2N7002E
GND PERST# PLTRST# [6,13,16,22,26,27]
19 20 RF_EN
UIM_C4 W_DISABLE# RF_EN [27]
17 18 3 1 WL_SMCLK
UIM_C8 GND [2,4,13] SMBCK1
15 16 R517 *0/short_4
GND UIM_VPP LFRAME# [13,27]
13 14 R518 *0/short_4 R294 *0/J_4
[2] CLK_PCIE_MPC_P REFCLK+ UIM_RESET LAD3 [13,27]
11 12 R519 *0/short_4
[2] CLK_PCIE_MPC_N REFCLK- UIM_CLK LAD2 [13,27]
9 10 R522 *0/short_4
GND UIM_DATA LAD1 [13,27]
7 8 R523 *0/short_4
[2] CLKREQ_MPC# CLKREQ# UIM_PWR LAD0 [13,27]
5 6
Reserved +1.5V
3 4
GND
GND
Reserved GND
1 2
WAKE# +3.3V
Q44 WLAN CONN
53
54
3 1 MINI1_WAKE#
[13,22] PCIE_WAKE#
+3V_Mini1_VDD *2N7002K
2
R530 *10K/J_4
+1.5V +1.5V_Mini1_VDD 0.5A

+3V +3V_Mini1_VDD 0.75A
R260 *0/J_8
C R531 *0/short_8 C
+3VSUS C385 C383 C250
C390 C391 C382 C386 C384
*1000P/50V_4 *0.1U/10V_4 *10U/10V_8
R527 *0/J_8
*10U/10V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4
Mini Card 2 (MNC) <2011/1/24(E1A)> Change from 10k to 100k to reduce leakage
no matter have 3G function or not, Peak:2.75A +3V_Mini2_VDD
+3VSUS +3V_Mini2_VDD Normal:1.1A 2nd source: CH4471K9B03
+1.5V_Mini2_VDD need to stuff this PU.
R241 *0/short_8
+3V_Mini2_VDD +3V_Mini2_VDD
1
+3V_Mini2_VDD R252 *0/short_6 C233 C373 C371 C370 C366 C389 C378
CN19 +3V_Mini2_VDD
51 52 3G@10U/10V_8 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/6.3V_4 3G@10P/50V_4 R210 R194
2
Reserved +3.3V R262 +3V
49 50
Reserved GND Q21 *3G@10K_4 *3G@10K_4
47 48
Reserved +1.5V
2
T39 45 46 100K/J_4 R224 *3G@0/J_8 *3G@2N7002E
Reserved LED_WPAN# WLAN_LED1#
43 44
GND LED_WLAN# 3G_MINI_LED# R222 *3G@0/J_6 PDAT_SMB 3 3G_SMDATA
41 42 3G_MINI_LED# [24] [13] PDAT_SMB
1
+3.3Vaux LED_WWAN#
39 40
+3.3Vaux GND USBP5+_R
37 38
GND USB_D+ USBP5-_R
35 36
GND USB_D- R207 *3G@0_4
[10] PCIE_TXP3 33 34
PETp0 GND 3G_SMDATA +1.5V
[10] PCIE_TXN3 31 32
PETn0 SMB_DATA 3G_SMCLK +1.5V_Mini2_VDD 0.5A
29 30
GND SMB_CLK
27 28
GND +1.5V R228 *3G@0/J_8
[10] PCIE_RXP3 25 26
PERp0 GND +3V_Mini2_VDD
[10] PCIE_RXN3 23 24
PERn0 +3.3Vaux PLTRST#_1 R516 *3G@0/J_4 PLTRST# C235 C369
21 22
GND PERST#
B 19 20 3G_EN [27] B
UIM_C4 W_DISABLE# *3G@1000P/50V_4 *[email protected]/10V_4 Q15
17 18
UIM_C8 GND
2
*3G@2N7002E
15 16 UIM_VPP
GND UIM_VPP UIM_RST PCLK_SMB 3 3G_SMCLK
[2] CLK_PCIE_MNC_P 13 14 [13] PCLK_SMB 1
REFCLK+ UIM_RESET UIM_CLK
[2] CLK_PCIE_MNC_N 11 12
REFCLK- UIM_CLK UIM_DATA
9 10
CLKREQ_3G# GND UIM_DATA UIM_PWR
T42 7 8
CLKREQ# UIM_PWR R201 *3G@0_4
5 6
Reserved +1.5V
3 4
GND
GND
Reserved GND
T41 1 2
WAKE# +3.3V
3G@3G CONN
53
54
R508 3G@0_4
USBP5+_R
USBP5+ [10]
USBP5-_R
USBP5- [10]
R510 3G@0_4
MultiMedia SIM (MNC)

<20090604(A1A)_Qualcomm design guide>
A <Layout Notes> Keep USIM signals max length within 8000mils. Place 0.1uF near connector's VCC pin A
UIM_PWR C13 3G@27P/50V_4
JSIM1 +3V UIM_PWR
Max: 7.5mA (Option)
UIM_CLK 6 1 UIM_DATA C11 3G@10P/50V_4
CLK(C3) GND(C5) UIM_PWR U18
[10] USBP4- 7 2
D-(C8) VCC(C1) UIM_VPP UIM_RST UIM_VPP
[10] USBP4+ 8 3 1 6
D+(C4) VPP(C6) CH1 CH4
2
9 4 UIM_RST UIM_CLK C12 3G@10P/50V_4 C321 C15
CT RST(C2) UIM_DATA
10 5 2 5
CD DATA(C7) VN VP 3G@1U/10V_6 [email protected]/10V_4
GND
GND
GND
GND
1
UIM_RST C10 3G@27P/50V_4 UIM_CLK 3 4 UIM_DATA
CH2 CH3 Quanta Computer Inc.
3G@SIM-CONN *3G@CM1293-04SO
13
11
12
14
UIM_VPP C9 *3G@33P/50V_4
PROJECT : ZE7
1B
<20110609> Un-stuff C9 since EM820W doesn't use Vpp Mini-Card/WL/3G/SIM
5 4 3 2 1
5 4 3 2 1
Card reader controller (MMC) 5 IN 1 Card Reader CONN (MMC) 26
+3V3_IN
D VCC_XD VCC_XD D
R319 CN20
*100K_4
13
SD_CD# SD-VCC
[6,13,16,22,25,27] PLTRST# 1
SD_WP/XD_D7 SD-CD-SW
2 45
SD_D1_R SD-WP-SW XD-VCC
3
C286 SD_D0_R SD-DAT1
4
*1U/6.3V_4 SD_CLK_R SD-DAT0 XD_CD#
10 28
SD_CMD_R SD-CLK XD-CD SD_D7/XD_RDY
19 29
SD_D3_R SD-CMD XD-R/B SD_D6/XD_RE#
23 30
SD_D2_R SD-DATA3 XD-RE SD_D5/XD_CE#
25 31
SD_D7/XD_RDY SD-DAT2 XD-CE MS_BS/XD_CLE
5 32
SD_D6/XD_RE# MMC-DATA7 XD-CLE MS_D5/XD_ALE
8 33
SD_D5/XD_CE# MMC-DATA6 XD-ALE SD_D4/XD_WE#
17 34
[2] CLKREQ_MMC# SD_D4/XD_WE# MMC-DATA5 XD-WE MS_D1/XD_WP#
21 35
MMC-DATA4 XD-WP
7
+3V3_IN SD-GND1 MS_D4/XD_D0
15 37
SD-GND2 XD-D0
TP3
TP2
TP1
26 38 MS_D0/XD_D1
C289 0.1U/10V_4 SD-WP-GND XD-D1 MS_D2/XD_D2
27 39
<Layout Note> Place Close to Chip Pin SD-CD-GND XD-D2 MS_D6/XD_D3
40
XD-D3 MS_D3/XD_D4
22 41
R323 6.2K/F_4 MS_BS/XD_CLE MS-VCC XD-D4 MS_D7/XD_D5
9 42
SD_WP/XD_D7
R305 33/J_4 MS_CLK C276 10P/50V_4 MS_D1/XD_WP# MS-BS XD-D5 XD_D6
11 43
MS_D0/XD_D1 MS-DATA1 XD-D6 SD_WP/XD_D7
12 44
CARDREF
MS-DATA0 XD-D7
PLTRST#
MS_INS#
MS_D2/XD_D2 14
SD_CD#
MS-DATA2
XD_D6
MS_INS# 16
EEDO
EECS
EESK
MS_D3/XD_D4 MS-INS
18
MS_CLK MS-DATA3
C 20 36 C
MS-SCLK XD-GND1
46
XD-GND2
48
47
46
45
44
43
42
41
40
39
38
37
6 47
U14 MS-GND1 XD-GND3
24
MS-GND2
CLK_REQ#
PERST#
MS_INS#
SD_CD#
SP15
SP14
3V3_IN
GPIO/EEDI
RREF
EEDO
EECS
EESK
Card Reader CONN
<20101206> Change to DFHS44FR015 by ME design change
[10] PCIE_TXP2 1 36 MS_D7/XD_D5

HSIP SP13
Zdiff = 80 ohm [10] PCIE_TXN2 2 35 MS_D3/XD_D4
HSIN SP12
[2] CLK_PCIE_MMC_P 3 34 MS_D6/XD_D3
REFCLKP SP11 VCC_XD
Zdiff = 95 ohm [2] CLK_PCIE_MMC_N 4 33 MS_D2/XD_D2
REFCLKN SP10
C295 4.7U/6.3V_6 AV12 5 32 MS_D0/XD_D1
AV12 SP9 C376 C381 C297 C387
[10] PCIE_RXP2 C292 0.1U/10V_4 PCIE_RXP2_C 6 31 MS_D4/XD_D0 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 4.7U/10V_8
HSOP SP8
Zdiff = 80 ohm
[10] PCIE_RXN2 C293 0.1U/10V_4 PCIE_RXN2_C 7
HSON RTS5209-GR SP7
30 MS_D1/XD_WP#
GND 8 29 MS_D5/XD_ALE
GND SP6 C255 4.7U/6.3V_6
C294 0.1U/10V_4 DV12 9 28 MS_BS/XD_CLE
B DV12 SP5 B
VCC_XD 10 27 DV12_S C262 0.1U/10V_4

Card1_3V3 DV12_S
+3V R332 *0/short_6 +3V3_IN 11 26 GND
3V3_IN GND
TP4 12 25 SD_D2 R269 33/J_4 SD_D2_R
Card2_3V3 SD_D2
C298 C290
4.7U/10V_8 0.1U/10V_4
<Layout Note> Place Close to Chip Pin
SD_CMD
DV33_18
XD_CD#
SD_CLK
SD_D1
SD_D0
SD_D3
GND
SP1
SP2
SP3
SP4
13
14
15
SD_D7/XD_RDY 16
SD_D6/XD_RE# 17
SD_D5/XD_CE# 18
SD_D4/XD_WE# 19
20
21
22
23
24
AV12 L33 *PBY160808T-601Y-N_1A DV12
<EMI>
XD_CD#
DV33_18
GND
SD_CMD
<Layout Note> Place Close to Chip Pin

SD_CLK
SD_D1
SD_D0
SD_D3
R286 33/J_4 SD_D3_R SD_D3_R C282 *10P/50V_4
R292 33/J_4 SD_CMD_R SD_CMD_R C284 *10P/50V_4
R303 33/J_4 SD_CLK_R SD_CLK_R C291 *10P/50V_4
A R307 33/J_4 SD_D0_R SD_D0_R C296 *10P/50V_4 A
R315 33/J_4 SD_D1_R SD_D1_R C392 *10P/50V_4

C288 C287
*4.7U/6.3V_6 0.1U/10V_4 SD_D2_R C393 *10P/50V_4
SD_CLK_R C274 10P/50V_4

PROJECT : ZE7
1B
RTS5209-GR (Card Reader)
5 4 3 2 1
5 4 3 2 1
L26 PBY160808T-250Y-N/3A/25ohm_6 30mil +A3VPCU I/O ADDRESS SETTING(KBC)

EC (KBC) C211 C202 R281 *0/short_6
27
+3V
.1U/10V_4 4.7U/6.3V_6 10mA
<Layout note> +3V_EC D22 *RB500V-40 SHBM=0: Enable shared memory with host BIOS
+3VPCU E791AGND
E791AGND Place every 0.1uF
R504 2.2/J_6 <20090602(A1A)_Vendor suggest>
1 2 +3VPCU_EC 0.03A (30mils) close to every Place 10nF-0.1uF capacitors for SHBM 3G_EN R160 10K/J_4
power pin C272 C281
C177 C182 C181 C374 C267 C232 .1U/10V_4 4.7U/6.3V_6 every AD input. And close to the AD
115
102
input.
19
46
76
88
4
4.7U/6.3V_6 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 U10
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
D E791AGND C186 .01U/16V_4 1/13 Comfirm by vendor mail : D
Disabled ('1') if using FWH device on LPC.
[13,25] LFRAME# 3 97 TEMP_MBAT [29]
126
LFRAME GPIO90/AD0
98
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
[13,25] LAD0 LAD0 GPIO91/AD1
[13,25] LAD1 127 LAD1 A/D GPIO92/AD2 99
ICMNT_EC R182 *0/short_4
[13,25] LAD2 128 LAD2 GPIO93/AD3 100 ICMNT [29]
[13,25] LAD3 1 LAD3
LCLK_EC 2 C188 3300P/50V_4
[2] LCLK_EC LCLK
GPIO94/DA0
101
E791AGND
SM BUS PU(KBC)
[13] CLKRUN# 8 GPIO11/CLKRUN D/A GPI95/DA1 105
106
GPI96/DA2
[11] GA20 121 GPIO85/GA20
[11] KBRST# 122 KBRST/GPIO86 *

+3VPCU
*
64 MBCLK R164 4.7K/J_4
GPIO01/TB2 ACIN [29]
29 LPC 79 MBDATA R165 4.7K/J_4
[12] EC_SCI# ECSCI/GPIO54 GPIO02
95
[18] EC_FPBACK# 6
GPIO24/LDRQ
GPIO03
GPIO04
96
108
USBOC#R2_R
USBOC#R1_R
R155
R214
*0/J_4
*0/J_4
NBSWON# [16,24]
USBOC#R [10,21]
+3V *
[20] AMP_MUTE# 124
GPIO10/LPCPD
GPIO05
GPIO06/IOX_DOUT/RTS1
93
94
USBOC#L [10,21]
LID# [18]
2ND_MBCLK
2ND_MBDATA
R154
R169
* *4.7K/J_4
*4.7K/J_4
<20110308> Change from +3V_S5 to
GPIO07 +3V for thermal sensor
7 114 CHARGE_IC_ON T56
[6,13,16,22,25,26] PLTRST# LREST GPIO16
109
GPIO30
[25] RF_EN 123 15 T25
GPIO67/PWUREQ GPIO36/CTS1 +3.3V_PRIME_ON
GPIO41 80 +3.3V_PRIME_ON [16,31,34]
125 17 HWPG 1ST: Battery
[11] SERIRQ SERIRQ GPIO42/SCL3B/TCK
20 THERM_ALERT#_R R276 *0/J_4 THERM_ALERT# [5,6,13]
9
GPIO43/SDA3B/TMS
21
2ND: CPU Thermal Sensor / DTS
[13] EC_SMI# GPIO65/SMI GPIO44/TDI SUSB# [13,16]
GPIO GPO47/SCL4
24 USB_CHARGE_ON T28 3RD: VGA Thermal Sensor
25 D/C# [29]
MX0 GPIO50/PSCLK3/TDO S5_ON
[19] MX0 54 26 S5_ON [16,30,35]
MX1 KBSIN0 GPIO51 HDMI_IN
[19] MX1 55 KBSIN1 GPIO52/PSDAT3/RDY 27 T27
MX2 56 28
[19] MX2 KBSIN2 GPIO53/SDA4
MX3 57 73
[19] MX3 KBSIN3 GPIO70 SUSC# [13,16]
MX4 58 74 PWROK_EC_uR R163 *0/short_4
C [19] MX4 KBSIN4 GPIO71 ECPWROK [5,8,13,16] C
MX5 59 75 RSMRST#_uR R162 *0/short_4
[19] MX5 KBSIN5 GPIO72 EC_RSMRST# [13,16]
MX6 60 82
[19] MX6 KBSIN6 GPIO75/SPI_SCK MAINON [16,32,33,34]
MX7 61 83 +3VPCU
[19] MX7
MY0 53
KBSIN7 GPO76/SHBM
GPIO77 84
91 DNBSWON#_1
T22
D10 RB500V-40
3G_EN [25]
*
[19] MY0 KBSOUT0/JENK GPIO81 DNBSWON# [13,16]
MY1 52 110 T40 BATLED0# R167 100K/J_4
[19] MY1 KBSOUT1/TCK GPO82/IOX_LDSH/TEST
MY2 51 112 BATLED1# R166 100K/J_4
[19] MY2 KBSOUT2/TMS GPO84/IOX_SCLK/XORTR USB_EN# [21]
MY3 50 107
[19] MY3 KBSOUT3/TDI GPIO97
MY4 49 KB
[19] MY4 KBSOUT4/JEN0
MY5 48 <20090831(A1A)_EC team suggest>
[19] MY5 KBSOUT5/TDO
MY6 47 31 1.change R166/R167 to 1M or 100K ohm
[19] MY6 KBSOUT6/RDY GPIO56/TA1 RTCRST#_EC [13]
MY7 43 117
[19] MY7 KBSOUT7 GPIO20/TA2/IOX_DIN_DIO SUSON [16,32,34] 2.change PWR/SUS LED's power from +3VPCU to +3V_S5 or +3VSUS
MY8 42 63
[19] MY8 KBSOUT8 GPIO14/TB1 FANSIG [6] can reduce pull-high resistor of SUSLED#/PWRLED#
MY9 41
[19] MY9 KBSOUT9/SDP_VIS
MY10 40 TIMER 32
[19] MY10 KBSOUT10/P80_CLK GPIO15/A_PWM CONTRAST [18]
MY11 39 118
[19] MY11 KBSOUT11/P80_DAT GPIO21/B_PWM PCBEEP [20]
MY12 38 62
[19] MY12 KBSOUT12/GPIO64 GPIO13/C_PWM PWRLED# [24]
MY13 37 65
[19]
[19]
MY13
MY14
MY14
MY15
36
KBSOUT13/GPIO63
KBSOUT14/GPIO62
GPIO32/D_PWM
GPIO45/E_PWM
22
BATLED0# [24]
CPUFAN# [6]
SPI FLASH(KBC)
[19] MY15 35 16 SUSLED# [24]
KBSOUT15/GPIO61/XOR_OUT GPIO40/F_PWM/RI1
34
GPIO60/KBSOUT16 GPIO66/G_PWM
81 1/13 Comfirm by vendor mail :
33 66 BATLED1# [24] If the Southbridge enables 'Long Wait Abort' by default, the
GPIO57/KBSOUT17 GPIO33/H_PWM/SOUT1
flash device should be 50MHz (or faster)
MBCLK 70 +3VPCU
[29] MBCLK GPIO17/SCL1
MBDATA 69
[29] MBDATA GPIO22/SDA1
2ND_MBCLK 67 SMB 113 <20090721_FAE suggestion> U8
[5] 2ND_MBCLK GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR
FOR CPU Thermal Sensor 2ND_MBDATA 68 14 Stuff 100K and close to EC side SPI_SDI_uR R159 22/J_4 SPI_SDI_uR_R 2 8
[5] 2ND_MBDATA GPIO74/SDA2 GPIO34/SIN1/CIRRXL SO VDD
T23 119
GPIO23/SCL3 IR GPIO46/CIRRXM/TRST
23
for improving power consumption SPI_SDO_uR_R C364
FOR VGA T24 120
GPIO31/SDA3 GPO83/SOUT_CR/TRIST
111 5
SI HOLD
7
SPI_SCK_uR_R 6 3 0.1U/16V_4
TPCLK SPI_SDI_uR SPI_SDI_uR SCK WP
[19] TPCLK 72 GPIO37/PSCLK1 F_SDI/F_SDIO1 86
TPDATA 71 87 SPI_SDO_uR R156 22/J_4 SPI_SDO_uR_R +3VPCU R158 10K/J_4 SPI_CS0#_uR 1 4
[19] TPDATA GPIO35/PSDAT1 F_SDO/F_SDIO0 CE VSS
B 10 PS/2 FIU 90 SPI_CS0#_uR B
GPIO26/PSCLK2 F_CS0 SPI_SCK_uR R153 22/J_4 SPI_SCK_uR_R W25Q16BVSSIG
[19,25] BT_POWERON# 11 92
GPIO27PSDAT2 F_SCK R157
[13] SUSCLK R161 *0/short_4 E775_32KX1 77 30 ECDB_CLOCK T26
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN_DIO 100K/J_4
85 VCC_POR# R506 47K/J_4 +3VPCU
R275 *0/short_4 VCC_POR ZS9 A1~A3-test W25Q16BVSSIG AKE38FP0N01 16M bit
12
VCORF
VTT
AGND
GND1
GND2
GND3
GND4
GND5
GND6
13 104 VREF_uR R206 *0/short_4 +A3VPCU

PECI VREF ZS9 A4-test W25Q16CVSSIG AKE38ZP0N02 16M bit
If PECI 3.0 access functionality is not used, ZS9 A5-test AKE38FP0Z01 16M bit
NPCE791L MX25L1606EM2I-12G
connect VTT pin to GND.
5
18
45
78
89
116
103
VCORF_uR 44
ZS9 A6-test MX25L1606EM2I-12G AKE38FP0Z01 16M bit

ZS9 A7-test W25Q16BVSSIG AKE38FP0N01 16M bit
L24
PBY160808T-250Y-N/3A/25ohm_6
C375 Winbond W25Q16BVSSIG AKE38FP0N01
1U/6.3V_4 EON EN25F16-75HCP AKE38ZA0Q00
E791AGND E791AGND MXIC MX25L1606EM2I-12G AKE38FP0Z01 (ZE6 MAC ID fail)
<EMI>
INTERNAL KEYBOARD STRIP SET (KBC) HWPG (KBC) <20110829> DDRAM_PWROK no need connecting to EC side
+3V
LCLK_EC
A A
D17 *RB500V-40 R278
[31] HWPG_VCCGFX
+3VPCU D14 *RB500V-40 R280
[8,32] DDRAM_PWROK
RP5 10K/J_10P8R 10K/J_4
10 1 MX3
10/26 UnStuff +3VPCU D19 RB500V-40 HWPG_R R277 *0/short_4 HWPG *22/J_4
[34] HWPG_1.8V HWPG [2,13,16]
MX4 9 2 MX2
3
MX5 8 3 MX1 MY0 R193 *10K/J_4 D21 *RB500V-40

[30] SYS_HWPG
MX6 7 4 MX0
MX7 6 5 D13 *RB500V-40 C271
[6,31] IMVP_PWRGD
[34] MAINON_ON_G 2 *10P/50V_4 Quanta Computer Inc.
+3VPCU Q28
2N7002K PROJECT : ZE7
1
1B
NPCE791L & FLASH
5 4 3 2 1
5 4 3 2 1
28
HOLE (OTH)
D D
TOP(HDD Hole) BOT(Thermal Hole) BOT(Mini-PCIe Hole) LED ESD PAD TP ESD PAD
HOLE5 HOLE8 HOLE12 HOLE15 HOLE13 HOLE18 HOLE17 HOLE19 HOLE20 HOLE21 PAD1 PAD2
2 5 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6 3 6
4 7 4 7 4 7 4 7 4 7
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
1
h-tc177bc295d120p2 h-tc177bc295d120p2 h-c197d63p2 h-c197d63p2 h-c197d63p2
*HG-C276D98P2 *HG-C276D98P2 *HG-C276D98P2 *ZE7-P1 *HG-C276D98P2
HOLE9 HOLE14 HOLE16 HOLE4 HOLE10

2 5 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6 3 6
C 4 7 4 7 4 7 4 7 4 7 C
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
*HG-TC276BC256D98P2 *HG-C276D98P2 * ZE7-P2 *HG-C276D98P2 *HG-TC276BC315D98P2
HOLE7 HOLE2 HOLE3 HOLE1 HOLE6

2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6
4 7 4 7 4 7 4 7
8
1
9
8
1
9
8
1
9
8
1
9
*HG-TC276BC315D98P2 *HG-TC276BC315D98P2 *HG-TC276BC315D98P2 *ZE7-P3 *O-ZE6-2
B B
HOLE11
1
*O-ZE6-3
A A

PROJECT : ZE7
1B
EMI/Hole
5 4 3 2 1
5 4 3 2 1
POWER_JACK
dcjk-2dc2003-000111-3p-v
VA1 PD7
PQ38
AO4427
PR133
.01_3216
PQ41
AO4427
29
PJ1 PL6 SBR1045SP5-13 VIN
1 FBMA-11-201209-800A50T 1 1 8 1 8
2 VA 3 VA2 2 7 1 2 2 7
2 3 6 3 6
3 5 5
PC88
PC86 PC83 PR132 CSIP_1 VIN PC87
7
6
5
4
4
0.1U/50V_6 0.1U/50V_6 220K/F_6 0.1U/50V_6 PR157
PC84 2200P/50V_4 33K/J_6
1
2200P/50V_6
D PD8 D
PC85 SMAJ20A(400W,20V)
0.1U/50V_6 1 6 PR156
PD6 10K/J_6
2
1SS355 PR131 2 5 D/C# [27]
220K/F_6
3 4 PR134
3
*0/short_4
PQ39
IMD2AT108
VIN 2
PQ40
CSIP_1 2N7002K
1
VIN
PC100
1U/10V_4
PR42 PR43
10/F_6 10/F_6
PC20
PR173 2200P/50V_4
PC22 4.7/J_6 PC25
0.1U/25V_4 1U/10V_4
ISL88731_VDDP
CSIP CSIN PC19 PC99
0.1U/50V_6 4.7U/25V_8
33
32
31
30
28
27
26
21
C C
1
+3VPCU PD1
5
*RB500V-40
CSSP
VDDP
NC
GND
GND
GND
GND
CSSN
VCC
PC34 PC17
+3VPCU PR47
1U/10V_4 0.1U/50V_6
2.7/J_6
88731B_2 88731B_1
11 VDDSMB BOOT 25 4
PQ1 .01_3216
AON7410 PR155
MBDATA 9 24 ISL88731_UGATE PL7
3
2
1
PR59 SDA UGATE 6.8uH/4.5A_7X7X3
100K/F_4 1 2 BAT-V
MBCLK 10 23 ISL88731_PHASE
SCL PHASE
5
13 20 ISL88731_LGATE PR54
[27] ACIN ACOK LGATE 2.2/F_4 PC9
4 .01U/25V_4
PR170 PC21 19
49.9/F_4 0.1U/25V_4 PGND
DCIN 22 PU2 PQ50 PC10
3
2
1
DCIN ISL88731C PR55 AON7410 2200P/50V_4
PR48 10/F_6 PC26
82.5K/F_4
CSOP 18 CSOP CSOP_1 2200P/50V_4 PC91 PC90
88731ACSET 2 10U/25V_1206 10U/25V_1206
ACIN PC31
+3VPCU 0.1U/25V_4
PR51 3 VREF
B
22K/F_4
CSON 17 CSON BAT-V
B
PR58
FBMA-11-201209-800A50T 4 *0/short_4 PR56 CSOP_1
PR25 PL2 ICOMP 10/F_6
NC 16
100K_4
5 PR148
PJ2 FBMA-11-201209-800A50T NC 100/J_4
PL1 15 BAT-V BAT-V
10 1 MBAT+ BAT-V VBF
2 6 VCOMP
PR24 100/J_4 29
3 TEMP_MBAT_C GND
Close battery side
GND
4 TEMP_MBAT [27]
ICM
NC
NC
5
6 PR57
7
14
12
7 2.21K/F_4
9 8 PC8 PC4
Batt_Conn 0.1U/25V_4 100P/50V_4
bat-btj-08tc0b-8p-l-v PC6 PC5
47P/50V_4 PC24 PC33
*1U/10V_4 .01U/25V_4
ISL88731 thermal pad
47P/50V_4 ICMNT
tie to Pin12
ICMNT [27]
PR23
*0/short_4
PR27 PR26 PC28 PC30

100/J_4 100/J_4 0.01U/25V_4 *0.01U/25V_4
PU1
*CM1293A-04SO
A MBDATA A
1 CH1 CH4 6
MBCLK [27]
2 VN VP 5 +3VPCU
MBDATA [27] TEMP_MBAT 3 4 MBCLK
CH2 CH3
Add ESD diode base on EC FAE suggestion

PROJECT : ZE7
1B
CHARGER (ISL88731)
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND [32,34] SYS_SHDN#
SYS_SHDN# [6,35] 30
SUSD
SUSD [34]
[27] SYS_HWPG VIN VIN VL 8223REF +3VPCU

+3VPCU
D VIN VIN D
PR190
4.7u/6.3V_6
4.7u/6.3V_6
PR82 10_8
665K/F_4
PC37 PR189
1u/6.3V_4 *0_4 PR67
8223_VIN
8223_EN
PC44 PC45 PC47 *0/short_4 PC40 PC39
PC38
PC49
4.7u/25V_8 2200p/50V_6 PR75 0.1u/25V_4 2200p/50V_6 4.7u/25V_8
*0/short_4
PR72
5
+5VPCU PR73 PR83 *0_4
100K/F_4 330K/F_4 PR186 +3VPCU
*0/short_4 PQ13
+5VPCU +3VPCU
16
17
5
3
AON7410
5 Volt +/- 5% 4 3 Volt +/- 5%
VIN
VREG3
VREG5
REF
TDC : 4.858A PQ14
SYS_SHDN# 13 EN SKIPSEL 14 +3V_SKIP TDC : 2.368A
4
3
2
1
PEAK : 6.5A AON7410 +3V_PG 23 PGOOD TONSEL 4 +3V_TON PEAK : 3.16A
OCP : 8A +5V_DH 21 10 +3V_DH PC43 OCP : 4A
1
2
3
UGATE1 UGATE2 0.1u/50V_6
Width : 200mil PL3 PC42 PR76 +5V_B 22 BOOT1 BOOT2 9 +3V_B PR78 PL4 Width : 100mil
2.2uH_7X7X3 0.1u/50V_6 1/F_6 PU3 1/F_6 2.2uH_7X7X3
+5V_LX 20 RT8223M 11 +3V_LX
PHASE1 PHASE2
+5V_DL 19 12 +3V_DL
LGATE1 LGATE2
5
C PR182 24 7 C
VOUT1 OUT2
ENTRIP1
ENTRIP2
15.4K/F_4 PR187 PR183
PQ21 +5V_FB 2 5 +3V_FB 4.7_6 6.81K/F_4
GND
GND
ENC
+ PR188 AON7702 FB1 FB2 +
4
4.7_6 4
PC118
18
25
15
PR81 0.1u/50V_6
1
2
3
PC46 PC113 *0/short_4 PQ17 PC111 PC58
3
2
1
220uF/6.3V_6X4.2 0.1u/50V_6 8223_EN AON7702 680p/50V_6 220uF/6.3V_6X4.2
PR185 PC112
2
10K/F_4 680p/50V_6 PR184
PR84 PC48 10K/F_4
100K/F_4 0.1u/10V_4
1
PR69
PR70 48.7K/F_4
97.6K/F_4
+5V_DL PR71
*0/short_6 OCP:4A
PC52 PR85 L(ripple current)
2 0.1u/50V_6 *0_6
OCP:8A PD3 +3V_DL =(9-3.3)*3.3/(2.2u*0.5M*9)
1PS302 3
L(ripple current) PR86
~1.9A
=(9-5)*5/(2.2u*0.4M*9) 1 *0/short_6 PR68
PC51 *0/short_6
Iocp=4-(1.9/2)=3.05A
B =2.525A 0.1u/50V_6 Vth=3.05A*14mOhm=42.7mV B
2
Iocp=8-(2.525/2)=6.74A PD2
R(Ilim)=(42.7mV*10)/10uA
Vth=6.74A*14mOhm=94.32mV 3
1PS302 =42.7K
PC50
R(Ilim)=(94.32mV*10)/10uA 1 0.1u/50V_6
~94.32K
+15V_ALWP
+15V
PR191
22_8
PC115
0.1u/50V_6
VIN +3V_S5 +5V_S5 +15V +5VPCU +5VPCU +3VPCU +3VPCU +3VPCU
PR123 PR124 PR74 PR125

TDC : 0.15A TDC : 0.94A
3
1M_6 22/J_8 22/J_8 1M_6
3
PEAK : 0.2A PEAK : 1.25A

S5D MAIND MAIND 2
S5D 2 Width : 10mil SUSD 2 Width : 40mil
2 2
3
PQ15 PQ24
A PQ35 PQ12 PQ22 AO3404 AO3404 A
1
2 AO3404 AO3404 AO3404
[16,27,35] S5_ON
1
2 2 2 +3V_S5 +3VSUS
PR126 PQ33 PQ16 PQ34
1
PQ32 1M_6 2N7002K 2N7002K 2N7002K

+5V_S5 +5V +3V
DTC144EU
1
TDC : 1.03A
TDC : 0.008A TDC : 1.858A
PEAK : 1.38A PROJECT : ZE7
PEAK : 0.01A PEAK : 2.477A
Width : 50mil Size Document Number Rev
Width : 10mil Width : 80mil SYSTEM 5V/3V (RT8206) 1B

5 4 3 2 1
5 4 3 2 1
31
VIN
8165_VCC +5V_S5
PC123 PC124 PC127

*22U/25V_1210 *22U/25V_1210 *22U/25V_1210
8165_VCC
PR37
2_6
PC89 PC98
D D
4.7u/6.3V_6 4.7u/6.3V_6
PR46 PR53 <20110428> For EMI request
130K/F_4 4.7_6
VIN
37
9
PC23
5
0.1u/25V_6
VCC
PVCC
PC27 PC102 PC103
8165_FBA 27 31 8165_TONSETA 2200P/50V_4 0.1u/50V_6 4.7u/25V_8
FBA TONSETA VCCGFX
4
PR32 PC7 PR29 PR39 PC12
100/F_4 100p/50V_4 *0/short_4 *0/short_4 33P/50V_4 34 8165_DH2 PQ2
UGATEA AON7410
VCCGFX
3
2
1
PR35 PR34 PR41 PR166 L=2.2uH, typ.DCR=18m-ohm
750/F_4 11K/F_4 88.7K/F_4 2.2_6
8165_COMPA 28 33 8165_BOOTA PL8
[7] GTVCC_SENSE COMPA BOOTA 2.2uH_7X7X3
for compensation fine
tune PC96
5
8165_RGNDA 26 35 8165_LX2 0.22U/25V_6
[7] GTVSS_SENSE RGNDA PHASEA
assume
PR158 PR153 ESR=9m-ohm
100/F_4 *0/short_4 PR175 PR163 PR161
36 8165_DL2 4 *2.2/F_6 6.98K/F_4 *0/short_4 +
LGATEA PC16 PC14
PQ4 0.1u/50V_6 330u/2V_7343
Place close to VR AON7702 PC108
3
2
1
+1.05V *1000P/50V_6
PR150 *0/short_4 8165_VCLK 25 PC95
[6] VR_SVID_CLK VCLK
8165_VCLK 30 8165_ISENAP 0.1u/25V_4
PR19 54.9/F_4 PR149 *0/short_4 8165_VDIO ISENAP
[6] VR_SVID_DATA 24
8165_VDIO VDIO PC94
PR15 110/F_4 PR146 *0/short_4 8165_ALERT# 23 *0.1u/10V_4 PR167 VCCGFX
[6] VR_SVID_ALERT# ALERT
8165_ALERT#
C PR1 *90.9/F_4 PR144 *0/short_4 8165_VRA 22 29 8165_ISENAN
1K_6_NTC(B=3650)
TDC : 2.58A C
[27] HWPG_VCCGFX VRA_READY ISENAN
PR12 100/J_4
8165_VRHOT#
PR143 *0/short_4 8165_VR
PEAK : 3.44A
[6,27] IMVP_PWRGD 21
VR_READY
OCP : 9A
PR142 *0/short_4 8165_VRHOT# 20 PC15 Rsense=12.63m-ohm PR165 PR159
[6] H_PROCHOT# VRHOT PU8 *0.1u/50V_6 1.15K/F_4 1K/F_4 Width : 120mil
RT8167BGQW
PR50 0_4 8165_EN 32 PR45 PR52 <20110428> For EMI request

+3V [16,33,34] HWPG_1.05V EN 130K/F_4 4.7_6
For HW Debug PR44 2 8165_TONSET
TONSET VIN
8165_VRA *0/short_4 8165_TEMPMAX 12
PR14 10K/F_4 PR49 *0_4 TEMPMAX
[16,27,34] +3.3V_PRIME_ON
8165_VR 8165_ICCMAX 13
PR13 10K/F_4 ICCMAX
8165_ICCMAXA 14 PC18
ICCMAXA 8165_DH1 0.1u/25V_6 PC29 PC104 PC106 PC105
40
PR40 8165_OCSET UGATE1 2200P/50V_4 0.1u/50V_6 4.7u/25V_8 4.7u/25V_8
16
5
100K_4 OCSET PR169
8165_OCSETA 18 2.2_6
OCSETA 8165_BOOT1
1
8165_SETINI BOOT1
11
SETINI
4
8165_SETINIA 10 39 8165_LX1
SETINIA PHASE1 PQ5 +VCC_CORE
8165_TSEN 15 PC97 AON7410 L=1.5uH, typ.DCR=14m-ohm
3
2
1
TSEN 0.22U/25V_6
8165_TSENA 17 38 8165_DL1 PL9
TSENA LGATE1 1.5uH_7X7X3
8165_FB 6 3
PR28 PC3 PR22 PR36 PC11 FB ISEN1P
5
100/F_4 470p/50V_4 *0/short_4 *0/short_4 36p/50V_4 + +
+VCC_CORE 4 PC109
ISEN1N PR174 PR162 PR160 PC107 PC32
0.1u/50V_6 assume
PR30 PR31 PR38 *2.2/F_6 3.57K/F_4 *0/short_4 330U/2V_7343 *330u/2V_7343 ESR=9m-ohm
2.55K/F_4 10K/F_4 88.7K/F_4 4
8165_COMP 5 41
B [7] CPUVCC_SENSE COMP GND PQ3
B
AON7702 PC101
+VCC_CORE
3
2
1
for droop fine tune *1000P/50V_6 PC92 0.1u/25V_4
8165_RGND
[7] CPUVSS_SENSE
7
RGND TDC : 3.18A
GFXPS2
PR171
PEAK : 4.23A
IBIAS
PR151 PR152 1K_6_NTC(B=3650)

100/F_4 *0/short_4
OCP : 10.4A
8
19
8165_ISEN1P Width : 160mil

Rsense=4.24m-ohm PR164 PR154
Load-line = -5.9mv/A
8165_IBIAS
8165_GFXPS2 PC93 1K/F_4 1K/F_4
8165_ISEN1N
*0.1u/10V_4 for Cedar trial-M
8165_VCC
PC13
8165_VCC 8165_TEMPMAX Temp max=100C PR11 *0.1u/50V_6
PR137 51K/F_4 53.6K/F_4
8165_ICCMAX VICCMAX=164mV, /19.2mV=8.563 for noise filtering,
PR138 274K/F_4 place close to
8165_ICCMAXA VICCMAXA=68mV, /19.2mV=3.532
PR168 PR172 PR139 182K/F_4 RT8165B
10K_6_NTC PR18 PR20 10K_6_NTC 8165_OCSETA OCSETA=2.619V
10K/F_4 10K/F_4 PR141 21K/F_4
8165_OCSET OCSET=2.56V
PR140 11.8K/F_4
place close to place close to 8165_SETINIA VBOOTA=1V
GFX inductor Vcore inductor PR135 16.9K/F_4
8165_SETINI VBOOT=1V
PR136 16.9K/F_4
PR16 PR17 8165_GFXPS2 GFX Not force PS2
750/F_4 750/F_4 PR145 *0_4
2.21K/F_4
10K/F_4
10K/F_4
10K/F_4
10K/F_4
10K/F_4
33K/F_4
5.1K/F_4
A 8165_TSENA 8165_TSEN A
PR21 *0/short_8
PC2 PR9 PR7 PC1
1u/10V_4 1K/F_4 1K/F_4 1u/10V_4
PR3
PR2
PR8
PR6
PR5
PR4
PR10
PR33 *0/short_8
PR147

PROJECT : ZE7
1B
CPU CORE (RT8165B)
5 4 3 2 1
5 4 3 2 1
32
[PWM]
PC67
10U/10V_8
20mil
PR111 PC73
0.375A *0/short_6 0.1U/50V_6
8207A_VBST
+0.75V_DDR_VTT
D VIN D
8207A_DH
PC60 PC59
10U/10V_8 10U/10V_8 8207A_LX
5
8207A_DL PC65 PC66
4.7U/25V_8 4.7U/25V_8
25
24
23
22
21
20
19
4
PC63
PQ25 2200P/50V_6
GND
VTT
VLDOIN
VBST
DRVH
LL
DRVL
AON7410 PL5
3
2
1
2.2uH_7X7X3
1 18 +1.5VSUS
VTTGND PGND
2 VTTSNS CS_GND 17
+1.5VSUS
3 PU5 16
1.5 Volt +/- 5%
GND CS
5
RT8207L
PR119 PR115
TDC : 4.32A
10mil +1.5VSUS 4 15 13K/F_4 *4.7/J_6 PEAK : 5.76A
MODE V5IN +5V_S5
+
0.188A 4 OCP : 10A
5 14 PR122
+SMDDR_VREF VTTREF V5FILT 5.1/F_6 PQ28 Width : 200mil
1
AON7702
3
2
1
VDDQSNS
+5V_S5 PC77 PC76 PC72
VDDQSET
6 COMP PGOOD 13
C 1U/10V_4 1U/10V_4 *680p/50V_6 PC61 PC64 C
2
330U/2V_7343 10U/10V_8
NC
NC
S3
S5
PC56
PR121 *100K/F_4 +3V_S5 <20110728> Change DDRAM_PWROK PU from +3V_S5 to +1.5VSUS (no connect at EC side )
0.033U/50V_6
7
10
11
12
PR198 0/J_4
DDRAM_PWROK [8,27]
PR120 (For RT8207A 400KHZ) close to PC2016
VIN
PR97 620K/F_4
*0/short_6
S5_1.8V
SUSON [16,27,34]
PR118 *0/short_4
PR96 S3_1.8V MAINON [16,27,33,34]

*0/short_6 PR113 *0/short_4
PR100 +5V_S5
*0/J_4
PR103
Vout = (PR150/PR149) X 0.75 + 0.75
PC68 10K/F_4
*33P/50V_6
AON7702 Rdson=11~14mOhm
B
8207A_SET
L(ripple current) B
S5_1.8V S3_1.8V
=(19-1.5)*1.5/(2.2u*400k*19)
PR110
PR117 *0/J_4
+1.5VSUS
~1.57A
10K/F_4
Vtrip= (10-1.57/2)*14mohm=0.12901V
RILIM=Vtrip/10uA~12.901Kohm
3
MAIND 2
[30,34] MAIND
PQ11 S3 S5 +1.5VSUS REF VTT

AO3404
1
S0 1 1 ON ON ON
+1.5V
S3 0 1 ON ON OFF
TDC : 1.24A S4/S5 0 0 OFF OFF OFF
PEAK : 1.65A
A Width : 60mil A

PROJECT : ZE7
1B
DDR 1.5V(TPS51116)
5 4 3 2 1
5 4 3 2 1
33
[PWM] VIN
+5V_S5
D D
PC121 PC122
PR89 PD4 2.2n/50V_4 4.7U/25V_8
10/J_6 RB500V-40
PR114
1
PR92 2.2/F_6 +1.05V
1M/F_4 PC74
5
4.7U/10V_6
2
PR99
33K/J_4 PU4 G5602 PR104 PC69 4
[16,27,32,34] MAINON 15 13 *0/short_6 0.1U/50V_6
EN/DEM BOOT PQ45
+3V 16 12 UGATE-1.05V AON7410 PL10
3
2
1
TON UGATE 2.2uH_7X7X3
1 11 PHASE-1.05V
VOUT PHASE
5
PR90 2 10 PR108
10K/J_4 VDD OC 3K/F_4
PC57 3 9 PC70
FB VDDP
1
C 0.1U/50V_6 1U/10V_4 PR192 + PC117 C
4 8 LGATE-1.05V 4 *4.7/J_6 .1U/10V_4
[16,31,34] HWPG_1.05V PGOOD LGATE
2
6 7 PQ51
GND PGND AON7702
3
2
1
5 17 PC119
NC TPAD *680p/50V_6
14 NC PC114
PC54 330U/2.5V
1U/10V_4 PC116
*10U/10V_8
PC55
*1000P/50V_6
B B
PR88 PC53
VOUT=(1+R1/R2)*0.75 +1.05V
R1 4.02K/F_4 *33P/50V_6
1.05 Volt +/- 5%
1.05V_FB
TDC : 1.36A
PEAK : 1.82A
PR93 OCP : 5A
10K/F_4
R2 Width : 60mil
PR94
*0/short_6
PR95
TON=3.85p*RTON*Vout/(Vin-0.5) *0/short_6
AON7702 Rdson=11~14mOhm
Frequency=Vout/(Vin*TON) L(ripple current)
=(19-1.05)*1.05/(2.2u*272k*19)
A
TON=3.85p*1M*1/(Vin-0.5) ~1.658A A
Rth=14m*(5-0.829)/20uA Quanta Computer Inc.

Frequency=1/(0.0036767)=272K RILIM=2.92Kohm
PROJECT : ZE7
1B
+1.05V(UP6111AQDD)
5 4 3 2 1
5 4 3 2 1
VIN +1.5VSUS +3VSUS +15V 34

PR194 PR195 PR197 PR196
1M/J_4 *22/J_8 22/J_8 1M/J_4
SUS_ON_G SUSD
SUSD [30]
3
3
PR193
[16,27,32] SUSON 2 PQ46 1M/J_4 2 2 2
DTC144EU PC120
PQ47 PQ48 PQ49 *2200P/50V_4
D D
*DMN601K-7 2N7002K 2N7002K
1
VIN +3V +5V +1.05V +1.5V +15V
PR91 PR101 PR98 PR80 PR79 PR77

1M/J_4 22/J_8 22/J_8 *22/J_8 22/J_8 1M/J_4
MAINON_ON_G MAIND
MAIND [30,32]
3
3
3
PR87
2 PQ23 1M/J_4 2 2 2 2 2
[16,27,32,33] MAINON
DTC144EU PC41
PQ26 PQ27 PQ20 PQ18 PQ19 *2200P/50V_4
2N7002K 2N7002K *DMN601K-7 2N7002K 2N7002K
1
1
MAINON_ON_G
MAINON_ON_G [27]
C C
Reserve For VCCGFX

+1.8V
1.8Volt +/- 5% +3VSUS
TDC : 0.113A
PEAK : 0.151A
1
PC80 +3V
Width : 20mil .1U/10V_4
PC81
2
+1.8V PQ29 10U/10V_8
AO4468
1 8 PR102
2 7 100K_4
3 6
PU7
5
G9334 ADJ
PR129 5 4
4
DRV PGD HWPG_1.8V [27]
261/F_4 Rg
PC79 PC82
10U/10V_8 10U/10V_8 1 PR181 0/J_4 +3.3V_PRIME_ON
EN +5V
3
FB
1
PC110 PR180 *0/J_4
GND
6 *0.1U/10V_4
VCC
2
1
PR130 Rh PR107 PC71
2
100/F_4 47/F_4 .1U/10V_4
<20100902> reserve for H/W debug
2
Vout1 = (1+Rg/Rh)*0.5 PC62
33N/25V_4
PR105 *30K/F_4
B B
<20101217> Reserve 30K for Duncan suggestion
VIN VCCGFX
For +3V_PRIME VIN +3.3V_PRIME +1.8V +15V +3V
PR176 PR178
*1M/J_4 *22/J_8
PR62 PR179 PR61 PR64
3
1M/J_4 22/J_8 22/J_8 1M/J_4
3
2
3
3
PR177
3
2 PQ42 *1M/J_4 2 PQ10

[16,31,33] HWPG_1.05V *DTC144EU PR60 AO3404 +3.3V_PRIME
1
PQ43 PR65 *0/short_4 2 PQ7 1M/J_4 2 2 2
*DMN601K-7 [16,27,31] +3.3V_PRIME_ON DTC144EU PC36
1
PQ44 PQ8 PQ6 *2.2n/50V_4

1
2N7002K 2N7002K 2N7002K

1
PC35 PR63
1
TDC : 0.17A
1
MAINON_ON_G PR66 *0/short_4 2 *1U/10V_4 *100K_4
PEAK : 0.22A
2
PQ9
A
2N7002K Width : 10mil A
1

PROJECT : ZE7
1B
Discharge/1.8V
5 4 3 2 1
1 2 3 4 5
35
Thermal Protection (DCD)
VIN
A PD5 A
1SS355
PR127
1
1M/F_4
PQ30
AO3409
TSNS_ON 2
3
S5_ON 2
3
PQ37
1
DTC144EU
B Thermal protection temperature = 70C VL VL B
<20111018>
Change PR112 from CS22212FB11 to CS21502FB14,
for change M/B from 60 to 70 SYS_SHDN# [6,30]
PR112 PR106
1.5K/F_4 200K/F_4
PC75 PR128
0.1U/25V_4 200K/F_4
3
2.52V
8
PR116
10K/J(NTC) _6 2.469V 3 +
1 2
2 - PQ36
3
PU6A 2N7002K
4
AS393MTR-E1 PC78
1
0.1U/25V_4
[16,27,30] S5_ON 2
PR109
C PQ31 200K/F_4 C
2N7002K
1
5 +
7
6 -
PU6B
AS393MTR-E1
D D

PROJECT : ZE7
1B
Thermal protect
1 2 3 4 5
5 4 3 2 1
(100MHz)
SRC_P/N WLAN(Mini Card 1)
(33MHz)
36
PCI_33 Debug Card
Page 25
CPU_ITPP/N
D
(100MHz) D
SATAP/N SATACLKP/N To CPU
Tigerpoint
(100MHz)
SRC_P/N
DMICLK100P/N
(24MHz) Audio
(48MHz) BIT_CLK
USB_48 CLK48 ALC271X
Page 20
LVDS_CLKP/N
(14.318MHz)
DDR_CLK0P/N REF CLK14
DDR_CLK1P/N PCICLK
(32.768KHz)
Cedarview-M SUSCLK
(400/533MHz) CLOCK GEN CK505
DDR3 SO-DIMM0 DDR_CLK2P/N Page 10~15
Page 4 SLG8LV631V
(400/533MHz)
DDR_CLK3P/N
C (100/133MHz) C
HPLLREFCLK_P/N CPU_0P/N
(100/133MHz) Y4(32.768K KHz)
DDR3REF_P/N CPU_1P/N
(100MHz)
DPL_REFSSCLKIN_P/N LCD_CLKP/N
(100MHz)
DMICLKIN_P/N SRC_P/N
(96MHz)
DPLREFCLK_P/N DOT_96P/N
(Max. 112MHz)
10.1" LED Panel LVDS_CLKP/N (33MHz) EC (33MHz) SPI Flash
Page 18 PCI_33 SPICLK
WPCE791L Page 27
Page 5~9
Page 2 Page 27
(Max. 340MHz)
HDMI DDI0_TXP/N3
Page 17
B AZIL_BCLK (100MHz) Card Reader B
SRC_P/N
RTS5209-GR
Page 26
Y3(27 MHz)
LAN
(100MHz)
SRC_P/N RTL8105TA-VC-CG Y5(25 MHz)
(24MHz) Page 22
From TPT
(100MHz) WLAN(Mini Card 2)

SRC_P/N
Page 25
A A
Y2(14.318 MHz)
PROJECT : ZE7
1B
Clock Distribution Diagram
5 4 3 2 1
5 4 3 2 1
37
+VCC_CORE(0.75V-1.18V,4.234A)
CPU core
(RT8165)
<HWPG_1.05V> BOM Structure
PU8 VCCGFX(0.76V~1.05V,3.438A)
<HWPG_1.05V>
Function Description
VIN
+1.05V +1.05V(1.8164A) 3G 3G@ w/ 3G module stuff 3G@
D (G5602) D
<MAINON+RC> w/o 3G module unstuff 3G@
PU4
BT@ w/ BT module stuff BT@
+5VPCU(4.03A) BT
<AC/DC Insert> w/o BT module unstuff BT@
(6.517A)
LVDS@ w/ LVDS (default) stuff LVDS@
+5VPCU
AO3404 +5V_S5(10mA) L38: CV+1003JN01 (0.1UH)
PQ35 <S5D> LVDS/EDP C334: CH5102K9B06 (1UF)
EDP@ w/ EDP stuff EDP@
AO3404 +5V(2.477A) L38: CS00003J951 (0ohm)
PQ12 <MAIND> C334:CS00002JB38 (0ohm)
1.5VPLL@ w/ 1.5VPLL (default) stuff 1.5VPLL@
+3VPCU(55mA) PLL Power
<AC/DC Insert>
VIN
SYSTEM 1.05VPLL@ w/ 1.05VPLL stuff 1.05VPLL@

C C
5V/3V
(RT8223) AO3404 +3V_S5(197mA)
PQ15 <S5D>
PU3
(3.034A)
+3VPCU
AO3404 +3VSUS(1.1A)
PQ24 <SUSD>
(1.182A)
+3VSUS
G9334
ADAPTER +1.8V(151mA)
VIN AO4468 <+3.3V_PRIME_ON>
CHARGER PU7/PQ29
(5.48A)
(ISL88731)
BATTERY PU9001 AO3404
+3V(1.38A)
PQ22 <MAIND>
(1.6A)
B +3V B
AO3404 +3.3V_PRIME(220mA)
PQ10 <+3.3V_PRIME_ON>
+1.5VSUS(3.362A)
<SUSON>
VIN
+1.5VSUS
(5.008A)
DDR PWR AO3404 +1.5V(1.646A)

1.5V PQ11 <MAIND>
(RT8207)
PU5
+SMDDR_VREF(0.25A)
<SUSON>
A A
+0.75V_DDR_VTT(0.5A)
<MAINON>

PROJECT : ZE7
1B
Power Tree
5 4 3 2 1
5 4 3 2 1
JE01_CT(Cedar Trail) Power On Sequence 38
From AC,BATT VIN

+5VPCU +3VPCU VCCRTC
D D
From PWM to EC HWPG_SYS(PCU)
>=18ms (VCCRTC to RTCRST#)(t200)
RTCRST#
From Button to EC NBSWON#
From EC to PWM S5_ON >=0ms (VCCRTC to S5 well)(t203)
+5V_S5 +5V_S5 power up before +3V_S5, or
after +3V_S5 within 0.7V (t201) +3V_S5 power down before +5V_S5,
+3V_S5 >=5ms (S5 well to EC_RSMRST#)(t205) or after +5V_S5 within 0.7V
From EC to SB EC_RSMRST# 100ms (EC define)
From EC to SB DNBSWON#(PWRBTN#)
1~2 RTCCLK (SUSC# to SUSB#)(t234) (1RTC: 28.992 s to 32.044 s)

From SB to EC SUSB#(SLP_S3#),SUSC#(SLP_S4#)
From EC to PWM SUSON
+3VSUS +SMDDR_VREF +1.5VSUS(to DDR3_DRAM_PWROK)
From PWM to EC HWPG_1.5V (SUS)

C C
From EC to PWM MAINON +5V power up before +3V, or

+3V power down before +5V,
after +3V within 0.7V (t209)
or after +5V within 0.7V
+5V +3V +1.5V +0.75V_DDR_VTT
V_CPU_IO power down before +1.5V,
or after +1.5V within 0.7V
+1.05V (also for V_CPU_IO of PCH) CPU: +1.5V power up before +1.05V ; PCH: +1.5V power up
before V_CPU_IO, or after V_CPU_IO within 0.7V (t211)
From PWM to CPU VR HWPG_1.05V

+VCC_CORE VCCGFX
From PWM to EC IMVP_PWRGD/HWPG_VCCGFX
From EC +3.3V_PRIME_ON
CPU:+3V_PRIME and +1.8V needs to be <700mV
+3V_PRIME +1.8V
From PWM to EC HWPG_1.8V
From PWM HWPG(to EC,VRMPWRGD,CK505) 100ms(EC define)
B B
From EC to CPU,SB ECPWROK(AND with HWPG to PWROK,to DDR3_VCCA_PWROK)
BCLK
From CLK Gen
99ms(S0 well of TPT to TPT_PWROK)(t214) NOTE:PWROK assertion indicates that PCICLK has been stable for at least 1 ms.
From EC to SB TPT_PWROK
From SB to CPU H_PWRGD
From SB to All PLTRST#
*Note: EC will sampling SUSB# & SUSC# every 5ms.
ICH SMBUS Table EC SMBUS Table
A
CLK GEN RAM *Mini Card (WLAN) *XDP Battery CPU Thermal Sensor GFX Thermal Sensor A
(SMB_DATA)/(SMB_CLK) (+3V_S5) V V V V EC791 SDA1 / SCL1 (+3VPCU) V

EC791 SDA2 / SCL2
Power Plane +3V +3V +3V +3V
EC791 SDA3 / SCL3
MOS CKT (Level shift) Stuff Stuff Stuff Stuff Power Plane +3VPCU
MOS CKT (Level shift) X Quanta Computer Inc.
*=Reserve PROJECT : ZE7
1B
Power Sequence
5 4 3 2 1
5 4 3 2 1
SLP_S3#(SUSB#): 4 39
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components NBSWON#
when system transitions to S3, S4, or S5 states. 5 +5VPCU +5V_S5
SLP_S4#(SUSC#): MOS
S5_ON PQ33
S4 Sleep Power plane control - Assertion of SLP_S4# shuts power off to non-critical components 6
when system transitions to S4 or S5 state. (S5D)
2 +3VPCU +3V_S5
1 MOS
AC Adapter +3VPCU PQ12
Always System power
BATT Charger VIN
D Regulator 7 D
PU2 +5VPCU
Battery EC_RSMRST#
PU2 RSMRST#
10 8
3
DNBSWON#
SUSON(SUSD) PWRBTN#
13 SUSC# 9
SLP_S4#
MAINON(MAIND)
EC SUSB#
14 SLP_S3#
MAIND +3VPCU/+5VPCU +3V
MOS +5V 22
23 PCH
ECPWROK
TPT_PWROK
PWRGD
MAIND +1.5VSUS
+1.5V
MOS
100ms
C
MAINON C
+RC VIN 15
+1.05V
VR
HWPG_1.05V VRM_PWRGOOD
16
CPU_PG PLTRST#
VIN +VCC_CORE
17
Regulator VCCGFX
PU8
HWPG_SYS
+3.3V_PRIME_ON IMVP_PWRGD/ HWPG_VCCGFX 18
(From EC)
19a 21
+3V 19b HWPG CK505 24 25
+3V_PRIME
MOS EN
PQ9 H_PWRGD PLTRST_N
B B
20 HWPG_1.8V D
+3VSUS
MOS MAINON_ON_G NMOS
+1.8V HWPG_1.5V G
PU7 S
D
GND
NMOS MAINON_ON_G 12
G For Power Down Sequence PWRGD RESET_L
S For Power Down Sequence
DDR3_VCCA_PWROK
GND
MAINON +0.75V_DDR_VTT
VIN
CPU
SUSON Regulator +SMDDR_VREF
+1.5VSUS
PU5 DDR3_DRAM_PWROK
11
+3VPCU
SUSD MOS +3VSUS
PQ22
A A

PROJECT : ZE7
power sequence block diagram 1B

5 4 3 2 1
5 4 3 2 1
MODEL
ZE7
Model REV CHANGE LIST FROM To
1A 1B
1A First Released (PCB: A)

ZE7 MB
<Page 5> Update CPU P/N to MP P/N
D 1B <Page 19> Un-stuff CA122084N98 at CP1 - CP6 by EMI confirmation D
<Page 18> Stuff R26 CS00003J951 (0/J_6) for +5V_LCD (IVO panel)
Change 0ohm resistors to short PAD
C C
B B
A A

DOC NO. PROJECT MODEL : ZE7 APPROVED BY: DATE: 2011/11/2 PROJECT : ZE7
1B
PART NUMBER: DRAWING BY: REVISON: 1B Change List1
5 4 3 2 1
www.s-manuals.com

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1 2 3 4 5 6 7 8

ZE7 Block Diagram (Intel Cedar Trail-M Platform) 01

USB PORT USB PORT CCD

P29 P32 +3.3V_PRIME P34

CPU Core Quanta Computer Inc.

Date: Wednesday, November 02, 2011 Sheet 1 of 40

CLK GEN (CLK) 02

R219 1 2 2.2/J_6 L27

SRC_2 41 CLK_PCIE_MNC_P [25]

Y2 14.318MHZ [4,13,25] SMBDT1 SMBCK1 8 SCL SRC_4 34 CLK_PCIE_DMIP [5]

33P/50V_4 CG_XOUT USB48_1/FSB SRC_5

R301 10K/J_4 R289 10K/J_4 R317 *10K/J_4 CLKREQ_MMC#_R R279 10K/J_4

Quanta Computer Inc.

DDR_STD(DDR) DIMM0 H=4mm 04

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

R191 1K/F_4 +SMDDR_VREF_DIMM_R +SMDDR_VREF_DIMM

R148 1K/F_4 +SMDDR_VREF_DQ0_R +SMDDR_VREF_DQ0

Cedar View (CPU) R397 *1K/J_4 +3V

HDMI: 7.5", 4 via, 1.65 Gbps [17] DDI0_HDMI_SCL H25

LCD Panel Power (LDS) U24A

[10] DMI_TXN2 N1 DMI_RXN2 DMI_TXN2 L8 DMI_RXN2 [10]

R360 DMI_REFCLKN RSVD_TP_R7 DMI_REF1.5V_R 7.5K/F_4

ECPWROK 2 TC7SH08FU LAYOUT NOTE: PLACE CLOSE TO PIN +3V

SCL SDA 2ND_MBDATA [27]

Quanta Computer Inc.

Cedar View (CPU) 06

L26 RSVD_L26 SMI# B18 H_SMI# [11]

H29 H_BPM4_PRDY# H_BPM4_PRDY# R442 *51/J_4

XDP_TCLK C25 B16

XDP_TCLK R446 51/J_4

125 Degree Protection(CPU) CPU FAN CTRL(THM)

+3V +5V +3V +5V

Cedar View PLL Power

LAYOUT NOTE: OVERLAP RESISTOR AND INDUCTOR

VCCAHPLL_1.05 10uH/100mA_8 L10

C32 C49 Quanta Computer Inc.

Cedar View (CPU) U24B 08

Quanta Computer Inc.

[5] DMI_RXN0 R23 DMI0RXN USBP0N H7 USBP0- [21]

<20110630> No support PCI-e in 3G card EMI

Quanta Computer Inc.

Tiger Point (CLG) 11

RSVD11 please follow CRB to have a 1K pull up at the moment. +1.05V

AA14 U16 GA20 GA20 [27]

RSVD30 INTR H_INTR [6]

Quanta Computer Inc.

Tiger Point (CLG) 12

A5 B22 PCI_INTB# RP3 1 2 8.2K_8P4R

ICH Boot BIOS select

A16 SWAP Override strap PIRQD USB UHCI Controller #2

PIRQE Internal LAN; Option for SCI, TCO, HPET#0,1,2

Tiger Point (CLG) 13

PCLK_SMB R378 8.2K/J_4

TPT Power OK (CLG) Platform Reset (CLG)

VPORT_6 Near CN13 470p/50V_4 470p/50V_4 0.1u/16V_6

R-L-SPEAKERS R225 0/J_6 22P-50V_4 TVS/6pF_4