Bist-Built in Self Test

BIST-BUILT IN SELF TEST
Introduction
In VLSI testing the circuits are put to the Test Mode to check whether
they are working properly or not.
If the circuits are working properly then they are skipped to the customers
for use,this is called Off-line testing.
But as we go into sub-micron then the circuits can still prone to the faults
during use. So there we always use some redundant circuits which can
replace the faulty parts.
And if the circuits are always tested before in operation or start-up, this
is called BIST(built in self test).
Basic Architecture of BIST

CUT with DFT
CUT with DFT contains circuit under test and scan chain.
Size of this block can have 90% of area.
Other blocks of BIST can have area 10-11% of the area of the CUT with
DFT. Example, if CUT with DFT have area of 100 units then remaining
blocks will have area 10 units or less
The block will have two outputs
(a) Primary output(when input is Normal).
(b) output (when input from the HTPG).
Hardware Test Pattern Generator
Suppose if we have n number of test patterns, then we will use that

pattern for testing the circuit which gives maximum number of faulty
outputs instead of checking at every possible pattern.
It is subset of OFF-LINE test patterns.
It can be made by using ATPG (i.e., follows some type of algorithm that
generate test patterns) but use of this ATPG type generator is costly
because it has high memory capacity so it occupies larger area so we try
to avoid this type of algorithm.
So we can implement this HTPG using shift registers to apply patterns.
Input MUX
It is used to choose the patterns that we want to apply to the DUT for
testing the CUT.
If M=0, then normal input will be applied to the DFT
If M=1, then input from the HTPG will be applied.
ROM
ROM will store the Golden outputs . Golden output is same as the output
that comes from CUT after test for comparing the results is it giving the
correct result or not.
So if every output related to every input is stored in the ROM then the size of
ROM will be very big as compared to the CUT with DFT hence only that
output will be stored whose input is given from the HTPG.
Output Response Compactor
This will compact the output coming from the CUT with DFT, but because
the output coming from the CUT with DFT is too large. After then outputs are
compared using COMPARATOR block and status is given.
Test Controller
Test controller will control the HTPG,MUX,ROM and output response

compactor when M=1.
When M=0 then normal input will be given.
Hardware Test Pattern Generator
HTPG can be implemented using LFSR(Linear feedback shift register)

because it follows two condition suited for HTPG
low area.
pseudo exhaustive pattern generator i.e. it can generate as many patterns
as possible from 0 to 2^n-1 but it cannot have 0 in pattern.
LFSR are of two types
Standard Feedback Shift Register(SFSR).
Modular feedback shift register(MFSR).
Standard Feedback Shift Register(SFSR)
SFSR block diagram is shown as follows
In the Block diagram h1, h2,...., hn-2, hn-1 are the feedback from the flip-
flops. The value of h1, h2,...., hn-2, hn-1 can be 0 or 1, but there will always
a feedback from first to the last flip-flop.
The block diagram can also be expressed by using XOR gates, replacing the
summation by XOR gates.Now if we find the relation between next state and
present state, then we will have the following matrix as follows.
X0(t+1) = X1(t).
X1(t+1) = X2(t).
..
Xn-2(t+1) = Xn-1(t).
Xn-1(t+1) = X0(t)+h1X1(t)+....+hn-2Xn-2(t)+hn-1Xn-1(t). So matrix is
We can see that we have a diagonal matrix if we skip last row and first
column.
Characteristic polynomial is
F(x) = 1+h1x+h2x^2+h3x^3+...........+h0x^(n-2)+x^(n-1).
Now we know that there will always be feedback from the first flip-flop to
the last one and there might be possibility of other feedbacks from the
intermediate flip-flop.
Example:
X0(t+1) = x1(t)
X1(t+1) = x2(t)
X2(t+1) = x0(t)+x2(t).
Modular Linear Feedback Shift Register
Modular Linear Feedback Shift register are faster than Standard linear
feedback shift register because there are so many XOR gates that are
connected to each other which results in delays in the circuit whereas in
Modular Linear Feedback shift register there is only one XOR gate in
between the adjacent flip-flop.
Block diagram of Modular linear feedback shift register
............ hn-2
hn-1
H1
H
0
X0 X1 Xn-2 Xn-1
There will always be a feedback from last flip-flop to the first flip-flop.
Relation between next state and present state
X0(t+1) = Xn-1(t).
X1(t+1) = X0(t) + h1Xn-1(t).
......
Xn-1(t+1) = Xn-2(t) + hn-1Xn-1(t).
LFSR's cannot generate all set of possible combination from 0 to 2^n - 1

Response Compactor
There is one thing before starting anything about Response Compactor i.e.
,Flat design.
We use ROM to store the Golden response so that it can be compared with
the response of the CUT .Now if the response of the CUT is big suppose of n-
bit and if we store the same result in the ROM then it will take n bits to store
the golden response, so storing the same result as it is in the ROM then ROM
will have the simple design that is called a Flat design.
But if compact the result of CUT by response compactor then it will take less
bits to store the data. Hence the size of the ROM will be less.
Now the compaction can be done by two methods
By counting number of 1's

By counting number of Transition.
By counting number of 1's

In the counting of number of 1's method, the number of 1's will be
counted from the response of CUT and will be stored in the ROM rather
than storing all the bits in the ROM to save space.
Example-
x0 1001110 no. of 1 is = 1
0001100
x1 0011101
0001000
x2 0111010
no. of 1 = 2
x0 1001110 0001100
x1 0011101
0001100
x2 0111010 1111111
S-a-1
when there is no fault in the circuit then no. of 1's in the output is 1 while we
can see that when there is stack fault(when all bits are 1) in the x2 signal then
no. of 1's in the output is 2.
So number one doesn't match that ROM has stored i.e. 1 with the response
after the compactness,here non-aliasing occurs. In the number of 1's count
both aliasing and non-aliasing occurs.
Aliasing Case: In the Aliasing case number of 1's will be same but the
position of 1's will be different.
Example:
no. of 1's = 2
1001110
0001100
0011101
0111010
Data stored by ROM

no. of 1's = 2
1001110
0011101
S-a-1 1000100
0111010
Response of Compactor
Now we can see that the Golden response of the ROM is different from
compactor response as the position of the 1's are different. Thus Aliasing is
there.
If we use any of the Compaction techniques then number of bits required to

store the data is log2 n whereas if no compaction technique is required then
number of bits required is n when the output result is of n-bits. So we can
clearly say that number of bits is less after compaction then by using Flat
design.
By counting number of transition
In the number of 1's transition we'll count the transition in bits of response
from the compactor which will be stored in the ROM.
Ex: 10101001 , number of transition in this word is
10101001 is 6
Normal circuit: no. of transition is 2

Faulty circuit:
no. of transition is 2
Now in this case the number of transition is same ie 2 but if we have used the
number of 1's count then result is different and we can say that there is some
error.
Question and Answer
Q:In BIST how do we know which LFSR is to be used for pattern generator?
A:
LFSR have same width as the number of input bits.
To generate all possible set of combination we will use primitive
polynomial but if we want to have some sets of combination then we
will use non-primitive polynomial.
We will decide Seed by fault simulation.
We will always try to cover the necessary seeds at first and unnecessary
seeds at last so that circuit can be tested fast.
Q:Why LFSR cannot have all 0 state?
A: LFSR cannot have all 0 state because the feedback is connected using
XOR gate which will continue to have 0 state in LFSR.

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BIST-BUILT IN SELF TEST

Basic Architecture of BIST

Hardware Test Pattern Generator

Suppose if we have n number of test patterns, then we will use that

Output Response Compactor

Test controller will control the HTPG,MUX,ROM and output response

Hardware Test Pattern Generator

HTPG can be implemented using LFSR(Linear feedback shift register)

Standard Feedback Shift Register(SFSR)

SFSR block diagram is shown as follows

LFSR's cannot generate all set of possible combination from 0 to 2^n - 1

Now the compaction can be done by two methods

By counting number of 1's

By counting number of 1's

Data stored by ROM

If we use any of the Compaction techniques then number of bits required to

By counting number of transition

Normal circuit: no. of transition is 2

Q:Why LFSR cannot have all 0 state?

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