685 I Transistor Analyzer

OPERAT I N G MANUAL
GENERAL DESCRIPTION

The EICO Model 685 Dynamic Semiconductor and Circuit Analyzer is a "state of the art" instrument
that tests bipolar transistors and field effect transistors (FET's) both in and out of circuit. It can
also be used to test UJT's, SCR's, and many types of diodes. In addition, an accurate voltmeter
and ohmmeter are integral parts of the Model 685. This tester has been designed to fulfill the
technician's requirements of convenience and speed while satisfying the engineer's need for
accuracy and versatility.

FEATURES

1. For bipolar transistors, checks power, signal and critical RF types in or out of circuit,
reading a-c beta accurately. Measurement of leakage currents I CBO' l CEO' and ICES can be made,
with the results displayed on an accurate compressed meter scale.

2. FET's can be checked for a-c transconductance (gm), as well as gate leakage (lGSS), zero bias
drain current (lDSS), and pinch-off voltage (Vp)' Both enhancement and depletion devices can be
checked with equal ease and with equally accurate results.

3. The versatility of the instrument permits its use in performing significant tests on other semi-
conductor devices such as unijunction transistors, controlled rectifiers, power rectifiers, signal
diodes, and zener diodes.

4. A built-in d-e voltmeter and ohmmeter, using a single knob setting, permits convenient testing
of the circuit that contains the semiconductor being checked.

5. A 50-microampere 6" Taut Band meter used in combination with close tolerance (1%) resistors,
ensures accurate readings and provides sufficient sensitivity to obtain meaningful leakage measure-
ments.

SPECIFICATIONS
Bipolar Transistor Tests
AC Beta (in and out of circuit) : 2-100 (readings to 1000) at Ic = 0.2 ma for RF
devices
2-100 and 2-1000 (readings to 10,000) at Ic = 2
ma for small signal devices
2-100 and 2-1000 (readings to 10,000) at I c = 20
rna for power devices
I CBO: 0-5 ma
lCEO: 0-5 ma
ICES : 0-5 ma

FET Tests
AC Transconductance (gm)(in and out 0-5000 and 0-50,000 micromhos at VDS = 5v
of circuit): and VGS = 0
IDSS: 0-50 ma (linear scale)
laSS: 0-5 ma
Vp : 0-20v at VDS = 5v

COPYRIGHT 19]0 [ICO ELECTRONIC INSTRU~ENT COMPANY, Inc.

1
UJT Test : Establishes co ndit ion of device

SCR and Triac Test : Establishes condition of dev ice and indicates
gate turn-on voltage

Signal Diode and Rectifier Test: E stablishe s condition of device from forward
and r ev erse current tests.

Zener Diode Test: E stablishe s co nd it ion of device a nd indicate s

ze ner breakdown volta ge

Voltmeter: 0-500 volts (30 volts center scale), 1 me gohm

r esistance

Ohmmeter : 400 ohms to 10 meg ohms (130 kilohms center

scale).

Semiconductor Complement: 2 - 2N5172

1 - 1N3600 (selected)
1 - 1N662
2 - 1N34
5 - 100 PIV, 500 rna r ectifier s
1 - 6. 8-volt ze ner
1 - 9. I-volt ze ner
1 - 24 -v olt zener

Meter Movement: 50 u a 2% Taut Band

Power Requirements : 105-132 volts, 50/60 Hz, 10 watts

Size : 12-1/2" high, 8-1 /2 " wide , 6" deep

Weight: 10 pounds

TRANSISTOR BASICS

General. The following paragraphs will provide the user of the EICO Model 685 with useful
transistor background information. Familiarity with this information will help the technic ia n
to make meaningful use of this instrument. For a more co mpr e he nsive description of the subje ct,
the r eader is r eferred to Howard W. Sa ms & Co. publication No. 20659, " P ractical Design with
Transis tor s. tt

Term inology. Since the Model 685 che cks ma ny parameters of both bip olar a nd FE T type
tr a ns is tor s, the user of this instrument s hould be familiar with the terms employed . The
terminals of a bipolar transistor a re de s ignated C (colle ct or), B (ba se) , and E (e m itte r) . In
a field effec t transistor (FE T), the terminals a re D (dra in), G (gate ), a nd S (source) . By using
these abbreviati ons a s subletters , various terms can be designated. For exa mple , bipolar
transistor term ICBO repre sents the leakage cur r e nt flow between collector (C) a nd base (B),
with the 0 indicating that the th ird e le me nt , the e mi tte r (E) in th is case , is ope n. Similarly, the
bip olar transistor term I CEO s tands for the leakage cur re nt flow between colle ctor and e mitter ,
with the base ope n.

2
The terms IDSS and less are used with FET's. IDSS represents the current flow from drain (D) to
source (S). The third subletter, S, indicates that the second element (the source) is shorted to the
third element (the gate) so that zero bias exists. Thus, IDSS is termed the zero bias drain current.
IGSS is gate -to-source leakage current. In this case, the second element (the source) is shorted to
the third element (the drain).

Bipolar Transistor Tests. The Model 685 is designed to measure a-c beta, ICBO, and ICEO of
bipolar transistors . Beta, represented by the Greek letter IJ ,is the current amplification factor.
It is the rate of change in the collector current divided by the change in the base current while
maintaining the collector-emitter voltage constant. The range of IJ values varies with transistor
types. The Model 685 provides five scales for measuring the IJ of r-f, signal, and power transistors.

ICBO, the leakage current that flows between base and collector, is another significant parameter
that can be measured. Leakage current is especially critical in circuit s where large temperature
variations are encountered, since the leakage current increases when the temperature rises.

ICEO, collector-to-emitter leakage current with the base lead open, is another bipolar transistor
parameter of interest. Transistors characterized by excessive values of leakage current ICEO
are undesirable for many applications. ICES' collector-to-emitter current with the base lead
connected to the emitter, can also be measured.

FET's. The FET is somewhat similar to the vacuum tube in that the input terminal (gate) is
reverse biased and the output (drain) current depends upon the gate voltage. Characterized by
a high-impedance input, the gain of an FET is a function of its transconductance (gm)' Its
characteristic curves resemble those of pentode vacuum tubes. The two basic FET types are
the junction FET (JFET) and the metal-oxide semiconductor gate FET (MOSFET). The latter
is also known as the insulated gate FET (IGFET). Both devices may have either a P-channel or
an N-channel.

Three modes of operation are associated with FET's: the depletion mode, the enhancement mode,
and the depletion-enhancement mode. JFET's operate in the depletion mode; i.e., drain current
flows even in the absence of a gate-to-source voltage, VGS' For the N-channel JFET, a negative
gate voltage lowers channel conduction. A positive gate voltage has a similar effect on the P-
channel JFET. The amount of voltage required to reduce channel conduction to zero is called the
pinch-off voltage, Vp'

Only IGFET's are used as enhancement devices. Here, zero bias cuts off drain current. For
N -channel FET's, drain current increases as VGS is made more positive. In P-channel FET's,
more negative values of VGS cause drain current to increase. IGFET's are made in both the
enhancement and depletion types. An ENHANCEMENT-DEPLETION switch on the Model 685
selects the proper bias for the type of FET to be tested.

FET Tests. The Model 685 provides readings of ac transconductance (gm) as well as IDSS, less,
and pinch-off voltage. IDSS is zero bias drain current. lGss is gate leakage current. These four
tests represent the most significant FET parameters. When used in balanced circuits, FET's must
be carefully matched for gm'

CIRCUIT DESCRIPTION

The following paragraphs provide a brief description of the circuits used when each of its various
test functions is being performed by the Model 685. In each case , a simplified schematic diagram
of the circuit is presented as an aid to understanding the associated description. For purposes of
simplification, N-channel FET's and NPN transistors are described in the text. However, the
drawings also show the circuit variations for testing P-channel FET's and PNP transistors.

3
a. FET gm Calibration (See fig ures l A a nd l B. )

In ge ne r al , the upper winding of Tl dev elops the basic drain voltage required for testing F ET 's
while the bot tom winding pe rforms a s imilar function for the F E T ga te . The a - c voltage dev e loped
acr os s the upper windi ng perfor m s a seco nd function . In conjunction with diode s Dl and D2 , it
p rovide s a full-wave r e ctified voltage that is filtered by R3 and Cl. A cons ta nt +6. 8 -volt le ve l is
de velope d a cross zener diode D5. This d- e voltage serve s as the colle ctor s upply for ba lance
transistors Ql a nd Q2 . It is also div ided down by R4 a nd R5 for use in othe r circuits of the
Mode l 685 .

RI
o "-... 01
RB
22
FET Qm
CAL
R1
10 0

~)
10 K

0 1 1 it'
~~ 03

TI
~
R3
3. 0
=

1
+
1 c2
~ II-r-
R4 'it'f- 011
~ CI
25 0
05
6 .BV
41 0 '" - - 10 0

~
od ~ T
*
R5
68 0

R2
10K * \.t-... )
R'
50

] ~

=
II- 04
0 1 02
c::::J
~
N - CHANNEL

P- CHAN NEL
~N- CHANNEL
RI2 RI3
400 10 0 RIO

/~
22 K
-L o _ P - CHANN EL

07 ~~ 08 ~
, RI4
22 .5 GATE
RI.
-
\ ,-
DRAI N

) SOURC E
RI5 IK
2.4 DEPL ETI ON
TYPE FET

F igure LA , gm CAL Ci r cuit, Depletion Mode F ET

4
 n --........... 01
R8
22
FETqm
CAL
R7
R' '00

CO
10K

TI
~
ol ~
~.
R3
390

"'=
~ 03

-+
, ~ 011 1"
~ lI Ci 250
~~~ 05
6 .8V
R4
470
MI
- - r - 100

'- 02 ~ r-
~
~ R5
680
-:...
R2
10K
tP)
\~
R9
50

] ~~
~
04
n/
c::::J
02

N- CHANNEl

P-CHANNEl
R'2
400
RI3
10 0
- RIO

/~
22 K
"L ENHAN CEME NT
TYPE FE T
RI9 DRAIN

07 ~ 08 '
RI4
22.5
IK GAT E
--- ~
' - - ' SOURCE
RIO
2.4

Figure l B. gm CAL Circuit, Enhancement Mode FET

Diodes D3 and D4, in conjunction with r e s is tor s Rl and R2, clip the negative -going voltage
excursions supplied by the same transformer winding . The waveform at the base of each
transistor is develope d as follows: When the a -c input is positive going, that transistor is forced
into saturation. At saturation, the collector-to -base voltage drops to a low va lue . This causes
the base voltage to r ise almost to the 6.8 collector voltage, producing the positive portion of the
waveform shown at the base . When the a-c input goes negative at the end of the first half-cycle ,
it forward biases the diodes connected at the bases, clipping the a-c voltage at abo ut 0.2 volt.
(The 0. 2 volt is the nega tive portion of the waveform shown. ) The associated transistor is turned
off as a r e su lt of the low base voltage . Thus, Ql and Q2 cond uct on alte rnate half cycles, switching
on a nd off.

5
When Q1 conduc ts, it s collector current passes through M1 in series with R9 (the combination of
whi ch is shunted by R7 and R8) and the n through series r esistor RIO. When Q2 conduct s, it causes
current to flow through the series com bination of M1, R8, and R7 , shunt-conne cted R9 , a nd series
resistor RIO. In this ca se , the direction of curr ent flow through M1 is r eversed. Sinc e the value
of RIO is much higher than the oth er r esistors , most of the voltage developed at the e mitte rs of Q1
and Q2 appears ac ros s RIO, producing the waveform shown. This cons titutes the drain voltage
supply for the FET under test.

When the front panel FET FUNCTION switch is set to the gm CAL position and a deple tion mode
FET is being tested , the gate of the FET under test is sh orted to the source via R19 (figure 1A).
For e nhance me nt mode FET's , the gate is similarly sh orted to the drain via R19 (figure 1B).
Therefore , the drain cur r e nt of the FET is controlled mainly by the drain voltage pul se s applied
from the Q1-Q2 switching cir cuit. The FET gm CAL contr ol R7, is adjuste d so that e qua l currents
flow through the meter on alternate half cycle s . Since equal curr e nt flows in both dire ctions , when
a djus te d, balan cing the circuit produ ces a zero meter r eading. This cal ibrate s the FET gm
circuit .

N-channel or P-channel FET's ope r ating in either the depletion or e nha ncement mode ca n be
calibr ate d for test. The switching circuit s in the Model 685 se t up the proper pol arities a nd
voltage s for the pa r ticula r type se le cte d, as sh own.

b. FET gm X 1 Operation.

When the FET FUNCTION switch is se t to the gm Xl position, the circuit assumes the form sh own
in figures 2A and 2B. At this time, a constant a mplitude (0.4 volt peak-to-peak) square wav e
developed acros s R14 a nd R15 is applied to the gate of the FET under test. The square wave is
derived from the lower winding of transformer T1. The combination of diodes D7 and D8 in series
with R12 clips the a -c waveform , which then appears acr oss R13, R14, and R15. Potentiom eter
R13 is adjusted so that pre cisely 0.4 volt peak -to-peak is developed a cross R14 and R15.

When the square wave s ignal is fe d to the ga te of the FET being tested, it cause s the FET to conduc t
more heavily on one half of the cy cle than the other. Current flow through the meter the n become s
unequal, producing a meter r eading. The signal polarity is arrang ed s o that meter cur rent in the
forwar d dire ction e xcee ds the meter curre nt in the reverse dire ction for the par ticular FET under
test , produ cing a normal up-dire ction me ter defle ction. Since gm = ~~ a nd AVG is ma intaine d
cons tant, the meter r e ading produced by the change in dra in current is proportional to the gm of
the FET and is calibrated a ccordingl y (0- 5000 v mhos).

c . FET gm X 10.

When the FET FUNCTION switch is set to the gm X10 position, the voltage applied to the gate of
AID
the FET under test is r educed fr om 0.4 volt to 0.04 volt peak-to-peak. Since gm = AV and the
G
constant AVG is 1/10 the value used for the gm Xl measurement, the meter r eading become s
gm X10, providing a maximum r eading of 50,UOO u mhos.

d. Mea sureme nt of IDSS' (See figure 3. )

Whe n measur ing IDSS (ze ro bias drain current), the gate is sh orted to the so urce for the dep letion
t ype FET a s described for gm calibration. Th is te st doe s not apply to e nha ncement type FET's.
For the IDSS measurement , mete r M1 is s hunte d by 1. 87-ohm r esistor RH. Resistor R9, in the
e mitte r circuit of Q2, is sh orted. When power is applied to the ci rcuit , a pul sed vol ta ge again
appear s at the drain of the FET under test. Howev er , cur re nt flows through meter Ml onl y whe n
Q1 is turned on. (When Q2 conducts , no cur rent fl ows thru M1. ) Th e me te r is cali brated with the
shunt to r ead 50 rna of IDSS at full scale.

6
 n 01
R8
FET g m
CAL
RI <, 22 R7
100
10'
ff"'" )

~~
~
TI
01~ R' =
0'

~ 390
+
, 1
I1
R4 c2
Oil
~~
MI
~ CI 0' 4 70 - ' 10 0
6 .81/
2' 0
'- 02 ~~ R,
-= 68 0

=
P)
R2
10 '
R'

I"'" '0

] 4 ~ 04

0 . 4 1/
o
c::::J
02

N ~CHANN E L

RI2 RI3 p -p p- CHANNEL

400 10 0 / RIO
-=

/~
22'
'L Om
XI
GATE
r > DRAIN
RI4 _ ~CE
07 ~~ 08 ~ r- . 041/ pP -.... W
, 22 .'

RI>
om
XIO
RI'
"
-
N - CHANNEL
2 .4
o p - CH ANNEL

Figure 2A. gm Xl - gm XIO Circuit , Depletion Mode F ET

e . Diode Testing .

The diode test cir cuit is the same as that used for mea sur ing lDSS' (see figure 3. ) In this case,
the diode under test r a ther than an FET is connecte d betwee n the drain and so urce terminals.
When the TYPE SE LE CTOR switch is set to the DIODE -ON so urce position, the ano de of the diode
is connected to the drain connection and the cathode to the source connection (gr ound terminal).

7
 n "--. 01
R8
22
FET Om
CAL
R7
RI
' DO

~)
lOX

D , .4 ~ 03

T' R3 ~
39 0

1c2
~

l1 Cl R4 ,~
~~
M'
~ [- 0' Oil - " DO
470
0 .8 V
2
'0
~
OzA ~ ~ R,
080

R2 '=
'OX
tV) R9
'0

] ~

-0:
II- 04

O.4 V
c:::J
0 /\;
N-C HANN EL

p -p
R.2 R' 3 p- CHANNEL

/.
400 'DO /
- R'O
22X
L 0m

R'4
1.::. GATE
r , ORA' N

~CE
07 ~ 08 ~r F- .04V
22 .'
p -p - - -
W om R'9
IX ----
X'D
RO> N-CHANNEL
2.4
o P- CHANNEL

F igure 2B. gm Xl - gm XI O Circuit, Enhanceme nt Mode FET

Since the diode is for ward bia sed, current flow through the meter ( a function of the QI collector
current) is r elatively high, and an up -meter deflection is produced. When the TYPE SELECTOR
switch is set to the DIODE- OF F po sition, the diode connections are r ever sed, the di ode is ba ck
biased , and no (or very little) meter defle ction occ ur s. The r atio of the diode-on to diode-off
meter r eadings is an indication of the quality of the device . Higher ratios are, of cour se, mo r e
de sirable .

8
 n ~ 01
R8
22
FET Om
CAL
R7
RI
100

~)
10K

4 ~ 03
01 ~~
TI R3 ~
,- 390

h \. R4 RII MI
+

, 011
1c2
- r - 100

'- 02 ~~
I
l CI
250
4 " 60 .8V
' 470

R5
1. 8 7

"'= 680
02
R2 ~
10 K
R9
I ce: ) 50

] "'=
~ 04

r:
c:::J alOD E ON
N - CH ANN E L ( FE T)

DiODE OFF
RI2 RI3 p ; CHANNEL (FET)
400 100 -=- RID

/~
22K
"L
R I4
GATE
- \
DRA I N

] DiODE
r 22 . '
07 4
08 1

RI5
RI9
<, SOURCE

r
IK
2.4

F igure 3 . lOSS Measurement (Dep letion Only) and Diode Te sting

f. Measurement of ICBO'

When measur ing lCBO in a bipolar transistor, the co llector an d base a re co nnecte d to a metering
circuit drive n by a 4-volt d- c s upp ly, as s hown in fi gure 4A. Diode 0 6 s hunts cur re nt a round the
me ter c irc u it at highe r leakage cur rent values, effective ly compre s s ing the uppe r end of the
0 -5000 u a leakage scale . At low le ak a ge value s , the diode opens , result ing in a linear scale at
the low e nd of the d ia l. Th us, low va l ue s of leakage can be accurate ly r ea d , while still per mi tting
high-le aka ge measurement, all on one s ca le and one knob setting. The NPN or PNP se tting of the
T YPE SELECTOR switch dete rm ines the connect ions for the transistor unde r te s t.

9
 01
R3

~
390n 6 .8V
0 11
-= CI PNP
02 20 0 0' R4
T -e-
4 70 R6
25K
4V
R,
680
0 - 5000uo
-=
06
\ NPN
E

A. I CBO

6 .8 V
6 .8V
0 11 Oil
R4
470 R6 r
R4
470 R6 .
~
N- CHANN EL

~
25K PNP 25K
N- CH

~
T
R, MI R, MI
68 0 680
0- 500 0 uo lNPN ~ 0 -5000uo P'C H AN N EL

7:-
..
06
C -=
7:-
...
~

06 P- CHANNE L

B . ::ICED

F igur e 4. lCBO' lCEO' and JoSS Measurement

g. Measurement of lCE O and ICES'

lCE O measurements are made in a similar fashion as lCBO ' (See figure 4B. ) In this case, the
base of the bipolar transistor under test is open, and the collector-e mitte r leakage is measured in
the same d-e cir cuit . ICES is measured using the identical circuit, but in this ca se the base lead of
the transistor is conne ctedto the e mitter lead of the transistor .

h. Measurement of lGSS'

When measuring lG S in an FET, the source and drain are shorted by the Model 685 and the s ame
basic circuit descrf6ed in "f " above, is used to measure leakage cur r e nt. (See figur e 4C. ) The N-

10
CHANNEL or P-CHANNEL se tti ng of the TYPE SELECTOR s wit ch determines the co nne ctio ns
r equired for the FET under te st.

i. Measure men t of Vp.

When me a suring Vp , a calibrated negative voltage is fed from the ar m of VOLTAGE control RlB to
the gate of the FET under test . (See figure 5. ) Drain cur re nt is then monitored by meter Ml,
which is connec te d in a s hunt diode co nfigur ation as previously de s cribed for the leakage measure-
ment circ uit s . As the a r m of the control is turned up , the FET gate is driven more ne gative and
the drain cur re nt r eading on the leakage scale is r educed. When cur re nt has decreased to the
pinch-off lev el (generally taken as 50 ua) , the Vp voltage is read off the 0-20V calibrated
VOLTAGE control dial.

6 . 8V
N- CHA NNEl
R4
470
P-C HANNEL
R5 G
680

06
IK RI9
IK

P/O RI6 RI7 VOLTAG E

TI 09 3 90 2K CONTRO L N- CHANNEL

P - CHANNE L
C3 010
]
, '- ... 100/25
.. RI8
5K
. . -0-_. N- CHAN N E L

P - CHANNEL

Figure 5. Vp Mea sureme nt

j. SCR and Triac Testing.

To che ck an SCR, it is conne cted a s shown in figure 6. The SCR ca thode is conne cted ba ck to the
arm of the VOLTAGE control , and the SCR ga te is r eturned to the bottom of the control a s sh own.
U the arm of the co ntrol is set to the low end, ga te vol ta ge is ze ro with r espe ct to the cathode, and
the SCR r emains off. As the a r m of the contr ol is r aised, the gate -to - cathode voltage rises. When
the turn-on voltage level is r eached, the SCR conduc ts, produc ing a defle ction on the meter . On
a good SCR , the dev ice can be turned on a s the voltage is increa sed fr om ze ro and tur ned off as the
voltage is r educed to ze ro .

A Triac is co nnec ted in a like manne r. The ga te connec tion is the sa me as for the SCR. One
anode i s connected to the cathode lead and the othe r to the an ode lead of the SCR test. In one
dire cti on of co nnection, the Tria c will con duct , r e gardle ss of the VOLTAGE control se tt ing.
Reversing the con nec tions to the Tria c a nodes will produce defle ction only a s the VOLTAGE
cont rol is advanced, a s in the ca se of the SCR.

11
 R30
330K

0-5000 MI
ua RI'
06 IK - 20V
+
RI8
R6 5K
25K VOLTAGE
CONTROL
+

. Figure 6. SCR Te s ting Figure 7. Zener Diode Testing

k, Zener Diode Testing.

In the test circuit shown in figure 7, the zener diode under test is connected across the 0-20-volt
supply. When the VOLTAGE control arm is turned up from its minimum voltage position, the
meter current through R30 increases and the d-c voltage across the diode rises. When the zener
breakdown voltage is reached, the diode under test conducts, limiting the voltage across the series
combination of R18 and R19 to the zener voltage. Further rotation of the VOLTAGE control arm
does not increase the voltage across R18 and R19 and the meter reading does not change. The
zener breakdown voltage can then be read off the VOLTAGE control dial as the lowest voltage
reading that will not permit the meter to deflect further.

1. Measuring (3 in Bipolar Transistors.

Transformer T2 supplies the voltages necessary to measure a-c beta ( (3 ) in bipolar transistors.
In the r-f transistor test circuit of figure 8A, diodes D12 and D13 clip the a-c voltage developed
across the BIPOLAR (3 CAL control so that a square wave of fixed voltage is impressed across
the primary of T2. This control sets the a-c input to T2 to a level that produces 0.2 rna of average
collector current in the transistor under test. The meter shunt resistors are designed to provide
full-scale deflection (corresponding to (3 = 2 on the Model 685) at 0.2 rna of collector current.
(The circuit shown applies to NPN transistors; the PNP test circuit is similar, with meter polarity
reversed. )

When the PUSH TO READ (3 switch is held down, the meter is transferred to the base circuit of the
transistor to measure the average base current. (See figure 8B.) Since 13 = ~~C and I C
is maintained constant at 0.2 rna, (3 is proportional to 4.iB and the meter is caribrated against
the average base current reading. The (3 scale on the Model 685 is calibrated downward rather
than upward because of the reciprocal function.

A similar circuit is used to measure (3 of signal transistors. (See figure 9.) In the SIG 13 Xl
position of the BIPOLAR FUNCTION switch, the BIPOLAR 13 CAL control is adjusted for an
average collector current of 2 rna . Operation of the 13 measuring circuit is the same as that
described for the RF 13 Xl position of the BIPOLAR FUNCTION switch.

12
 R25
450

C6
50 0

R23
900 O. lma

+ M

T2

011
01 2 9V R21
10 K
BIP OLAR
9V fJ CAL C5 R24
0 13 4 50
C4 50
.1
R2 0 C7
5K ,012

A. CALIB RATION CIRCUIT

C6
500

R24
4 50 O.2 ma

JlI R2 5
4 50
0 11

R2~
900

C5 C
50
\
)
'--'
E

B . TEST CIRCUIT

Figure 8. RF T ransistor Testing

13
 C6
500 C6
500

.2 3
900 2m, . 25
45 0 2m,

. 26 . 28
2 3.65 50
C5
T2 0 11 50 T2
.23 ..- C

]II .26
23 . 65 .24
4 50 /'
C JlI 9 00
8
--.:::.)
8 \ t E
MI
C7
. 0 12
.28 E 0 11
50

A. CALtBRATION CIRCUI T B. TEST CIRCUIT

Figure 9. SIG 13 Xl Transistor Te sting

In the SIG X10 position , the resistance in the base circuit is increased to 10 times its original
value (from 45 oh ms to 450 ohms) so that the same full -scale defle ction of 2 ma (now co r re s -
ponding to 13 = 20 on the Model 685) is produced by 1/10 the base cur rent. (See fi gure 10. ) In
effe ct, the metering cir cuit is now 10 times more sensitive, measuring 13 values fr om 20 to
1000, with readings to 10,000.
C6
500

.23 .24
900 2m , 4 50 2m ,

.26
23 .65

C
T2 T2
~

0 11 C5 8
50
]11 .26 ]11
.23
900 '-.: E
23.65 C
. 24
450
8
..-
011

A . CALI BR AT ION CIR CUIT B. TE ST CIRCUIT

F igur e 10 . SIG 13 X10 Transistor Testing

14
 When using th e PWR /l Xl position of the BIPOLAR FUNCTION s witch, ful l -scale me ter defle ction
is produ ced by 20 rna of co llector cur re nt . (See figure 11. ) As in th e othe r /l p os itions, the me ter
is switched to th e base circuit to me asure the /l of powe r transistors.

C6
500
+
C6
500
. 23 +
9 00 lO ma
. 24
4 50
20ma

. 27 . 29
Oil 2 .26 4~ 4
C5
72 50
T2 C
.23
]/1 . 27
2 .2 6 . 29 ,,-
C
]11
900 B
~

4 .5 4 I
E
) C7
.24 E .0 12
450
01

B. TE ST CIRCUIT
A . CALI BRATION CIRCUIT

Figure II. PWR /l Xl Transis tor T e sting

In the PWR /l XlO position, the base r esistance is again mad e 10 times its previous va lue ,
pe rmitting /l value s be tween 20 and 1000 to be measure d, with r e ading s to 10 ,000 . (See figure 12. )

m. Ohmmeter Operation.

Th e oh m me ter c irc uit a l so mak e s use of the diode - controlled co mpre s sed sca le circuit. (See
figure 13 . ) The VOLTS/OHMS te r minal s ca n be used to measure resista nce values ranging fro m
400 ohms to 10 megohm s , all on one scale and at the same knob setting.

n, Voltme ter Operation .

In vo ltmete r ope ra tion, d-c power is r emoved fr om the metering ci rcuit . (See fi gure 14. )
Multiplier r e sis to r R30 per mits me a sure ment up to 500 volts. Aga in , the co mpr e ssed sca le
prov ide s a linear calibra tion at lower vo ltages (nor ma lly used in tra nsistor circuit s) , while
permitting h ighe r vo ltage measure me nts on the comp r essed e nd of the s ca le . All r e a di ngs a re
made while using onl y one knob se tting .

15
 A. CALI BRATIO N CIRC UI T B. T EST CI RCUI T

Figure 12. PWR IJ X10 Transistor Testing

+ 6 .8
+ 6 .8
011
0 11
~
R4
47 0 R5
~I
r
R4
4 70 R5 ..,-
25' 2 5' R3 0

t + T + MI
'3'38K
VOll/ OHMS
MI VOLT/ OHMS R5
R5 5 80
5 80

-= ~I
, 1 VOLT/ OHMS
----<

-=- ..
~ 1 VOLT / OHMS

05 05

Figure 13. Ohmmeter Circuit Figure 14. Voltme te r Cir c uit

16
OPERATING CONT ROLS AND INDICATORS

T able 1 lists the ope rating co ntrol s on the Model 685 and indicates their functions.

Table 1. Controls and Indicators

It em Function

TYPE SE LECTOR switch Two-position s witch that selects typ e of

ope r a tion.

Left -ha nd position

N-CHANNEL - for FET transistor s
NPN - for bipol ar tra nsistor s
400-10M OHMS - ohm me te r
DIODE -ON - forward b ia s on di ode unde r test
ZE NER - fo r zener diode tests

Right -hand position

P-CHANNEL - for F ET tr a ns istors
P NP - for bipol ar trans istor s
0 - 500 VOLTS - d-e voltmeter
DIODE -OFF - r ever se b ia s on diode under test
SCR - for SCR and T ria c tests

DEVICE SE LECTOR swi tch Two -p osition s witch that se le cts de vice or
function tested .

Le ft - hand p osition
FET - fo r a ll Field Effe ct Tran s is tor te s ts
UJT - for Unijunc tion T ra nsistor tests
DIODE - for power r e ctifie r and signal di ode
te s t s
SCR - for SCR a nd T r ia c te s t s
ZE NER - for ze ne r di ode tests

Ri ght -h and pos it ion

BIPOLAR - for bip ola r trans is tor testing
0 -5 00 VOLTS - d - c voltme te r
400 -10M OHMS - ohm me te r

EN HANCE ME NT -DEPLE TI ON Se lect s proper FET ga te bias for e nhancement

sw itc h mode (IG FE T ' s only) or DEPLETION m ode
(J F E T ' s a nd ce r ta in lGFE T ' s )

P USH FOR ZEN E R T EST Depressed when performing ze ne r di ode tests

momentary a ction switch

17
 Table 1. Controls and Indicators (cont)

Item Function
.

FET FUNCTION switch Selects FET parameter or other device to be

tested

Position Function
Reads 0-5000 P mho FET
transconductance
Used when zero calibrating
gm meter scale
Reads 0 -50,000 P mho FET
transconductance
IDSS Used for measuring I DSS in
DIODE FET's on 0-50 rna scale and
for testing diodes
V Used for measuring VII in
S~R,ZENER FET's and for testing SCR's,
Triacs and zener diodes on
voltage scale printed on panel
IGSS Used for measuring lass in
UJT FET's on 0-5000 ua scale
and for testing UJT's

FET gm CAL control (10 turn)

VOLTAGE control Used to determine Vp in FET's, allows for SCR

gate turn-on and turn-off, and measures zener
diode breakdown voltages. Calibrated from 0
to 20 volts

PUSH TO READ fj momentary When depressed, permits fj to be measured on

action switch upper s cale when BIPOLAR FUNCTION switch
is set to a fj or fj XlO position

BIPOLAR FUNCTION switch In some positions, selects type of bipolar

transistor for fj measurement. Also sets
up instrument for measuring leakage currents.

Position Function
RF Used for measuring fj (2 to 100 range-
fj Xl readings to 1000) in r -f transistors at
0.2 rna collector current
SIG Used for measuring fj (2 to 100 range-
fj Xl readings to 1000) in signal transistors
at 2 rna collector current
SIG Used for measuring fj (20 to 1000
fj XlO range -readings to 10,000) in signal
transistors at 2 rna collector current

18
 Table 1. Controls and Indicators (cont)

Item Function

Position Function
PWR Used for measuring {3 (2 to 100
{3 Xl range -readings to 1000) in power
transistors at 20 rna collector
current
PWR Used for measuring (3(20 to 1000
{3 X10 range-readings to 10,000) in power
transistors at 20 rna collector
current
Used for measuring I CBO (0 to
5000 ua)
ICEO Used for measuring I CE O
500V /I! and ICES (0-5000 ~a s cale)
and for setting up d-c volt-
meter or ohmmeter

BIPOLAR {3 CAL contr ol (10 turn) Calibrates meter to full scale prior to making
{3 measurements

FET jacks: SOURCE , GATE 1, Used to connect Model 685 to FET or UJT
DRAIN , and GATE 2 under test

BIPOLAR jacks : EMITTER , Used to connect Model 685 to bipolar transistor

BASE, and COLLECTOR under test

METER jacks: VOLTS /OHMS Connects external cir cuit to voltmeter or

ohmmeter cir cuit in Model 685.

SCR DIODE jacks : CATHODE , GATE, All three jacks are used to connect to SCR under
ANODE test. When testing diodes, only cathode and
anode connections are used.

ZENER ja cks : CATHODE, ANODE Connects Model 685 to zener diode under test

VOLTAGE switch Placed in ON position for all functions except

voltmeter operation, at which time it is set
to PWR OFF.

OPERATING PROCEDURES

The markings on the meter scales and the nomenclature on the front panel of the Model 685 are
color coded to simplify its operation. Red markings refer to bipolar transistors, blue markings
apply to FET's , while silver on the panel signifies other components and functions (such as diodes ,
SCR's voltmeter, ohmme te r, e tc. ). In addition , the four test leads supplied with the unit and the
associated ja cks on the panel have different color s for the same r eason. Although the Model 685
offers a wide variety of test functions , you will find that with a little practice, operation becomes
quite simple. The normal precautions pertinent to transistors should be followed to prevent
damaging them. Insulated ga te FET 's (IGFET's) must be handled in a special manner as outlined
in the foll owin g paragraph . Bef ore attempting to use the Model 685, be sure that you understand
the operating instructions in this section.

19
a. safety Pre cautions whe n Handling lGFET's.

Out of circuit, the lGFET (al so known a s MOSF E T) is subject to s ta tic build-up on an ope n gate
lead and is theref ore subject to damage whe n handled. (Whe n connected in circuit , it is quite
rugged. ) The lG FET is ge ne rally shipped with its le ads sh orted together to prev ent such static
build -up . When testing the lGFET out of circuit, connect the leads fro m the Model 685 to the
lGFET BEFORE the short is r e moved. It is ge nerally wise to take the followi ng precautions.

1. If you are going to connect the lGFET to a cir cuit , keep the sh orting clip on the leads
until the y are soldered to the circuit; then r emove the clip . When r emoving a n lG FET,
sh ort its leads together with a clip before unsoldering them.

2. When soldering or unsoldering the lGFET le ads, gr ound the s oldering iron tip. This
ca n be accomplis hed by connecting a clip le ad fr om the barrel of the s oldering iron to
the Model 685 ca se (a s s uming the uni t is plugged into the a -c line) or to conduit ground.
DO NOT use a soldering gun.

3. Remove power fr om a circuit be fore installing or r emovi ng an lGFET to prev ent damage
fr om voltage transient s . .

b. Measuring Beta (/l ) in Bipola r Trans istors.

1. Determ ine in which of the following categor ie s the transi stor falls : rf , signal, or power.
Transistor r efe r ences co nta in this infor mation. You mu st al so determine whether the
transistor is an NP N or PNP type .

2. Set the panel switches a s follows :

TYPE SELECTOR: NPN or PNP (a s applicable )

DEVICE SELE CTOR: BIPOLAR
BIPOLAR FUNCTION : To appropriate /l position

3. Set the /l CAL co ntrol to the ma ximum counterclockwise positio n.

4. Conne ct the EMITTER (black), BASE (yello w), and COLLECTOR (r ed) leads on the
Model 685 to the cor responding tr a nsistor te rm inal s .

NOTE : You may che ck /l with the transistor IN OR OUT of the circuit. You will
get more accurate r eadings in the out -of-c ircuit te s t.

5. Adj ust BIPOLAR /l CAL control for a full - scale r eading (to /l - CAL mark) on the meter.

6. Pre ss PUSH TO READ /l swit ch and r ead value on top r ed sc ale. (If in a XlO position,
multiply r eading on meter by 10.)

c . Measuring lCBO of Bipolar Transistor .

1. Set the panel switc hes as follows:

TYPE SE LEC TOR : NPN or PNP

DEVICE SE LEC TOR: BIP OLAR
BIPOLAR F UNCTIO N: ICBO
2. Conne ct the leads (as in step b. 4 for /l te sts) to the transistor . Note tha t the trans istor
mu s t be OUT OF CIRCUIT for this te st.

3. Read l CBO val ue on the 0 - 5000 "A LEAKAGE red scale .

20
d. Measuring I CE O and ICES of Bipolar Transistor.

I. For I
CEO
1. set the panel switches as follows:

TYPE SELECTOR: NPN or PNP

DEVICE SELECTOR: BIPOLAR
BIPOLAR FUNCTION: I CEO

2. Connect leads (as in step b.4 for {j test) to the transistor. Transistor must be OUT
OF CIRCUIT for this test.

3. Read I CEO value on the 0-5000 " A LEAKAGE red scale.

II. For ICES

1. set the panel switches as follows:

TYPE SELECTOR: NPN or PNP

DEVICE SELECTOR: BIPOLAR
BIPOLAR FUNCTION: ICEO
2. Connect collector lead to collector of transistor and connect emitter lead to both
the base and emitter of transistor. Transistor must be OUT OF CIRCUIT for this
test.

3. Read ICES value on 0-5000 " A LEAKAGE red scale.

e. Measuring gm of FET.

Before connecting the Model 685 to an FET, determine if that FET is N-channel or P-channel and
if it is an enhancement type, depletion type , or a combination of both. All junction FET's (JFET's)
are depletion types. Insulated gate FET's (IGFET's) may be enhancement or enhancement-
depletion types. U an IGFET is to be tested, be sure to follow the safety precautions previously
outlined.

1. set the panel switche s as follows :

TYPE SELECTOR: N-CHANNEL or P-CHANNEL

DEVICE SELECTOR: FET
ENHANCEMENT-DEPLETION: As required
FET FUNCTION: gm CAL
NOTE : For enhancement-depletion types, you may che ck gm separately in each of
these modes.

2. Connect the source (black), gate 1 (yellow), drain (red), and gate 2 (white, if used) leads
on the Model 685 to the cor r e sponding FET terminals.

21
 NOTE: You may check gm with the FET IN OR OUT OF CIRCUIT .

3. Adjust FET gm CAL for zero (gm CAL) r eading on Model 685.

4. Set FET FUNCTION switch to gmXI or gmXIO (as appropriate) and read gm value
(in " mhos ) on second scale (blue). (If in XIO position, multiply r eading on meter
s cale by 10.)

NOTE: T o check the gm for ga te 2, connec t the leads as ab ove to the transistor ,
except conne ct gate 2 to yellow and gate I to white .

f. Measuring Inss of FET. (Applies to depletion -type only .)

1. Set the FET FUNCTION switch to Inss ' leaving the other switches as for gm
measurement.

2. Conne ct FET as for gm measurement.

3. Read I nss (in ma l fr om blue FET I nss scale.

g. Measuring I of FET.
GSS

1. Set the FET FUNCTION switch to IGSS' leaving the othe r switches as for gm
measurement.

2. Connect FET as for gm measurement.

3. Read I (in "a ) fr om red "A LEAKAGE s cale.

GSS
h. Measuring V of FET.
p

1. Set VOLTAGE contr ol to 0, then place FET FUNCTION switch in V position. Leave
p
othe r switches in same positions as for gm measurement.

2. Connect FET as for gm measurement.

3. Meter on Model 685 will read up scale . Turn up Vp control slowly and note that meter
r eading de creases. When reading on r ed " A LEAKAGE s ca le drops to 50 " a (or to
lower value , if desired), r ead value of Vp fr om calibr a te d dial at VOLTAGE control knob .

NOTE: 50 " a is a ge ner ally r e commended va lue of drain current that corresponds
to Vp. In ge ne ral , a value that lies between 1/100 and 1/1000 of I nss may
be used to establi s h Vp '

i. Che cking Diodes.

The Model 685 provides a forwar d-to-reverse curr ent test that will e s tablish whether or not a
diode is ope rati ng properly, a s described below.

22
 NOTE : This test is most accurate when checki ng OUT OF CIRCUIT. If the di ode
is shunted by a low resistance e lement in th e circ uit, the r esults will be
meaningle s s .

1. Se t the panel s witches a s follows :

TYPE SELECTOR: DIODE ON

DEVICE SELECTOR: DIODE
FE T FUNCTION: DIODE

2. Connect the cathode (black) and a node (red) le ads on the Mode l 685 to the di ode under
te st a nd note the r e la tive r eading on th e blue 0-50 -ma s cale.

3. Turn th e TYPE SELECTOR s witch to the DIODE-OFF position. Mete r defle ction sh oul d
now be ve ry low or none xistent. If it is not , the diode sh ould be di scarde d.

j. Che cking SCR' s.

The SCR te st will indicate th e co nditio n of the device. This te st sh ould be pe rfo rmed with the
SCR OUT OF CIRCUIT.

1. Set the pa nel co ntrols a s follows:

TYPE SELECTOR: SCR

DEVICE SELECTOR: SCR
FET FUNCTION: SCR
VOLTAGE potentiom eter : o
2. Connect ca thode (black), gate (yellow), a nd anode (red) le ads on the Model 685 to the
SCR under test. Th ere should be no defle ction on th e meter.

3 . Slowl y tur n up VOLTAGE pot until a meter defle ction occur s . This indicates th at th e
gate can turn on the SCR.

4. Turn th e VOLTAGE co nt rol ba ck to O. The meter sh ould not defle ct , indicating th at

the SCR will cut off whe n the diode is r ever se bia sed.

k, Che ck ing Tria c s .

The Tr ia c te st will indicate the co ndition of the device . This te st s houl d be performed wi th the
Tria c OUT OF CIRCUIT .

1. Set the pan el controls as follows:

TYPE SELECTOR: SCR

DE VICE SELE CTOR: SCR
FET FUN CTION: SCR
VOLTAGE potentiometer : o
2. Connect gate (yellow) le a d on the Mode l 685 to the ga te of the Tria c unde r te s t . Conne ct
the cathode (black) le a d to one a node and th e a node (red) le a d to th e second a node . If
there is no defle ction on th e meter, r e ver se the leads to the a nodes on the Tria c. When
it ha s been e stabli s he d th a t th e Tria c conduc ts in one direction, r eve r se the le ads to
the Tria c. Now, there s hould be no deflection on th e meter .

23
 1. Set the panel switches as follows :

TYPE SELECTOR: 400-10M OHMS

DEVICE SELECTOR : 400-10M OHMS
BIPOLAR FUNCTION: 500V/n

2. Conne ct the red and black VOLT f ORMS leads on the Model 685 across the circuit to be
measured and read resistance from bottom r ed scale.

o. Voltmeter.

The voltmeter uses the 0-500 segment that corresp onds to the " A LEAKAGE scale. The lower
end of the dial is conveniently expanded to accurately r ead the lower voltage values generally
encountered in transistor c ir cu it s.

1. Set panel switches as follows:

TYPE SELECTOR: 0-500 VOLTS

DEVICE SELECTOR: 0-500 VOLTS
BIPOLAR FUNCTION: 500V / n
VOLTMETER: POWER OFF

2. Connect the red (+) and black (-) leads on the Model 685 across the d-e voltage to be
measured.

CAUTION: If unit on which voltage measurement is to be made does not have a fl oating
power supply, pull the a-c plug on the Model 685 out of the line before
performing measurement.

CALIBRATION (see figure 15.)

Three potentiometers on the PC board must be calibrated prior to operation. several items of test
equipment are required : a standard VTVM and either an a-c VTVM or a scope for measuring peak-
to-peak voltages. The EICO Models 232, 235, 240, or 242 may be used here.

Preliminary Procedure

Set the controls on the Model 685 as follows :

TYPE SELECTOR: N-CHANNEL

DEVICE SELECTOR: FET
ENHANCEMENT-DEPLETION : DEPLETION
FET FUNCTION: gm Xl
BIPOLAR FUNCTION:
VOLTAGE pot: ~U~gax. clockwise)
FET gm CAL pot : fully counte r clockwise
BIPOLAR f3 CAL pot: fully counterclockwise
VOLTMETER: ON

Calibration of R13

1. Conne ct GATE 1 (yellow) and SOURCE (black) leads of Model 685 to peak-to-peak
r eading a-c vtv m or s cope.

2. Adjust R13 (top potentiometer near 250 mfd capacitor) for reading of 0.4 volt peak-to-
peak.

25
Calibration of R17

1. Connect d-c vtvm between terminals F (+) a nd G (-) on PC board.

2. Adjust R17 (top potentiometer near 100 mfd capacitor) for reading of 20 volts de,

Calibration of R6

1. Set DEVICE SELECTOR switch to 400-10M OHMS.

2. Conne ct the red and black VOLT/OHMS lead s ac ros s the 1K, 1% re sistor (11080) ,
supplied with kits onl y.

3. Adjust R6 (near bottom of PC board) so bott om r ed ohms scale on Model 685 r eads
at 1K.

MAINTENANCE

To ga in acce s s to the chassis , r emove the four s crews at the r ear of the ca binet. (Two of these
supp ort the line cor d while in storage. ) Slide the cha ssis from the front of the cabinet.

Visually che ck the parts on the printed circuit board for evide nce of arcing or ove r heating. Make
sure that the wiring between panel swit ches a nd the board is intact.

If trouble should occur in the unit, a thorough understanding of cir cuit ope ration (se e CIRCUIT
DESCRIPTION) will facilitate trouble localizati on. Some troubleshooting hints are outlined below.
Use the overall s che matic diagram as a troubleshooting aid. Each part on the PC board is
identified by a r eference designation which r elate s to the designations on the s chematic diagram.

TROUBLESHOOTING CHART

Symp tom Probable Cause Remedy

No gm r eading can be made. D7 or D8 sh orted. Check both diodes out of
tJ and leakage tests are c ircuit with Model 685.
normal.

gm r ead ings too high or Pote nti ome ter R13 not Calibrate R13 pe r instruc-
too low. calibrate d. tions in this manual.

Leakage a nd gm te sts R22 ope n. Check for ope n r esistor R22

normal , but tJ cannot with ohm meter and r eplace
be measured. if nece s sary .

Meter swings to le ft or right Diode s D3 or D4, or tr an - Che ck diodes and trans is tor s
whe n measuring gm' Beta sistors Ql or Q2 defe ctive. and r epla ce if nece s sary .
and leakage te sts normal.

gm' leakage , di ode , Vp, SCR, D5 or CI sh orted, or R3 There s hould be 6.8 volts at
and ohm me te r functions ope n. + e nd of C1. Che ck D5 a nd
ab normal. Beta and zener Cl for sh ort a nd R3 for open
diode r ec ordings are circui t.
normal.

26
 TROUBLESHOOTING CHART (cont)

Symptom Probable Cause Remedy

Meter reading is abnormal Potentiometer R6 not Recalibrate R6 per mstruc-
for all leakage measure- calibrate d. tions in this manual.
ments, VS' zener diode
tests, an ohmmeter; gf.'
and fJ readings norma.

V , zener diode, and SCR Defective component in 20- Check for 20 volts across
tlsts cannot be made. All volt power supply section. VOLTAGE control. If ab-
other functions are normal. normal, check diodes D9
andD10, C3, R16, and
potentiometer R17.

Calibration of VOLTAGE Potentiometer R17 not Recalibrate R17 per instruc-

control is inaccurate. calibrated. tions in this manual.

RI3

+
@ @
RI7

CI

R6

Figure 15. Location of Calibration Controls

27
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