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    Blackfin Processor

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    KameshSonti
    The Blackfin processor is an embedded media processor designed for audio, video, and communications applications. It combines a RISC instruction set with dual 16-bit multiply accumulate units. This enables it to perform both signal processing and control processing tasks, simplifying hardware and software design. The Blackfin offers high performance while consuming low power, making it suitable for applications such as wireless broadband, Internet appliances, and mobile communications.

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    Blackfin Processor

    Uploaded by

    KameshSonti
    175 views2 pages
    The Blackfin processor is an embedded media processor designed for audio, video, and communications applications. It combines a RISC instruction set with dual 16-bit multiply accumulate units. This enables it to perform both signal processing and control processing tasks, simplifying hardware and software design. The Blackfin offers high performance while consuming low power, making it suitable for applications such as wireless broadband, Internet appliances, and mobile communications.

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    DSP Blackfin Processor

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    The Blackfin processor is an embedded media processor designed for audio, video, and communications applications. It combines a RISC instruction set with dual 16-bit multiply accumulate units. This enables it to perform both signal processing and control processing tasks, simplifying hardware and software design. The Blackfin offers high performance while consuming low power, making it suitable for applications such as wireless broadband, Internet appliances, and mobile communications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    175 views2 pages

    Blackfin Processor

    Uploaded by

    KameshSonti
    The Blackfin processor is an embedded media processor designed for audio, video, and communications applications. It combines a RISC instruction set with dual 16-bit multiply accumulate units. This enables it to perform both signal processing and control processing tasks, simplifying hardware and software design. The Blackfin offers high performance while consuming low power, making it suitable for applications such as wireless broadband, Internet appliances, and mobile communications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Blackfin Processor Architecture Overview

    Blackfin Processors are a new breed of embedded media processor designed


    specifically to meet the computational demands and power constraints of today's
    embedded audio, video and communications applications. Blackfin Processors
    combine a 32-bit RISC-like instruction set and dual 16-bit multiply accumulate
    (MAC) signal processing.
    This combination of processing attributes enables Blackfin Processors to perform
    equally well in both signal processing and control processing applications-in many
    cases deleting the requirement for separate heterogeneous processors. This capability
    greatly simplifies both the hardware and software design implementation tasks.
    The Blackfin Processor offer a combination of high performance and low power. This
    behaviour is essential in meeting the needs of today's and future signal processing
    applications including broadband wireless, audio/video capable Internet appliances,
    and mobile communications.

    Blackfin Processor Core Basics

    The Blackfin Processor core is a load-store architecture consisting of a Data


    Arithmetic Unit, an Address Arithmetic Unit, and a sequencer unit:
    Data Arithmetic Unit
    The Data Arithmetic Unit contains roughly twice the system resources as previous
    Analog Devices 16-bit architectures. It contains:
    Two 16-bit MACs,
    Two 40-bit ALUs,
    Four 8-bit Video ALUs, and a
    Single Barrel Shifter.

    All computational resources can process 8, 16, or 32-bit operands from the data
    register file. Each register can be accessed as a 32-bit register or a 16-bit register high
    or low half.

    Address Arithmetic Unit


    Two data address generators (DAGs) provide addresses for simultaneous dual
    operand fetches from memory. The DAGs share a register file that contains four sets
    of 32-bit index (I), length(L), base(B), and modify(M) registers. There are also eight
    additional 32-bit address registers that can be used as pointers for general indexing of
    variables and stack locations. The four sets of I, L, B, and M registers are useful for
    implementing circular buffering. Used together, each set of Index, Length, and Base
    registers can implement a unique circular buffer in internal or external memory. The
    Blackfin architecture also supports a variety of addressing modes including indirect,
    auto-increment and decrement, indexed, and bit reversed.

    Program Sequencer Unit


    The program sequencer controls the flow of instruction execution and supports
    conditional jumps and subroutine calls, as well as nested zero-overhead looping. A
    multi-stage fully interlocked pipeline guarantees code is executed as expected and
    that all data hazards are hidden from the programmer.

    The Blackfin architecture supports 16 & 32-bit instruction lengths in addition


    to limited multi-issue 64-bit instruction packets. This ensures maximum code
    density by encoding the most frequently used control instructions as compact
    16-bit words and the more challenging math operations as 32-bit double
    words.

    The family of the blackfin processors is much immense but the product we are going
    to use in our project is the Analog Blackfin BF535.

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