Chapter12 - Arithmetic Circuits in CMOS VLSI PDF

Introduction to VLSI Circuits and Systems
Chapter 12
Arithmetic Circuits in CMOS VLSI
Dept. of Electronic Engineering

National Chin-Yi University of Technology
Fall 2007
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
Bit Adder Circuits

Ripple-Carry Adders
Carry Look-Ahead Adders
Other High-Speed Adders
Multipliers
Half-Adder Circuits
Consider two binary digit x and y, and the binary

sum is denoted by x + y such that
0+0=0
0 +1 =1
1+ 0 =1
1 + 1 = 10
(12.1)
Figure 12.1 Half-adder
symbol and operation
A half-adder has 2 inputs (x and y) and 2 outputs

(the sum s and the carry-out c)
s = x y
c = x y
(12.2)
Figure 12.2 Half-adder
logic diagram
Full-Adder Circuits
Adding n-bit binary words

a3a2 a1a0
+ b3b2b1b0
(12.3)
c4 s3 s2 s1s0
In the standard carry algorithm, each of the ith columns (i = 0, 1, 2, 3) operates according
to the full-adder equation
ci
ai
bi
(a) NAND2 logic
(b) NOR-based
network
Figure 12.3 Alternate half-adder

logic networks
(12.4)
ci +1 si
Expressions for the network are

si = ai bi ci
ci +1 = ai bi + ci (ai bi )
(12.5)
Figure 12.4 Full-adder symbol
and function table
or
ci +1 = aibi + ci (ai + bi )
(12.6)
Complementary Pass-transistor Logic
Dual-rail complementary pass-transistor logic (CPL)

ai bi and ai bi
(12.7)
sn = (ai bi ) ci + (ai bi ) ci
(12.8)
ai bi + bi ci
(12.9)
bi ci + ai bi
(12.10)
ai bi + bi ci
(12.11)
bi ci + ai bi
(12.12)
(a) 2-input array
(b) Sum circuit
(c) Carry circuit

Figure 12.5 CPL full-adder design
Full-Adder Circuits (1/2)
(a) Gate-level logic
(b) HA-based design
(a) Standard nFET logic
Figure 12.6 Full-adder logic networks
(b) Mirror circuit

Figure 12.7 AOI full-adder logic
Figure 12.8 Evolution of carry-out circuit

Full-Adder Circuits (2/2)
Figure 12.9 Mirror AOI CMOS full-adder
Figure 12.10 Transmission-gate full-adder circuit
Outline
Bit Adder Circuits

Ripple-Carry Adders
Multipliers
Ripple-Carry Adders
Figure 12.11 An n-bit adder
Figure 12.12 A 4-bit ripple-carry adder
Figure 12.13 Worst-case delay through the

4-bit ripple adder
Figure 12.14 4-ibt adder-subtractor circuit
Outline
Bit Adder Circuits

Ripple-Carry Adders
Multipliers
Carry Look-Ahead Adders (1/3)
Figure 12.15 Basis of the carry

look-ahead algorithm
Figure 12.16 Logic network for

4-bit CLA carry bits
Figure 12.17 Sum calculation

using the CLA network
(a) C1 logic
(b) C2 logic
(a) Complementary
(c) C3 logic
(b) Pseudo nMOS
(d) C4 logic
(c) Dynamic
Figure 12.18 nFET logic arrays for the CLA terms
Figure 12.19 Possible uses of the nFET logic

arrays in Figure 12.18
(a) Series-parallel circuit
Figure 12.22 MODL carry circuit

(b) Mirror equivalent
Figure 12.21 Static mirror

circuit for C2
Figure 12.20 Static CLA

mirror circuit
Manchester Carry Chains
Figure 12.23 Propagate, generate,

and carry-kill values
(a) Static circuit
(b) Dynamic circuit
Figure 12.25 Manchester circuit styles
Figure 12.24 Switching network

for the carry-out equation
Figure 12.26 Dynamic Manchester carry chain

Extension to Wide Adders (1/2)
Figure 12.27 An n-bit adder network
Figure 12.28 4-bit lookahead carry

generator signals
Figure 12.29 Block lookahead generator logic

Extension to Wide Adders (2/2)
Figure 12.31 64-bit CLA architecture
Figure 12.30 Multilevel CLA block

scheme for a 16-bit adder
Outline
Bit Adder Circuits

Ripple-Carry Adders
Multipliers
Carry-Skip Circuits
(a) Carry-skip logic
(b) Generalization
Figure 12.33 A 16-bit adder using carry-skip circuits
Figure 12.34 A 2-level carry-skip adder
Figure 12.32 Carry-skip circuitry

Carry-Select Adders
Figure 12.35 8-bit carry-select adder
Carry-Save Adders
(a) Symbol
(b) 3-to-2 reduction

Figure 12.36 Basic of a carry-save adder
Figure 12.37 Creation of an n-bit carry-save adder

Outline
Bit Adder Circuits

Ripple-Carry Adders
Multipliers
Multipliers (1/2)
Figure 12.38 A 7-to-2 reduction using

carry-save adders
Figure 12.39 Bit-level multiplier
Figure 12.40 Multiplication of two 4-bit words
Figure 12.41 Shift register for multiplication or

division by a factor of 2
Multipliers (2/2)
Figure 12.42 Alternate view of multiplication process
Figure 12.44 Shift-right multiplication sequence
Figure 12.43 Using a product register for multiplication
Figure 12.45 Register-based multiplier network

Array Multipliers
Figure 12.46 An array multiplier
Figure 12.48 Details for a 4 X 4 array multiplier

Figure 12.47 Modularized view of the
multiplication sequence
Other Multipliers
Figure 12.49 Clocked input registers
Figure 12.50 Initial cell placement for the array

Figure 12.51 Summary of Booth
encoded digit operations

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What are the different types of adders discussed?

What are the different types of adders discussed?

How do carry look-ahead adders work?

How do carry look-ahead adders work?

Introduction to VLSI Circuits and Systems

Dept. of Electronic Engineering

Introduction to VLSI Circuits and Systems, NCUT 2007

Bit Adder Circuits

Introduction to VLSI Circuits and Systems, NCUT 2007

Consider two binary digit x and y, and the binary

A half-adder has 2 inputs (x and y) and 2 outputs

Adding n-bit binary words

(a) NAND2 logic

Figure 12.3 Alternate half-adder

Expressions for the network are

Complementary Pass-transistor Logic

Dual-rail complementary pass-transistor logic (CPL)

(a) 2-input array

(b) Sum circuit

(c) Carry circuit

Full-Adder Circuits (1/2)

(a) Gate-level logic

(b) HA-based design

(a) Standard nFET logic

Figure 12.6 Full-adder logic networks

(b) Mirror circuit

Figure 12.8 Evolution of carry-out circuit

Full-Adder Circuits (2/2)

Figure 12.9 Mirror AOI CMOS full-adder

Figure 12.10 Transmission-gate full-adder circuit

Introduction to VLSI Circuits and Systems, NCUT 2007

Bit Adder Circuits

Introduction to VLSI Circuits and Systems, NCUT 2007

Figure 12.11 An n-bit adder

Figure 12.12 A 4-bit ripple-carry adder

Figure 12.13 Worst-case delay through the

Figure 12.14 4-ibt adder-subtractor circuit

Introduction to VLSI Circuits and Systems, NCUT 2007

Bit Adder Circuits

Introduction to VLSI Circuits and Systems, NCUT 2007

Carry Look-Ahead Adders (1/3)

Figure 12.15 Basis of the carry

Figure 12.16 Logic network for

Figure 12.17 Sum calculation

Introduction to VLSI Circuits and Systems, NCUT 2007

Carry Look-Ahead Adders (2/3)

(b) Pseudo nMOS

Figure 12.18 nFET logic arrays for the CLA terms

Figure 12.19 Possible uses of the nFET logic

Carry Look-Ahead Adders (3/3)

(a) Series-parallel circuit

Figure 12.22 MODL carry circuit

Figure 12.21 Static mirror

Figure 12.20 Static CLA

Manchester Carry Chains

Figure 12.23 Propagate, generate,

(b) Dynamic circuit

Figure 12.25 Manchester circuit styles

Figure 12.24 Switching network