Embedded Systems Lecture 15: HW & SW Optimisations: Björn Franke University of Edinburgh

Embedded Systems
Lecture 15: HW & SW Optimisations

Bjrn Franke
University of Edinburgh
Overview
SW Optimisations
Floating-Point to Fixed-Point Conversion
HW Optimisations
Application-Specific Instruction Set Processors (ASIPs)
Application-Specific Hardware Platforms
IP-Based Design
Reconfigurable Systems
Floating & Fixed Point Arithmetic

Floating Point Arithmetic
After each arithmetic operation numbers are normalised
Used where precision and dynamic range are important
Most algorithms are developed in FP
Ease of coding
More Cost (Area, Speed, Power)
Fixed Point Arithmetic

Place of decimal is fixed
Simpler HW, low power, less silicon
Converting FP simulation to Fixed point simulation is time consuming
Multiplication doubles the number of bits: NxN multiplier produces 2N bits
The code is less readable, need to worry about overflow and scaling issues
System-level Design Flow and Fixed-point

Arithmetic
Fixed-point vs Floating-point Hardware

Algorithms are developed in floating point format using tools like Matlab
Floating point processors and HW are expensive
Fixed-point processors and HW are often used in embedded systems
After algorithms are designed and tested then they are converted into fixedpoint implementation
The algorithms are ported on Fixed-point processor or application specific
hardware
Qn.m Format for Fixed-point Arithmetic

Qn.m format is a fixed positional number system for representing fixed-point
numbers
A Qn.m format N-bit binary number assumes n bits to the left and m bits to
the right of the binary point
Qn.m Key Idea
Qn.m Positive Numbers
Conversion to Qn.m
Example
Range Determination for Qn.m Format
Application-Specific Instruction Set Processor ASIP

Designed for a fixed application (domain), e.g. 4G baseband processing
Designed to accelerate heavy and most used functions
Designed to implement the instruction set with minimum hardware cost
Biggest challenges: silicon cost and power consumption
Goals of ASIP design: highest performance over silicon, over power
consumption, as well over the design cost
Involves: ASIP design flow, source code profiling, architecture exploration,
assembly instruction set design, design of assembly language programming
tool chain, firmware design, benchmarking, and micro architecture design
What Makes an ASIP Specific?

What can we specialise in a processor?
Instruction set (IS) specialisation
Exclude instructions which are not used
reduces instruction word length (fewer bits needed for encoding);
keeps controller and data path simple.
Introduce instructions, even exotic ones, which are specific to the
application: combinations of arithmetic instructions (multiply-accumulate),
small algorithms (encoding/decoding, filter), vector operations, string
manipulation or string matching, pixel operations, etc.
reduces code size
reduced memory size, memory bandwidth, power
consumption, execution time

Function unit and data path specialisation
Once an application specific IS is defined, this IS can be implemented
using a more or less specific data path and more or less specific function
units.
Adaptation of word length.
Adaptation of register number.
Adaptation of functional units
Highly specialised functional units can be introduced for string
matching and manipulation, pixel operation, arithmetics, and even
complex units to perform certain sequences of computations (coprocessors).

Memory specialisation
Number and size of memory banks. Number and size of access ports.
They both influence the degree of parallelism in memory access.
Having several smaller memory blocks (instead of one big) increases
parallelism and speed, and reduces power consumption.
Sophisticated memory structures can increase cost and bandwidth
requirement.
Cache configuration: separate instruction/data? associativity, cache size, line
size
Depends very much on the characteristics of the application and, in particular, on
the properties related to locality.
Very large impact on performance and power consumption.

Interconnect specialisation
Interconnect of functional modules and registers.
Interconnect to memory and cache.
How many internal buses?
What kind of protocol?
Additional connections increase the potential of parallelism.
Control specialisation
Centralised control or distributed (globally asynchronous)?
Pipelining?
Out of order execution?
Hardwired or microprogrammed
ASIP Design Flow
Case Study: A SoC for Multimedia Applications
Specialisation of a VLIW ASIP
Specialisation of a VLIW ASIP (contd)

Traditionally the datapath is organised as single register file shared by all
functional units.
Problem: Such a centralised structure does not scale!
We increase the no. of functional units in order to increase parallelism
We have to increase the number of registers in the register file, too
Internal storage and communication between functional units and
registers becomes dominant in terms of area, delay, and power.
High performance VLIW processors are limited not by arithmetic capacity but
by internal bandwidth

A solution: clustering.
Restrict the connectivity between functional units and registers, so that each
functional unit can read/write from/to a subset of registers.
Organise the datapath as clusters of functional units and local register files.
Nothing is for free!!!
Moving data between registers belonging to different clusters takes much time
and power!
You have to drastically minimise the number of such moves by:
Carefully adapting the structure of clusters to the application.
Using very clever compilers.

Instruction set specialisation: nothing special. Maybe DSP instructions.
Function unit and data path specialisation
Determine the number of clusters.
For each cluster determine
the number and type of functional units;
the dimension of the register file.
Memory specialisation is extremely important because we need to stream large
amounts of data to the clusters at high rate; one has to adapt the memory structure
to the access characteristics of the application.
determine the number and size of memory banks

Interconnect specialisation
Determine the interconnect structure between clusters and from clusters to
memory:
one or several buses,
crossbar interconnection
etc.
Control specialisation
Thats more or less done, as we have decided for a VLIW processor.
Maybe Zero-Overhead Loops...
Tool Support for Processor Specialisation

Design Tools for ASIP Design Flow
In order to be able to generate a specialised architecture you need:
Architecture Design Tools (e.g. Synopsys Processor Designer)
Retargetable compiler
Configurable simulator
Application Specific Platforms

Not only processors but also hardware platforms can be specialised for
classes of applications.
The platform will define a certain communication infrastructure (buses and
protocols), certain processor cores, peripherals, accelerators commonly used
in the particular application area, and basic memory structure.
Think of TI OMAP, Exynos, ... for smartphones
IP-Based Design (Design Reuse)

The key concept in order to increase designers productivity is reuse.
In order to manage the complexity of current large designs we do not start
from scratch but reuse as much as possible from previous designs, or use
commercially available pre-designed IP blocks.
IP: intellectual property
e.g. ARM cores, Imagination Technologies GPUs, ...
Some people call this IP-based design, core-based design, reuse techniques,
etc.:
Core-based design is the process of composing a new system design by
reusing existing components.
IP-Based Design (contd)

What are the blocks (cores) we reuse?
interfaces, encoders/decoders, filters, memories, timers, microcontrollercores, DSP-cores, RISC-cores, GP processor-cores.
Possible(!) definition
A core is a design block which is larger than a typical RTL component.
Of course: We also reuse software components!
IP-Based Design (contd)
Programmable Hardware Circuits:
They implement arbitrary combinational or sequential circuits and can be
configured by loading a local memory that determines the interconnection
among logic blocks.
Reconfiguration can be applied an unlimited number of times.
Main applications:
Software acceleration
Prototyping
Summary
SW Optimisations
Floating-Point to Fixed-Point Conversion
HW Optimisations
Application-Specific Instruction Set Processors (ASIPs)
Application-Specific Hardware Platforms
IP-Based Design
Preview
Dynamic Frequency Scaling
Dynamic Voltage Scaling

Embedded Systems Lecture 15: HW & SW Optimisations: Björn Franke University of Edinburgh

Uploaded by

Copyright:

Available Formats

Embedded Systems Lecture 15: HW & SW Optimisations: Björn Franke University of Edinburgh

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Embedded Systems Lecture 15: HW & SW Optimisations: Björn Franke University of Edinburgh

Uploaded by

Copyright:

Available Formats

Embedded Systems

Lecture 15: HW & SW Optimisations

Floating & Fixed Point Arithmetic

Fixed Point Arithmetic

System-level Design Flow and Fixed-point

Fixed-point vs Floating-point Hardware

Qn.m Format for Fixed-point Arithmetic

Qn.m Key Idea

Qn.m Positive Numbers

Range Determination for Qn.m Format

Application-Specific Instruction Set Processor ASIP

What Makes an ASIP Specific?

reduced memory size, memory bandwidth, power

consumption, execution time

What Makes an ASIP Specific?

What Makes an ASIP Specific?

What Makes an ASIP Specific?

ASIP Design Flow

Case Study: A SoC for Multimedia Applications

Specialisation of a VLIW ASIP

Specialisation of a VLIW ASIP (contd)

Specialisation of a VLIW ASIP (contd)

Specialisation of a VLIW ASIP (contd)

Specialisation of a VLIW ASIP (contd)

Specialisation of a VLIW ASIP (contd)

Tool Support for Processor Specialisation

Application Specific Platforms

IP-Based Design (Design Reuse)

IP-Based Design (contd)

IP-Based Design (contd)

You might also like