Signal Description of 8086

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and
packaged
in a 40 pin CERDIP or plastic package.
The 8086 operates in single processor or multiprocessor configuration to achieve high
performance. The pins serve a particular function in minimum mode (single processor
mode) and other function in maximum mode configuration (multiprocessor mode ).
The 8086 signals can be categorized in three groups. The first are the signal having
common functions in minimum as well as maximum mode.

The second are the signals which have special functions for minimum mode and third
are the signals having special functions for maximum mode.
The following signal descriptions are common for both modes.
AD15-AD0 : These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T1 state, while the data is available on the data
bus
during T2, T3, Tw and T4.
These lines are active high and float to a tristate during interrupt acknowledge and
local
bus hold acknowledge cycles
A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status
lines.
During T1 these are the most significant address lines for memory operations.
During I/O operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T2,T3,Tw and T4.
The status of the interrupt enable flag bit is updated at the beginning of each clock
cycle.
The S4 and S3 combinedly indicate which segment register is presently being used for
memory accesses as in below fig.
These lines float to tri-state off during the local bus hold acknowledge. The status line
S6 is always low .
The address bit are separated from the status bit using latches controlled by the ALE
signal.

BHE /S7

: The bus high enable is used to indicate the transfer of data over the higherorder (
D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15- D8 and is used to derive
chip selects of odd address memory bank or peripherals. BHE is
low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be
transferred on higher byte of data bus. The status information is available during T2, T3
and T4. The signal is active low and tristated during hold. It is low during T1 for the
first
pulse of the interrupt acknowledge cycle.

RD Read : This signal on low indicates the peripheral that the processor is
performing s memory or I/O read operation. RD is active low and shows the state for
T2,
T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge.
READY : This is the acknowledgement from the slow device or memory that they
have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the 8086. the signal is active high.
INTR-Interrupt Request : This is a triggered input. This is sampled during the last
clock cycles of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resulting the interrupt enable flag. This signal is
active
high and internally synchronized.
TEST : This input is examined by a WAIT instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
CLK- Clock Input : The clock input provides the basic timing for processor operation
and bus control activity. Its an asymmetric square wave with 33% duty cycle
MN/ MX : The logic level at this pin decides whether the processor is to operate in
either
minimum or maximum mode.
The following pin functions are for the minimum mode operation of 8086.
M/ IO Memory/IO : This is a status line logically equivalent to S2 in maximum
mode. When it is low, it indicates the CPU is having an I/O operation, and when it is
high, it indicates that the CPU is having a memory operation. This line

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comes active high in the previous T4 and remains active till final T4 of the current cycle. It is
tri stated during local bus hold acknowledge .

Interrupt Acknowledge : This signal is used as a read strobe for interrupt

acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.
INTA

rishna Kumar

ALE Address Latch Enable :This output signal indicates the availability of the
valid address on the address/data lines, and is connected to latch enable input of latches.
This signal is active high and is never tri stated.
DT/ R Data Transmit/Receive: This output is used to decide the direction of data
flow through the transceivers (bidirectional buffers). When the processor sends out data,
this signal is high and when the processor is receiving data, this signal is low.
DEN Data Enable :This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transceivers ( bi directional buffers ) to
separate the data from the multiplexed address/data signal. It is active from the middle
of T2 until the middle of T4. This is tri stated during hold acknowledge cycle.
HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the
processor that another master is requesting the bus access.
The processor, after receiving the HOLD request, issues the hold acknowledge signal
on
HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.
At the same time, the processor floats the local bus and control lines. When the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an
asynchronous input, and is should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle, it will
release the local bus during T4 provided :
1.The request occurs on or before T2 state of the current cycle.
2.The current cycle is not operating over the lower byte of a word.
3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed
The following pin function are applicable for maximum mode operation of 8086.
S2, S1, S0 Status Lines : These are the status lines which reflect the type of
operation,
being carried out by the processor. These become activity during T4 of the previous cycle

and active during T1 and T2 of the current bus cycles.

Prof. Krishna
Kumar

LOCK

: This output pin indicates that other system bus master will be prevented from

gaining the system bus, while the LOCK signal is low

The LOCK signal is activated by the LOCK prefix instruction and remains active
until the completion of the next instruction. When the CPU is executing a critical
instruction which requires the system bus, the LOCK prefix instruction ensures that
other processors connected in the system will not gain the control of the bus.
The 8086, while executing the prefixed instruction, asserts the bus lock signal output,
which may be connected to an external bus controller.
QS1, QS0 Queue Status: These lines give information about the status of the codeprefetch queue. These are active during the CLK cycle after while the queue operation is
performed.
This modification in a simple fetch and execute architecture of a conventional
microprocessor offers an added advantage of pipelined processing of the instructions.
The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6bytes) instruction can be prefetched from the memory and stored in the prefetch. This
results in a faster execution of the instructions.
In 8085 an instruction is fetched, decoded and executed and only after the execution of
this instruction, the next one is fetched.
By prefetching the instruction, there is a considerable speeding up in instruction
execution in 8086. This is known as instruction pipelining.
At the starting the CS:IP is loaded with the required address from which the execution
is to be started. Initially, the queue will be empty an the microprocessor starts a fetch
operation to bring one byte (the first byte) of instruction code, if the CS:IP address is
odd
or two bytes at a time, if the CS:IP address is even.
The first byte is a complete opcode in case of some instruction (one byte opcode
instruction) and is a part of opcode, in case of some instructions ( two byte opcode
instructions), the remaining part of code lie in second byte.
The second byte is then decoded in continuation with the first byte to decide the
instruction length and the number of subsequent bytes to be treated as instruction data.
The queue is updated after every byte is read from the queue but the fetch cycle is
initiated by BIU only if at least two bytes of the queue are empty and the EU may be
concurrently executing the fetched instructions
RQ / GT0 , RQ / GT1 Request/Grant : These pins are used by the other local bus master in
maximum mode, to force the processor to release the local bus at the end of the processor current bus
cycle.

Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
RQ/GT pins have internal pull-up resistors and may be left unconnected.

Request/Grant sequence is as follows:

1.A pulse of one clock wide from another bus master requests the bus access to 8086.
2.During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it
will enter the hold acknowledge state at next cycle. The CPU bus interface unit is
likely to be disconnected from the local bus of the system.
3.A one clock wide pulse from the another master indicates to the 8086 that the hold
request is about to end and the 8086 may regain control of the local bus at the next clock
cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses.
There must be at least one dead clock cycle after each bus exchange.
The request and grant pulses are active low.
For the bus request those are received while 8086 is performing memory or I/O cycle,
the granting of the bus is governed by the rules as in case of HOLD and HLDA in
minimum mode.
General Bus Operation:
The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package.
The bus can be de multiplexed using a few latches and transceivers, when ever
required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are
refered to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is
present on the bus only for one cycle.
The negative edge of this ALE pulse is used to separate the address and the data or
status
information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the
type of operation.
Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4

Krishna

Prof. Krishna
Kumar

Minimum Mode 8086 System

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum
mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
The remaining components in the system are latches, transreceivers, clock generator,

memory and I/O devices. Some type of chip selection logic may be required for selecting memory
or I/O devices, depending upon the address map of the system.
Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are
used for separating the valid address from the multiplexed address/data signals and
arecontrolled by the ALE signal generated by 8086.
Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.
They are controlled by two signals namely, DEN and DT/R
The DEN signal indicates the direction of data, i.e. from or to the processor. The system
contains memory for the monitor and users program storage.
Usually, EPROM are used for monitor storage, while RAM for users program storage.
A system may contain I/O devices.
The working of the minimum mode configuration system can be better described in
terms of the timing diagrams rather than qualitatively describing the operations.
The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle.
The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and
also M / IO signal. During the negative going edge of this signal, the valid address is
latched on the local bus.
The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO
signal indicates a memory or I/O operation.
At T2, the address is removed from the local bus and is sent to the output. The bus is
then tristated. The read (RD) control signal is also activated in T2.
The read (RD) signal causes the address device to enable its data bus drivers. After RD
goes low, the valid data is available on the data bus.
The addressed device will drive the READY line high. When the processor returns the
read signal to high level, the addressed device will again tristate its bus drivers.
A write cycle also begins with the assertion of ALE and the emission of the address.
The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after
sending the address in T1, the processor sends the data to be written to the addressed
location.
The data remains on the bus until middle of T4 state. The WR becomes active at the
beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O
word to be read or write.
The M/IO, RD and WR signals indicate the type of data transfer as specified in table
below.

Prof. Krishna
Hold Response sequence: The HOLD pin is checked at leading edge of each clock
Kumar
pulse. If it is received active by the processor before T4 of the previous cycle or during
T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for
succeeding bus cycles, the bus will be given to another requesting master.

The control of the bus is not regained by the processor until the requesting master does
not drop the HOLD pin low. When the request is dropped by the requesting master, the
HLDA is dropped by the processor at the trailing edge of the next clock.

Maximum Mode 8086 System

In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus

controller derives the control signal using this status information .

In the maximum mode, there may be more than one microprocessor in the system
configuration.
The components in the system are same as in the minimum mode system.

The basic function of the bus controller chip IC8288, is to derive control signals like
RD and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the
information by the processor on the status lines.
The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are
driven by CPU.
It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.
AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance
of the MCE/PDEN output depends upon the status of the IOB pin.
If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it
acts as peripheral data enable used in the multiple bus configurations.
INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an
interrupting device
IORC, IOWC are I/O read command and I/O write command signals respectively
.These signals enable an IO interface to read or write the data from or to the address
port.
The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
All these command signals instructs the memory to accept or send data from or to the
bus.
For both of these write command signals, the advanced signals namely AIOWC and
AMWTC are available.
Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals.

R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse
as on the ALE and apply a required signal to its DT / R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
If reader input is not activated before T3, wait state will be inserted between T3 and T4.
Timings for RQ/ GT Signals :
The request/grant response sequence contains a series of three pulses. The request/grant
pins are checked at each rising pulse of clock input.
When a request is detected and if the condition for HOLD request are satisfied, the
processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or
T1 (next) state.
When the requesting master receives this pulse, it accepts the control of the bus, it sends
a release pulse to the processor using RQ/GT pin.

Minimum Mode Interface

When the Minimum mode operation is selected, the 8086 provides all control signals
needed to implement the memory and I/O interface.
The minimum mode signal can be divided into the following basic groups : address/data
bus, status, control, interrupt and DMA.
Address/Data Bus : these lines serve two functions. As an address bus is 20 bits long
and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A
20bit address gives the 8086 a 1Mbyte memory address space. More over it has an
independent I/O address space which is 64K bytes in length.
The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0
through A15 respectively. By multiplexed we mean that the bus work as an address bus
during first machine cycle and as a data bus during next machine cycles. D15 is the MSB

and D0 LSB.
When acting as a data bus, they carry read/write data for memory, input/output data for
I/O devices, and interrupt type codes from an interrupt controller.

Prof. Krishna

tatus signal:
Kumar
The four most significant address lines A19 through A16 are also multiplexed but in this
case with status signals S6 through S3. These status bits are output on the bus at the
same
time that data are transferred over the other bus lines.
Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086
internal
segment registers are used to generate the physical address that was output on the
address
bus during the current bus cycle.
Code S4S3 = 00 identifies a register known as extra segment register as the source of
the segment address.
Status line S5 reflects the status of another internal characteristic of the 8086. It is the
logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level

Prof. Krishna
Kumar

Control Signals :
The control signals are provided to support the 8086 memory I/O interfaces. They
control functions such as when the bus is to carry a valid address in which direction data

are to be transferred over the bus, when valid write data are on the bus and when to put
read data on the system bus.
ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on
the bus. This address must be latched in external circuitry on the 1-to-0 edge of the
pulse
Another control signal that is produced during the bus cycle is BHE bank high enable.
Logic 0 on this used as a memory enable signal for the most significant byte half of the
data bus D8 through D1. These lines also serves a second function, which is as the S
status line.
Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress
and in which direction data are to be transferred over the bus.
The logic level of M/IO tells external circuitry whether a memory or I/O transfer is
taking place over the bus. Logic 1 at this output signals a memory operation and logic 0
an I/O operation.
The direction of data transfer over the bus is signaled by the logic level output at DT/R.
When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the
transmit mode. Therefore, data are either written into memory or output to an I/O
device.
On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This
corresponds to reading data from memory or input of data from an input port.
The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is
in progress. The 8086 switches WR to logic 0 to signal external device that valid write
or output data are on the bus
7

On the other hand, RD indicates that the 8086 is performing a read of data of the bus.
During read operations, one other control signal is also supplied. This is DEN ( data
enable) and it signals external devices when they should put data on the bus.
There is one other control signal that is involved with the memory and I/O interface.
This is the READY signal.
READY signal is used to insert wait states into the bus cycle such that it is extended by

a number of clock periods. This signal is provided by an external clock generator device
and can be supplied by the memory or I/O sub-system to signal the 8086 when they are
ready to permit the data transfer to be completed
Maximum Mode Interface
When the 8086 is set for the maximum-mode configuration, it provides signals for
implementing a multiprocessor / coprocessor system environment.
By multiprocessor environment we mean that one microprocessor exists in the system
and that each processor is executing its own program.
Usually in this type of system environment, there are some system resources that are
common to all processors.
They are called as global resources. There are also other resources that are assigned to
specific processors. These are known as local or private resources.
Coprocessor also means that there is a second processor in the system. In this two
processor does not access the bus at the same time.

Prof. Krishna
Kumar

One passes the control of the system bus to the other and then may suspend its
operation.
In the maximum-mode 8086 system, facilities are provided for implementing allocation
of global resources and passing bus control to other microprocessor or coprocessor

Prof. Krishna
Kumar

8288 Bus Controller Bus Command and Control Signals:

8086 does not directly provide all the signals that are required to control the memory,
I/O and interrupt interfaces.
Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced
by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of
each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow.
S2S1S0 are input to the external bus controller device, the bus controller generates the
appropriately timed command and control signals.

The 8288 produces one or two of these eight command signals for each bus cycles. For
instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O
read
cycle is to be performed.
In the code 111 is output by the 8086, it is signaling that no bus activity is to take place.
The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals
provide the same functions as those described for the minimum system mode. This set
of bus commands and control signals is compatible with the Multibus and industry
standard for interfacing microprocessor systems
Queue Status Signals : Two new signals that are produced by the 8086 in the
maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2bit queue status code, QS1QS0.

Local Bus Control Signal Request / Grant Signals: In a maximum mode

configuration, the minimum mode HOLD, HLDA interface is also changed. These two
are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a
prioritized bus access mechanism for accessing the local bus.

Prof. Krishna Kumar

We have four common types of memory:

Read only memory ( ROM )
Flash memory ( EPROM )
Static Random access memory ( SRAM )
Dynamic Random access memory ( DRAM ).
Pin connections common to all memory devices are: The address input, data
output or input/outputs, selection input and control input used to select a read or
write operation.

Address connections: All memory devices have address inputs that select a
memory location within the memory device. Address inputs are labeled from A0
to An.
Data connections: All memory devices have a set of data outputs or
input/outputs. Today many of them have bi-directional common I/O pins.

Selection connections: Each memory device has an input, that selects orenables
the memory device. This kind of input is most often called a chip select ( CS ),chip
enable ( CE ) or simply select ( S ) input.
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Prof. Krishna Kumar

The OE connection enables and disables a set of three-state

buffer located within
the memory device and must be active to read data.
A RAM memory device has either one or two control inputs. If
there is one
control input it is often called R/ W .
This pin selects a read operation or a write operation only if the
device is selected
by the selection input ( CS ).
If the RAM has two control inputs, they are usually labeled WE or
W and OE or G .
( WE ) write enable must be active to perform a memory write
operation and OE
must be active to perform a memory read operation.
When these two controls WE and OE are present, they must
never be active at
the same time.
The ROM read only memory permanently stores programs and
data and data was
always present, even when power is disconnected.
It is also called as nonvolatile memory.
EPROM ( erasable programmable read only memory ) is also
erasable if exposed
to high intensity ultraviolet light for about 20 minutes or less,
depending upon the
type of EPROM.
We have PROM (programmable read only memory )
RMM ( read mostly memory ) is also called the flash memory.
The flash memory is also called as an EEPROM
(electrically erasable
programmable ROM), EAROM ( electrically alterable ROM ),
or a NOVROM
( nonvolatile ROM ).
These memory devices are electrically erasable in the system,
but require more
time to erase than a normal RAM.
EPROM contains the series of 27XXX contains the following
part numbers :
2704( 512 * 8 ), 2708(1K * 8 ), 2716( 2K * 8 ), 2732( 4K * 8 ),
2764( 8K * 8 ),
27128( 16K * 8) etc..
Each of these parts contains address pins, eight data
connections, one or more
chip selection inputs ( CE ) and an output enable pin ( OE ).
This device contains 11 address inputs and 8 data outputs.
If both the pin connection CE and OE are at logic 0, data will
appear on the
output connection . If both the pins are not at logic 0, the data
output connections
remains at their high impedance or off state.
To read data from the EPROM Vpp pin must be placed at a
logic 1.

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upper 8-bit bank is called as odd address memory bank and the
lower 8-bit bank is called as even address memory bank.
2. Connect available memory address lines of memory chip with
those of the
microprocessor and also connect the memory RD and WR
inputs to the
corresponding processor control signals. Connect the 16-bit
data bus of the
memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and A0
are used for
decoding the required chip select signals for the odd and even
memory banks. The CS of memory is derived from the o/p of
the decoding circuit.
As a good and efficient interfacing practice, the address map of
the system should be continuous as far as possible, i.e. there should
not be no windows in the mapand no fold back space should be
allowed.
A memory location should have a single address corresponding to
it, i.e. absolute
decoding should be preferred and minimum hardware should be
used for decoding

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Dynamic RAM
Whenever a large capacity memory is required in a microcomputer
system, the
memory subsystem is generally designed using dynamic RAM
because there are
various advantages of dynamic RAM.

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Prof. Krishna
aspects.
1. The memory address is not provided by the CPU address bus, Kumar
rather it is
generated by a refresh mechanism counter called as refresh
counter.
2. Unlike memory read cycle, more than one memory chip may be
enabled at a time
so as to reduce the number of total memory refresh cycles.
3. The data enable control of the selected memory chip is
deactivated, and data is
not allowed to appear on the system data bus during refresh, as
more than one
memory units are refreshed simultaneously. This is to avoid the
data from the
different chips to appear on the bus simultaneously.
4. Memory read is either a processor initiated or an external bus
master initiated and carried out by the refresh mechanism.

Dynamic RAM is available in units of several kilobits to megabits

of memory.
This memory is arranged internally in a two dimensional matrix
array so that it
will have n rows and m columns. The row address n and column
address m are

important for the refreshing operation.

For example, a typical 4K bit dynamic RAM chip has an
internally arranged bit
array of dimension 64 * 64 , i.e. 64 rows and 64 columns. The
row address and
column address will require 6 bits each. These 6 bits for each
row address and
column address will be generated by the refresh counter, during the refresh
cycles.
A complete row of 64 cells is refreshed at a time to minimizes the refreshing
time. Thus the refresh counter needs to generate only row addresses. The row
address are multiplexed, over lower order address lines.
The refresh signals act to control the multiplexer, i.e. when refresh cycle is in
process the refresh counter puts the row address over the address bus for
refreshing. Otherwise, the address bus of the processor is connected to the
address

the

bus of DRAM, during normal processor initiated activities.

A timer, called refresh timer, derives a pulse for refreshing action after each
refresh interval.
Refresh interval can be qualitatively defined as the time for which a dynamic
RAM cell can hold data charge level practically constant, i.e. no data loss takes
place.
Suppose the typical dynamic RAM chip has 64 rows, then each row should be
refreshed after each refresh interval or in other words, all the 64 rows are to
refreshed in a single refresh interval.
This refresh interval depends upon the manufacturing technology of the dynamic
RAM cell. It may range anywhere from 1ms to 3ms.
Let us consider 2ms as a typical refresh time interval. Hence, the frequency of

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the

The following block diagram explains the refreshing logic and 8086 interfacing
with dynamic RAM.
Each chip is of 16K * 1-bit dynamic RAM cell array. The system contains two
16K byte dynamic RAM units. All the address and data lines are assumed to be
available from an 8086 microprocessor system.
The OE pin controls output data buffer of the memory chips. The CE pins are
active high chip selects of memory chips. The refresh cycle starts, if the refresh
output of the refresh timer goes high, OE and CE also tend to go high.
The high CE enables the memory chip for refreshing, while high OE prevents
data from appearing on the data bus, as discussed in memory refresh cycle. The
16K * 1-bit dynamic RAM has an internal array of 128*128 cells, requiring 7
bits
for row address. The lower order seven lines A -A are multiplexed with the
refresh counter output A10-A16.
0

Microprocessors and Microcontrollers

Prof. Krishna
Kumar

If the RAM has two control inputs, they are usually labeled WE or W

and OE
or G .
( WE ) write enable must be active to perform a memory write
operation and OE
must be active to perform a memory read operation.
When these two controls WE and OE are present, they must never be
active at
the same time.
The ROM read only memory permanently stores programs and data
and data was
always present, even when power is disconnected.
It is also called as nonvolatile memory.
EPROM ( erasable programmable read only memory ) is also erasable
if exposed
to high intensity ultraviolet light for about 20 minutes or less,
depending upon the
type of EPROM.
We have PROM (programmable read only memory )
RMM ( read mostly memory ) is also called the flash memory.
The flash memory is also called as an EEPROM
(electrically
erasable
programmable ROM), EAROM ( electrically alterable ROM ), or a
NOVROM
( nonvolatile ROM ).
These memory devices are electrically erasable in the system, but
require more
time to erase than a normal RAM.
EPROM contains the series of 27XXX contains the following part
numbers :
2704( 512 * 8 ), 2708(1K * 8 ), 2716( 2K * 8 ), 2732( 4K * 8 ),
2764( 8K * 8 ),
27128( 16K * 8) etc..
Each of these parts contains address pins, eight data connections, one
or more
chip selection inputs ( CE ) and an output enable pin ( OE ).
This device contains 11 address inputs and 8 data outputs.
If both the pin connection CE and OE are at logic 0, data will appear
on the

output connection . If both the pins are not at logic 0, the data output
connections
remains at their high impedance or off state.
To read data from the EPROM Vpp pin must be placed at a logic 1.