S - Digital Electronic Circuits-V7
S - Digital Electronic Circuits-V7
S - Digital Electronic Circuits-V7
Course Outline
Introduction
Integrated Circuits (IC): arbitrary number of
interconnected gates in a silicon
semiconductor crystal (chip)
Contains electronic components for constructing
digital gates
Mounted in a ceramic or plastic container that
exposes a number of pins (tens to thousands)
Levels of Integration
Small scale Integration (SSI): typically fewer than 10
independent gates early 60s
Medium Scale Integration (MSI): 10 to 1000 of gates
(decoders, adders, multiplexers) late 60s
Large Scale Integration (LSI): thousands of gates (1st and 2nd
generation processors, memory chips, PLD) mid 70s
Very Large Scale Integration (VLSI/ULSI): hundreds of
thousands of gates to several billions (complex
microcomputers chips) 80s till present
System-on-a-Chip (SoC): all components needed by a
computer is included on a single chip.
Lower manufacturing cost and reduced power budget. Why?
Fan-Out
Power Dissipation
Propagation Delay
Noise Margin
760
760
Q3
Q3
AA
BB
CC
QQ4 4
QQ1 1
3.5k
3.5k
QQ2 2
Output
Output
QQ5 5
370
370
350
350
QQ6 6
Power Dissipation
Propagation Delay
10 mW
1.5 nseconds
1 mW
4 nseconds
ECL - Simplified
Emitter Follower Output
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
Q1
Q2
Q5
VBB=-1.3V
50 K
VEE=-5.2 V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
Q1
Q2
Q5
779
50 K
50 K
VEE=-5.2 V
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
Q1
Q2
Q5
779
50 K
50 K
A = High (-0.8) B
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VEE=-5.2 V
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
ON
Q1
Q2
Q5
-1.6 V
779
50 K
50 K
A = High (-0.8) B
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VEE=-5.2 V
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
Q1
Q2
Q5
-1.6 V
779
50 K
50 K
A = High (-0.8) B
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VEE=-5.2 V
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
Q1
Q2
Q5
-1.6 V
779
50 K
50 K
A = High (-0.8) B
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VEE=-5.2 V
VBB=-1.3V
-0.8 V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
(-1.6 - -5.2)*220/779
1.0 V
220
OR
-0.8 V
NOR
-1.8 V
Q7
Q1
Q2
Q5
-1.6 V
779
50 K
50 K
A = High (-0.8) B
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VEE=-5.2 V
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
Q1
Q2
Q5
779
50 K
50 K
VEE=-5.2 V
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
NOR
Q1
Q2
Q5
779
50 K
= Low (-1.8)
50 K
VEE=-5.2 V
= Low (-1.8)
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
Q8
OR
220
Q7
cut-off
Q1
NOR
cut-off
Q2
Q5
-2.1 V
779
50 K
= Low (-1.8)
50 K
VEE=-5.2 V
= Low (-1.8)
VBB=-1.3V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
1.0 V
Q8
OR
220
Q7
cut-off
Q1
NOR
cut-off
Q2
Q5
-2.1 V
779
50 K
= Low (-1.8)
50 K
VEE=-5.2 V
= Low (-1.8)
VBB=-1.3V
-1.8 V
ECL - Simplified
-0.8 V High
-1.8 V Low
GND
GND
245
1.0 V
Q8
OR
220
-1.8 V
Q7
cut-off
Q1
NOR
cut-off
Q2
Q5
-2.1 V
779
50 K
= Low (-1.8)
50 K
VEE=-5.2 V
= Low (-1.8)
VBB=-1.3V
-0.8 V
MOS Transistors
p-channel
n-type substrate (lightly doped)
Two heavily doped regions with p-type impurities (source and drain)
The region between the source and drain is called the channel
The gate is the metal plate separated from the substrate by an insulated
dielectric of silicon dioxide
A negative voltage at the gate => induced electric field at the channel =>
attracts p-type carriers (holes) => conductivity increases => current flows
from source to drain
Dr. Samer Arandi - An-Najah National University
MOS Transistors
Two modes of operation (depends on the
state of the channel at zero voltage):
Depletion
channel is initially doped with p-type impurities,
i.e. a conducting channel exists at 0 V
Enhancement
region beneath the gate is initially uncharged
a voltage must be applied to the gate to induced a
channel i.e. current is enhanced by gate voltage
MOS Transistors
The majority carriers enter the device from the source
terminal to the drain when the voltage applied to the gate
exceeds a threshold VT
p-channel
The source is connected to the substrate and a negative voltage
is applied to the drain
When the gate voltage is sufficiently negative below VT p-type
carriers flow from S to D (positive current flow)
n-channel
The source is connected to the substrate and a positive voltage
is applied to the drain
When the gate voltage is sufficiently positive above VT n-type
carriers flow from S to D (equivalent to positive current flow
from D to S)
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MOS Transistors
Enhancement Mode
RQ2<<RQ1
Q2
Q3
Complementary MOS
Takes advantage of the ability to fabricate
both n-type and p-type on the same substrate
Basic circuit is the inverter:
The n-MOS conducts when
gate-to-source is pos+
The p-MOS conducts when
gate-to-source is neg Both are turned off when
gate-to-source is zero
s
d
d
s
CMOS Models/Symbols
Determine the
electrical
Characteristics of
the transistor
VFB
F
k * t ni
ln
F =
q
NA
Thermal voltage
= 26mV
ni
NA
K
QB0 =
q * NA * Xd
Xd =
VSB
Cox
ox
tox
: gate-oxide capacitance
: permittivity of oxide
: oxide thickness
q
Xd
Si
2 * Si* | 2F |
q * NA
Cox =
ox
tox
Signs
VFB is negative in nMOS, positive in pMOS
F is negative in nMOS, positive in pMOS
QB0 and QB are negative in nNMOS, positive in
pMOS
VSB is positive in nMOS, negative in pMOS
Current-Voltage Characteristics
MOS has three modes of operation:
Cut-off
Linear
Saturation
Linear Mode
At VDS = 0, the inverted channel is in equilibrium
and IDS = 0
If a small VDS > 0 is applied, IDS will flow from S
to D, such that IDS is proportional to VDS
The transistor
(the channel) acts
as a voltage
controlled resistor
Linear Mode
K
2
IDS [2(VGS VT )VDS VDS ]
2
W
K K'
L
K ' n * Cox
nox
tox
n : carrier mobility
Saturation Mode
As the drain voltage is increased the inversion
layer charge and the channel depth at the drain
decreases
At VDS = VGS-VT0 (called VDSAT) the channel
inversion charge at the drain becomes zero
(pinch-off point)
As VDS > VDSAT the inversion layer near the drain
vanishes -> channel length decreases
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Saturation Mode
2
K
IDS (VGS VT )
2
2
K
IDS (VGS VT )(1 *VDS )
2
(account for channel modulation)
:channel length
modulation
coefficient
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Pinch-off point
Saturation Mode
Practical Considerations
The I-V characteristics discussed so far neglect
many effects that are important in modern
fabrication processes:
Velocity Saturation
We assumed that carrier drift velocity and hence
current increase linearly with the electric field
between source and drain.
This is only true for weak electric fields, at high
electric fields and short channel lengths carrier drift
velocity saturates (saturation occurs when carriers
reach saturation velocity)
Thus, saturation current is linearly dependent on
voltage rather than quadratically dependent
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Sub-threshold conduction
We assumed that no current flows from source to drain
when Vgs < Vt. In reality this is not true and current drops
off exponentially. This current is termed as leakage current
Tunneling
According to quantum mechanics, there is a finite
probability that carriers will tunnel through the gate oxide.
This results in gate leakage current flowing into the gate.
Probability of tunneling drops off exponentially with oxide
thickness, and so was negligible until recently.
Temperature
Carrier mobility decreases with temperature
The magnitude of the threshold voltage decreases nearly
linearly with temperature
Junction leakage increases with temperature because Is is
strongly temperature dependent.
Net effect: ON current decreases, OFF current increases,
worse performance at high temperature
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MOS Capacitance
The switching speed of MOS circuits is limited
by the time required to charge/discharge the
capacitances at the internal nodes
The capacitances must be calculated from
device dimensions and dielectric constants
The values are usually specified in femtoFarads per meter of width (fF/m)
CG vs. Cg
Non-linear
voltage-dependant
linear
voltage-independant
Thin-Oxide Capacitance
The most important capacitance in MOS
The two plates of the capacitor are the gate
and the channel
The dielectric is the oxide between the two
plates
CG W * Cg
Cg Cox *L
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ox
tox
*L
Thin-Oxide Capacitance
The gate capacitance is decomposed into
three capacitances:
Cgs: gate-to-source capacitance
Cgd: gate-to-drain capacitance
Cgb: gate-to-bulk capacitance
Thin-Oxide Capacitance
Capacitance
Cut-off
Linear
Saturation
Cgb
Cgd
Cgs
Cg *
Cg
Cg
2/3 Cg
Junction Capacitance
The S and D regions and the substrate forms
pn junctions that give rise to two additional
capacitances - Csb and Cdb
In addition, a junction capacitance is formed
between the inverted channel and the
substrate Cjc
This capacitance depends on the terminal
voltage
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Junction Capacitance
Cj 0 * A
CJ
VJ m
(1 )
B
(si * q) NA * ND
si * q * NA
Cj 0
*
(2 *B) NA ND
2 *B
k * T NA * ND
B
ln
q
ni 2
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Junction Capacitance
Since the terminal voltages change during
dynamic operation we need to calculate the
capacitance under such transient conditions
We approximate this capacitance by finding the
large-signal average junction capacitance*:
CJ Keq * Cj 0 * A
2 * B
Keq
* ( B V 2 B V 1)
V 2 V1
Keq: dimensionless coefficient
*calculated for a transition between two known voltages, V1 and V2
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Overlap Capacitance
Voltage-independent capacitance that exists on both sides of the gate
Composed of two components:
diffusion capacitance
between the gate and
the diffusion extensions
of the source
and drain - Cov
fringing capacitance
between sidewall of
the poly-silicon
and surface of drain
and source - Cf
Col = Cov + Cf
Overlap Capacitance
Col Cov Cf
2ox
Tpoly
Cf
ln(1
)
tox
Cov Cox * LD
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MOS Inverter
Static Characteristics
DC Voltage
Transfer
Characteristics
Vout
Gain =
Vin
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Practical VTC
Practical VTC
The input ranges that define 0 and 1 are smaller than the ideal case
- 0 to VIL
- VIH to VDD
The two output ranges are larger than the ideal case
- VOL to VOUL
- VOUH to VOH
Noise
When the input range is larger than the output
range, the gate retains the noise rejection property
i.e. output fluctuation are small even with large
input fluctuation
This attenuates the noise when multiple gates are
connected successively
Noise Margins
The noise margin specifies the range over
which the circuit will function properly.
Noise margin metrics:
single-source noise margin (SSNM): assumes a
single noise source affecting one logic node (not
realistic)
multiple-source noise margin (MSNM): assumes
multiple noise sources potentially affecting all
nodes (more realistic)
Noiseless System
System with
single-stage
noise of
magnitude Vn
System with multi-stage
noise
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Inverter
Vout
Vin
Buffer
Vout = VDS
VSB = 0
VT = VT0
Since IG is
negligible
I R = ID
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VTC
Calculating VOH
To calculate VOH we set
the input voltage
below VT
Therefore, no current
flows
And so:
VOH = VDD
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Calculating VOL
When a logic 1 is applied at the gate input
(represented by VOH of a previous gate) the
transistor is driven into the linear region.
This implies:
IR = IDS (linear)
VDD VOL K
2
[2(VOH VT )VOL VOL ]
RL
2
Calculating VOL
VDD
VOL
1 k * RL(VDD VT )
To make VOL small:
increase k (i.e. W/L) [increase area, faster falltime]
increase RL[increase area, slower rise-time]
RL
) *VDD
Calculating VIL
At Vin = VIL the output voltage is near VDD and
the transistor is operating in the saturation
region.
This implies:
IR = IDS (saturation)
2
VDD VOut k
(VIL VT )
RL
2
Calculating VIL
1
VIL VT
k * RL
To increase VIL:
Decrease k and RL. However, this increases VOL
which is not desirable
Both VIL and VOL shift in the same direction and so
it's difficult to affect the NML significantly
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Calculating VIH
When Vin=VIH the output voltage is near 0 and
the transistor is operating in the linear region
IR = IDS (linear)
Following a similar procedure we end-up with:
8 *VDD
1
VIH VT
3 * k * RL k * RL
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Calculating VIH
8 *VDD
1
VIH VT
3 * k * RL k * RL
To decrease VIH we can increase kRL, however,
this increases the rising delay and increases
the power slightly
Changes in k and RL have no effect on VOH so
its possible to increase NMH
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Pull-up
transistor
Pull-down
transistor
Pull-up
transistor
Pull-down
transistor
Solution?
Depletion Load Inverter
Better noise margins
Single power supply
Smaller overall layer
More complicated fabrication
process
CMOS Inverter
Steady-state power dissipation negligible (only
due to leakage currents)
VTC Transition is very sharp (close to an ideal
inverter)
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CMOS Inverter
Vin is at VDD: the NMOS
device is conducting while the
PMOS (VGS=0) is cut-off and so
VOUT is 0 and IDN is almost
zero.
Vin is at GND, the NMOS is
cut-off while the PMOS is
conducting and so Vout is
equal to VDD and IDN is almost
zero.
large noise
VOH = VDD
VOL = 0
margins
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VTC
5 regions
VTC
Region
Vin
Vout
NMOS
PMOS
< VT0,n
VOH
Cut-off
Linear
II
VIL
III
Vs
Vs
IV
VIH
Low VOL
Linear
Saturation
> VDD+VT0,p
VOL
Linear
Cut-off
Linear
Saturation Saturation
VTC Symmetry
A completely symmetrical VTC is obtained if
VTP = - VTN and kP = kN
WN
ECN * LN
WP
ECP * LP
nWN
pWP
tpHL (propagation delay high to low): time delay between V50% transition of
the rising input voltage and the V50% transition of the falling output voltage.
tpLH (propagation delay low to low): time delay between V50% transition of
the falling input voltage and the V50% transition of the rising output voltage.
t PHL t PLH
tP
2
Vout(t ) VDD * e
-t/RN*CL
Vout(t ) VDD * (1 e
-t/RP*CL
Effective On-Resistance
Reff is inversely proportional to W/L
The NMOS and PMOS have difference Reff.
RN = Reqn*(LN/WN)
RP = Reqp*(LP/WP)
Reqn is defined in units
of L/W
intrinsic
Internal Capacitance
Comprised of the Capacitances connected to
the output (D):
Cdb1 and Cdb2 are the junction capacitance (D-to-B)
Since we mostly work in cut-off
and saturation Cgd12 (gate
capacitance) is almost
negligible except from
the overlap
capacitance
Fan-out Capacitance
The Fan-out capacitance is due to the input of
subsequent gates.
This capacitance can be large:
the sum of each of the driven
gate capacitances
tp vs. VDD
5.5
5
4
3.5
3
t (normalized)
4.5
2.5
2
1.5
1
0.8
1.2
1.4
1.6
1.8
(V)
DD
2.2
2.4
CMOS Fabrication
CMOS Fabrication
CMOS Technology depends on using both N-Type and PType devices on the same chip.
The two main technologies to do this task are:
P-Well
The substrate is N-Type. The N-Channel device is built into a PType well within the parent N-Type substrate. The P-channel
device is built directly on the substrate.
N-Well
The substrate is P-Type. The N-channel device is built directly
on the substrate, while the P-channel device is built into a Ntype well within the parent P-Type substrate.
Lithography
Each processing step requires that certain areas
are defined on chip by appropriate masks.
Consequently, the integrated circuit may be
viewed as a set of patterned layers of doped
silicon, polysilicon, metal and insulating silicon
dioxide.
In general, a layer must be patterned before the
next layer of material is applied on chip.
The process used to transfer a pattern to a layer
on the chip is called lithography.
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Basic Steps
PhotoResist
Summary
9 steps to make this simple
hole:
1. Oxidize silicon surface
2. Deposit photoresist
3. Anneal photoresist
4. Mount mask above silicon
5. Expose to UV light
6. Develop photoresist
7. Etch photoresist exposed
to UV
8. Etch SiO2 through
photoresist hole
9. Remove photoresist