Digital Circuits and Logic Designs

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DIRECTORATE OF DISTANCE EDUCATION
DIGITAL CIRCUITS AND

LOGIC DESIGNS
Copyright 2013, Dr Krishna Raj

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SYLLABUS
Digital Circuits and Logic Designs
Objectives: To enable the student to understand digital circuits and design of logic gates. Student will learn Boolean algebra,
various types of logic gates, combinational circuits, sequential circuits. Student will also learn the storage mechanism of
various memories and conversion system.
S.No.
Description
1.
Basic Concepts: Number systems - Binary, Octal, Decimal, Hexadecimal, conversion from one to another.
2.
Boolean Algebra: Complement arithmetic, Boolean theorems of Boolean algebra.
3.
Minimization of Boolean Algebra: Sum of products and product of sums, Minterms and Maxterms, Karnaugh
map, Tabulation and computer aided minimization procedures.
4.
Logic Gates: RTL, DTL, TTL, ECL, ICL, HTL, NMOS & CMOS logic gates, Circuit diagram and analysis
characteristics and specifications, tri-state gates.
5.
Combinational Circuits: Problem formulation and design of combinational circuits, Adder / Subtractor, Encoder
/ decoder, Mux /Demux, Code-converters, Comparators, Implementation of combinational logic using standard
ICs.
6.
Memories: ROM, EPROM, EEPROM, PAL, PLA and their use in combinational circuit design.
7.
Sequential Circuits: Flipflops - SR, JK, T, D, Master/Slave FF, Triggering of FF, Analysis of clocked sequential
circuits - their design.
8.
State minimization, state assignment, Circuit implementation, Registers-Shift registers, Ripple counters,
Synchronous counters, Timing signal, RAM, Memory decoding, Semiconductor memories.
9.
A/D and D/A Converters: Principle of analog to digital conversion, Weighted resistor and ladder networks, single
slope, dual slope, successive approximation and flash converters.
CONTENTS
Unit 1:
Number Systems
Unit 2:
Logic Gates
16
Unit 3:
Boolean Algebra
32
Unit 4:
Minimization of Boolean Algebra
47
Unit 5:
Combinational Circuits
63
Unit 6:
Implementation of Combinational Logic Circuit
77
Unit 7:
Standard Integrated Circuits (ICs)
94
Unit 8:
Memory
119
Unit 9:
Flip-Flops
140
Unit 10:
Clocked Sequential Circuits
158
Unit 11:
Registers and Counters
177
Unit 12:
A/D and D/A Converters
200
Unit 1: Number Systems
Notes
CONTENTS
Objectives
Introduction
1.1
Decimal Number System
1.2
Binary Number System
1.3
Hexadecimal Number System
1.4
Octal Number System
1.5
Conversion from One Number System to Another

1.5.1
Converting from Another Base to Decimal
1.5.2
Converting from Decimal to Another Base (Division-remainder Technique)
1.5.3
Converting from a Base Other Than 10 to Another Base Other Than 10
1.5.4
Short-cut Method for Binary to Octal Conversion
1.5.5
Short-cut Method for Octal to Binary Conversion
1.5.6
Short-cut Method for Binary to Hexadecimal Conversion
1.5.7
Short-cut Method for Hexadecimal to Binary Conversion
1.6
Summary
1.7
Keywords
1.8
Review Questions
1.9
Further Readings
Objectives
After studying this unit, you will be able to:
Discuss the decimal number system
Explain about binary number system
Discuss the hexadecimal number system concept
Discuss the octal number system
Elaborate upon the conversions between number system concept
Introduction
Modern computers do not work with decimal numbers like 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. Instead
they process binary numbers which are in the groups of Os and 1s. As electronic devices are most
reliable when designed for two states either on or off, binary notation used two digits for the
same. People do not like working with binary numbers because they are very long. Entering
binary numbers into computer becomes tedious. Therefore octal and Hexadecimal numbers are
widely used to compress long strings of binary numbers.
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Notes
We will now discuss two kinds of number systems:
Non-positional number systems

A non-positional number system uses a limited number of symbols in which each symbol has a
value. However, the position a symbol occupies in the number normally bears no relation to its
valuethe value of each symbol is fixed. To find the value of a number, we add the value of all
symbols present in the representation.
Positional number systems

In a positional number system, the position a symbol occupies in the number determines the
value it represents.
In this system, a number represented as:
(sk 1 ...s1s0 .s1s2 ...s l )b

has the value of:
n = sk 1 b k 1 + ... + s1 b1 + s0 s 0 + s1 b 1 + s2 b 2 + ... + s l b l
in which S is the set of symbols, b is the base (or radix).
Example: Octal, Decimal, Hexadecimal, etc.
1.1 Decimal Number System

The decimal number system is a positional number system. The actual number of symbols used
in a positional number system depends on its base (also called the radix). The highest numerical
symbol always has a value of one less than the base. The decimal number system has a base of
10, so the numeral with the highest value is 9; the octal number system has a base of 8, so the
numeral with the highest value is 7, the binary number system has a base of 2, so the numeral
with the highest value is 1, etc. Any number can be represented by arranging symbols in specific
positions. You know that in the decimal number system, the successive positions to the left of
the decimal point represent units (ones), tens, hundreds, thousands, etc. Put another way, each
position represents a specific power of base 10.
Example: The decimal number 1,275 (written 127510) can be expanded as follows:
Note n0 = 1, or any number raised to the zero power is equal to 1.
In the example above, 1 is called the most significant digit (MSD) as it carries the maximum
weight (Thousand) and 5 carries the least weight (Unit) and is called the least significant digit
(LSD).
Notes
Our counting system is based on the number 10 (10 fingers). The main principle of the decimal
system is that 10 is considered as a new unit from which point counting starts again. Ten tens is
again a new unit. The multiples of 10 are counted by the same systems as 1 to 9.
1
10
11
12
13
14
15
16
17
18
19
20
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
91
92
93
94
95
96
97
98
99
100
This way of counting is old. Indo-European languages are spoken from India to Europe and have
the same counting system and very similar number words. We can conclude that the basic Indo
European mother language had the same method of counting called decimal counting
(3000 BC).
Note No decimal number-system spoken words like twenty three belong to the decimal
counting system, 23 belongs to the decimal number notation.
Self Assessment
State whether the following statements are true or false:
1.
A positional number system uses a limited number of symbols in which each symbol has
a value.
2.
The decimal number system is a positional number system.
3.
The actual number of symbols used in a positional number system depends on its radix.
1.2 Binary Number System

This is also a positional number where the base of the binary number system is two, so each
position of the binary number represents a successive power of two. Because of its straightforward
implementation in digital electronic circuitry, the binary system is used internally by almost all
modern computers and computer-based devices such as mobile phones. From right to left, the
successive positions of the binary number are weighted 1, 2, 4, 8, 16, 32, 64, etc. A list of the first
several powers of 2 follows:
20 = 1
21 = 2
22 = 4
23 = 8
24 = 16
25 = 32
26 = 64
27 = 128
28 = 256
29 = 512
210 = 1024
211 = 2048
Notes
For reference, the following table shows the decimal numbers 0 through 31 with their binary
equivalents:
Table 1.1: Binary Equivalents of Decimal Numbers
Source: http://www.thevbprogrammer.com/Ch04/Number%20Systems%20Tutorial.pdf
To convert a Binary Number to a Decimal Number, we can expand the number using the
positional weights as follows:
Example:
Task Convert (1100110)2 to decimal number.
Self Assessment
4.
Radix of the Binary Number System is 10.
5.
From left to right, the successive positions of the binary number are weighted 1, 2, 4, 8, 16,
32, 64, and so on.
6.
The decimal equivalent of (1101010) 2 is (106)10
Did u know? The Indian scholar Pingala (around 5th2nd centuries BC) developed
mathematical concepts for describing prosody, and in doing so presented the first known
description of a binary numeral system.
Notes
1.3 Hexadecimal Number System

The hexadecimal (base 16) number system is a positional number system. In this system the
highest numerical symbol always has a value of one less than the base. Also, only one symbol
must ever be used to represent a value in any position of the number.
For number systems with a base of 10 or less, a combination of Arabic numerals can be used to
represent any value in that number system. The decimal number system uses the Arabic numerals
0 through 9; the binary number system uses the Arabic numerals 0 and 1; the octal number
system uses the Arabic numerals 0 through 7; and any other number system with a base less than
10 would use the Arabic numerals from 0 to one less than the base of that number system.
However, if the base of the number system is greater than 10, more than 10 symbols are needed
to represent all of the possible positional values in that number system. The hexadecimal number
system uses not only the Arabic numerals 0 through 9, but also uses the letters A, B, C, D, E, and
F to represent the equivalent of 1010 through 1510, respectively.
For reference, the following table shows the decimal numbers 0 through 31 with their hexadecimal
equivalents:
Table 1.2: Hexadecimal Equivalents of Decimal Numbers
The same principles of positional number systems we applied to the decimal, binary, and octal
number systems can be applied to the hexadecimal number system. However, the base of the
hexadecimal number system is 16, so each position of the hexadecimal number represents a
successive power of 16. From right to left, the successive positions of the hexadecimal number
are weighted 1, 16, 256, 4096, 65536, etc.:
160 = 1
161 = 16
163 = 4096
164 = 65536
162 = 256
Self Assessment
Fill in the blanks:
7.
The hexadecimal number system is a ........................ number system.
8.
The radix value of hexadecimal number system is ........................ .
Notes
9.
To represent the decimal number 10, the hexadecimal number system uses the symbol
........................ .
10.
From ........................ to ........................, the successive positions of the hexadecimal number

are weighted 1, 16, 256, 4096, 65536, and so on.
1.4 Octal Number System

The same principles of positional number systems we applied to the decimal and binary number
systems can be applied to the octal number system. However, the base of the octal number
system is eight, so each position of the octal number represents a successive power of eight.
From right to left, the successive positions of the octal number are weighted 1, 8, 64, 512, etc.
A list of the first several powers of 8 follows:
80 = 1
81 = 8
82 = 64
83 = 512
84 = 4096
85 = 32768
For reference, the following table shows the decimal numbers 0 through 31 with their octal
equivalents:
Table 1.3: Octal Equivalents of Decimal Numbers
To convert octal to binary, replace each octal digit by its binary representation.
Example: Convert 518 to binary:
5 8 = 1012
1 8 = 0012
Therefore, 518 = 101 0012.
The process to convert binary to octal is the reverse of the previous algorithm. The binary digits
are grouped by threes, starting from the least significant bit and proceeding to the left and to the
right. Add leading 0s (or trailing zeros to the right of decimal point) to fill out the last group of
three if necessary. Then replace each trio with the equivalent octal digit.
Notes
Example: Convert binary 1010111100 to octal:
001
010
111
100
Therefore, 10101111002 = 12748.
Unit and Number

The unit is a single object whereas number is a symbol that is used to represent one or more
units.
Base (Radix)
It is the number of symbols used in the system. The octal system uses eight symbols0 to 7 and
hence its base is 8.
Positional Notation
The octal number system is also positional notation number system which uses 8 to find the
value of the position of a number.
Self Assessment
Fill in the blanks:
11.
The base of the octal number system is ........................ .
12.
In the process to convert binary to octal, binary digits are grouped in a set of .................. .
13.
The number of symbols used in the system is called the ........................ .
14.
........................ is a symbol that is used to represent one or more units.
1.5 Conversion from One Number System to Another

We have been using the decimal representation since the day we learnt about numbers. But we
can represent them in various other types of number systems. This is due to the need and
requirements of the scenario. For example, as our electronic devices work on binary system, we
need to convert our decimal numbers to their equivalent binary representation.
We will now discuss in detail about these conversions and ways to convert them.
1.5.1
Converting from Another Base to Decimal
In order to convert a number in any other base to a decimal number, follow the steps below:
As per the base of the number system and position of the digit, find the positional value of
each digit.
Multiply the values obtained in the previous step by the digits in the corresponding
columns.
Add the products calculated in the step above.
Notes
The sum obtained is the equivalent value in decimal.

Example:
Convert 1011001012 to the corresponding base-ten number.
(a)
List the digits in order, and count them off from the RIGHT, starting with zero:
Digits:
Numbering:
The first row above (labelled digits) contains the digits from the binary number; the
second row (labelled numbering) contains the power of 2 (the base) corresponding to
each digits.
Use this listing to convert each digit to the power of two that it represents:
128 + 027 + 126 + 125 + 024 + 023 + 122 + 021 + 120
= 1256 + 0128 + 164 + 132 + 016 + 08 + 14 + 02 + 11
= 256 + 64 + 32 + 4 + 1
= 357
Hence 1011001012 converts to 35710.
(b)
Convert 537028 8 to the corresponding base-ten number.

537028
= 5 x 84 + 3 x 83 + 7 x 82 + 0 x 81 + 1 x 80
= 4096s 512s 64s
8s
1s (units)
To change this number to base 10, multiply each placeholder by the amount its location
represents and add:
(5 4096) + (3 512) + (7 64) + (0 8) + (1 1)
= 20,480 + 1536 + 448 + 0 + 1
= 22,46510
Hence 537028 8 converts to 22,46510
Task Convert 537CA16 to decimal.
1.5.2
Converting from Decimal to Another Base (Division-remainder

Technique)
We can also convert a decimal number to a number in another base using the following steps:
Divide the decimal number by the value of the new base.
The remainder from the step above is the rightmost digit (least significant digit) of the
new base number.
Divide the quotient of the previous division by the new base.
Record the remainder from Step 3 as the next digit (to the left) of the new base number.
Repeat Steps 3 and 4, recording remainders from right to left, until the quotient becomes
zero in Step 3.
The last remainder is the most significant digit of the new base number.
Notes
Example: Convert the decimal number 82 to base 6:

82/6
13
remainder 4
13/6
remainder 1
2/6
remainder 2
The answer is formed by taking the remainders in reverse order: (2 1 4)6
1.5.3
Converting from a Base Other Than 10 to Another Base Other

Than 10
It is not necessary to convert between systems with base 10. We can also have conversion of a
number in a base other than 10, to number base other than 10. To do this, follow the steps below:
Convert the original number to a base (decimal) number.
Convert the decimal number obtained in step 1 to the new base number.
Example:
Convert (45)6 = ?
Step 1: Convert from base 6 to base 10

45 = 4*61 + 5*60
= 4*6 + 5*1
= 24 + 5
= 29 10
Step 2: Convert 2910 to base 4
29/4 = 7, Remainder is 1
29 10 = 1314
1.5.4
Short-cut Method for Binary to Octal Conversion
Count off from right to left by three and translate each triad into base 10. These digits will be the
base-8 symbols to express this binary number in octal.
Example:
Notes
1.5.5
Short-cut Method for Octal to Binary Conversion
Convert each octal digit to a 3 digit binary and combine all the resulting binary groups (of 3
digits each) into a single binary number.
Example:
Change 6300768 to a binary number.
6
110 011 000 000 111 110
therefore, the binary number is

1100110000001111102
1.5.6
Short-cut Method for Binary to Hexadecimal Conversion
Count off from right to left by four and translate each quad into base 10. These digits will be the
base-16 symbols to express this binary number in hexadecimal.
Example:
Change 10010111012 to hexadecimal number.
0010
0101
1101
13/D
1.5.7
therefore, the hexadecimal number if 25D16
Short-cut Method for Hexadecimal to Binary Conversion
Convert each hexadecimal digit to a 4 digit binary and combine all the resulting binary groups
(of 4 digits each) into a single binary number.
Example:
Change A3D916 to a binary number.
A
1010
0011
1101
1001
therefore, the binary number is 10100011110110012
The relationships between the various number systems are summarized in the Table below:
Table 1.4: Relationships between the Various Number Systems
Contd...
10
Notes
Source: http://a-tu-z.blogspot.in/2012/06/number-systems.html
Case Study
Understanding Place Value the Base Ten Game
he initial objectives of this project were to research approaches for improving

students mathematical learning outcomes in relation to the base ten number system
and methods for tracking students understanding of number within a whole class
setting. The research also aimed to explore the strategies that support the learning of each
student as he or she progresses to the next stage of understanding of the number system.
The research attempted to build upon the work of previous studies that explored ways
teachers could more actively assist students to develop their understanding of the structure
of the number system. The project explored the role of a commonly used teaching activity,
referred to in the project as the base ten game, in developing childrens understanding of
our number system. The game involves students using a place value board and concrete
materials to develop an understanding of the structure of the number system and to learn
to operate on numbers using this structure. To play the most basic version of the game, the
student rolls two dice, adds the numbers shown, and collects that quantity of pop-sticks to
add to their game-board, which is ruled up into place value columns (see Figure 1). The
only rule of the game is that there can be no more than nine items in any one column. Once
there are nine sticks
Figure 1: Game Board Showing 25 Pop-sticks
in the units column, the tenth stick is combined to make a bundle of ten sticks which is
then placed in the tens column. Rubber bands can be used to hold the bundles of sticks
together. The only rule of the game is that there can be no more than nine in any one
column, that is, in the units column there can be no more than nine sticks, in the tens
column there can be nor more than nine bundles of ten sticks, in the hundreds column
there can be nor more than nine bundles of 100 sticks, and so on. The project was undertaken
using a model of action research, involving nine teachers. The teachers selected to
participate in this study had all previously undertaken extended professional development
to incorporate constructivist learning theories in their teaching, and the teachers were
Contd...
11
Notes
keen to explore the use of concrete materials, especially the base ten game in relation to
student learning. The five project schools represented the diverse range of communities
within the independent sector, including an isolated rural school with high numbers of
Indigenous students, small and large urban schools, and two schools with high numbers
of students from a low socio-economic background. The research took place between
March and October of 2001, and involved approximately 280 primary students. The research
methodology enabled the teacher researchers to focus on improved student learning
through changes in teacher practice and allowed concentration on the practical, day-today realities of the classroom. Under the broad question, What are the most effective
teaching methods and management structures that will maximize the learning of the base
ten number system in a whole class setting? Each teacher developed their own specific
research question. Within the parameters of each individual research question were
common elements of investigation that included:
the range of teaching and learning strategies that were employed to enhance base
ten learning;
monitoring and evaluation of these strategies;
teacher knowledge that was required to effectively help students learn; and
the use of concrete materials to assist learning.
Throughout the project the teacher researchers were guided by a Project Officer, Mrs.
Andrea Broadbent. The teacher researchers came together for professional development
and sharing of experiences, received visits to their schools, and kept reflective journals
and student work samples. Each teacher reflected upon their learning and wrote a report
of their learning journey. A final research report, drawing together common elements
was constructed. The major findings from this project are listed below:
Teachers needed to develop their own knowledge of the base ten number system
before they could help students learn. The teachers own understanding of the number
system improved when they focussed on features of the number system that they
wanted their students to learn. By clarifying the desired learning outcomes, the
project teachers were better able to identify children who were having difficulty,
and plan appropriate learning experiences for these children. Professional
development which focused on the childrens conceptual understanding was likely
also to assist teachers to develop their own understandings.
Once teachers had developed their own relational understanding of the number
system, they were better able to:
discover what each student already knew about base ten;
diagnose any misconceptions that a student may have developed;
offer learning activities that enabled students to build their knowledge;
adapt learning activities to meet the individual learning needs of the diversity
of students in the class.
Concrete materials, such as those used in the base ten game, can make a significant
contribution to the development of students conceptual and procedural knowledge
about the number system across all year levels.
Any one set of concrete materials or any one teaching activity highlights only
certain aspects of the number system. A deep understanding requires a range of
Contd...
12
materials and activities, chosen according to the features of the number system that
they highlight.
Notes
The base ten game is a valuable core activity for students of all year levels who are
still trying to make sense of the structure of the number system. Its usefulness will
be enhanced by the addition of complementary activities which both support the
ideas being developed through the base ten game, and which look at the same ideas
in a different way.
This project revealed the necessity of explicitly developing links between the concrete
materials, the learning activities and the structure of the number system to support the
development of relational understanding of place-value.
Figure 2: Using 0-9 digit cards
on rings to support learning
about how numbers are written
Figure 3: A year 5 student using four disc

to explore continuous addition of larger
numbers through the base ten game.
Questions:
1.
Discuss the model used by the project.
2.
Discuss the major findings from this project.
Source: http://www.eric.ed.gov/ERICWebPortal/search/detailmini.jsp?_nfpb=true&_&ERICExtSearch_SearchValue_0=EJ793952&ERICE
xtSearch_SearchType_0=no&accno=EJ793952
Self Assessment
Fill in the blanks:
15.
To convert Binary to Octal we group binary into set of ........................ digits.
16.
To convert Binary to Hexadecimal we group binary into set of ........................ digits.
1.6 Summary
Modern computers do not work with decimal numbers like 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.

Instead they process binary numbers which are in the groups of Os and 1s.
A non-positional number system uses a limited number of symbols in which each symbol
has a value.
In a positional number system, the position a symbol occupies in the number determines
the value it represents.
13
Notes
The actual number of symbols used in a positional number system depends on its base
(also called the radix).
The decimal number system has a base of 10, so the numeral with the highest value is 9.
Most significant digit (MSD) carries the maximum weight and least significant digit (LSD)
carries the minimum weight.
Binary number system is a positional number where the base of the binary number
system is two, so each position of the binary number represents a successive power of two.
The hexadecimal (base 16) number system is a positional number system.
However, the base of the octal number system is eight, so each position of the octal
number represents a successive power of eight.
The unit is a single object whereas number is a symbol that is used to represent one or
more units.
It is possible to convert from one number system to another.
1.7 Keywords
Binary Number System: It has a base of 2 and two values 0 and 1.
Decimal Number System: It has a base of 10, so the numeral with the highest value is 9.
Hexadecimal Number System: It has a base of 16.
Least Significant Digit (LSD): It carries the minimum weight.
Most Significant Digit (MSD): It carries the maximum weight.
Non-positional Number System: It uses a limited number of symbols in which each symbol has
a value.
Octal Number System: It has a base of 8.
Positional Number System: The position a symbol occupies in the number determines the value
it represents.
Radix/base: The actual number of symbols used in a positional number system depends on it.
1.8 Review Questions
14
1.
What is number system?
2.
Differentiate between positional and non-positional number systems.
3.
What is radix? Why is it used?
4.
What is a unit?
5.
Explain the decimal number system with an example.
6.
Give the steps to converting from a base other than 10 to another base other than 10.
7.
How do we convert an octal number to binary?
8.
How do we convert an binary number to hexadecimal?
9.
Explain the steps to convert a decimal number to binary form.
10.
Explain the relationship between the various number systems.
Notes
Answers: Self Assessment

1.
False
2.
True
3.
True
4.
False
5.
False
6.
True
7.
Positional
8.
16
9.
10.
Right , Left
11.
12.
13.
Base
14.
Number
15.
16.
1.9 Further Readings
Books
Anil K. Maini, Digital Electronics: Principles, Devices and Applications, John Wiley
& Sons
Doug Lowe, Digital Electronics: Integrated Circuit Logic Gates
J. Stanley Warford, Jones & Bartlett Learning, Computer Systems, 4th Edition
Mano, Digital Logic & Computer Design
Online links
http://cis.sac.alamo.edu/~gboswell/net1305102102/Computer_Number_
Systems.pdf
http://courses.cs.vt.edu/~cs1104/number_conversion/convexp.html
http://mae.ucdavis.edu/dsouza/Classes/ECS15-W13/counting.pdf
http://www.rit.edu/~wasc/documents/services/resources/handouts/
DM4%20Octal%20and%20Hexadecimal%20Number%20Systems.pdf
15
Notes
Unit 2: Logic Gates

CONTENTS
Objectives
Introduction
2.1
2.2
Types of Logic Gates

2.1.1
The NOT (Inverter) Gate
2.1.2
The AND Gate
2.1.3
The OR Gate
2.1.4
NAND Gate
2.1.5
The NOR Gate
2.1.6
XOR Gate (Exclusive-OR)
2.1.7
XNOR Gate
2.1.8
Non-Inverter or Buffer
2.1.9
Open Collector and Open Drain
Tri-State Gates
2.2.1
Active HIGH Tri-state Gates
2.2.2
Active LOW Tri-state Gate
2.2.3
Tri-state Gate Control
2.2.4
Double Inversion Using NOT Gates
2.2.5
Gate Fan-out Example
2.3
Summary
2.4
Keywords
2.5
Review Questions
2.6
Further Readings
Objectives
Explain the types of logic gates
Describe the circuit diagram of gates
Discuss tri-state gates
Introduction
Logic gates or gates are the basic building blocks of digital circuitry. As their name implies, they
function by opening or closing to admit or reject the flow of digital information. It is an
idealized or physical device implementing a Boolean function, that is, it performs a logical
operation on one or more logical inputs, and produces a single logical output. Gates implement
16
Unit 2: Logic Gates
electronically simple logical operations on Boolean variables, i.e. variables that can have only
one of two states (0/1, low/high, false/true). From an electrical point of view and for the TTL
(transistor-transistor-logic) family of digital electronics, any voltage in the range 0-0,7 V and in
the range 2,5-5 V, represent logic states 0 and 1, respectively.
Notes
2.1 Types of Logic Gates

There are mainly 7 types of logic gates that are used in expressions. By combining them in
different ways, you will be able to implement all types of digital components. Let us take a look
at each basic logic gate and their operation.
2.1.1
The NOT (Inverter) Gate
The NOT gate is also called as an inverter as it changes the input to its opposite. The NOT gate is
having only one input and one corresponding output. It is a device whose output is always the
compliment of the given input. That means, the NOT gate produces an output of logic 1 state
when the input is of logic 0 state and also produce the output of logic 0 state when the input is of
logic 1 state. The NOT operation is denoted by -(bar). When the input variable to the NOT gate
is represented by X and the output is represented by Z, then the output is read as Z is equal to
X bar. The logic symbol and truth table are given below:
Figure 2.1: NOT Gate
Source: http://www.circuitstoday.com/logic-gates#NOT
The NOT gate is used in the inverter integrated circuit 7404. It was used to build the mini and
mainframe computers of the 1960s and 1970s. It has six inverters inside and to make this integrated
circuit work, you need to connect it to a 5 V power supply.
Figure 2.2: IC-7404
Source: https://faculty-web.msoe.edu/tritt/hs/hsdig01.html
2.1.2
The AND Gate
It takes in two or more inputs and produce only one output. The AND gate produces an output
of logic 1 state when each of the inputs are at logic 1 state and also produces an output of logic 0
17
Notes
state even if any of its inputs are at logic 0 state. The symbol for AND operation is ., or we use
no symbol for representing. If the inputs are of X and Y, then the output can be expressed as
Z=XY. The AND gate is so named because, if 0 is called false and 1 is called true, the gate
performs in the same way as the logical and operator. The AND gate is also named as all or
nothing gate. The logic symbols and truth tables of two-input and three-input AND gates are
given below:
Figure 2.3: AND Gate
Source: http://www.circuitstoday.com/logic-gates#AND
The AND gate is used in the integrated circuit 7408.

Figure 2.4: IC-7408
2.1.3
The OR Gate
Similar to AND gate, an OR gate may also have two or more inputs but produce only one output.
The OR gate produces an output of logic 1 state even if any of its inputs is in logic 1 state and also
produces an output of logic 0 state if any of its inputs is in logic 0 state. The symbol for OR
operation is +. If the inputs are of X and Y, then the output can be represented as Z=X+Y. An OR
gate may also be defined as a device whose output is 1, even if one of its input is 1. OR gate is also
called as any or all gate. It is also called as an inclusive OR gate because it consists of the
condition of both the inputs can be present. The logic symbols and truth table for two-input and
three-input OR gates are given below:
Figure 2.5: OR Gate
Source: http://www.circuitstoday.com/logic-gates#OR
18
Unit 2: Logic Gates
The OR gate is used in the integrated circuit 7432.
Notes
Figure 2.6: IC-7432
2.1.4
NAND Gate
The NAND gate is a universal gate. NAND has the ability to perform three basic logic functions
such as AND, OR and NOT. NAND gate is a combination of an AND gate and a NOT gate. The
expression for the NAND gate is whole bar. The output of the NAND gate is at logic 0 level
only when each of the inputs assumes a logic 1 level. The truth table of two-input NAND gate is
given below:
Figure 2.7: NAND Gate
Source: http://www.circuitstoday.com/logic-gates#NAND
It is possible to expand the number of inputs using the NAND gate too.
Figure 2.8: Expanding Inputs Width NAND Gate
Source: http://www.hardwaresecrets.com/article/Introduction-to-Logic-Gates/237/4
You can also easily transform NAND gate into inverters by shorting its inputs.
Figure 2.9: Realizing NOT Gate Through NAND Gate
Source: http://www.nptel.iitm.ac.in/courses/Webcourse-contents/IIT-KANPUR/esc102/node28.html
19
Notes
The NAND gate is used in the integrated circuit 7411.

Figure 2.10: IC-7411
2.1.5
The NOR Gate
NOR means NOT OR. That means, NOR gate is a combination of an OR gate and a NOT gate. The
output is logic 1 level, only when each of its inputs assumes a logic 0 level. For any other
combination of inputs, the output is a logic 0 level. The truth table of two-input NOR gate is
given below:
Figure 2.11: NOR Gate
Table 2.1: Truth Table for NOR Gate
It is possible to expand the number of inputs using the NOR gate.

Figure 2.12: Expanding Inputs Width NOR Gate
20
Unit 2: Logic Gates
You can also easily transform NOR gate into inverters by shorting its inputs.
Notes
Figure 2.13: Realizing NOT Gate Through NOR Gate
The NOR gate is used in the integrated circuit 7402.

Self Assessment
Fill in the blanks:
1.
Boolean variables can take up two numeric values ........................ or ........................ .
2.
The ........................ gate is also called as an inverter as it changes the input to its opposite.
3.
The ........................ gate is used in the integrated circuit 7432.
4.
NOR gate is a combination of an ........................ gate and a ........................ gate.
2.1.6
XOR Gate (Exclusive-OR)
An X-OR gate is a two input, one output logic circuit. X-OR gate assumes logic 1 state when any
of its two inputs assumes a logic 1 state. When both the inputs assume the logic 0 state or when
both the inputs assume the logic 1 state, the output assumes a logic 0 state. The output of the XOR gate will be the sum of the modulo sum of its inputs. X-OR gate is also termed as anticoincidence gate or inequality detector. An X-OR gate can also be used as inverter by connecting
one of the two input terminals to logic1 and also by inputting the sequence to be inverted to the
other terminal.
Figure 2.15: X-OR Gate
Source: http://www.circuitstoday.com/logic-gates#XOR
21
Notes
It is possible to expand the number of inputs using the X-OR gate.

Figure 2.16: Expanding Inputs Width X-OR Gate
The X-OR gate is used in the integrated circuit 7486.

2.1.7
XNOR Gate
An X-NOR gate is a combination of an X-OR gate and a NOT gate. The X-NOR gate is also a two
input, one output concept. The output of the X-NOR gate will be logic 1 state when both the
inputs assume a 0 state or when both the inputs assume a 1 state. The output of the X-NOR gate
will be logic 0 state when one of the inputs assume a 0 state and the other a 1 state. It is also
named as coincidence gate, because its output will be 1 only when the inputs coincide. X-NOR
gate can also be used as inverter by connecting one of the two input terminals to logic 0 and also
by inputting the sequence to be inverted to the other terminal.
Figure 2.18: X-NOR Gate
Source: http://www.circuitstoday.com/logic-gates#XNOR
22
Unit 2: Logic Gates
It is possible to expand the number of inputs using the X-NOR gate.
Notes
Figure 2.19: Expanding Inputs Width X-NOR Gate
The X-NOR gate is used in the integrated circuit 747266.

Figure 2.20: IC-747266
2.1.8
Non-Inverter or Buffer
The buffer is a single-input device which has a gain of 1, mirroring the input at the output. It has
value for impedance matching and for isolation of the input and output.
Figure 2.21: Buffer
Source: http://www.hardwaresecrets.com/printpage/Introduction-to-Logic-Gates/237
Table 2.2: Truth Table for Buffer
Source: http://www.hardwaresecrets.com/printpage/Introduction-to-Logic-Gates/237
The buffer has multiple applications in day to day life. It is used in the integrated circuit 74367.
23
Notes
Figure 2.22: IC-74367
It is also used to increase the fan-out of a given logic gate where fan-out is the maximum number
of gates a given integrated circuit is capable of being connected to. A non-inverter is to create a
delay line.
Figure 2.23: Delay Line Using the Buffer
Source: http://www.hardwaresecrets.com/fullimage.php?image=2349
2.1.9
Open Collector and Open Drain
When driving external devices, it is sometimes necessary to use open-collector or open-drain

outputs. Open-collector or open-drain outputs do not source current, they can only sink current.
Essentially, they act as simple switches to ground. In their high state, they are open circuits, and
in their low state they pull the output pin to ground, sinking as much current as needed, up to a
limit. The digital outputs of the PDQ Board, QCard Controller, and other Wildcards are not
open-collector. Instead, they are more generally useful totem-pole, three-state outputs they
have transistors to actively source current for a logic high, and to sink current for logic low, as
well as the ability to turn off both transistors to isolate the output in a high impedance state.
When in the high impedance state the pins can usually be used as inputs. But sometimes your
application may require the simpler open collector output. For example, to drive 3.3 volt logic
devices you would not want to drive their inputs to a 5 volt logic high, as it would be greater
than their power supply voltage. So, you would use an open collector output to actively drive
the external input low, but allow it to be pulled high passively by a pull-up resistor only to 3.3V.
There are two ways to make a PDQ Board output pin simulate the behavior of an open-collector
pin, one in software and one in hardware. In either case, you can use the output to connect to
devices that pull-up to a voltage less than 5V, such as 3.3V logic inputs. You cannot connect use
these methods to connect to external voltages greater than 5V, as that may harm the output pin.
24
Unit 2: Logic Gates
Figure 2.24: Converting-Digital-Output-to-open-Collector
Notes
Source: http://www.mosaic-industries.com/embedded-systems/_detail/microcontroller-projects/electronic-circuits/converting-digital-outputto-open-collector.png?id=microcontroller-projects:electronic-circuits:open-collector-outputs
Self Assessment
Fill in the blanks:
5.
The ........................ gate is used in the integrated circuit 7486.
6.
An X-NOR gate is a combination of an ........................ gate and a ........................ gate.
7.
The buffer is a ........................ input device which has a gain of 1, mirroring the input at the
output.
8.
A ........................ is to create a delay line.
2.2 Tri-State Gates

A tri-state buffer is a useful device that allows us to control when current passes through the
device, and when it doesnt.
Figure 2.25: Tri-state Buffer
Source: http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/CompOrg/tristate.html
A tri-state buffer has two inputs: a data input x and a control input c. The control input acts like
a valve. When the control input is active, the output is the input. That is, it behaves just like a
normal buffer. The valve is open. When the control input is not active, the output is Z. The
valve is open, and no electrical current flows through. Thus, even if x is 0 or 1, that value does
not flow through.
25
Notes
Figure 2.26: Tri-state Buffer
Source: http://openbookproject.net/electricCircuits/Digital/DIGI_3.html
2.2.1
Active HIGH Tri-state Gates
In this case, when the output is Z, that means its high impedance, neither 0, nor 1, i.e., no current.
Table 2.3: High Tri-state Gate
When c = 1 the valve is open, and z = x. When c = 0 the valve is closed, and z = Z (e.g., high
impedance/no current).
2.2.2
Active LOW Tri-state Gate
Some tri-state buffers are active low. In an active-low tri-state buffer, c = 0 turns open the valve,
while c = 1 turns it off. Heres the condensed truth table for an active-low tri-state buffer.
Table 2.4: Active Low Tri-state Gate
As you can see, when c = 0 the valve is open, and z = x. When c = 1 the valve is closed, and z = Z
(e.g., high impedance/no current). Thus, it has the opposite behavior of a tri-state buffer.
2.2.3
Tri-state Gate Control
The third state (Hi-Z) removes the devices influence from the rest of the circuit. If more than one
device is electrically connected, putting an output into the Hi-Z state is often used to prevent
26
Unit 2: Logic Gates
short circuits, or one device driving high (logical 1) against another device driving low (logical
0). Three-state buffers can also be used to implement efficient multiplexers, especially those
with large numbers of inputs. In particular, they are essential to the operation of a shared
electronic bus. Three-state logic can reduce the number of wires needed to drive a set of LED.
Notes
Figure 2.27: Tri-state Gate Control Connected to a Single Wire or Bus
Source: http://www.electronics-tutorials.ws/logic/logic_9.html
2.2.4
Double Inversion Using NOT Gates
A non-inverting digital Gate can be used to isolate other gates or circuits from each other. They
are also used to drive high current loads such as transistor switches because their output drive
capability is much higher than their input signal requirements.
Figure 2.28: Double Inversion Using NOT Gates
Source: http://www.electronics-tutorials.ws/logic/logic_9.html
2.2.5
Gate Fan-out Example
Fan-out of a logic gate output is the number of gate inputs to which it is connected. In most
designs, logic gates are connected to form more complex circuits. While no more than one logic
gate output is connected to any single input, it is common for one output to be connected to
several inputs. It is used to implement logic gates usually allows a certain number of gate inputs
to be wired directly together without additional interfacing circuitry. The maximum fan-out of
an output measures its load-driving capability: it is the greatest number of inputs of gates of the
same type to which the output can be safely connected.
Figure 2.29: Example of a Fan-out
Source: http://www.ece.unm.edu/~jimp/vlsi/slides/chap5_1.html
27
Notes
Self Assessment
9.
A tri-state buffer is a useful device that allows us to control when current passes through
the device, and when it doesnt.
10.
A tri-state buffer has 3 states and 1 buffer state.
11.
A inverting digital Gate can be used to isolate other gates or circuits from each other.
12.
Fan-in of a logic gate output is the number of gate inputs to which it is connected.
13.
The maximum fan-out of an output measures its load-driving capability.
14.
In Active HIGH Tri-state Gates when the output is Z, that means its high impedance,
neither 0, nor 1, i.e., no current.
15.
In an active-low tri-state buffer, c = 0 turns open the valve, while c = 1 turns it off.
Case Study
Digital Logic Circuit
igital logic is a rational process for making simple true or false decisions
based on the rules of Boolean algebra. Binary logic was first proposed by 19thcentury British logician and mathematician George Boole, who in 1847 invented
a two-valued system of algebra that represented logical relationships and operations.
This system of algebra, called Boolean Algebra, was used by German engineer Konrad
Zuse in the 1930s for his Z1 calculating machine. It was also used in the design of the first
digital computer in the late 1930s by American physicist John Atanasoff and his graduate
student Clifford Berry. During 1944 and 1945 Hungarian-born American mathematician
John von Neumann suggested using the binary arithmetic system for storing programs in
computers. In the 1930s and 1940s British mathematician Alan Turing and American
mathematician Claude Shannon also recognized how binary logic was well suited to the
development of digital computers.
Functions performed by logic circuits
True can be represented by a 1 and false by a 0, and in logic circuits the numerals
appear as signals of two different voltages. Logic circuits are used to make specific truefalse decisions based on the presence of multiple true-false signals at the inputs. The
signals may be generated by mechanical switches or by solid-state transducers. Once the
input signal has been accepted and conditioned (to remove unwanted electrical signals, or
noise), it is processed by the digital logic circuits. The various families of digital logic
devices, usually integrated circuits, perform a variety of logic functions through logic
gates, including OR, AND, and NOT, and combinations of these (such as NOR,
which includes both OR and NOT).
Types of Logic Components
One widely used logic family is the transistor-transistor logic (TTL). Another family is the
complementary metal oxide semiconductor logic (CMOS), which performs similar functions
at very low power levels but at slightly lower operating speeds. Several other, less popular
families of logic circuits exist, including the currently obsolete resistor-transistor logic
(RTL) and the emitter coupled logic (ELC), the latter used for very-high-speed systems.
Contd...
28
Unit 2: Logic Gates
Notes
Logical Gates
The elemental blocks in a logic device are called digital logic gates.
An AND gate has two or more inputs and a single output.

The output of an AND gate is true only if all the inputs are
true.
An OR gate has two or more inputs and a single output. The
output of an OR gate is true if any one of the inputs is true
and is false if all of the inputs are false.
An INVERTER has a single input and a single output
terminal and can change a true signal to a false signal, thus
performing the NOT function.
A NAND gate has two or more inputs and a single output.
The output of a NAND gate is true if any one of the inputs
is false and is false if all the inputs are true.
The output of an NOR gate is true if all the inputs are
false and is false if the inputs are different.
The output of an EXCLUSIVE OR gate is true if the inputs
are different and is false if the inputs are the same.
Obs. You can easily observe how the NAND gate can be emulated by two other gates
(AND, NOT). The output of the AND gate is connected to the input of the NOT gate.
The output of the NAND gate is true if the one of the input is false. Now lets verify: We put
true and false on the inputs of the AND gate. This gate now returns false answer (0). This
false answer is the input of the NOT gate. This gate returns true (opposite of false). You can
now see that the answer is similar to the one witch NAND returned.
Other facts
To perform a desired overall function, large numbers of logic elements may be connected
in complex circuits. In some cases microprocessors are utilized to perform many of the
switching and timing functions of the individual logic elements. The processors are
specifically programmed with individual instructions to perform a given task or tasks. An
advantage of microprocessors is that they make possible the performance of different
logic functions, depending on the program instructions that are stored. A disadvantage of
microprocessors is that normally they operate in a sequential mode, which may be too
slow for some applications. In these cases specifically designed logic circuits are used.
Questions:
1.
Discuss the types of logical components.
2.
Discuss various digital logic gates.
Source: http://library.thinkquest.org/C006657/electronics/digital_logic_circuit.htm
2.3 Summary
Logic gates or gates are the basic building blocks of digital circuitry
Boolean variables, i.e. variables that can have only one of two states (0/1, low/high,
false/true).
29
Notes
The NOT gate is also called as an inverter as it changes the input to its opposite.
The AND Gate: It takes in two or more inputs and produce only one output
The OR gate produces an output of logic 1 state even if any of its inputs is in logic 1 state
and also produces an output of logic 0 state if any of its inputs is in logic 0 state.
The NAND gate is a universal gate. NAND has the ability to perform three basic logic
functions such as AND, OR and NOT. NAND gate is a combination of an AND gate and a
NOT gate.
NOR means NOT OR. That means, NOR gate is a combination of an OR gate and a NOT
gate.
An X-OR gate is a two input, one output logic circuit. X-OR gate assumes logic 1 state when
any of its two inputs assumes a logic 1 state.
An X-NOR gate is a combination of an X-OR gate and a NOT gate. The X-NOR gate is also
a two input, one output concept
The buffer is a single-input device which has a gain of 1, mirroring the input at the output.
Open-collector or open-drain outputs do not source current, they can only sink current.
A tri-state buffer is a useful device that allows us to control when current passes through
the device, and when it doesnt.
2.4 Keywords
AND Gate: It takes in two or more inputs and produce only one output.
Boolean variables : These variables that can have only one of two states (0/1, low/high, false/
true).
Buffer: It is a single-input device which has a gain of 1, mirroring the input at the output.
Gates: They are the basic building blocks of digital circuitry.
NAND gate: It is a universal gate. NAND has the ability to perform three basic logic functions
such as AND, OR and NOT. NAND gate is a combination of an AND gate and a NOT gate.
NOR gate: It means NOT OR. That means, NOR gate is a combination of an OR gate and a NOT
gate.
NOT gate: It is also called as an inverter as it changes the input to its opposite.
OR gate: It produces an output of logic 1 state even if any of its inputs is in logic 1 state and also
produces an output of logic 0 state if any of its inputs is in logic 0 state.
X-NOR gate: It is a combination of an X-OR gate and a NOT gate. The X-NOR gate is also a two
input, one output concept.
X-OR gate: It is a two input, one output logic circuit. X-OR gate assumes logic 1 state when any
of its two inputs assumes a logic 1 state.
30
1.
What are logic gates?
2.
Explain the types of logic gates with suitable examples.
3.
Differentiate between basic and universal gates.
Unit 2: Logic Gates
Notes
4.
What is a buffer?
5.
Explain open drain concept.
6.
What is the use of tri-state gate?
7.
What do you mean by high impedance state?
8.
Explain tri-state gate control.
9.
How do we use Not gate as double invertor?
10.
Explain the gate fan out example.

1.
0,1
2.
NOT
3.
OR
4.
OR, NOT
5.
X-OR
6.
X-OR, NOT
7.
Single
8.
Buffer
9.
True
10.
False
11.
False
12.
False
13.
True
14.
True
15.
True
Books
Anil K. Maini, Digital Electronics: Principles, Devices and Applications, John Wiley &
Sons
J. Stanley Warford, Jones & Bartlett Learning, Computer Systems, 4th Edition
Online links
ftp://ftp.powerfast.net/pub/manuales/electronic/Engineering%20%20Fundamentals%20of%20Digital%20Electronics.pdf
http://www.circuitstoday.com/logic-gates#XNOR
http://www.colorado.edu/physics/phys3330/phys3330_sp12/phys3330_sp12/
Lab_Manual_files/Exp_9_Spring12_re.pdf
http://www.hardwaresecrets.com/article/Introduction-to-Logic-Gates/237/9
31
Notes
Unit 3: Boolean Algebra

CONTENTS
Objectives
Introduction
3.1
3.2
Boolean Algebra
3.1.1
Boolean Arithmetic
3.1.2
Boolean Algebraic Identities
3.1.3
Boolean Algebraic Properties
3.1.4
Translating Truth Tables into Boolean Expressions
3.1.5
Boolean Rules for Simplification
Boolean Theorems
3.2.1
3.3
Multivariable Theorems
De Morgans Theorems
3.3.1
Implications of De Morgans Theorems
3.4
Summary
3.5
Keywords
3.6
Review Questions
3.7
Further Readings
Objectives
Discuss Boolean algebra
Explain the concept of Boolean theorems
Elaborate upon the De Morgan's theorem
Introduction
Have you ever wondered how a computer can do something like balance a check book, or play
chess, or spell-check a document? These are things that, just a few decades ago, only humans
could do. Now computers do them with apparent ease. How can a chip made up of silicon and
wires do something that seems like it requires human thought? If you want to understand the
answer to this question down at the very core, the first thing you need to understand is something
called Boolean logic. Boolean logic, allows quite a few unexpected things to be mapped into bits
and bytes. The Karnaugh map or K-map is a method to simplify Boolean algebra expressions.
Maurice Karnaugh introduced it in 1953 as a refinement of Edward Veitchs 1952 Veitch diagram.
3.1 Boolean Algebra

It is the branch of mathematics that includes methods for manipulating logical variables and
logical expressions. It is named after George Boole, a mid-nineteenth century mathematician
32
and philosopher who was among the first to try to formalize what we call logic and reasoning.
In the mid-twentieth century, an electrical engineer and mathematician named Claude Shannon
applied Booles ideas for manipulating logical expressions to the analysis of what are now
called digital circuits, the foundation of digital electronic devices. The fact that the two distinct
logical values, T and F, are also represented 1 and 0 should hint that Boolean Algebra has an
application in binary things, a fundamental feature of modern digital electronic devices.
3.1.1
Notes
Boolean Arithmetic
Arithmetic operations are possible on binary numbers just as they are on decimal numbers. In
fact the procedures are quite similar in both systems. Let us know see the four basic operations
namely addition, subtraction, multiplication and division on binary numbers 0 and 1.
Binary Addition
It forms the base for binary subtraction, multiplication, division. There four rules of the binary
addition. The complement of A denoted as A-not or A-bar. Sometimes a prime symbol
is used to represent complementation.
Figure 3.1 : Rules of Addition
Source: http://www.allaboutcircuits.com/vol_4/chpt_7/2.html
Notes In fourth case, a binary addition is creating a sum of (1+1=10) i.e. 0 is the sum and 1
is a carry over value.
33
Notes
Example:
Binary Subtraction
Subtraction and Borrow are the words used very frequently for the binary subtraction. There
four rules of the binary Subtraction.
Figure 3.2 : Rules of Subtraction
Source: http://www.tutorialspoint.com/computer_logical_organization/binary_arithmetic.htm
Example:
Binary Multiplication
Binary multiplication is similar to decimal multiplication and much simpler too as it includes
only 0s and 1s. There four rules of the binary multiplication.
Figure 3.3 : Rules of Multiplication
34
Notes
Example:
Binary Division
Binary division is similar to decimal division. It is called as the long division procedure.
Example:
Complement
Other than the four basic operations Boolean algebra also supports complement of a variable i.e.
the opposite of its value. Boolean algebra uses capital alphabetical letters to denote variables.
Example:
Figure 3.4 : Complement
Complement of A is read as A-not or A-bar. We can also use a prime symbol is used to represent
complementation.
35
Notes
3.1.2
Boolean Algebraic Identities
An identity is a statement true for all possible values of its variable or variables. Boolean
algebra has its own unique identities based on the bivalent states of Boolean variables.
Boolean Addition
X+0 = X
X+1 = 1
X+X = X
X+ X
= 1
Boolean Multiplication
X. 0 = 0
X. 1 = X
X.X = X
X. X
3.1.3
= 0
Boolean Algebraic Properties
Laws or rules for Boolean Algebra expressions have been invented to help reduce the number of
logic gates needed to perform a particular logic operation resulting in a list of functions or
theorems known commonly as the Laws of Boolean.
Additive Laws
Commutative Law: X + Y = Y + X
Distributive Law: X + (Y + Z) = (X + Y) + Z
Multiplicative Laws
Commutative Law: X .Y = Y.X
Distributive Law: X.(Y.Z) = (X.Y).Z
3.1.4
Translating Truth Tables into Boolean Expressions
A truth table is a chart of 1s and 0s arranged to indicate the results (or outputs) of all possible
inputs. The list of all possible inputs are arranged in columns on the left and the resulting
outputs are listed in columns on the right. There are 2n possible states (or combination of inputs).
Table 3.1: Truth Table
36
Notes
Note If the number of inputs are n, then the truth table will have 2n rows.
There are two basic ways to convert truth tables into Boolean expressions:
Sum of Products (SOP)

To convert a truth table to a SOP expression, follow the steps below:
First, list the binary values of the input variables for which the output is 1.
Next, convert each binary value to the corresponding product term by replacing each 1
with the corresponding variable and each 0 with the corresponding variable complement.
Example:
1010 A B C D
If you substitute, you can see that the product term is 1:

ABCD = 1.0.1.0 = 1.1.1.1 = 1
Product of Sum (POS)

To convert a truth table to a POS expression, follow the steps below:
First, list the binary values for which the output is 0.
Next, convert each binary value to the corresponding sum term by replacing each 1 with
the corresponding variable complement and each 0 with the corresponding variable.
Example:
1001 A + B + C + D
If you substitute, you can see that the sum term is 0:

A+ B+C +D = 1 +0+0+ 1
= 0+0+0+0=0
3.1.5
Boolean Rules for Simplification
Boolean algebra is used to simplify logic circuits. Applying certain algebraic rules to a Boolean
equation resulting from a truth table, we will get a simpler equation.
Table 3.2: Boolean Identities
Contd...
37
Notes
Source: http://homepages.ius.edu/rwisman/C251/html/chapter11.htm
Self Assessment
Fill in the blanks:
1.
........................ is the branch of mathematics that includes methods for manipulating logical
variables and logical expressions.
2.
1 + 1 = ........................ in binary logic.
3.
0-1 gives ........................ as borrow value.
4.
An ........................ is a statement true for all possible values of its variable or variables.
5.
There are ........................ possible states in a truth table.
3.2 Boolean Theorems

Like Boolean identities, Boolean theorems also help us to simplify logic expressions and logic
circuits. The following figure shows seven single variable theorems.
Figure 3.5: Boolean Theorems
Source: http://www.ee.usyd.edu.au/tutorials/digital_tutorial/chapter4/4_4.html
38
Theorem 1 says that any input ANDed with 0 = 0, since both inputs in an AND gate must be 1
for the result to be 1.
Example:
Notes
1%0=0
0%0=0
Theorem 2 says that any input ANDed with 1 = the original input.
Example:
1%1=1
0%1=0
Theorem 3 says that any input ANDed with itself = itself.

Example:
1%1=1
0%0=0
Theorem 4 says that any input ANDed with the opposite of that input will always be zero.
Example:
1%0=0
0%1=0
Theorem 5 says that any input ORed with 0 = the original input.
Example:
1+0=1
0+0=0
Theorem 6 says that any input ORed with 1 = 1.

Example:
1+1=1
0+1=1
Theorem 7 says that any input ORed with itself = itself.

Example:
1+1=1
0+0=0
3.2.1
Multivariable Theorems
Just like single variable theorems, we have some multi variable theorems to work upon and
make expressions easier and simpler. They are as follows:
1.
x + y = y + x (commutative law)
2.
x * y = y * x (commutative law)
3.
x+ (y+z) = (x+y) +z = x+y+z (associative law)
4.
x (yz) = (xy) z = xyz (associative law)
5.
x (y+z) = xy + xz
39
Notes
6.
(w+x)(y+z) = wy + xy + wz + x
7.
x + xy = x
8.
x + xy = x + y
Proof of theorem 14:

x + xy = x (1+y)
= x * 1 [using theorem (6)]
= x [using theorem (2)]
Task Prove absorption law using the other laws including idempotent , inverse, identity
and the distributive laws.
Self Assessment
6.
Any input ANDed with 0 = 0.
7.
Any input ORed with 0 = 0.
8.
The commutative law over addition states that x + y = y + x.
9.
The associative law over addition states that x (yz) = (xy) z = xyz.
10.
x + xy = x+y is a correct identity.
3.3 De Morgans Theorems

Two extremely important logic laws are called De Morgans Theorems. They are stated as
follows:
De Morgans theorem makes it easy to transform POS to SOP or SOP to POS forms. They are also
useful in the implementation of the basic gate operations with alternative gates, particularly
with NAND and NOR gates which are readily available in IC form.
Steps to perform De Morgans law are given below:
40
Complement the whole expression on which De Morgans law needs to be applied
Change all ANDs to ORs and all ORs to ANDs
Then, Complement all the terms in the expression.
Proof of the De Morgans theorems can be given using truth tables as given below:
Notes
Here 1 represents true, 0 represents false.

Theorem 1: ( p q ) ( p) ( q )
Table 3.3: Truth Table to Prove First De Morgans Theorem
Source: http://en.wikipedia.org/wiki/De_Morgan%27s_laws
Since the values in the 4th and last columns are the same for all rows (which cover all possible
truth value assignments to the variables), we can conclude that the two expressions are logically
equivalent.
Theorem 2: ( p q ) ( p) ( q )
Table 3.4: Truth Table to Prove Second De Morgans Theorem
Source: http://en.wikipedia.org/wiki/De_Morgan%27s_laws
Since the values in the 4th and last columns are the same for all rows (which cover all possible
truth value assignments to the variables), we can conclude that the two expressions are logically
equivalent.
Example:
Caution It is advisable to open the longest bar first while solving a Boolean expression and
never open more than one bar in a single step.
41
Notes
3.3.1
Implications of De Morgans Theorems
Inverting all inputs to a gate reverses that gates essential function from AND to OR, or vice
versa, and also inverts the output. So, an OR gate with all inputs inverted (a Negative-OR gate)
behaves the same as a NAND gate, and an AND gate with all inputs inverted (a Negative-AND
gate) behaves the same as a NOR gate. De Morgans theorems state the same equivalence in
backward form: that inverting the output of any gate results in the same function as the
opposite type of gate (AND vs. OR) with inverted inputs:
Figure 3.6: Equivalent Circuits Implied by Theorems 1 and 2
Source: http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/demorgan.html#c2
Did u know? De Morgans Theorem was given by Augustus De Morgan who was a
mathematician and contemporary of George Boole and John Venn.
Self Assessment
Fill in the blanks:
11.
........................ is the first De Morgans theorem.
12.
........................ is the second De Morgans theorem.
13.
........................ the whole expression on which De Morgans law needs to be applied is the
first step to solve an equation using De Morgans theorems.
14.
Change all ........................ to ........................ and all ........................ to ........................ is the

second step to apply De Morgans theorems.
15.
AB + A + B = ........................ using De Morgans theorems.
Case Study
History of Boolean Algebra
oolean Algebra is a two valued algebra, applied earlier to statements and sets
which were either true or false and now to switches which are either closed or
open, i.e., ON or Off respectively. George Boole developed this branch of
mathematics in his book. An Investigation of the Laws Of Thought now known as
symbolic logic. This provided the basic logic for operations on binary numbers (1 and 0).
Contd...
42
Since modern business machines are based on binary system, the symbolic logic of George
Boole was found extremely useful and is being considered as the base of Modern
Mathematics.
Notes
In the 19th century Symbolic Logic was invented, it was used much later when in the 20th
century. Claude Shannon discovered the similarity of structure between it and telephone
switching circuits. His paper A Symbolic Analysis of Relay and Switching Circuits
made an important contribution to the use of Boolean algebra towards the designing of
modern Business Machine based on Binary Number.
Figure 1: Truth Tables
Figure 2: Logic Gates
Figure 3: De Morgan Equivalents
Figure 4: Venn Diagrams
Structure:
Basic Properties
Derived Properties
Boolean Functions
Canonical Form
Boolean Addition
Boolean Multiplication
Electrical Switching System
Circuits with Composite Operations
Contd...
43
Notes
There are three basic operations in Boolean algebra AND, OR and NOT. These are
symbolized by ), U and {} respectively in case of the theory of sets. In this chapter the
more common symbolic plus+, dot . and prime ( 2 ) would be used for the three operations
respectively.
Questions:
1.
Discuss the history of Boolean Algebra.
2.
Discuss basic operation of boolean algebra.
Source: http://sumon3get.hubpages.com/hub/Basic-Concept-And-History-Of-Boolean-Algebra#
3.4 Summary
44
Boolean Algebra is the branch of mathematics that includes methods for manipulating
logical variables and logical expressions.
Arithmetic operations are possible on binary numbers just as they are on decimal numbers.
We can perform addition, subtraction, multiplication, division and complement on binary

numbers.
Binary division is similar to decimal division. It is called as the long division procedure.
An identity is a statement true for all possible values of its variable or variables. Boolean
algebra has its own unique identities based on the bivalent states of Boolean variables.
Laws or rules for Boolean Algebra expressions have been invented to help reduce the
number of logic gates needed to perform a particular logic operation resulting in a list of
functions or theorems known commonly as the Laws of Boolean.
A truth table is a chart of 1s and 0s arranged to indicate the results (or outputs) of all
possible inputs. There are 2n possible states (or combination of inputs).
Boolean Rules and Boolean Theorems are used for Simplification.
Just like single variable theorems, we have some multi variable theorems to work upon
and make expressions easier and simpler.
( p q ) ( p) ( q ) and ( p q ) ( p) ( q ) are called De Morgans Laws.
Notes
3.5 Keywords
Binary: Having only two possible values.
Boolean Algebra: It is the branch of mathematics that includes methods for manipulating logical
variables and logical expressions.
Boolean Variables: These variables that can have only one of two states (0/1, low/high, false/
true).
Gates: They are the basic building blocks of digital circuitry.
Identity: It is a statement true for all possible values of its variable or variables.
Laws or Rules for Boolean Algebra: They were invented to help reduce the number of logic gates
needed to perform a particular logic operation.
Multi Variable: Has more than one variable.
Truth Table: It is a chart of 1s and 0s arranged to indicate the results (or outputs) of all possible
inputs.
Variable: It changes the value often.

1.
What is Boolean algebra?
2.
Give all the rules for binary addition with examples.
3.
Explain the difference and borrow in binary subtraction.
4.
Multiply (00110011) and (11001110).
5.
Divide (10111001) by (101) by long division method.
6.
What are the various Boolean identities used to simplify Boolean expressions?
7.
Find the complement of (11001111).
8.
Give the steps to convert a truth table to Boolean Expression.
9.
List all Boolean theorems.
10.
State and prove De Morgans Laws.
45
Notes

1.
Boolean Algebra
2.
Zero
3.
One
4.
Identity
5.
2n
6.
True
7.
False
8.
True
9.
False
10.
False
11.
(x+y)=x.y
12.
(x.y)=x+y
13.
Complement
14.
AND, OR , OR , AND
15.
AB + A + B
= AB + (AB) [since accordingly (AB) = A + B which is a Demorgans law]
= 1 [as in Boolean algebra A+A=1]
Books
Bradford Henry Arnold, Logic and Boolean Algebra

Givant, Steven, Halmos, Paul, Introduction to Boolean Algebras
J. Crowe, Introduction to Digital Electronics, Barrie Hayes-Gill
Morris Mano, Digital-design
Online links
http://homepages.ius.edu/rwisman/C251/html/chapter11.htm
http://www.allaboutcircuits.com/vol_4/chpt_7/8.html
http://www.electrical4u.com/de-morgans-theorem-and-demorgans-laws/
http://www.tutorialspoint.com/computer_logical_organization/
binary_arithmetic.htm
46
Unit 4: Minimization of Boolean Algebra
Notes
CONTENTS
Objectives
Introduction
4.1
Minterms and Maxterms
4.2
Sum-of-Products and Product-of-Sums Forms of Logic Expressions
4.3
4.2.1
Sum-of-Products (SOP)
4.2.2
Product-of-Sums (POS)
Karnaugh Maps
4.3.1
Karnaugh Map Format
4.3.2
Looping
4.4
Summary
4.5
Keywords
4.6
Review Questions
4.7
Further Readings
Objectives
Discuss Boolean algebra
Explain the concept of Boolean theorems
Elaborate upon the De Morgan's theorem
Introduction
Boolean expression is an expression in a programming language that produces a Boolean value
when evaluated, i.e. one of true or false. It can be written in two ways Sum of Product (SOP) and
Product of Sum (POS).
A sum of products (SOP) expression contains only OR (sum) operations at the outermost level
where each term that is summed must be a product of literals.
Example: f(x,y,z) = y + xyz + xz
A product of sums (POS) expression contains only AND (product) operations at the outermost
level where each term must be a sum of literals.
Example: f(x,y,z) = y (x + y + z) (x + z)
A K-map shows the value of a function for every combination of input values just like a truth
table, but a K-map spatially arranges the values so it is easy to find common terms that can be
factored out.
47
Notes
Figure 4.1: 2 Variable K-maps
Note the sequence of numbers across the top of the map. It is not in binary sequence which
would be 00, 01, 10, 11. It is 00, 01, 11 10, which is Gray code sequence. Gray code sequence only
changes one binary bit as we go from one number to the next in the sequence, unlike binary.
That means that adjacent cells will only vary by one bit, or Boolean variable. This is what we
need to organize the outputs of a logic function so that we may view commonality. Moreover,
the column and row headings must be in Gray code order, or the map will not work as a
Karnaugh map. Cells sharing common Boolean variables would no longer be adjacent, nor
show visual patterns. Adjacent cells vary by only one bit because a Gray code sequence varies by
only one bit.
4.1 Minterms and Maxterms

A literal is a Boolean variable or its complement. A Boolean expression can be written as a
combination of minterms or maxterms. A minterm is a special product of literals, in which each
input variable appears exactly once. A function with n variables has 2n minterms (since each
variable can appear complemented or not). A three-variable function, such as f(x,y,z), has 23 = 8
minterms.
xyz
xyz
xyz
xyz
xyz
xyz
xyz
xyz
Each minterm is true for exactly one combination of inputs:
Every function can be written as a sum of minterms, which is a special kind of sum of products
form
48
The sum of minterms form for any function is unique
If you have a truth table for a function, you can write a sum of minterms expression just by
picking out the rows of the table where the function output is 1.
Table 4.1: Minterms
Notes
Source: http://www.cs.uiuc.edu/class/sp08/cs231/lectures/04-Kmap.pdf
In order to place a minterm in a K-map, there are some generalized steps to be followed:
Identify the minterm (product term) term to be mapped.
Write the corresponding binary numeric value.
Use binary value as an address to place a 1 in the K-map.
Repeat steps for other minterms (P-terms within a Sum-Of-Products).

Figure 4.2: Place a Minterm in a K-map
To write Sum-Of-Products reduced Boolean equation from a K-map, there are a number of steps
to be followed:
Form largest groups of 1s possible covering all minterms.
Note Groups must be a power of 2.

Write binary numeric value for groups.
Convert binary value to a product term.
Repeat steps for other groups. Each group yields a p-terms within a Sum-Of-Products.
A maxterm on the other hand is a sum of literals, in which each input variable appears exactly
once. A function with n variables has 2n maxterms. The maxterms for a three-variable function
f(x,y,z).
x + y + z
x + y + z
49
Notes
x + y + z
x+ y + z
x + y + z
x + y + z
x + y + z
x+y+z
Each maxterm is false for exactly one combination of inputs:
Every function can be written as a unique product of maxterms. If you have a truth table for a
function, you can write a product of maxterms expression by picking out the rows of the table
where the function output is 0.
Table 4.2: Maxterms
Source: http://www.cs.uiuc.edu/class/sp08/cs231/lectures/04-Kmap.pdf
The steps to follow to place a maxterm in the K-map is:

Identify the Sum term to be mapped.
Write corresponding binary numeric value.
Form the complement
Use the complement as an address to place a 0 in the K-map
Repeat for other maxterms (Sum terms within Product-of-Sums expression).

Figure 4.3: Place a Maxterm in a K-map
50
The procedure for writing the Product-Of-Sums Boolean reduction for a K-map is as follows:
Notes
Form largest groups of 0s possible, covering all maxterms.
Note Groups must be a power of 2.

Write the corresponding binary numeric value for group.
Complement binary numeric value for group.
Convert complement value to a sum-term.
Repeat steps for other groups. Each group yields a sum-term within a Product-Of-Sums
result.
Any minterm mi is the complement of the corresponding maxterm Mi.
Example: m4 = M4 because (xyz) = x + y + z
Task Write the minterms and maxterms for a three-variable expression.
Self Assessment
Fill in the blanks:
1.
Boolean expression is an expression in a programming language that produces a

........................ or ........................ value when evaluated.
2.
A ........................ expression contains only OR operations at the outermost level where

each term that is summed must be a product of literals.
3.
A ........................ expression contains only AND (product) operations at the outermost

level where each term must be a sum of literals.
4.
The column and row headings must be in ........................ order, or the map will not work
as a Karnaugh map.
5.
A function with n variables has ........................ minterms and ........................ maxterms.
4.2 Sum-of-Products and Product-of-Sums Forms of Logic

Expressions
We have two ways to represent Boolean Functions. Let us discuss them both in detail.
51
Notes
4.2.1
Sum-of-Products (SOP)
An SOP expression is one in which two or more product terms are summed by Boolean addition.
Example:
F(x,y,z) = xyz
The sum of one product.
G(x,y,z) = xyz + xyz The sum of two products
Caution In an SOP form, a single overbar cannot extend over more than one variable;
however, more than one variable in a term can have an overbar.
This is correct: A B C
This is incorrect: ABC
4.2.2 Product-of-Sums (POS)

When two or more sum terms are multiplied, the result expression is a product-of-sums (POS).
Example:
F(x,y,z) = x+y+z
The sum of one product.
G(x,y,z) = ( x+y+z) (x+y+z) The sum of two products
Caution In a POS form, a single overbar cannot extend over more than one variable;
however, more than one variable in a term can have an overbar.
This is correct
A+ B+C
This is incorrect
A + B+C
Example:
Plot the logical expression F (A, B, C, D) = ABCD + ABCD + ABC + AB on a four-variable
Karnaugh map. Obtain the simplified expression.
To form a Karnaugh map for a logical expression, the function is to be expanded to either
canonical SOP form or canonical POS form. The canonical SOP form for the above expression can
be obtained as follows.
F (A, B, C, D) = ABCD + ABCD + ABC + AB
= ABCD + ABCD + ABC (D + D) + AB (C + C) (D + D)
= ABCD + ABCD + ABCD + ABCD + (ABC + ABC) (D + D)
= ABCD + ABCD + ABCD + ABCD + ABCD + ABCD +ABCD + ABCD
= ABCD + ABCD + ABCD + ABCD+ ABCD + ABCD + ABCD
= (8, 10, 11, 12, 13, 14, 15)
52
Notes
F = AB + AC + AD
Example: Simplify the following function to both SOP &POS forms: F(A, B, C, D) =
S m(0, 1, 2, 5, 8, 9, 10)
1.
Place 1s in the squares for minterms (0, 1, 2, 5, 8, 9, 10)
2.
Place 0s in the remaining squares (3, 4, 6, 7, 11, 12, 13, 14, 15)
3.
Group the adjacent 1s into the largest 2n groupings. According to the map shown below,
we obtain a minimum SOP for the function:
F = BD + BC + ACD
4.
Group the adjacent 0 squares into the largest 2n groupings possible.
5.
According to the map shown below, we obtain the simplified complement function:
F = AB + CD +BD
6.
Apply DeMorgans theorem (by taking the dual and complementing each literal) to obtain
the simplified function in a POS form:
F = (F) = (A + B)(C + D)(B + D)
Figure 4.4: 2 variable K map
Source: http://www.cecs.csulb.edu/~rallison/pdf/Simplification_of_Boolean_Functions.pdf
The SOP expression is implemented with a group of AND gates that feed an OR gates. The POS
expression is implemented with a group of OR gates that feed an AND gate. This configuration
pattern for both a SOP and a POS is the general form by which any Boolean function is
implemented when expressed in standard form.
Note It is a two-level implementation as shown below. But that it is assumed that the
complemented versions of the literals are available.
53
Notes
Figure 4.5: Circuit Diagram
Source: http://www.cecs.csulb.edu/~rallison/pdf/Simplification_of_Boolean_Functions.pdf
Self Assessment
6.
A maxterm is a special product of literals, in which each input variable appears exactly
once.
7.
A minterm on the other hand is a sum of literals, in which each input variable appears
exactly once.
8.
In a SOP form, a single overbar cannot extend over more than one variable.
9.
In a POS form, a single overbar can extend over more than one variable.
10.
In a POS and SOP form more than one variable in a term can have an overbar.
4.3 Karnaugh Maps

Boolean functions use basic laws and theorems for simplification. But at times this procedure is
awkward because it lacks specific rules to predict each succeeding step in the minimization
process. The map method provides a simple straightforward procedure for minimizing Boolean
functions.. They are referred to as Karnaugh maps (K-maps). The map is a diagram made up of
squares. Each square represents one minterm. Recall that any Boolean function can be expressed
as the sum of minterms. The map represents a visual diagram of all possible ways a function
may be expressed in standard form. By recognizing various patterns, one can derive alternative
algebraic expressions for the same function, from which he can select the simplest one. We shall
assume that the simplest expression is any one in a SOP or POS that has a minimum number of
literals.
Did u know? K-maps were developed by an electrical engineer, Maurice Karnaugh, at Bell
Labs.
Table 4.3: Sample Truth Table
Source: http://zebu.uoregon.edu/~rayfrey/432/notes2.pdf
54
Table 4.4: K map for the Truth Table of Figure
Notes
4.3.1 Karnaugh Map Format

There are several methods for simplification of Boolean logic expressions. The process is usually
called logic minimization, and the goal is to form a result which is efficient. Two methods we
will discuss are algebraic minimization and Karnaugh maps. For very complicated problems
the former method can be done using special software analysis programs. Karnaugh maps are
also limited to problems with up to 4 binary inputs.
Example: The table below gives an arbitrary truth table involving 2 logic inputs.
Table 4.5: Truth Table
There are two overall strategies:

1.
Write down an expression directly from the truth table. Use Boolean algebra, if desired, to
simplify.
2.
Use Karnaugh mapping. This is only applicable if there are _ 4 inputs. In our example
above, we can use two different ways of writing down a result directly from the truth
table. We can write down all TRUE terms and OR the result. This gives:
Q = AB+ AB + AB
While correct, without further simplification this expression would involve 3 2-input AND
gates, 2 inverters, and 1 3-input OR gate.
Alternatively, one can write down an expression for all of the FALSE states of the truth table.
This is simpler in this case:
Q = AB Q = AB = A + B
where the last step results from Eqn. 3. Presumably, the two expressions can be found to be
equivalent with some algebra. Certainly, the 2nd is simpler, and involves only an inverter and
one 2-input OR gate.
Finally, one can try a K-map solution. The first step is to write out the truth table in the form
below, with the input states the headings of rows and columns of a table, and the corresponding
outputs within, as shown below:
55
Notes
Table 4.6: K-map for the above Table
The steps/rules are as follows:

1.
Form the 2-dimensional table as above. Combine 2 inputs in a gray code way.
2.
Form groups of 1s and circle them; the groups are rectangular and must have sides of
length 2n x 2m, where n and m are integers 0; 1; 2; 3. The groups can overlap.
3.
Write down an expression of the inputs for each group.
4.
OR together these expressions. Thats it.
5.
Groups can wrap across table edges.
6.
As before, one can alternatively form groups of 0s to give a solution for Q.
7.
The bigger the groups one can form, the better (simpler) the result.
8.
There are usually many alternative solutions, all equivalent, some better than others
depending upon what one is trying to optimize.
Here is one way of doing it:

The two groups we have drawn are A and B. So the solution (as before) is:
Q = A + B
4.3.2
Looping
The truth table has its 1s and 0s written into the Karnaugh map in the corresponding locations,
then each location in the Karnaugh map represents one minterm. Then two, four or eight
adjacent squares that contain 1s are looped to create a simplified boolean expression (note the
number of adjacent squares in a power of 2). The expression for the loop will eliminate the
variable(s) that appear in both normal and complemented form.
Looping Groups of Two (Pairs)

We can create a group of two elements from the K map to simplify an expression. Let us show
this through an example:
x y+x y+x y
Here is the Karnaugh map with the appropriate 1s placed in cells and then grouped:
Figure 4.6 : Creating Group of 2
Source: http://www.gitam.edu/eresource/comp/gvr/4.7.htm
56
The only group that we can make that has the upper right cell in it is the pair in the second
column. And the only group that contains the lower left cell is the pair in the second row. Note
that we can use the lower right cell in both groups. Once you have grouped cells, you can
determine the minimized logical expression. Each group reduces to one conjunction in the
minimized expression. A group reduces to a conjunction containing just those literals that
remain the same for every cell in the group. For example, the group in the above Karnaugh map
that contains the two cells in the second column reduces to the expression not x because both
of its members have a not x in their DNF conjunctions. The group consisting of both cells in
the bottom row reduces to not y. Thus the minimized logical expression is:
Notes
x+y
Looping Groups of Four (Quads)

Groupings can also be formed from four adjacent minterms in which case two redundant variables
can be discarded. In fact, any group of 2n adjacent minterms can be gathered together, where n is
a positive integer. For example, 21 = two minterms, 22 = four minterms, 23 = eight minterms, and
so forth.
Figure 4.7: Some Examples to Show Grouping of Quad
Source: http://www.benchmark-companies.com/Electronics/ELT147_Digital_Devices_I/ELT147_Handouts/
ELT147HO06%20Karnaugh%20Maps.pdf
Looping Groups of Eight (Octets)

Eight cells show adjacency or wrapping adjacency. It minimizes the Boolean expression as eight
terms become one term and the remaining term have three variables removed. There will be
only one variable common in four variable map.
57
Notes
Example:
F = ABD+BD+C
Figure 4.8: K map with Grouping of 2, 4 and 8
Source: http://www.ece.ualberta.ca/~spramani/courses/ECE210/Fall12/LEC10_K-maps_1.pdf
Complete Simplification Process

As we saw in the discussion above, a variable that appears in both complemented and
uncomplemented form within a loop is eliminated from the expression using K-map
simplification. Variables that are the same for all squares of the loop must appear in the final
expression. A larger loop of 1s eliminates more variables. To be exact, a loop of two eliminates
one variable, a loop of four eliminates two, and a loop of eight eliminates three. This principle
will now be used to obtain a simplified logic expression from a K-map that contains any
combination of 1s and 0s.
The set of steps to be followed in order to simplify a Boolean expression with K-maps is given
below:
1.
Construct a label for the K-Map. Place 1s in cells corresponding to the 1s in the truth table.
Place 0s in the other cells.
2.
Identify and group all isolated 1s. Isolated 1s are ones that cannot be grouped with any
other one, or can only be grouped with one other adjacent one.
3.
Group any hex.
4.
Group any octet, even if it contains some 1s already grouped but not enclosed in a hex.
5.
Group any quad, even if it contains some 1s already grouped but not enclosed in a hex or
octet.
6.
Group any pair, even if it contains some 1s already grouped but not enclosed in a hex,
octet, or quad. OR together all terms to generate the SOP equation.
Dont Care Conditions

Sometimes a situation arises in which some input variable combinations are not allowed.
BCD code has six invalid combinations: 1010, 1011, 1100, 1101, 1110, and 1111.
Since these un allowed states will never occur in an application involving the BCD code, they
can be treated as dont care terms with respect to their effect on the output. The dont care terms
can be used to advantage on the K-map.
58
Notes
Figure 4.9: Dont Care Terms
Source: www.cs.su.ac.th/~apisake/course/517341/.../08-LogicSimplification.ppt
Without the dont care terms the simplifies expression is Y = ABC + ABCD
Whereas considering the dont care terms, the expression turns out to be Y = A + BCD
Case Study
Press Wiring
n electrical layout is needed for a hydraulic press. The press uses a 24Vdc double
actuated solenoid valve to advance and retract the press. This device has a single
common and two input wires. Putting 24Vdc on one wire will cause the press to
advance, putting 24Vdc on the second wire will cause it to retract. The press is driven by a
large hydraulic pump that requires 220Vac rated at 20A, this should be running as long as
the press is on. The press is outfitted with three push buttons, one is a NC stop button, the
other is a NO manual retract button, and the third is a NO start automatic cycle button. There
are limit switches at the top and bottom of the press travels that must also be connected.
Contd...
59
Notes
The input and output cards were both selected to be 24Vdc so that they may share a single
24Vdc power supply. In this case the solenoid valve was wired directly to the output card,
while the hydraulic pump was connected indirectly using a relay (only the coil is shown
for simplicity). This decision was primarily made because the hydraulic pump requires
more current than any PLC can handle, but a relay would be relatively easy to purchase
and install for that load. All of the input switches are connected to the same supply and to
the inputs.
Questions:
1.
Discuss the working of hydraulic press.
Source: http://engineeronadisk.com/V2/book_PLC/engineeronadisk-12.html
Self Assessment
11.
A Karnaugh map is nothing more than a special form of truth table, useful for reducing
logic functions into minimal Boolean expressions.
12.
A larger loop of 1s eliminates less variables in K maps.
13.
A loop of two eliminates one variable in a K map.
14.
The expressions, A.B = A + B , , are equivalent.
15.
Each 1 entry in a K-map square represents a HIGH for each input truth table condition
that produces a HIGH output.
4.4 Summary
60
Boolean expression is an expression in a programming language that produces a Boolean

value when evaluated, i.e. one of true or false.
A literal is a Boolean variable or its complement.
A sum of products (SOP) expression contains only OR (sum) operations at the outermost
level where each term that is summed must be a product of literals.
A product of sums (POS) expression contains only AND (product) operations at the
outermost level where each term must be a sum of literals.
A minterm is a special product of literals, in which each input variable appears exactly
once.
A maxterm on the other hand is a sum of literals, in which each input variable appears
exactly once.
Any minterm mi is the complement of the corresponding maxterm Mi.
A Karnaugh map is nothing more than a special form of truth table, useful for reducing
logic functions into minimal Boolean expressions.
We group terms to allow further reduction in the boolean expression.
The un allowed states will never occur in an application involving the BCD code, they can
be treated as dont care terms with respect to their effect on the output.
Notes
4.5 Keywords
Karnaugh Map: It is nothing more than a special form of truth table, useful for reducing logic
functions into minimal Boolean expressions.
Literal: It is a Boolean variable or its complement.
Maxterm: It is a sum of literals, in which each input variable appears exactly once.
Minterm: It is a special product of literals, in which each input variable appears exactly once.
Octet: Groups of eight elements.
Pair: Groups of two elements.
POS: It contains only AND (product) operations at the outermost level where each term must
be a sum of literals.
Quad: Groups of four elements.
SOP: It contains only OR (sum) operations at the outermost level where each term that is
summed must be a product of literals.

1.
How can we simplify a Boolean expression?
2.
Give the steps to place a minterm in a K-map.
3.
Give the steps to place a maxterm in a K-map.
4.
Differentiate between minterms and maxterms with examples.
5.
What is SOP?
6.
How is POS different from SOP?
7.
What is the Gray Code format in K map?
8.
Explain looping in K maps.
9.
Explain the simplification steps in K maps.
10.
Why are dont care conditions used in K maps?

1.
True, False
2.
SOP
3.
POS
4.
Gray Code
5.
2n, 2n
6.
False
7.
False
8.
True
9.
False
10.
True
11.
True
12.
False
13.
True
14.
True
15.
True
61
Notes
Books
& Sons
J. Stanley Warford, Computer Systems, 4th Edition, Jones & Bartlett Learning
Online links
http://homepages.ius.edu/rwisman/C251/html/chapter11.htm
http://sandbox.mc.edu/~bennet/cs110/boolalg/simple.html
http://www.ece.ualberta.ca/~spramani/courses/ECE210/Fall12/LEC10_Kmaps_1.pdf
http://www.iit.edu/arc/workshops/pdfs/kmaps.pdf
62
Unit 5: Combinational Circuits
Notes
CONTENTS
Objectives
Introduction
5.1
5.2
5.3
Adder
5.1.1
Half Adder
5.1.2
Full Adder
Subtractor
5.2.1
Half Subtractor
5.2.2
Full Subtractor
Encoder
5.3.1
Binary Encoder
5.3.2
Priority Encoder
5.4
Decoder
5.5
Summary
5.6
Keywords
5.7
Review Questions
5.8
Further Readings
Objectives
Explain the concept of adders
Describe subtractors
Discuss the concept of encoders
Explain decoders
Introduction
Combination Logic Circuits are made up from basic gates (AND, OR, NOT) or universal gates
(NAND, NOR) gates that are combined or connected together to produce more complicated
switching circuits. These logic gates are the building blocks of combinational logic circuits.
An example of a combinational circuit is a decoder, which converts the binary code data present
at its input into a number of different output lines, one at a time producing an equivalent
decimal code at its output. In these circuits the outputs at any instant of time depends on the
inputs present at that instant only. For the design of Combinational digital circuits Basic gates or
universal gates are used. Examples for combinational digital circuits are Half adder, Full adder,
Half subtractor, Full subtractor, Code converter, Decoder, Multiplexer, Demultiplexer, Encoder,
ROM, etc.
63
Notes
Figure 5.1: Combinational Circuits
Source: media.careerlauncher.com.s3.amazonaws.com/gate/material/2.pdf
5.1 Adder
In electronics, an adder is a digital circuit that performs addition of numbers. In many computers
and other kinds of processors, adders are used not only in the arithmetic logic unit but also in
other parts of the processor, where they are used to calculate addresses, table indices, and
similar operations. Although adders can be constructed for many numerical representations,
such as binary-coded decimal or excess-3, the most common adders operate on binary numbers.
In cases where twos complement or ones complement is being used to represent negative
numbers, it is trivial to modify an adder into an addersubtractor. Other signed number
representations require a more complex adder.
We will now discuss the two kinds of adders in detail. : Half Adder and Full Adder.
5.1.1
Half Adder
A half adder is a logical circuit that performs an addition operation on two binary digits. The
half adder produces a sum and a carry value which are both binary digits.
Table 5.1: Truth Table for Half Adder
Figure 5.2: Half Adder
Figure 5.3: Half Adder
Source: http://commons.wikimedia.org/wiki/File:Half_Adder.svg
64
5.1.2
Notes
Full Adder
Full adder circuit adds three bit binary numbers (X,Y,Z) & outputs two nos. of one bit binary
numbers, Sum & Carry.
Table 5.2: Full Adder
Figure 5.4: Full Adder
si = ai bi cin
cout = aibi+ ci(ai bi)
Figure 5.5: Full Adder
Source: http://commons.wikimedia.org/wiki/File:Full_Adder.svg
Full adder can be implemented by using two half adders and an OR gate.
Figure 5.6: Full Adder using two Half Adders
Source: http://verticalhorizons.in/full-adder-in-digital-electronics/
Self Assessment
1.
Adder is an example of combinational digital circuits.
2.
Adder is a digital circuit that performs addition of numbers.
3.
A full adder is a logical circuit that performs an addition operation on two binary digits
and produces a sum and a carry value which are both binary digits.
65
Notes
4.
Half adder circuit adds three bit binary numbers (X,Y,Z) & outputs two nos. of one bit
binary numbers, Sum & Carry.
5.
5.2 Subtractor
These circuits take two binary numbers as input and subtract one binary number input from the
other binary number input. Just like adders, it gives out two outputs, difference and borrows
(carryin the case of Adder).
We will now discuss two kinds of subtractors in detail: Half Subtractor and Full Subtractor.
5.2.1
Half Subtractor
It is a combinational circuit which is used to perform subtraction of two bits. It has two inputs,
X (minuend) and Y (subtrahend) and two outputs Difference and Borrow.
Table 5.3: Truth Table of Half Subtractor
Source: http://en.wikipedia.org/wiki/Subtractor
Figure 5.7: Implementation of Half Subtractor
Source: http://verticalhorizons.in/wp-content/uploads/2011/08/Half_Subtractor_Implementation.bmp
D = AB + AB = A B
Bo = AB
A Half adder can be converted into half subtractor with an additional inverter.
Task Implement Boolean function F = ABC+AC+BC using half adder.
5.2.2
Full Subtractor
It subtracts one bit from the other by taking pervious borrow into account and generates difference
and borrow.
66
Table 5.4: Truth Table for X-Y-Z
Notes
Figure 5.8: Full Subtractor
Source: http://www.knowelectronics.org/full-subtractor/
Task Implement a full subtractor using two half subtractors.
Self Assessment
Fill in the blanks:
6.
........................ Subtractor take two binary numbers as input and subtract one binary number
input from the other binary number input.
7.
........................ is a combinational circuit which is used to perform subtraction of two bits.
8.
A Half adder can be converted into half subtractor with an additional ..............................
9.
........................ subtracts one bit from the other by taking pervious borrow into account and
generates difference and borrow.
10.
The Boolean equation for borrow in full subtractor is ........................ taking the inputs as
X,Y and Z.
5.3 Encoder
It is a device used to change a signal (such as a bitstream) or data into a code. The code may serve
any of a number of purposes such as compressing information for transmission or storage,
67
Notes
encrypting or adding redundancies to the input code, or translating from one code to another. In
digital electronics this would mean that a decoder is a multiple-input, multiple-output logic
circuit (2n-n).
5.3.1
Binary Encoder
An Encoder has 2n number of inputs, one of which is in the high state or active, and an n-bit code
is generated upon which of the inputs is excited. An encoder is a digital function that produces
a reverse operation from that of a decoder. An encoder has (2n or less) input lines and n output
lines. The output lines generate the binary code for the input variables. Encoders reduce the
number of bits needed to represent given information.
Did u know? Encoders are used in transmitting information in a digital system.
Figure 5.9: Binary Encoder
Source: jjackson.eng.ua.edu/courses/ece380/lectures/lect22-6.pdf
Table 5.5: Truth Table of a Binary Encoder
Figure 5.10: Circuit Diagram of a Binary Encoder
5.3.2
Priority Encoder
Another useful class of encoders is based on the priority of the input signals. In a priority
encoder, each input has a priority level associated with it. The encoder outputs indicate the
active input that has the highest priority. When an input with a high priority is asserted, the
other lower priority inputs are ignored.
68
Assume that w0 has the lowest priority and w3 has the highest. The output z indicates when none
of the inputs are 1.
Let:
Notes
i 0 = w3w2w1w0
i 1 = w3w2w1
i 2 = w3w2
i 3 = w3
y 0 = i 1 +i 3
y 1 = i 2 +i 3
z = i1+i2 +i3+i4
Table 5.6: Truth Table for a 4 to 2 Priority Encoder
Task Draw the truth table and circuit diagram for an 8-to-3 priority encoder.
Self Assessment
Fill in the blanks:
11.
........................ is a device used to change a signal or data into a code.
12.
........................ is a class of encoders is based on the priority of the input signals.
5.4 Decoder
A decoder is a logic circuit that converts an n bit binary input code into M (2n) output lines such
that each output line will be activated for only one of the possible combinations of inputs. It is
a Combinational circuit that converts binary information from n input lines to a maximum of
2n unique output lines.
For example, 2 4 line Decoder (it is also called one four line decoder). Decoders are available
in two different types of output forms:
Active high output type decoders

They are constructed with AND gates and active low output type of decoders are constructed
with NAND gates.
69
Notes
Table 5.7: Truth Table of Active High Output Type Decoder
Figure 5.11: A 2 4 Active High Output Type Decoder
Figure 5.12: A 2 4 Active High Output Type Decoders
Source: http://www.gitam.edu/eresource/comp/gvr/5.6.htm
Active low output types of decoders

They will give the output low for given input combination and all other outputs are high.
Table 5.8: Truth Table of Active Low Output Type Decoder
70
Figure 5.13: A 2 4 Active Low Output Type Decoder
Notes
Figure 5.14: A 2 4 Active Low Output Type Decoder
3 to 8 line decoder is also called Binary-to-Octal decoder or converter. It is also called 1 of 8

decoder, because only one of the 8 outputs is active at a time.
Figure 5.15: A 3 8 Decoder
Decoders are widely used in the memory system of computer, where they respond to the
address code input from the CPU to activate the memory storage location specified by the
address code. They are also used to convert binary data to a form suitable for displaying on
decimal read outs and to implement combinational circuits, Boolean functions, etc.
Task Design a 4 16 decoder.
71
Notes
Case Study
Combinatorial Game Theory
ombinatorial game theory (CGT) is a branch of applied mathematics and theoretical

computer science that studies sequential games with perfect information that is,
two-player games which have a position in which the players take turns changing
in defined ways or moves to achieve a defined winning condition. CGT does not study
games with imperfect or incomplete information (sometimes called games of chance, like
poker). It restricts itself to games whose position is public to both players, and in which
the set of available moves is also public (perfect information). Combinatorial games
include well-known games like chess, checkers, Go, Arimaa, Hex, and Connect. They also
include one-player combinatorial puzzles, and even no-player automata, like Conways
Game of Life. In CGT, the moves in these games are represented as a game tree. Game
theory in general includes games of chance, games of imperfect knowledge, and games in
which players can move simultaneously, and they tend to represent real-life decision
making situations. CGT has a different emphasis than traditional or economic game
theory, which was initially developed to study games with simple combinatorial structure,
but with elements of chance (although it also considers sequential moves, see extensiveform game). Essentially, CGT contributed new methods for analyzing game trees, for
example using surreal numbers, which are a subclass of all two-player perfect-information
games. The type of games studied by CGT is also of interest in artificial intelligence,
particularly for automated planning and scheduling. In CGT there has been less emphasis
on refining practical search algorithms (like the alpha-beta pruning heuristic included in
most artificial intelligence textbooks today), but more emphasis on descriptive theoretical
results (like measures of game complexity or proofs of optimal solution existence without
necessarily specifying an algorithm see strategy-stealing argument for instance). An
important notion in CGT is that of solved game (which has several flavors), meaning for
example that one can prove that the game of tic-tac-toe results in a draw if both players
play optimally. While this is a trivial result, deriving similar results for games with rich
combinatorial structures is difficult. For instance, in 2007 it was announced that checkers
has been (weakly, but not strongly) solvedoptimal play by both sides also leads to a
drawbut this result was a computer-assisted proof. Other real world games are mostly
too complicated to allow complete analysis today (although the theory has had some
recent successes in analyzing Go endgames). Applying CGT to a position attempts to
determine the optimum sequence of moves for both players until the game ends, and by
doing so discover the optimum move in any position. In practice, this process is tortuously
difficult unless the game is very simple.
History
CGT arose in relation to the theory of impartial games, in which any play available to one
player must be available to the other as well. One very important such game is nim, which
can be solved completely. Nim is an impartial game for two players, and subject to the
normal play condition, which means that a player who cannot move loses. In the 1930s,
the Sprague-Grundy theorem showed that all impartial games are equivalent to heaps in
nim, thus showing that major unifications are possible in games considered at a
combinatorial level (in which detailed strategies matter, not just pay-offs). In the 1960s,
Elwyn R. Berlekamp, John H. Conway and Richard K. Guy jointly introduced the theory of
a partisan game, in which the requirement that a play available to one player be available
to both is relaxed. Their results were published in their book Winning Ways for your
Contd...
72
Mathematical Plays in 1982. However, the first book published on the subject was Conways
On Numbers and Games, also known as ONAG, which introduced the concept of surreal
numbers and the generalization to games. On Numbers and Games was also a fruit of the
collaboration between Berlekamp, Conway, and Guy. Combinatorial games are generally,
by convention, put into a form where one player wins when the other has no moves
remaining. It is easy to convert any finite game with only two possible results into an
equivalent one where this convention applies. One of the most important concepts in the
theory of combinatorial games is that of the sum of two games, which is a game where
each player may choose to move either in one game or the other at any point in the game,
and a player wins when his opponent has no move in either game. This way of combining
games leads to a rich and powerful mathematical structure. John Conway states in ONAG
that the inspiration for the theory of partisan games was based on his observation of the
play in go endgames, which can often be decomposed into sums of simpler endgames
isolated from each other in different parts of the board.
Notes
Examples
The introductory text Winning Ways introduced a large number of games, but the
following were used as motivating examples for the introductory theory:
Blue-Red Hackenbush - At the finite level, this partisan combinatorial game allows
constructions of games whose values are dyadic rational numbers. At the infinite
level, it allows one to construct all real values, as well as many infinite ones which
fall within the class of surreal numbers.
Blue-Red-Green Hackenbush - Allows for additional game values that are not
numbers in the traditional sense, for example, star.
Toads and Frogs - Allows various game values. Unlike most other games, a position
is easily represented by a short string of characters.
Domineering - Various interesting games, such as hot games, appear as positions in

Domineering, because there is sometimes an incentive to move, and sometimes not.
This allows discussion of a games temperature.
Nim - An impartial game. This allows for the construction of the nimbers. (It can
also be seen as a green-only special case of Blue-Red-Green Hackenbush.)
The classic game Go was influential on the early combinatorial game theory, and
Berlekamp and Wolfe subsequently developed an endgame and temperature theory for it
(see references). Armed with this they were able to construct plausible Go endgame
positions from which they could give expert Go players a choice of sides and then defeat
them either way.
Questions:
1.
Discuss the history of Combinatorial Game Theory
2.
Given some examples for the introductory theory.
Source: http://en.wikipedia.org/wiki/Combinatorial_game_theory
Self Assessment
13.
A decoder is a Combinational circuit that converts binary information from n input lines
to a maximum of 2n unique output lines.
73
Notes
14.
Active low output type decoders are constructed with AND gates and active low output
type of decoders are constructed with NAND gates.
15.
Active high output types of decoders will give the output low for given input combination
and all other outputs are high.
5.5 Summary
Adder is an example of combinational digital circuits. It is a digital circuit that performs

addition of numbers.
A half adder is a logical circuit that performs an addition operation on two binary digits.
The half adder produces a sum and a carry value which are both binary digits.
Full adder circuit adds three bit binary numbers (X,Y,Z) & outputs two nos. of one bit
binary numbers, Sum & Carry.
Subtractor take two binary numbers as input and subtract one binary number input from
the other binary number input.
Half Subtractor is a combinational circuit which is used to perform subtraction of two bits.
A Half adder can be converted into half subtractor with an additional inverter.
Full Subtractor subtracts one bit from the other by taking pervious borrow into account
and generates difference and borrow.
Encoder is a device used to change a signal (such as a bitstream) or data into a code.
Binary Encoder is an Encoder has 2n number of inputs, one of which is in the high state or
active, and an n-bit code is generated upon which of the inputs is excited.
In a priority encoder, each input has a priority level associated with it.
A decoder is a logic circuit that converts an n bit binary input code into M (2n) output lines
such that each output line will be activated for only one of the possible combinations of
inputs.
Active high output type decoders are constructed with AND gates and active low output
Active low output types of decoders will give the output low for given input combination
5.6 Keywords
Active High Output Type Decoders: They are constructed with AND gates and active low output
Active Low Output Types of Decoders: It will give the output low for given input combination
Adder: It is a digital circuit that performs addition of numbers.
Decoder: It is a logic circuit that converts an n bit binary input code into M (2n) output lines such
that each output line will be activated for only one of the possible combinations of inputs.
74
Encoder: It is a device used to change a signal (such as a bitstream) or data into a code.
Notes
Full Adder: It adds three bit binary numbers (X,Y,Z) & outputs two nos. of one bit binary
numbers, Sum & Carry.
Full Subtractor: It subtracts one bit from the other by taking pervious borrow into account and
generates difference and borrow.
Half Adder: It is a logical circuit that performs an addition operation on two binary digits.
Half Subtractor: It is a combinational circuit which is used to perform subtraction of two bits.
Priority Encoder: It has a priority given to each input.
Subtractor: It take two binary numbers as input and subtract one binary number input from the
other binary number input.

1.
What is a combinational circuit?
2.
Explain the use of adder.
3.
Give the block diagram of a half adder.
4.
Can a full adder be made from half adder? If yes, how?
5.
What is a subtractor?
6.
Give the truth table of a full subtractor.
7.
Why do we use an encoder?
8.
Explain binary encoders.
9.
What is a decoder?
10.
What are the types of decoder?

1.
True
2.
True
3.
False
4.
False
5.
True
6.
Subtractor
7.
Half Subtractor
8.
Inverter
9.
Full Subtractor
10.
XY+YZ+XZ
11.
Encoder
12.
Priority Encoder
13.
True
14.
False
15.
False
Books
& Sons
75
Notes
H. A. Thurston, The Number System

Ray Ryan, Basic digital electronics: Understanding number systems, Boolean Algebra
& Logic Circuits
Online links
http://verticalhorizons.in/full-adder-in-digital-electronics/
http://www.electronics-tutorials.ws/combination/comb_5.html
http://www.gitam.edu/eresource/comp/gvr/5.6.htm
media.careerlauncher.com.s3.amazonaws.com/gate/material/2.pdf
76
Unit 6: Implementation of Combinational Logic Circuit
Notes
CONTENTS
Objectives
Introduction
6.1
Multiplexers
6.1.1
Synthesis of Logic Functions Using Multiplexers
6.1.2
Multiplexer Synthesis Using Shannons Expansion
6.2
Demultiplexer
6.3
Code Converters
6.4
Comparators
6.5
Summary
6.6
Keywords
6.7
Review Questions
6.8
Further Readings
Objectives
Explain the concept of Multiplexer
Describe Demultiplexer
Discuss code converters
Describe comparators
Introduction
Combinational logic or time-independent logic is a type of digital logic which is implemented
by Boolean circuits, where the output is a pure function of the present input only. It is used in
computer circuits to do Boolean algebra on input signals and on stored data. An arithmetic logic
unit, or ALU, that does mathematical calculations is constructed using combinational logic.
Other circuits used in computers, such as half adders, full adders, half subtractors, full subtractors,
multiplexers, demultiplexers, encoders and decoders are also made by using combinational
logic.
6.1 Multiplexers
A multiplexer or MUX is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which
are used to select which input line to send to the output. A 2n-to-1 multiplexer sends one of
2n input lines to a single output line. A multiplexer has two sets of inputs: 2n data input lines and
n select lines, to pick one of the 2n data inputs. The MUX output is a single bit, which is one of the
2n data inputs.
77
Notes
2-to-1 MUX
Here we have 2 inputs which will be multiplexed and outputted as a single output.
Figure 6.1: 2 1 MUX
Source: gatecomputer.files.wordpress.com/2012/02/chapter-81.pdf
For S = 0, the Boolean expression for the output becomes Y = I0 and for S = 1, the Boolean
expression for the output becomes Y = I1.
Table 6.1: Truth Table for 2 1 MUX
Thus, inputs I0 and I1 are respectively switched to the output for S = 0 and S = 1.
Figure 6.2: 2 1 MUX
4-to-1 MUX
A 4X1 MUX has 4 inputs which will be multiplexed and outputted as a single output.
Figure 6.3: 4 1 MUX
78
Table 6.2: Truth Table for 4 1 MUX
Notes
The input combinations 00,01, 10 and 11 on the select lines respectively switch I0, I1, I2 and I3 to
the output.
8-to-1 MUX
Multiplexers are circuits which select one of many inputs. Assume that we have one-bit inputs.
Suppose we have eight inputs: I0, I1, I2, I3, I4, I5, I6, I7 and we want one of them to be output based
on selection signals. 3 bits of selection signals to decide which input goes to output. Here X is
MSB and Z is LSB.
Figure 6.4: 8 1 MUX
Source: http://class.ece.iastate.edu/arun/CprE281_F05/lectures/f05_week05.pdf
Table 6.3: Truth Table of a 8 1 MUX
Source: http://class.ece.iastate.edu/arun/CprE281_F05/lectures/f05_week05.pdf
The final equation formed with the 8X1 MUX is given below:
F = X Y Z I0 + X Y Z I1 + X Y Z I2 + X Y Z I3 + X Y Z I4 + X Y Z I5 + X Y Z I6 + X Y Z I7
The practical implementation of MUX are in crossbar switches.
79
Notes
Figure 6.5: Practical Application of MUX
Source: http://people.wallawalla.edu/~curt.nelson/engr354/lecture/chapter6.pdf
Task Design an 8X1 MUX using 4X1 MUX.
6.1.1
Synthesis of Logic Functions Using Multiplexers
MUX can be used to synthesize logic functions to create truth table, compress as necessary and
implement. An N variable function can be implemented with one N-1 multiplexer, and (at most)
one inverter.
Figure 6.6: 2 Input Majority Function
Source: www.ece.mcmaster.ca/~shirani/2di4/chapter6.pdf
80
Notes
Figure 6.9: 3 Input XOR function
Figure 6.10: 3 Input XOR function
81
Notes
6.1.2
Multiplexer Synthesis Using Shannons Expansion
Shannons expansion theorem says that, Any Boolean function f(w1, , wn) can be written in the
form:
Shannons expansion can be used multiple times. Multiplexers can be used to implement any
Boolean function based on Shannons expansion.
Self Assessment
Fill in the blanks:
1.
A multiplexer has two sets of inputs: ................. data input lines and .................. select lines.
2.
An N variable function can be implemented with one .......................... multiplexer, and (at
most) one inverter.
3.
MUX can be used to synthesize logic functions to create ..................................
6.2 Demultiplexer
A demultiplexer (DMUX) is a combinational logic circuit with an input line, 2n output lines and
n select lines. It routes the information present on the input line to any of the output lines. The
output line that gets the information present on the input line is decided by the bit status of the
selection lines.
Figure 6.11: Block Diagram of a DMUX
Source: www.itglitz.in/Digital/MultiplexersDemultiplexers.ppt
82
Notes
1 to 4 DMUX
It takes in 1 input and gives out 4 different outputs.
Figure 6.12: Block Diagram of 1 4 DMUX
Table 6.4: Truth Table of 1 4 DMUX
Source: http://faculty.kfupm.edu.sa/COE/abouh/Lesson3_5.pdf
The input E is directed to one of the outputs, as specified by the two select lines S1 and S0.
D0 = E if S1S0 = 00 D0 = S1 S0 E
D1 = E if S1S0 = 01 D1 = S1 S0 E
D2 = E if S1S0 = 10 D2 = S1 S0 E
D3 = E if S1S0 = 11 D3 = S1 S0 E
Figure 6.13: Circuit Diagram of 1 4 DMUX
Task Give the truth table and circuit diagram for 1 8 DMUX.
83
Notes
Self Assessment
4.
A demultiplexer is a combinational logic circuit with an input line, 2n output lines and n
select lines.
5.
A 1X4 DMUX gives 24 outputs.
6.
A 1X4 DMUX has 2 select lines.
6.3 Code Converters

They are used to convert one code to another. Some examples include, BCD-to-Binary converter,
Binary-to-Gray converter and Gray-to-binary converter.
BCD to 7-Segment Display Converter

Digital Decoder IC, is a device which converts one digital format into another and one of the
most commonly used device for doing this is called the Binary Coded Decimal (BCD) to 7Segment Display Decoder. 7-segment LED (Light Emitting Diode) or LCD (Liquid Crystal Display)
type displays, provide a very convenient way of displaying information or digital data in the
form of numbers, letters or even alpha-numerical characters.
Typically 7-segment displays consist of seven individual coloured LEDs (called the segments),
within one single display package. In order to produce the required numbers or HEX characters
from 0 to 9 and A to F respectively, on the display the correct combination of LED segments need
to be illuminated and BCD to 7-segment Display Decoders such as the 74LS47 do just that.
A standard 7-segment LED display generally has 8 input connections, one for each LED segment
and one that acts as a common terminal or connection for all the internal display segments.
Some single displays have also have an additional input pin to display a decimal point in their
lower right or left hand corner.
In electronics there are two important types of 7-segment LED digital display.
The Common Cathode Display (CCD) In the common cathode display, all the cathode
connections of the LEDs are joined together to logic 0 or ground. The individual segments
are illuminated by application of a HIGH, logic 1 signal to the individual Anode
terminals.
The Common Anode Display (CAD) In the common anode display, all the anode
connections of the LEDs are joined together to logic 1 and the individual segments are
illuminated by connecting the individual Cathode terminals to a LOW, logic 0 signal
Figure 6.14: Common Cathode and Anode
Source: http://www.electronics-tutorials.ws/combination/comb_6.html
84
Electrical connection of the individual diodes for a common cathode display and a common
anode display and by illuminating each light emitting diode individually, they can be made to
display a variety of numbers or characters.
Notes
7-Segment Display Format

Figure 6.15: 7 Segment Display
So in order to display the number 3 for example, segments a, b, c, d and g would need to be
illuminated. If we wanted to display a different number or letter then a different set of segments
would need to be illuminated. Then for a 7-segment display, we can produce a truth table giving
the segments that need to be illuminated in order to produce the required character as shown
below.
Table 6.5: Truth Table of 7 Segment Display
It can be seen that to display any single digit number from to 9 or letter from A to F, we would
need 7 separate segment connections plus one additional connection for the LEDs common
connection. Also as the segments are basically a standard light emitting diode, the driving
circuit would need to produce up to 20mA of current to illuminate each individual segment and
85
Notes
to display the number 8, all 7 segments would need to be lit resulting a total current of nearly
140mA, (8 x 20mA).
Obviously, the use of so many connections and power consumption is impractical for some
electronic or microprocessor based circuits and so in order to reduce the number of signal lines
required to drive just one single display, display decoders such as the BCD to 7-Segment Display
Decoder and Driver ICs are used instead.
Binary Coded Decimal

Binary Coded Decimal numbers are made up using just 4 data bits (a nibble or half a byte)
similar to the Hexadecimal numbers we saw in the binary tutorial, but unlike hexadecimal
numbers that range in full from 0 through to F, BCD numbers only range from 0 to 9, with the
binary number patterns of 1010 through to 1111 (A to F) being invalid inputs for this type of
display and so are not used as shown below.
Table 6.6: Truth Table Showing Invalid Inputs
BCD to 7-Segment Display Decoders

A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or 74LS48,
have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a smaller 4-bit
binary number (half a byte) to be used to display all the binary numbers from 0 to 9 and by
adding two displays together, a full range of numbers from 00 to 99 can be displayed with just
a single byte of 8 data bits.
Figure 6.17: 7 Segment Display Decoder
86
The use of packed BCD allows two BCD digits to be stored within a single byte (8-bits) of data,
allowing a single data byte to hold a BCD number in the range of 00 to 99.
Notes
Example: 4-bit BCD input (0100) representing the number 4 is given below:
In practice current limiting resistors of about 150 to 220 would be connected in series between
the decoder/driver chip and each LED display segment to limit the maximum current flow.
Different display decoders or drivers are available for the different types of display available,
e.g. 74LS48 for common-cathode LED types, 74LS47 for common-anode LED types, or the CMOS
CD4543 for liquid crystal display (LCD) types.
Liquid crystal displays (LCDs) have one major advantage over similar LED types in that they
consume much less power and nowadays, both LCD and LED displays are combined together to
form larger Dot-Matrix Alphanumeric type displays which can show letters and characters as
well as numbers in standard Red or Tri-colour outputs.
Self Assessment
Fill in the blanks:
7.
........................ are used to convert one code to another.
8.
A standard 7-segment LED display generally has ........................ input connections.
9.
There are two important types of 7-segment LED digital display: ........................ and
........................ .
10.
........................ data bits are equal to a nibble.
6.4 Comparators
Another common and very useful combinational logic circuit is that of the Digital Comparator
circuit. Digital or Binary Comparators are made up from standard AND, NOR and NOT gates
that compare the digital signals present at their input terminals and produce an output depending
upon the condition of those inputs.
87
Notes
For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or equal
to the value at input B etc. The digital comparator accomplishes this using several logic gates
that operate on the principles of Boolean algebra. There are two main types of Digital Comparator
available and these are.
Identity Comparator an Identity Comparator is a digital comparator that has only one
output terminal for when A = B either HIGH A = B = 1 or LOW A = B = 0
Magnitude Comparator a Magnitude Comparator is a type of digital comparator that

has three output terminals, one each for equality, A = B greater than, A > B and less than
A < B.
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers.

Example: A (A1, A2, A3, .... An, etc.) against that of a constant or unknown value such as
B (B1, B2, B3, .... Bn, etc.) and produce an output condition or flag depending upon the result of the
comparison. For example, a magnitude comparator of two 1-bit, (A and B) inputs would produce
the following three output conditions when compared to each other.
A > B, A = B, A < B
Which means: A is greater than B, A is equal to B, and A is less than B.
This is useful if we want to compare two variables and want to produce an output when any of
the above three conditions are achieved. For example, produce an output from a counter when
a certain count number is reached. Consider the simple 1-bit comparator below.
1-bit Digital Comparator

Figure 6.19: 1-bit Digital Comparator
Then the operation of a 1-bit digital comparator is given in the following Truth Table.
Table 6.7: Truth Table of a 1-bit Digital Comparator
You may notice two distinct features about the comparator from the above truth table. Firstly,
the circuit does not distinguish between either two 0 or two 1s as an output A = B is
88
produced when they are both equal, either A = B = 0 or A = B = 1. Secondly, the output
condition for A = B resembles that of a commonly available logic gate, the Exclusive-NOR or ExNOR function (equivalence) on each of the n-bits giving: Q = A B
Notes
Digital comparators actually use Exclusive-NOR gates within their design for comparing their
respective pairs of bits. When we are comparing two binary or BCD values or variables against
each other, we are comparing the magnitude of these values, a logic 0 against a logic 1
which is where the term Magnitude Comparator comes from.
As well as comparing individual bits, we can design larger bit comparators by cascading together
n of these and produce a n-bit comparator just as we did for the n-bit adder in the previous
tutorial. Multi-bit comparators can be constructed to compare whole binary or BCD words to
produce an output if one word is larger, equal to or less than the other.
A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit words (nibbles)
are compared to each other to produce the relevant output with one word connected to inputs A
and the other to be compared against connected to input B as shown below.
4-bit Magnitude Comparator

Figure 6.20: 4-bit Magnitude Comparator
Some commercially available digital comparators such as the TTL 74LS85 or CMOS 4063 4-bit
magnitude comparator have additional input terminals that allow more individual comparators
to be cascaded together to compare words larger than 4-bits with magnitude comparators of
n-bits being produced. These cascading inputs are connected directly to the corresponding
outputs of the previous comparator as shown to compare 8, 16 or even 32-bit words.
8-bit Word Comparator

Figure 6.21: 8-bit Word Comparator
89
Notes
When comparing large binary or BCD numbers like the example above, to save time the
comparator starts by comparing the highest-order bit (MSB) first. If equality exists, A = B then it
compares the next lowest bit and so on until it reaches the lowest-order bit, (LSB). If equality still
exists then the two numbers are defined as being equal.
If inequality is found, either A > B or A < B the relationship between the two numbers is
determined and the comparison between any additional lower order bits stops. Digital
Comparator are used widely in Analogue-to-Digital converters, (ADC) and Arithmetic Logic
Units, (ALU) to perform a variety of arithmetic operations.
Case Study
Boolean Logic Operation
s we all know the microprocessor is the brain of the modern digital computer,
but have you ever wondered how a piece of silicon manages to process information
so accurately and at such a high speed rate? The answer lies behind the basic
building blocks of the processor, the logic gates, and a special type of information processing
technique invented in the middle of the 1800s by George Boole, called Boolean logic.
Basically, Boolean logic operates only in the binary system by following a couple of
simple rules. There are about seven simple logic gates that need to be studies in order to
understand the full picture of how Boolean logic and computer microprocessors work by
combining logical gates in a single electronic circuit that may contain several million
transistors.
Well start with the simplest of all the NOT gate, or the logical inverter (see bottom
image, lower left corner). The NOT gate has one entrance and one exit and has the role of
inverting logic bits. This basically means that when a 1 logic bit is applied on the a
terminal for example, the c terminal must produce a 0 logic bit. The situation is reversed
when 0 logic is applied on the a terminal by forcing the c terminal to output a 1 logic
bit. Inversion is one of the basic operations in Boolean logic.
Figure
Another logic gate of critical importance is the AND gate (upper left corner), which
practically designates an operation similar to multiplying. As you can see, the AND gate
has two input terminals (a, b) and an output terminal (c). In fact the number of input
Contd...
90
terminals is unlimited. Boolean logic puts it very simple. If one of the input values is 0
logic, then the value of the other bits is irrelevant and the output will always produce a 0
logic. A 1 logic bit is present at the output terminal, only when all input bits are equal to
1 logic.
Notes
The OR gate, operates according to the logic that if one of the input terminals bears a 1
logic bit, then the c terminal will always produce a 1. The situation reverses when all of
the input bits are 0 logic. The NAND (NOT AND) and NOR (NOT OR) gates can be
imagined as an AND respectively an OR gate to whose output terminals a NOT gate (see
image for symbols) is connected. Their logic is basically identical to that of AND and OR
gates, but the output value is always reversed.
The last two significant logic gates are the XOR and XNOR gates, both of which can be
constructed by using the basic logic gates (similar to the case of NAND and OR gates). XOR
outputs a 1 logic only when a single input value equals 1 logic. In other cases the output
produces a 0 bit. XNOR gates produce XOR reverse values.
By combining logic gates in logic ways a whole range of electronic devices can be
constructed, starting with flip-flops, simple memories, counters, Random Access Memories
all the way up to highly complex logical circuitry such as computer processors. You would
be amazed at how simple some of these devices are.
Questions:
1.
Discuss the logic used for OR gate.
2.
Differentiate between XOR and XNOR gate.
Source: http://news.softpedia.com/news/How-Logic-Gates-Work-87673.shtml
Self Assessment
11.
Binary Comparators are made up from standard AND, NOR and NOT gates.
12.
Output of binary comparators do not depend upon the condition of the inputs.
13.
Digital comparators use NOR gates within their design for comparing their respective
pairs of bits.
14.
Digital Comparator are used widely in Analogue-to-Digital converters, (ADC) and

Arithmetic Logic Units, (ALU) to perform a variety of arithmetic operations.
6.5 Summary
Combinational logic or time-independent logic is a type of digital logic which is

implemented by Boolean circuits, where the output is a pure function of the present input
only.
A multiplexer or MUX is a device that selects one of several analog or digital input signals
and forwards the selected input into a single line.
A multiplexer has two sets of inputs: 2n data input lines and n select lines.
An N variable function can be implemented with one N-1 multiplexer, and (at most) one
inverter.
91
Notes
A demultiplexer (DMUX) is a combinational logic circuit with an input line, 2n output

lines and n select lines.
Code Converters are used to convert one code to another.
Digital Decoder IC, is a device which converts one digital format into another and one of
the most commonly used device for doing this is called the Binary Coded Decimal (BCD)
to 7-Segment Display Decoder.
A standard 7-segment LED display generally has 8 input connections.
In electronics there are two important types of 7-segment LED digital display: CCD, CAD.
Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output depending
upon the condition of those inputs.
There are two main types of Digital Comparator: Identity Comparator and magnitude
comparator.
Digital comparators actually use Exclusive-NOR gates within their design for comparing
their respective pairs of bits.
When we are comparing two binary or BCD values or variables against each other, we are
comparing the magnitude of these values, a logic 0 against a logic 1 which is where
the term Magnitude Comparator comes from.
6.6 Keywords
AND Gate: It takes in two or more inputs and produce only one output.
Code Converters: They are used to convert one code to another.
Digital Comparators: They actually use Exclusive-NOR gates within their design for comparing
their respective pairs of bits.
DMUX: It is a combinational logic circuit with an input line, 2n output lines and n select lines.
Magnitude Comparator: When we are comparing two binary or BCD values or variables against
each other.
MUX: It is a device that selects one of several analog or digital input signals and forwards the
selected input into a single line.
NOT Gate: It is also called as an inverter as it changes the input to its opposite.
OR Gate: It produces an output of logic 1 state even if any of its inputs is in logic 1 state and also
produces an output of logic 0 state if any of its inputs is in logic 0 state.
92
1.
What is a MUX?
2.
Explain 2X1 MUX with suitable diagram.
3.
What is Shannons theorem?
4.
Explain the concept of DMUX.
5.
Give the truth table for 1X4 DMUX.
6.
What is a BCD to 7 segment decoder?
Notes
7.
Differentiate between CCD and CAD.
8.
Why do we use a digital comparator?
9.
Discuss 4 bit magnitude comparator.
10.
Give the logic diagram of 8 bit word comparator.

1.
True
2.
False
3.
True
4.
2n ,n
5.
n-1
6.
Truth table
7.
True
8.
False
9.
False
10.
True
11.
Code converter
12.
13.
CCD, CAD
14.
Books
& Sons
J. Stanley Warford, Computer Systems, 4th Edition , Jones & Bartlett Learning
Online links
gatecomputer.files.wordpress.com/2012/02/chapter-81.pdf
http://cs.uwindsor.ca/~angom/teaching/cs265/lec7.pdf
http://faculty.kfupm.edu.sa/COE/abouh/Lesson3_5.pdf
https://uqu.edu.sa/files2/tiny_mce/plugins/filemanager/files/4280247/
digital/271-7.pdf
93
Notes
Unit 7: Standard Integrated Circuits (ICs)

CONTENTS
Objectives
Introduction
7.1
7.2
7.3
Resistor-Transistor Logic (RTL)

7.1.1
RTL inverter
7.1.2
One-transistor RTL NOR Gate
7.1.3
Multi-transistor RTL NOR Gate
Diode-Transistor Logic (DTL)

7.2.1
Implementations
7.2.2
Speed Acceleration
7.2.3
Interfacing considerations
Transistor-Transistor Logic (TTL)

7.3.1
7.4
7.5
Test Parameters for TTL Devices
Emitter-Coupled Logic (ECL)

7.4.1
Implementation
7.4.2
Operation
Integrated Circuit (IC)

7.5.1
Design
7.5.2
The Manufacturing Process
7.6
High Threshold Logic (HTL)
7.7
NMOS and CMOS Logic Gates

7.7.1
Overview of CMOS
7.7.2
Important Features of CMOS
7.7.3
Test Parameters of CMOS
7.7.4
Important Features of NMOS
7.7.5
CMOS versus TTL
7.8
Summary
7.9
Keywords

Objectives
94
Explain the resistor-transistor logic (RTL)
Elaborate upon transistor-transistor logic (TTL)
Discuss the diode-transistor logic (DTL)
Understand emitter-coupled logic (ECL)
Discuss about integrated circuit (IC)
Explain about high threshed logic (HTL)
Understand NMOS and CMOS
Notes
Introduction
An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small
plate of semiconductor material, normally silicon. Integrated circuits have revolutionized the
world of electronics. Computers, mobile phones, and other digital home appliances are built
upon these ICs. They can be made in a variety of sizes. ICs were made possible by experimental
discoveries showing that semiconductor devices could perform the functions of vacuum tubes
and by mid-20th century technology advancements in semiconductor device fabrication. The
integration of large numbers of tiny transistors into a small chip was an enormous improvement
over the manual assembly of circuits using discrete electronic components. The integrated
circuits mass production capability, reliability, and building-block approach to circuit design
ensured the rapid adoption of standardized Integrated Circuits in place of designs using discrete
transistors. There are two main advantages of ICs over discrete circuits: cost and performance.
Cost is low because the chips, with all their components, are printed as a unit by photolithography
rather than being constructed one transistor at a time. Furthermore, much less material is used
to construct a packaged IC die than to construct a discrete circuit. Performance is high because
the components switch quickly and consume little power (compared to their discrete counterparts)
as a result of the small size and close proximity of the components. As of 2012, typical chip areas
range from a few square millimeters to around 450 mm2, with up to 9 million transistors per
mm 2 .
Did u know? Jack Kilby and Texas Instruments received U.S. patent #3,138,743 for
miniaturized electronic circuits. Robert Noyce and the Fairchild Semiconductor Corporation
received U.S. patent #2,981,877 for a silicon based integrated circuit in 1959.
7.1 Resistor-Transistor Logic (RTL)

It is a type of digital circuit built with the help of resistors as the input network and bipolar
junction transistors (BJTs) as switching devices. RTL is the earliest class of transistorized digital
logic circuit used; other classes include diodetransistor logic (DTL) and transistortransistor
logic (TTL). The concept had been used in early computers with electron tubes, and in RTL
circuits constructed with discrete components, but in 1961 it became the first digital logic family
to be produced as a monolithic integrated circuit. Such were used in the US space program in
1962.
7.1.1
RTL inverter
A bipolar transistor switch is the simplest RTL gate. It consists of a common-emitter stage with
a base resistor connected between the base and the input voltage source. The role of the base
resistor is to expand the negligible transistor input voltage range (about 0.7 V) to the logical 1
level (about 3.5 V) by converting the input voltage into current. Its resistance is settled by a
95
Notes
compromise: it is chosen low enough to saturate the transistor and high enough to obtain high
input resistance. The role of the collector resistor is to convert the collector current into voltage;
its resistance is chosen high enough to saturate the transistor and low enough to obtain low
output resistance (high fan-out).
Figure 7.1: One-transistor RTL NOR Gate
Source: http://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_logic
Advantages
RTL technology had minimum number of transistors, which was an important consideration
before integrated circuit technology, as transistors were the most expensive component to
produce. Early IC logic production (such as Fairchilds in 1961) used the same approach briefly,
but quickly transitioned to higher-performance circuits such as diodetransistor logic and then
transistortransistor logic (starting 1963 at Sylvania), since diodes and transistors were no more
expensive than resistors in the IC.
Limitations
The disadvantage of RTL is its high power dissipation when the transistor is switched on (the
power is dissipated mainly by the base resistors connected to logical 1 and by the collector
resistor). This requires that more current be supplied to and heat be removed from RTL circuits.
In contrast, TTL circuits with totem-pole output stage minimize both of these requirements.
Another limitation of RTL was its limited fan-in: 3 inputs being the limit for many circuit
designs, before it completely lost usable noise immunity. It has a low noise margin. Lancaster
says that integrated circuit RTL NOR gates (which have one transistor per input) may be
constructed with any reasonable number of logic inputs, and gives an example of an 8-input
NOR gate. A standard integrated circuit RTL NOR gate can drive up to 3 other similar gates.
Alternatively, it has enough output to drive up to 2 standard integrated circuit RTL buffers,
each of which can drive up to 25 other standard RTL NOR gates.
7.1.2
One-transistor RTL NOR Gate
By connecting additional base resistors (R3 and R4) to the inverter it is expanded to the simplest
RTL NOR gate. It is interesting fact that the basic input logical operation OR is performed by
applying consecutively the two arithmetic operations addition and comparison (the input resistor
network acts as a parallel voltage summer with equally weighted inputs and the next commonemitter transistor stage as a voltage comparator with a threshold about 0.7 V). The equivalent
resistance of all the resistors connected to logical 1 and the equivalent resistance of all the
resistors connected to logical 0 form the two legs of a composed voltage divider driving the
transistor. The base resistances and the number of the inputs are chosen (limited) so that only
96
one logical 1 is sufficient to create base-emitter voltage exceeding the threshold and, as a
result, saturating the transistor. If all the input voltages are low (logical 0), the transistor is
cut-off. The pull-down resistor R1 provides reliable cut-off of the transistor (it is not absolutely
necessary in the case of a silicon transistor). The output is inverted since the voltage drop across
the collector-emitter junction of the transistor Q1 is taken as a grounded output instead the
voltage drop across the floating collector resistor R2. Thus, the analog resistive network and the
analog transistor stage perform the logic function NOR.
Notes
Figure 7.2: Dual NOR Gate Chip used to Build the Apollo Guidance Computer
Figure 7.3: Schematic of a Multi-transistor RTL NOR Gate used to Build

the Apollo Guidance Computer
Figure 7.4 : Flatpack RTL NOR Gate Integrated Circuits in the Apollo Guidance Computer
97
Notes
7.1.3
Multi-transistor RTL NOR Gate
The limitations of the one-transistor RTL NOR gate are overcome by the multi-transistor RTL
implementation. It consists of a set of parallel-connected transistor switches driven by the logic
inputs. In this configuration, the inputs are completely separated and the number of inputs is
limited only by the small reverse saturation current of the cut-off transistors at output logical
1. The same idea is used later for building DCTL, ECL, some TTL (7450, 7460), NMOS and
CMOS gates.
Self Assessment
1.
There are two main disadvantages of ICs over discrete circuits: cost and performance.
2.
A bipolar transistor switch is the simplest RTL gate.
3.
The role of the collector resistor is to convert the collector current into voltage.
4.
RTL technology had maximum number of transistors.
7.2 Diode-Transistor Logic (DTL)

Diodetransistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor
transistor logic. It is called so because the logic gating function (e.g., AND) is performed by a
diode network and the amplifying function is performed by a transistor (in contrast with RTL
and TTL).
7.2.1
Implementations
Figure 7.5: Schematic of Basic Two-input DTL NAND Gate. R3, R4 and V-Shift
the Positive Output Voltage of the Input DL Stage Below the Ground
(to cut off the Transistor at Low Input Voltage).
Source: http://en.wikipedia.org/wiki/Diode%E2%80%93transistor_logic
The DTL circuit shown in the picture consists of three stages: an input diode logic stage
(D1, D2 and R1), an intermediate level shifting stage (R3, R4 and V-) and an output commonemitter switching-transistor stage (Q1 and R2). The two resistors R3 and R4 form a resistive
summing circuit with weighted inputs that adds the negative bias voltage V- to the positive
98
diode logic output voltage. As a result, the unipolar (positive) diode output voltage (about
V+ for logical one and 1.0 V for logical zero) is converted into a bipolar voltage (a few volts
above and below ground) to drive the output transistor. The IBM 1401 (announced in 1959])
used DTL circuits similar to the simplified circuit. IBM called the logic complemented
transistor diode logic (CTDL). CTDL avoided the level shifting stage (R3, R4, and V-) by
alternating NPN and PNP based gates operating on different power supply voltages. The
1401 used germanium transistors and diodes in its basic gates. The 1401 also added an
inductor in series with R2. The physical packaging used the IBM Standard Modular System.
In an integrated circuit version of the DTL gate, two series connected level shifting diodes
replace R3. Also the bottom of R4 is connected to ground to provide bias current for the
diodes and a discharge path for the transistor base. The resulting integrated circuit runs off
a single power supply voltage.
7.2.2
Notes
Speed Acceleration
The DTL propagation delay is relatively large. When the transistor goes into saturation from
all inputs being high, charge is stored in the base region. When it comes out of saturation (one
input goes low) this charge has to be removed and will dominate the propagation time. A
Baker clamp can be used to keep the transistor from saturating. Another way to speed up DTL
is to add a small capacitor across R3. The capacitor helps turn off the transistor by removing
the stored base charge; the capacitor also helps turn on the transistor by increasing the initial
base drive.
7.2.3
Interfacing considerations
A major advantage over the earlier resistortransistor logic is the increased fan-in. Alternatively,
to increase fan-out of the gate, an additional transistor and diode may be used.
Self Assessment
Fill in the blanks:
5.
Multi-transistor RTL NOR gate consists of a set of ........................ connected transistor

switches driven by the logic inputs.
6.
........................ is a class of digital circuits that is the direct ancestor of transistortransistor

logic.
7.
CTDL stands for ........................ .
8.
The ........................ propagation delay is relatively large.
7.3 Transistor-Transistor Logic (TTL)

Transistortransistor logic (TTL) is a class of digital circuits built from bipolar junction transistors
(BJT) and resistors. It is called transistortransistor logic because both the logic gating function
and the amplifying function are performed by transistors (contrast with RTL and DTL). TTL is
notable for being a widespread integrated circuit (IC) family used in many applications such as
computers, industrial controls, test equipment and instrumentation, consumer electronics,
synthesizers, etc. The designation TTL is sometimes used to mean TTL-compatible logic levels,
even when not associated directly with TTL integrated circuits, for example as a label on the
inputs and outputs of electronic instruments.
99
Notes
Figure 7.6: A Motorola 68000-based Computer with Various

TTL Chips Mounted on Protoboards.
Source: http://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic
After introduction in integrated circuit form in 1963 by Sylvania, TTL integrated circuits were
manufactured by several semiconductor companies, with the 7400 series by Texas Instruments
becoming particularly popular. TTL manufacturers offered a wide range of logic gate, flip-flops,
counters, and other circuits. Several variations from the original bipolar TTL concept were
developed, giving circuits with higher speed or lower power dissipation to allow optimization
of a design. TTL circuits simplified design of systems compared to earlier logic families, offering
superior speed to resistor-transistor logic (RTL) and easier design layout than emitter-coupled
logic (ECL). The design of the input and outputs of TTL gates allowed many elements to be
interconnected. TTL became the foundation of computers and other digital electronics. Even
after much larger scale integrated circuits made multiple-circuit-board processors obsolete, TTL
devices still found extensive use as the glue logic interfacing more densely integrated
components. TTL devices were originally made in ceramic and plastic dual-in-line (DIP) packages,
and flat-pack form. TTL chips are now also made in surface-mount packages. Successors to the
original bipolar TTL logic often are interchangeable in function with the original circuits, but
with improved speed or lower power dissipation.
Did u know? TTL was invented in 1961 by James L. Buie of TRW, particularly suited to the
newly developing integrated circuit design technology, and it was originally named
transistor-coupled transistor logic (TCTL)
Fundamental TTL Gate

Figure 7.7: Two-input TTL NAND Gate with a Simple Output Stage
100
TTL inputs are the emitters of a multiple-emitter transistor. This IC structure is functionally
equivalent to multiple transistors where the bases and collectors are tied together. The output is
buffered by a common emitter amplifier. Inputs both logical ones. When all the inputs are held
at high voltage, the base-emitter junctions of the multiple-emitter transistor are reverse-biased.
Unlike DTL, a small collector current (approximately 10A) is drawn by each of the inputs.
This is because the transistor is in reverse-active mode. An approximately constant current
flows from the positive rail, through the resistor and into the base of the multiple emitter
transistor. This current passes through the base-emitter junction of the output transistor, allowing
it to conduct and pulling the output voltage low (logical zero). An input logical zero. Note that
the base-collector junction of the multiple-emitter transistor and the base-emitter junction of the
output transistor are in series between the bottom of the resistor and ground. If one input
voltage becomes zero, the corresponding base-emitter junction of the multiple-emitter transistor
is in parallel with these two junctions. A phenomenon called current steering means that when
two voltage-stable elements with different threshold voltages are connected in parallel, the
current flows through the path with the smaller threshold voltage. As a result, no current flows
through the base of the output transistor, causing it to stop conducting and the output voltage
becomes high (logical one). During the transition the input transistor is briefly in its active
region; so it draws a large current away from the base of the output transistor and thus quickly
discharges its base. This is a critical advantage of TTL over DTL that speeds up the transition over
a diode input structure.
Notes
The main disadvantage of TTL with a simple output stage is the relatively high output resistance
at output logical 1 that is completely determined by the output collector resistor. It limits the
number of inputs that can be connected (the fan out). Some advantage of the simple output stage
is the high voltage level (up to VCC) of the output logical 1 when the output is not loaded. Logic
of this type is most frequently encountered with the collector resistor of the output transistor
omitted, making an open collector output. This allows the designer to fabricate logic by
connecting the open collector outputs of several logic gates together and providing a single
external pull-up resistor. If any of the logic gates becomes logic low (transistor conducting), the
combined output will be low. Examples of this type of gate are the 7401 and 7403 series.
TTL with a totem-pole output stage

Figure 7.8: Standard TTL NAND with a totem-pole Output Stage, one of Four in 7400
101
Notes
To solve the problem with the high output resistance of the simple output stage the second
schematic adds to this a totem-pole (pushpull) output. It consists of the two n-p-n transistors
V3 and V4, the lifting diode V5 and the current-limiting resistor R3 (see the figure on the right).
It is driven by applying the same current steering idea as above. When V2 is off, V4 is off as
well and V3 operates in active region as a voltage follower producing high output voltage
(logical 1). When V2 is on, it activates V4, driving low voltage (logical 0) to the output. V2
and V4 collector-emitter junctions connect V4 baseemitter junction in parallel to the seriesconnected V3 base-emitter and V5 anode-cathode junctions. V3 base current is deprived; the
transistor turns off and it does not impact on the output. In the middle of the transition, the
resistor R3 limits the current flowing directly through the series connected transistor V3, diode
V5 and transistor V4 that are all conducting. It also limits the output current in the case of output
logical 1 and short connection to the ground. The strength of the gate may be increased
without proportionally affecting the power consumption by removing the pull-up and pulldown resistors from the output stage.
The main advantage of TTL with a totem-pole output stage is the low output resistance at
output logical 1. It is determined by the upper output transistor V3 operating in active region
as a voltage follower. The resistor R3 does not increase the output resistance since it is connected
in the V3 collector and its influence is compensated by the negative feedback. A disadvantage of
the totem-pole output stage is the decreased voltage level (no more than 3.5 V) of the output
logical 1 (even, if the output is unloaded). The reason of this reduction are the voltage drops
across the V3 baseemitter and V5 anodecathode junctions.
Interfacing Considerations
Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring
them to a logic 0 level. At low input voltage, the TTL input sources current which must be
absorbed by the previous stage. The maximum value of this current is about 1.6 mA for a
standard TTL gate. The input source has to be low-resistive enough (< 800 ) so that the
flowing current creates only a negligible voltage drop (< 0.8 V) across it, for the input to be
considered as a logical 0. TTL inputs are sometimes simply left floating to provide a
logical 1, though this usage is not recommended. Standard TTL circuits operate with a
5-volt power supply. A TTL input signal is defined as low when between 0 V and 0.8 V
with respect to the ground terminal, and high when between 2.2 V and 5 V[18] (precise logic
levels vary slightly between sub-types and by temperature). TTL outputs are typically
restricted to narrower limits of between 0 V and 0.4 V for a low and between 2.6 V and
5 V for a high, providing 0.4V of noise immunity. Standardization of the TTL levels was so
ubiquitous that complex circuit boards often contained TTL chips made by many different
manufacturers selected for availability and cost, compatibility being assured; two circuit
board units off the same assembly line on different successive days or weeks might have a
different mix of brands of chips in the same positions on the board; repair was possible with
chips manufactured years (sometimes over a decade) later than original components. Within
usefully broad limits, logic gates could be treated as ideal Boolean devices without concern
for electrical limitations. In some cases (e.g., when the output of a TTL logic gate needs to be
used for driving the input of a CMOS gate), the voltage level of the totem-pole output
stage at output logical 1 can be increased up to VCC by connecting an external resistor
between the V3 collector and the positive rail. It pulls up the V 5 cathode and cuts-off the
diode. However, this technique actually converts the sophisticated totem-pole output
into a simple output stage having significant output resistance when driving a high level
(determined by the external resistor).
102
7.3.1
Test Parameters for TTL Devices
Notes
Table 7.1: Test Parameters
Source: http://www.siliconfareast.com/testparams_ttl.htm
Self Assessment
Fill in the blanks:
9.
........................ is a class of digital circuits built from bipolar junction transistors (BJT) and
resistors.
10.
The main disadvantage of TTL with a simple output stage is the relatively high output
resistance at output logical ........................ .
11.
To solve the problem with the high output resistance of the simple output stage the second
schematic adds to this a ........................ output.
7.4 Emitter-Coupled Logic (ECL)

It is a high-speed integrated circuit bipolar transistor logic family. ECL uses an overdriven BJT
differential amplifier with single-ended input and limited emitter current to avoid the saturated
(fully on) region of operation and its slow turn-off behavior. As the current is steered between
two legs of an emitter-coupled pair, ECL is sometimes called current-steering logic (CSL),
current-mode logic (CML) or current-switch emitter-follower (CSEF) logic.
103
Notes
In ECL, the transistors are never in saturation, the input/output voltages have a small swing (0.8
V), the input impedance is high and the output resistance is low; as a result, the transistors
change states quickly, gate delays are low, and the fan out capability is high. In addition, the
essentially-constant current draw of the differential amplifiers minimizes delays and glitches
due to supply-line inductance and capacitance, and the complementary outputs decrease the
propagation time of the whole circuit by saving additional inverters.
ECLs major disadvantage is that each gate continuously draws current, which means it requires
(and dissipates) significantly more power than those of other logic families, especially when
quiescent. The equivalent of emitter-coupled logic made out of FETs is called source-coupled
FET logic (SCFL). A variation of ECL in which all signal paths and gate inputs are differential is
known as differential current switch (DCS) logic.
Figure 7.9: ECL
Source: http://en.wikipedia.org/wiki/File:ECL.svg
Did u know? ECL was invented in August 1956 at IBM by Hannon S. Yourke. Originally
called current-steering logic, it was used in the Stretch, IBM 7090, and IBM 7094 computers.]
The logic was also called a current mode circuit.
7.4.1
Implementation
Figure 7.10: ECL
Source: http://nortonkit.co.in/tutorial/digital/electronics/ecl_gates.html
104
Emitter-Coupled Logic is based on the use of a multi-input differential amplifier to amplify and
combine the digital signals, and emitter followers to adjust the dc voltage levels. As a result,
none of the transistors in the gate ever enter saturation, nor do they ever get turned completely
off. The transistors remain entirely within their active operating regions at all times. As a result,
the transistors do not have a charge storage time to contend with, and can change states much
more rapidly. Thus, the main advantage of this type of logic gate is extremely high speed.
Notes
The schematic diagram shown here is taken from Motorolas 1000/10,000 series of MECL devices.
This particular circuit is of one 4-input OR/NOR gate. Standard voltages for this circuit are -5.2
volts (VEE) and ground (VCC). Unused inputs are connected to VEE. The bias circuit at the right side,
consisting of one transistor and its associated diodes and resistors, can handle any number of
gates in a single IC package. Typical ICs include dual 4-input, triple 3-input, and quad 2-input
gates. In each case, the gates themselves differ only in how many input transistors they have.
A single bias circuit serves all gates. In operation, a logical output changes state by only 0.85
volt, from a low of -1.60 volts to a high of -0.75 volt. The internal bias circuit supplies a fixed
voltage of -1.175 volts to the bias transistor in the differential amplifier. If all inputs are at
-1.6 volts (or tied to VEE), the input transistors will all be off, and only the internal differential
transistor will conduct current. This reduces the base voltage of the OR output transistor, lowering
its output voltage to -1.60 volts. At the same time, no input transistors are affecting the NOR
output transistors base, so its output rises to -0.75 volt. This is simply the emitter-base voltage,
VBE, of the transistor itself. (All transistors are alike within the IC, and are designed to have a
VBE of 0.75 volt.) When any input rises to -0.75 volt, that transistor siphons emitter current away
from the internal differential transistor, causing the outputs to switch states. The voltage changes
in this type of circuit are small, and are dictated by the VBE of the transistors involved when they
are on. Of greater importance to the operation of the circuit is the amount of current flowing
through various transistors, rather than the precise voltages involved. Accordingly, EmitterCoupled Logic is also known as Current Mode Logic (CML). This is not the only technology to
implement CML by any means, but it does fall into that general description. In any case, this
leads us to a major drawback of this type of gate: it draws a great deal of current from the power
supply, and hence tends to dissipate a significant amount of heat. To minimize this problem,
some devices such as frequency counters use an ECL decade counter at the input end of the
circuitry, followed by TTL or high-speed CMOS counters at the later digit positions. This puts
the fast, expensive IC where it is absolutely required, and allows us to use cheaper ICs in
locations where the signal will never be at that high a frequency.
7.4.2
Operation
The ECL circuit operation is considered below with assumption that the input voltage is applied
to T1 base, while T2 input is unused or a logical 0 is applied. During the transition, the core of
the circuit the emitter-coupled pair (T1 and T3) acts as a differential amplifier with singleended input. The long-tail current source (RE) sets the total current flowing through the two
legs of the pair. The input voltage controls the current flowing through the transistors by
sharing it between the two legs, steering it all to one side when not near the switching point. The
gain is higher than at the end states and the circuit switches quickly. At low input voltage
(logical 0) or at high input voltage (logical 1) the differential amplifier is overdriven. The
one transistor (T1 or T3) is cut-off and the other (T3 or T1) is in active linear region acting as a
common-emitter stage with emitter degeneration that takes all the current, starving the other
cut-off transistor. The active transistor is loaded with the relatively high emitter resistance RE
that introduces a significant negative feedback (emitter degeneration). To prevent saturation of
the active transistor so that the diffusion time that slows the recovery from saturation will not
be involved in the logic delay, the emitter and collector resistances are chosen such that at
maximum input voltage some voltage is left across the transistor. The residual gain is low
(K = RC/RE < 1). The circuit is insensitive to the input voltage variations and the transistor stays
105
Notes
firmly in active linear region. The input resistance is high because of the series negative feedback.
The cut-off transistor breaks the connection between its input and output. As a result, its input
voltage does not affect the output voltage. The input resistance is high again since the baseemitter junction is cut-off.
7.5 Integrated Circuit (IC)

An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a
microchip) is a set of electronic circuits on one small plate (chip) of semiconductor material,
normally silicon. This can be made much smaller than a discrete circuit made from independent
components. Integrated circuits are used in virtually all electronic equipment today and have
revolutionized the world of electronics. Computers, mobile phones, and other digital home
appliances are now inextricable parts of the structure of modern societies, made possible by the
low cost of producing integrated circuits. ICs can be made very compact, having up to several
billion transistors and other electronic components in an area the size of a fingernail. The width
of each conducting line in a circuit (the line width) can be made smaller and smaller as the
technology advances; in 2008 it dropped below 100 nanometers and in 2013 it is expected to be
in the tens of nanometers.
7.5.1
Design
Integrated circuit design, or IC design, is a subset of electrical engineering, encompassing the

particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs
consist of miniaturized electronic components built into an electrical network on a monolithic
semiconductor substrate by photolithography. IC design can be divided into the broad categories
of digital and analog IC design. Digital IC design is to produce components such as
microprocessors, FPGAs, memories (RAM, ROM, and flash) and digital ASICs. Digital design
focuses on logical correctness, maximizing circuit density, and placing circuits so that clock and
timing signals are routed efficiently. Analog IC design also has specializations in power IC
design and RF IC design. Analog IC design is used in the design of op-amps, linear regulators,
phase locked loops, oscillators and active filters. Analog design is more concerned with the
physics of the semiconductor devices such as gain, matching, power dissipation, and resistance.
Fidelity of analog signal amplification and filtering is usually critical and as a result, analog ICs
use larger area active devices than digital designs and are usually less dense in circuitry. Modern
ICs are enormously complicated. A large chip, as of 2009 has close to 1 billion transistors. The
rules for what can and cannot be manufactured are also extremely complex. An IC process as of
2006 may well have more than 600 rules. Furthermore, since the manufacturing process itself is
not completely predictable, designers must account for its statistical nature. The complexity of
modern IC design, as well as market pressure to produce designs rapidly, has led to the extensive
use of automated design tools in the IC design process. In short, the design of an IC using EDA
software is the design, test, and verification of the instructions that the IC is to carry out.
7.5.2
The Manufacturing Process
Semiconductor device fabrication is the process used to create the integrated circuits that are
present in everyday electrical and electronic devices. It is a multiple-step sequence of
photolithographic and chemical processing steps during which electronic circuits are gradually
created on a wafer made of pure semiconducting material. Silicon is almost always used, but
various compound semiconductors are used for specialized applications. The entire
manufacturing process, from start to packaged chips ready for shipment, takes six to eight
weeks.
106
Notes
Preparing the Silicon Wafer

A cylindrical ingot of silicon about 1.5 to 4.0 inches (3.8 to 10.2 cm) in diameter is held vertically
inside a vacuum chamber with a high-temperature heating coil encircling it. Starting at the top
of the cylinder, the silicon is heated to its melting point of about 2550F (1400C). To avoid
contamination, the heated region is contained only by the surface tension of the molten silicon.
As the region melts, any impurities in the silicon become mobile. The heating coil is slowly
moved down the length of the cylinder, and the impurities are carried along with the melted
region. When the heating coil reaches the bottom, almost all of the impurities have been swept
along and are concentrated there. The bottom is then slice off, leaving a cylindrical ingot of
purified silicon. A thin, round wafer of silicon is cut off the ingot using a precise cutting machine
called a wafer slicer. Each slice is about 0.01 to 0.025 inches (0.004 to 0.01 cm) thick. The surface on
which the integrated circuits are to be formed is polished. The surfaces of the wafer are coated
with a layer of silicon dioxide to form an insulating base and to prevent any oxidation of the
silicon which would cause impurities. The silicon dioxide is formed by subjecting the wafer to
superheated steam at about 1830F (1000C) under several atmospheres of pressure to allow the
oxygen in the water vapour to react with the silicon. Controlling the temperature and length of
exposure controls the thickness of the silicon dioxide layer.
Masking
A photomask is a quartz plate with one layer of patterns for all of the ICs on a wafer on it.
A reticle only has the patterns for a few ICs on it .The patterns are formed with opaque substances
such as emulsion or chrome. Emulsion images on the glass substrate are difficult to clean.
Typically they are used for a limited number of exposures and then discarded. On the other
hand, chrome images on the glass substrate can be cleaned, inspected, and reused many times.
DopingAtomic Diffusion
Diffusion is the movement of impurity atoms in a semiconductor material at high temperatures.
The driving force of diffusion is the concentration gradient. There is a wide range of diffusivities
for the various dopant species, which depend on how easy the respective dopant impurity can
move through the material. Diffusion is applied to anneal the crystal defects after ion implantation
or to introduce dopant atoms into silicon from a chemical vapor source. In the last case the
diffusion time and temperature determine the depth of dopant penetration. Diffusion is used to
form the source, drain, and channel regions in a MOS transistor. But diffusion can also be an
unwanted parasitic effect, because it takes place during all high temperature process steps.
DopingIon Implantation
Ion implantation is the dominant technique to introduce dopant impurities into crystalline
silicon. This is performed with an electric field which accelerates the ionized atoms or molecules
so that these particles penetrate into the target material until they come to rest because of
interactions with the silicon atoms. Ion implantation is able to control exactly the distribution
and dose of the dopants in silicon, because the penetration depth depends on the kinetic
energy of the ions which is proportional to the electric field. The dopant dose can be controlled
by varying the ion source. Unfortunately, after ion implantation the crystal structure is damaged
which implies worse electrical properties. Another problem is that the implanted dopants are
electrically inactive, because they are situated on interstitial sites. Therefore after ion
implantation a thermal process step is necessary which repairs the crystal damage and activates
the dopants.
107
Notes
Making Successive Layers

The process of masking and etching or doping is repeated for each successive layer depending
on the doping process used until all of the integrated circuit chips are complete. Sometimes a
layer of silicon dioxide is laid down to provide an insulator between layers or components. This
is done through a process known as chemical vapor deposition, in which the wafers surface is
heated to about 752F (400C), and a reaction between the gases silane and oxygen deposits a
layer of silicon dioxide. A final silicon dioxide layer seals the surface, a final etching opens up
contact points, and a layer of aluminum is deposited to make the contact pads. At this point, the
individual ICs are tested for electrical function.
Making Individual ICs

The thin wafer is like a piece of glass. The hundreds of individual chips are separated by scoring
a crosshatch of lines with a fine diamond cutter and then putting the wafer under stress to cause
each chip to separate. Those ICs that failed the electrical test are discarded. Inspection under a
microscope reveals other ICs that were damaged by the separation process, and these are also
discarded. The good ICs are individually bonded into their mounting package and the thin wire
leads are connected by either ultrasonic bonding or thermo compression. The mounting package
is marked with identifying part numbers and other information. The completed integrated
circuits are sealed in anti-static plastic bags to be stored or shipped to the end-user.
Self Assessment
12.
In ECL, the transistors are never in saturation.
13.
Masking is the movement of impurity atoms in a semiconductor material at high

temperatures
7.6 High Threshold Logic (HTL)

HTL is a high threshold logic based on the modified DTL circuit. It is a variant of DTL which is
used in such environments where noise is very high. The threshold values at the input to a logic
gate determine whether a particular input is interpreted as a logic 0 or a logic 1. (e.g. anything
less than 1 V is a logic 0 and anything above 3 V is a logic 1. In this example, the threshold values
are 1V and 3V). HTL incorporates Zener diodes to create a large offset between logic 1 and logic
0 voltage levels. These devices usually ran off a 15 V power supply and were found in industrial
control, where the high differential was intended to minimize the effect of noise.
Figure 7.11: HTL
Source: http://en.wikipedia.org/wiki/High_Threshold_Logic
108
7.7 NMOS and CMOS Logic Gates
Notes
N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect

transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors
have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called
active), and velocity saturation. The n-type MOSFETs are arranged in a so-called pull-down
network (PDN) between the logic gate output and negative supply voltage, while a resistor is
placed between the logic gate output and the positive supply voltage. The circuit is designed
such that if the desired output is low, then the PDN will be active, creating a current path
between the negative supply and the output.
Figure 7.12: NMOS
Source: http://en.wikipedia.org/wiki/NMOS_logic
Example: Here is a NOR gate in NMOS logic. If either input A or input B is high
(logic 1, = True), the respective MOS transistor acts as a very low resistance between the output
and the negative supply, forcing the output to be low (logic 0, = False). When both A and B are
high, both transistors are conductive, creating an even lower resistance path to ground. The only
case where the output is high is when both transistors are off, which occurs only when both A
and B are low, thus satisfying the truth table of a NOR gate:
A MOSFET can be made to operate as a resistor, so the whole circuit can be made with n-channel
MOSFETs only. For many years, this made NMOS circuits much faster than comparable PMOS
and CMOS circuits, which had to use much slower p-channel transistors. It was also easier to
manufacture NMOS than CMOS, as the latter has to implement p-channel transistors in special
n-wells on the p-substrate. The major problem with NMOS (and most other logic families) is
that a DC current must flow through a logic gate even when the output is in a steady state (low
in the case of NMOS). This means static power dissipation, i.e. power drain even when the circuit
is not switching. This is a similar situation to the modern high speed, high density CMOS
circuits (microprocessors etc.) Which also has significant static current draw, although this is due
to leakage, not bias. However, older and/or slower static CMOS circuits used for ASICs, SRAM
etc., typically have very low static power consumption.
Also, NMOS circuits are slow to transition from low to high. When transitioning from high to
low, the transistors provide low resistance, and the capacitive charge at the output drains away
very quickly (similar to discharging a capacitor through a very low resistor). But the resistance
between the output and the positive supply rail is much greater, so the low to high transition
takes longer (similar to charging a capacitor through a high value resistor). Using a resistor of
lower value will speed up the process but also increases static power dissipation. However, a
109
Notes
better (and the most common) way to make the gates faster is to use depletion-mode transistors
instead of enhancement-mode transistors as loads. This is called depletion-load NMOS logic.
Additionally, just like in DTL, TTL and ECL etc., the asymmetric input logic levels make NMOS
circuits somewhat susceptible to noise. These disadvantages are why the CMOS logic now has
supplanted most of these types in most high-speed digital circuits such as microprocessors
(despite the fact that CMOS was originally very slow).
Complementary metal-oxide-semiconductor (CMOS) is a technology for constructing integrated
circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other
digital logic circuits. CMOS technology is also used for several analog circuits such as image
sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of
communication. Frank Wanlass patented CMOS in 1967 (US patent 3,356,858).
CMOS is also sometimes referred to as complementary-symmetry metal-oxide-semiconductor
(or COS-MOS). The words complementary-symmetry refer to the fact that the typical digital
design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal
oxide semiconductor field effect transistors (MOSFETs) for logic functions.
7.7.1
Overview of CMOS
Two important characteristics of CMOS devices are high noise immunity and low static power
consumption. Since one transistor of the pair is always off, the series combination draws
significant power only momentarily during switching between on and off states. Consequently,
CMOS devices do not produce as much waste heat as other forms of logic, for example transistortransistor logic (TTL) or NMOS logic, which normally have some standing current even when
not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily
for this reason that CMOS became the most used technology to be implemented in VLSI chips.
The phrase metaloxidesemiconductor is a reference to the physical structure of certain fieldeffect transistors, having a metal gate electrode placed on top of an oxide insulator, which in
turn is on top of a semiconductor material. Aluminium was once used but now the material is
polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric
materials in the CMOS process, as announced by IBM and Intel for the 45 nanometre node and
beyond.
Figure 7.13: CMOS
Source: http://en.wikipedia.org/wiki/CMOS_logic
7.7.2
Important Features of CMOS
Some of the advantages of CMOS over NMOS are:
110
Reduce the complexity of the circuit
Low static power consumption
Notes
High noise immunity
High density of logic function on a chip
The most important advantage of CMOS is the very low static power consumption in compare
with NMOS technology. On the other hand, CMOS technology is more complex to fabricate then
NMOS technology, so it is more expensive. However, almost every todays digital circuits are
CMOS. You want to use NMOS only when you want to fabricate fast and low-cost a simple
circuit. The most important advantage of CMOS is the very low static power consumption in
compare with NMOS technology. On the other hand, CMOS technology is more complex to
fabricate then NMOS technology, so it is more expensive. However, almost every todays digital
circuits are CMOS. You want to use NMOS only when you want to fabricate fast and low-cost a
simple circuit.
7.7.3
Test Parameters of CMOS
The test parameters of CMOS are summarized in the table below:

Table 7.2: Test Parameters of CMOS
Source: http://www.siliconfareast.com/testparams_cmos.htm
111
Notes
7.7.4
Important Features of NMOS
n-channel MOSFETs have some inherent performance advantages over p-channel MOSFETs.
The mobility of electrons, which are carriers in the case of an n-channel device, is about two
times greater than that of holes, which are the carriers in the p-channel device. Thus an n-channel
device is faster than a p-channel device. However, PMOS circuits have following advantages:
PMOS technology is highly controllable.
It is a low cost process.
It has good yield and high noise immunity.
In addition to inherent fast speed properly, NMOS device also have following advantages:
Since electron mobility is twice (say) that of hole mobility, an n-channel device will have
one-half the on-resistance or impedance of an equivalent p-channel device with the same
geometry and under the same operating conditions. Thus n-channel transistors need only
halt the size of p-channel devices to achieve the same impedance. Therefore, n-channel ICs
can be smaller for the same complexity or, even more important, they can be more complex
with no increase in silicon area.
NMOS circuits offer a speed advantage over PMOS due to smaller junction areas. Since the
operating speed of an MOS IC is largely limited by internal RC time constants and
capacitance of diode is directly proportional to its size, an n-channel junction can have
smaller capacitance. This, in turn, improves its speed.
Problems of NMOS are as stated below:

1.
The n-channel device has following problems in the device processing. Most of the
mobile contaminants are positively charged. Since NMOS operates with the gate
positively based with respect to the substrate, these ions collect along the oxide-silicon
interface. This charge causes a shift in VTh. Also, there is fixed positive charge at the
Si-SiO2 interface resulting from various steps of the manufacturing process. This also
shifts the threshold voltage. Both these charges have tendency to make the device
normally on. These two charges exist in PMOS device too, but the positive ions are
pulled to the Al-SiO2 interlace by the negative bias applied to gate. There, they cannot
affect the device threshold severely.
2.
Another problem with NMOS device occurs during the oxidation of silicon which takes
place at the Si-SiO2 interface. No real abrupt change occurs between silicon and SiO2;
rather there is a transition zone. This transition zone contains positively charged Silicon
atoms which increase the absolute magnitude of the threshold voltage for a p-channel
device and decrease the absolute magnitude of the threshold voltage for an n-channel
device. This means it is difficult to make an n-channel device that is off at zero gate
voltage. This is why it is more difficult to make an n-channel device than a p-channel
device.
7.7.5
CMOS versus TTL
Characteristics of CMOS logic are that,

1.
112
Dissipates Low Power: The power dissipation is dependent on the power supply voltage,
frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation
is typically 10 nW per gate.
2.
Short Propagation Delays: Depending on the power supply, the propagation delays are
usually around 25 nS to 50 nS.
3.
Rise and Fall Times are Controlled: The rise and falls are usually ramps instead of step
functions, and they are 2040% longer than the propagation delays.
4.
Noise immunity approaches 50% or 45% of the full logic swing.
5.
Levels of the logic signal will be essentially equal to the power supplied since the input
impedance is so high.
Notes
Characteristics of TTL logic are that,

1.
Power dissipation is usually 10 mW per gate.
2.
Propagation delays are 10 nS when driving a 15 pF/400 ohm load.
3.
Voltage levels range from 0 to Vcc where Vcc is typically 4.75V5.25V. Voltage range
0V0.8V creates logic level 0. Voltage range 2VVcc creates logic level 1.
If we compare,
1.
CMOS components are typically more expensive that TTL equivalents. However, CMOS
technology is usually less expensive on a system level due to CMOS chips being smaller
and requiring less regulation.
2.
CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS
power consumption increases faster with higher clock speeds than TTL does. Lower
current draw requires less power supply distribution, therefore causing a simpler and
cheaper design.
3.
Due to longer rise and fall times, the transmission of digital signals become simpler and
less expensive with CMOS chips.
4.
CMOS components are more susceptible to damage from electrostatic discharge than TTL
components.
Case Study
MEMSIC
ts hard enough to design mixed-signal processing onto the same chip as a MEMS
device, but MEMSIC has managed to integrate these technologies on the same silicon
and sell hundreds of thousands of accelerometers in a variety of industries. The company
has also overcome two other hurdles: keeping production costs low by sticking to a standard
CMOS IC process, and standardizing development on a single, lean set of EDA tools.
Detecting Acceleration and Motion
Most accelerometers depend on moving mass to determine motion, but MEMSIC
differentiates itself from its competitors through its use of a thermo-mechanical sensor in
silicon. In the center of the 1 mm-square sensor is a heater operating at 100C above
ambient temperature. Around the heater are symmetrically placed thermopiles for
reporting temperature in different locations. (A thermopile is a series of thermocouples,
or temperature-sensing elements, connected in a series to boost voltage.) The entire sensor
is hermetically sealed in an air/gas cavity, outside of which is analog circuitry for
amplification, control, analog-to-digital conversion and, in the 3-axis models, digital
compensation/calibration circuitry. In the absence of motion, the thermal profile is balanced
Contd...
113
Notes
among the thermopiles, but any motion or acceleration modifies the convection pattern
around the heater, such that the thermopiles in the direction of the acceleration become
hotter than the others. The analog circuitry interprets the resulting signal changes from
the thermopiles as motion and acceleration. With no moving parts, MEMSICs
accelerometers are longer-lasting, more reliable, and as much as 25 times more shockresistant (up to 100,000 g) than their mechanical counterparts for measuring tilt, inclination,
shock, or vibration. The chips appear in such products as car alarms, mobile electronics,
global positioning systems, elevator controls, patient monitoring devices and headmounted displays for gaming.
One Toolset for Analog and MEMS
Back in the 1990s our design center used Tanner tools, so we adopted them and have used
them ever since, explains MEMSICs Director of Technology Partnership and Development,
Yongyao Cai. Our accelerometers combine MEMS IP and analog circuitry IP, and the
Tanner tools are flexible enough for both our circuitry and the sensor. We model the
sensor as a resistor, and we can also model it as a polarized resistor because the thermopile
has a polarity. Tanner tools have been 100% reliable for us ever since we started using
them in 1999. Weve never had a tapeout error due to verification. For the current
generation of accelerometers, MEMSIC engineers use MEMS Pro, a tool from SoftMEMS
that sits on top of L-Edit for designing and analyzing MEMS. In fact, early MEMSIC products
were even simpler and did not require full mechanical simulation, so the MEMS designers
worked directly in L-Edit. The engineers at MEMSIC use MEMS Pro for 3D mechanical
model extraction for finite element analysis. They use L-Edit to modify the details of the
sensor, and to do layout and pattern list. After layout they use Tanner L-Edit LVS and LEdit Standard DRC. Finally, they export from L-Edit to a GDS layout file and send the
result to tapeout for TSMC.
MEMS Designs, CMOS Fabrication
To take advantage of lower fabrication costs, MEMSIC designs its sensors almost exclusively
with standard CMOS layers: for example, the heater is gate polysilicon and the first layer
of the thermopile is metal and polysilicon. We have a tremendous advantage over our
competitors, continues Yongyao. Our process is almost independent of the fabrication
foundry because our design is 95-99% CMOS. We can easily change process and foundry to
take advantage of better production pricing. Our competitors, on the other hand, use
proprietary MEMS processes, fabricating either by themselves or through a specialized
foundry, and that is always more expensive than working with a traditional CMOS
foundry. MEMSIC also enjoys an advantage when changing geometry. Most of its
competitors are still producing at 1-2 micron, and a change to .25 micron in MEMS would
result in a completely different process and a costly conversion. MEMSIC has produced in
.6 and .25 micron with .18 micron on the roadmap and its standard CMOS IC process
allows it to ramp up volume and production quickly after a change in geometry.
92,000 Accelerometers in Beijing
The marquee application of MEMSICs technology was in the electronic Waving Torch
distributed to all attendees of the opening ceremonies for the 2008 Olympics in Beijing.
The torch resembles a 20-30cm wand, with a linear array of LEDs. Shaken from side to side,
the torch tricks the human eye into seeing iconic Olympic images symbols for major
sports, the Olympic logo, Chinese greetings, and the five Olympic mascots displayed in
mid-air as the LEDs switch on and off. The core technology in the torch includes a MEMSIC
algorithm and accelerometer (designed with Tanner tools) to detect the users back-andforth hand movement and to fire each LED as needed for the image. We worked on this
Contd...
114
project for half a year as an Olympic promotional tool, says Yongyao. The user waves
the torch through the air, and the LEDs display the pattern according to the motion. Its a
good example of how much information an accelerometer can provide on position,
orientation and speed.
Notes
About MEMSIC
MEMSIC, Inc. designs, manufactures and markets CMOS Micro-Electro-Mechanical Systems
(MEMS) IC products that have on-chip mixed signal processing. MEMSIC is the first and
the only company that integrates a MEMS inertial sensor with mixed signal processing
circuitry onto a single chip using a standard CMOS IC process. This combination of
technology has successfully yielded products at substantially lower cost and higher system
performance and functionality than competitive products in the market for sophisticated
accelerometers. In addition, this technological approach allows the Company to easily
integrate additional functions, or create new sensors, using a standard CMOS IC process to
expand into other MEMS application areas beyond accelerometers. The Companys
accelerometers, sometimes called inertial sensors are used to measure tilt or inclination,
shock or vibration, or inertial acceleration. Any application that requires the control or
measurement of motion is a potential application for accelerometers.
About MEMS Pro
MEMS Pro is a tool suite from SoftMEMS LLC for designing and analyzing MEMS. Its
integration with Tanner and other tool suites shortens development time and provides
designers reliable analysis for manufacture. The MEMS Pro suite offers mixed MEMS/IC
schematic capture and simulation, full custom mask layout capability and verification, 3D
model generation and visualization, behavioral model creation, and links to 3D analysis
packages. SoftMEMS was founded in 2004 by Dr. Mary Ann Maher. The companys products
are based on the MEMS Pro software developed by Dr. Mahers team at Tanner Research in
1997 and the MEMS Xplorer software developed by Dr. Jean Michel Karams teams at
TIMA and MEMSCAP.
Questions:
1.
Discuss the hurdle handled by the company.
2.
Discuss the concept of MEMSPro.
Source: http://www.tannereda.com/memsic-cs
Self Assessment
14.
HTL is used in such environments where noise is very high.
15.
Two important characteristics of CMOS devices are low noise immunity and low static
power consumption.
7.8 Summary
An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one

small plate of semiconductor material, normally silicon.
There are two main advantages of ICs over discrete circuits: cost and performance.
Resistor-Transistor Logic (RTL) is a type of digital circuit built with the help of resistors as
the input network and bipolar junction transistors (BJTs) as switching devices.
115
Notes
A bipolar transistor switch is the simplest RTL gate.
The role of the base resistor is to expand the negligible transistor input voltage range
(about 0.7 V) to the logical 1 level (about 3.5 V) by converting the input voltage into
current.
The role of the collector resistor is to convert the collector current into voltage.
RTL technology had minimum number of transistors.
Multi-transistor RTL NOR gate consists of a set of parallel-connected transistor switches

driven by the logic inputs
Diodetransistor logic (DTL) is a class of digital circuits that is the direct ancestor of
transistortransistor logic.
The DTL propagation delay is relatively large.
Transistortransistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors.
TTL inputs are the emitters of a multiple-emitter transistor.
Emitter-Coupled Logic (ECL) is a high-speed integrated circuit bipolar transistor logic

family
Diffusion is the movement of impurity atoms in a semiconductor material at high

temperatures.
Ion implantation is the dominant technique to introduce dopant impurities into crystalline
silicon.
HTL is a high threshold logic based on the modified DTL circuit. It is a variant of DTL
which is used in such environments where noise is very high.
N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field

effect transistors (MOSFETs) to implement logic gates and other digital circuits.
Two important characteristics of CMOS devices are high noise immunity and low static
power consumption.
7.9 Keywords
Base Resistor: Converting the input voltage into current.
Diffusion: It is the movement of impurity atoms in a semiconductor material at high temperatures.
Diode-transistor Logic (DTL): It is a class of digital circuits that is the direct ancestor of transistortransistor logic.
Emitter-Coupled Logic (ECL): It is a high-speed integrated circuit bipolar transistor logic family.
HTL: It is a high threshold logic based on the modified DTL circuit. It is a variant of DTL which
is used in such environments where noise is very high.
IC: It is a set of electronic circuits on one small plate of semiconductor.
Ion implantation: It is the dominant technique to introduce dopant impurities into crystalline
silicon.
Multi-transistor RTL NOR Gate: It consists of a set of parallel-connected transistor switches
driven by the logic inputs.
116
Resistor-Transistor Logic (RTL): It is a type of digital circuit built with the help of resistors as
the input network and bipolar junction transistors (BJTs) as switching devices.
Notes
Transistortransistor Logic (TTL): It is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors.

1.
What is an IC?
2.
What are the advantages of IC?
3.
Discuss the pros and cons of RTL.
4.
Differentiate between one and multi transistor RTL.
5.
Give the manufacturing process of an IC.
6.
Compare RTL, DTL and TTL.
7.
Discuss the advantages and disadvantages of TTL.
8.
Explain the concept of ECL.
9.
What is CMOS?
10.
Differentiate between CMOS and TTL.

1.
False
2.
True
3.
True
4.
False
5.
Parallel
6.
DTL
7.
Complemented Transistor Diode Logic
8.
DTL
9.
TTL
10.
One
11.
Totem-pole
12.
True
13.
False
14.
True
15.
False
Books
A. P. Godse, Linear Integrated Circuits, U. A. Bakshi

B. S. Sonde, Introduction to System Design using Integrated Circuit
D Choudhury Roy, Linear Integrated Circuits
Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis & Design, Sung-Mo (Steve)
Kang
117
Notes
Online links
http://www.iue.tuwien.ac.at/phd/hollauer/node6.html
http://www.madehow.com/Volume-2/Integrated-Circuit.html
www.allaboutcircuits.com/
www.siliconfareast.com/testparams_cmos.htm
118
Unit 8: Memory
Unit 8: Memory
Notes
CONTENTS
Objectives
Introduction
8.1
Random Access Memory (RAM)
8.2
Read Only Memory (ROM)

8.2.1
Use for Storing Programs
8.2.2
Use for Storing Data
8.2.3
Types
8.3
Programmable Read Only Memory (PROM)
8.4
Erasable Programmable Read Only Memory (EPROM)

8.4.1
8.5
8.6
8.7
8.8
8.9
Cache Memory
Electrically Erasable Programmable Read Only Memory (EEPROM)

8.5.1
EEPROM Structure
8.5.2
EEPROM Limitations
Programmable Logic Array (PLA)

8.6.1
Minterms
8.6.2
Programming
Programmable Array Logic (PAL)

8.7.1
Programmable Logic Plane
8.7.2
Output Logic
Use of PAL and PLA in Combinational Circuit

8.8.1
Combinational Circuit Implementation with PLA
8.8.2
Summary
8.10 Keywords
Objectives
Explain random access memory
Elaborate upon read only memory
Explain the concept of programmable read only memory
Discuss the erasable programmable read only memory
119
Notes
Explain the electrically erasable programmable read-only memory
Elaborate upon the programmable logic array
Describe the programmable array logic
Discuss the use of PAL and PLA in combinational circuit
Introduction
Memory refers to the physical devices used to store a sequences of instructions or data on a
temporary or permanent basis for use in a computer or other digital electronic device. Primary
memory is used for the information in physical systems which function at high-speed (i.e.
RAM), as a distinction from secondary memory, which are physical devices for program and
data storage which are slow to access but offer higher memory capacity. Primary memory
stored on secondary memory is called virtual memory.
The term memory, meaning primary memory is often associated with addressable semiconductor
memory, i.e. integrated circuits consisting of silicon-based transistors, used for example as
primary memory but also other purposes in computers and other digital electronic devices.
There are two main types of semiconductor memory: volatile and non-volatile. Examples of
non-volatile memory are flash memory and ROM/PROM/EPROM/EEPROM memory.
Example of volatile memory are primary memory (typically dynamic RAM, DRAM),
and fast CPU cache memory (typically static RAM, SRAM, which is fast but energy-consuming
and offer lower memory capacity per area unit than DRAM).
Most semiconductor memory is organized into memory cells or bi stable flip-flops, each storing
one bit (0 or 1). Flash memory organization includes both one bit per memory cell and multiple
bits per cell (called MLC, Multiple Level Cell). The memory cells are grouped into words of
fixed word length, for example 1, 2, 4, 8, 16, 32, 64 or 128 bit. Each word can be accessed by a
binary address of N bit, making it possible to store 2N words in the memory. This implies that
processor registers normally are not considered as memory, since they only store one word and
do not include an addressing mechanism.
The term storage is often used to describe secondary memory such as tape, magnetic disks and
optical discs (CD-ROM and DVD-ROM).
8.1 Random Access Memory (RAM)

It is a form of computer data storage. A random-access device allows stored data to be accessed
directly in any random order. In contrast, other data storage media such as hard disks, CDs,
DVDs and magnetic tape, as well as early primary memory types such as drum memory, read
and write data only in a predetermined order, consecutively, because of mechanical design
limitations. Therefore the time to access a given data location varies significantly depending on
its physical location. Today, random-access memory takes the form of integrated circuits. Strictly
speaking, modern types of DRAM are not random access, as data is read in bursts, although the
name DRAM/RAM has stuck. However, many types of SRAM, ROM, OTP, and NOR flash are
still random access even in a strict sense. RAM is often associated with volatile types of memory
(such as DRAM memory modules), where its stored information is lost if the power is removed.
Many other types of non-volatile memory are RAM as well, including most types of ROM and
a type of flash memory called NOR-Flash.
120
Unit 8: Memory
Notes
Did u know? The first practical form of random-access memory was the Williams tube
starting in 1947.
The three main forms of modern RAM are static RAM (SRAM), dynamic RAM (DRAM) and
phase-change memory (PRAM). In SRAM, a bit of data is stored using the state of a flip-flop. This
form of RAM is more expensive to produce, but is generally faster and requires less power than
DRAM and, in modern computers, is often used as cache memory for the CPU. DRAM stores a bit
of data using a transistor and capacitor pair, which together comprise a memory cell. The
capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that
lets the control circuitry on the chip read the capacitors state of charge or change it. As this form
of memory is less expensive to produce than static RAM, it is the predominant form of computer
memory used in modern computers.
Both static and dynamic RAM are considered volatile, as their state is lost or reset when power
is removed from the system.
One can read and overwrite data in RAM. Many computer systems have a memory hierarchy
consisting of CPU registers, on-die SRAM caches, external caches, DRAM, paging systems and
virtual memory or swap space on a hard drive. This entire pool of memory may be referred to
as RAM by many developers, even though the various subsystems can have very different
access times, violating the original concept behind the random access term in RAM. Even within
a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave
organization of the components make the access time variable, although not to the extent that
rotating storage media or a tape is variable. The overall goal of using a memory hierarchy is to
obtain the higher possible average access performance while minimizing the total cost of the
entire memory system (generally, the memory hierarchy follows the access time with the fast
CPU registers at the top and the slow hard drive at the bottom).
In many modern personal computers, the RAM comes in an easily upgraded form of modules
called memory modules or DRAM modules about the size of a few sticks of chewing gum. These
can quickly be replaced should they become damaged or when changing needs demand more
storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated
in the CPU and other ICs on the motherboard, as well as in hard-drives, CD-ROMs, and several
other parts of the computer system.
Figure 8.1: Random Access Memory
Source: http://en.wikipedia.org/wiki/File:Memory_module_DDRAM_20-03-2006.jpg
Self Assessment
1.
Primary memory stored on secondary memory is called virtual memory.
2.
Static RAM is volatile while dynamic RAM is considered nonvolatile.
121
Notes
8.2 Read Only Memory (ROM)

It is a class of storage medium used in computers and other electronic devices. Data stored in
ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used
to distribute firmware (software that is very closely tied to specific hardware, and unlikely to
need frequent updates). ROM refers only to mask ROM (the oldest type of solid state ROM),
which is fabricated with the desired data permanently stored in it, and thus can never be modified.
Despite the simplicity, speed and economies of scale of mask ROM, field-programmability
often make reprogrammable memories more flexible and inexpensive. Other types of nonvolatile memory such as erasable programmable read only memory (EPROM) and electrically
erasable programmable read-only memory (EEPROM or Flash ROM) are sometimes referred
to, in an abbreviated way, as read-only memory (ROM); although these types of memory can
be erased and reprogrammed multiple times, writing to this memory takes longer and may
require different procedures than reading the memory. When used in this less precise way,
ROM indicates a non-volatile memory which serves functions typically provided by mask
ROM, such as storage of program code and nonvolatile data.
8.2.1
Use for Storing Programs
Every stored-program computer needs some form of non-volatile storage (that is, storage that
retains its data when power is removed) to store the initial program that runs when the computer
is powered on or otherwise begins execution (a process known as bootstrapping, often
abbreviated to booting or booting up). Likewise, every non-trivial computer needs some
form of mutable memory to record changes in its state as it executes.
Did u know? Forms of read-only memory were employed as non-volatile storage for
programs in most early stored-program computers, such as ENIAC after 1948 (until then
it was not a stored-program computer as every program had to be manually wired into
the machine, which could take days to weeks).
Read-only memory was simpler to implement since it needed only a mechanism to read stored
values, and not to change them in-place, and thus could be implemented with very crude
electromechanical devices With the advent of integrated circuits in the 1960s, both ROM and its
mutable counterpart static RAM were implemented as arrays of transistors in silicon chips;
however, a ROM memory cell could be implemented using fewer transistors than an SRAM
memory cell, since the latter needs a latch (comprising 5-20 transistors) to retain its contents,
while a ROM cell might consist of the absence (logical 0) or presence (logical 1) of one transistor
connecting a bit line to a word line. Consequently, ROM could be implemented at a lower costper-bit than RAM for many years.
Most home computers of the 1980s stored a BASIC interpreter or operating system in ROM as
other forms of non-volatile storage such as magnetic disk drives were too costly. For example,
the Commodore 64 included 64 KB of RAM and 20 KB of ROM contained a BASIC interpreter and
the KERNAL of its operating system. Later home or office computers such as the IBM PC XT
often included magnetic disk drives, and larger amounts of RAM, allowing them to load their
operating systems from disk into RAM, with only a minimal hardware initialization core and
bootloader remaining in ROM (known as the BIOS in IBM-compatible computers). This
arrangement allowed for a more complex and easily upgradeable operating system.
In modern PCs, ROM (or flash) is used to store the basic bootstrapping firmware for the main
processor, as well as the various firmware needed to internally control self contained devices
such as graphic cards, hard disks, DVD drives, TFT screens, etc., in the system. Today, many of
122
Unit 8: Memory
these read-only memories especially the BIOS are often replaced with Flash memory (see
below), to permit in-place reprogramming should the need for a firmware upgrade arise.
However, simple and mature sub-systems (such as the keyboard or some communication
controllers in the integrated circuits on the main board, for example) may employ mask ROM or
OTP (one-time programmable). ROM and successor technologies such as flash are prevalent in
embedded systems. These are in everything from industrial robots to home appliances and
consumer electronics (MP3 players, set-top boxes, etc.) all of which are designed for specific
functions, but are based on general-purpose microprocessors. With software usually tightly
coupled to hardware, program changes are rarely needed in such devices (which typically lack
hard disks for reasons of cost, size, or power consumption). As of 2008, most products use Flash
rather than mask ROM, and many provide some means for connecting to a PC for firmware
updates; for example, a digital audio player might be updated to support a new file format.
Some hobbyists have taken advantage of this flexibility to reprogram consumer products for
new purposes; for example, the iPodLinux and OpenWrt projects have enabled users to run fullfeatured Linux distributions on their MP3 players and wireless routers, respectively. ROM is
also useful for binary storage of cryptographic data, as it makes them difficult to replace, which
may be desirable in order to enhance information security.
8.2.2
Notes
Use for Storing Data
Since ROM (at least in hard-wired mask form) cannot be modified, it is really only suitable for
storing data which is not expected to need modification for the life of the device. To that end,
ROM has been used in many computers to store look-up tables for the evaluation of mathematical
and logical functions (for example, a floating-point unit might tabulate the sine function in
order to facilitate faster computation). This was especially effective when CPUs were slow and
ROM was cheap compared to RAM.
Notably, the display adapters of early personal computers stored tables of bitmapped font
characters in ROM. This usually meant that the text display font could not be changed interactively.
This was the case for both the CGA and MDA adapters available with the IBM PC XT.
The use of ROM to store such small amounts of data has disappeared almost completely in
modern general-purpose computers. However, Flash ROM has taken over a new role as a
medium for mass storage or secondary storage of files.
8.2.3
Types
Classic mask-programmed ROM chips are integrated circuits that physically encode the data to
be stored, and thus it is impossible to change their contents after fabrication. Other types of nonvolatile solid-state memory permit some degree of modification.
Figure 8.2: The First EPROM, an Intel 1702, with the Die and Wire Bonds
Clearly Visible Through the Erase Window.
Source: http://en.wikipedia.org/wiki/File:EPROM_Intel_C1702A.jpg
123
Notes
Some of the semiconductor based examples include:

Programmable Read-Only Memory (PROM): It can be written to or programmed via a special
device called a PROM programmer. Typically, this device uses high voltages to permanently
destroy or create internal links (fuses or antifuses) within the chip. Consequently, a PROM can
only be programmed once.
Erasable Programmable Read-Only Memory (EPROM): It can be erased by exposure to strong
ultraviolet light (typically for 10 minutes or longer), then rewritten with a process that again
needs higher than usual voltage applied. Repeated exposure to UV light will eventually wear
out an EPROM, but the endurance of most EPROM chips exceeds 1000 cycles of erasing and
reprogramming. EPROM chip packages can often be identified by the prominent quartz window
which allows UV light to enter. After programming, the window is typically covered with a
label to prevent accidental erasure. Some EPROM chips are factory-erased before they are
packaged, and include no window; these are effectively PROM.
Electrically Erasable Programmable Read-Only Memory (EEPROM): It is based on a similar
semiconductor structure to EPROM, but allows its entire contents (or selected banks) to be
electrically erased, then rewritten electrically, so that they need not be removed from the computer
(or camera, MP3 player, etc.). Writing or flashing an EEPROM is much slower (milliseconds per
bit) than reading from a ROM or writing to a RAM (nanoseconds in both cases).
Electrically alterable read-only memory (EAROM) is a type of EEPROM that can be modified
one bit at a time. Writing is a very slow process and again needs higher voltage (usually
around 12 V) than is used for read access. EAROMs are intended for applications that
require infrequent and only partial rewriting. EAROM may be used as non-volatile storage
for critical system setup information; in many applications, EAROM has been supplanted
by CMOS RAM supplied by mains power and backed-up with a lithium battery.
Flash memory (or simply flash) can be erased and rewritten faster than ordinary EEPROM,
and newer designs feature very high endurance (exceeding 1,000,000 cycles). Modern
NAND flash makes efficient use of silicon chip area, resulting in individual ICs with a
capacity as high as 32 GB as of 2007; this feature, along with its endurance and physical
durability, has allowed NAND flash to replace magnetic in some applications (such as
USB flash drives). Flash memory is sometimes called flash ROM or flash EEPROM when
used as a replacement for older ROM types, but not in applications that take advantage of
its ability to be modified quickly and frequently.
Did u know? Flash memory is a modern type of EEPROM invented in 1984.
By applying write protection, some types of reprogrammable ROMs may temporarily become
read-only memory.
Self Assessment
Fill in the blanks:
3.
........................ can be written to or programmed via a special device called a PROM

programmer.
4.
........................ is a type of EEPROM that can be modified one bit at a time.
8.3 Programmable Read Only Memory (PROM)

A programmable read-only memory (PROM) or field programmable read-only memory (FPROM)
or one-time programmable non-volatile memory (OTP NVM) is a form of digital memory
124
Unit 8: Memory
where the setting of each bit is locked by a fuse or antifuse. Such PROMs are used to store
programs permanently. The key difference from a strict ROM is that the programming is applied
after the device is constructed.
Notes
PROMs are manufactured blank and, depending on the technology, can be programmed at
wafer, final test, or in system. The availability of this technology allows companies to keep a
supply of blank PROMs in stock, and program them at the last minute to avoid large volume
commitment. These types of memories are frequently seen in video game consoles, mobile
phones, radio-frequency identification (RFID) tags, implantable medical devices, high-definition
multimedia interfaces (HDMI) and in many other consumer and automotive electronics products.
Did u know? The PROM was invented in 1956 by Wen Tsing Chow, working for the Arma
Division of the American Bosch Arma Corporation in Garden City, New York.
A typical PROM comes with all bits reading as 1. Burning a fuse bit during programming
causes the bit to read as 0. The memory can be programmed just once after manufacturing by
blowing the fuses, which is an irreversible process. Blowing a fuse opens a connection while
programming an antifuse closes a connection (hence the name). While it is impossible to unblow
the fuses, it is often possible to change the contents of the memory after initial programming by
blowing additional fuses, changing some remaining 1 bits in the memory to 0s. (Once all of
the bits are 0, no further programming change is possible.)
The bit cell is programmed by applying a high-voltage pulse not encountered during normal
operation across the gate and substrate of the thin oxide transistor (around 6V for a 2 nm thick
oxide, or 30MV/cm) to break down the oxide between gate and substrate. The positive voltage
on the transistors gate forms an inversion channel in the substrate below the gate, causing a
tunneling current to flow through the oxide. The current produces additional traps in the oxide,
increasing the current through the oxide and ultimately melting the oxide and forming a
conductive channel from gate to substrate. The current required to form the conductive channel
is around 100A/100nm2 and the breakdown occurs in approximately 100s or less.
Figure 8.3: PROM
Source: http://www.ustudy.in/node/2921
Self Assessment
5.
A programmable read-only memory (PROM) is used to store programs permanently.
6.
A typical PROM comes with all bits reading as 0.
125
Notes
8.4 Erasable Programmable Read Only Memory (EPROM)

An EPROM or erasable programmable read only memory, is a type of memory chip that retains
its data when its power supply is switched off. In other words, it is non-volatile. It is an array of
floating-gate transistors individually programmed by an electronic device that supplies higher
voltages than those normally used in digital circuits. Once programmed, an EPROM can be
erased by exposing it to strong ultraviolet light source (such as from a mercury-vapor light).
EPROMs are easily recognizable by the transparent fused quartz window in the top of the
package, through which the silicon chip is visible, and which permits exposure to UV light
during erasing.
EPROM chips are of two types one in which the stored information is erased by exposing the
chip for some time of ultraviolet light and the other one in which the stored information is
erased by using high voltage electric pulses is known as Ultra Violet EPROM (UVEPROAM) and
the latter is known as Electrically EPROM (EEPROM).
Figure 8.4: EPROM
Source: http://touque.ca/EC/ICS2O/students/2010-09/ICS2O7C/ShaoZ/culminatingassignment.html
8.4.1
Cache Memory
The Cache Memory is the Memory which is very nearest to the CPU. All the recent instructions
are stored into the cache memory. The cache memory is attached for storing the input which is
given by the user and which is necessary for the CPU to perform a task. But the capacity of the
cache memory is too low in compare to memory and hard disk. The cache memory lies in the
path between the processor and the memory. The cache memory therefore, has lesser access
time than memory and is faster than the main memory. A cache memory have an access time of
100ns, while the main memory may have an access time of 700ns. The cache memory is very
expensive and hence is limited in capacity. Earlier cache memories were available separately
but the microprocessors contain the cache memory on the chip itself. The need for the cache
memory is due to the mismatch between the speeds of the main memory and the CPU. The CPU
clock as discussed earlier is very fast, whereas the main memory access time is comparatively
slower. Hence, no matter how fast the processor is, the processing speed depends more on the
speed of the main memory (the strength of a chain is the strength of its weakest link). It is
because of this reason that a cache memory having access time closer to the processor speed is
introduced. The cache memory stores the program (or its part) currently being executed or
which may be executed within a short period of time. The cache memory also stores temporary
data that the CPU may frequently require for manipulation. The cache memory works according
to various algorithms, which decide what information it has to store. These algorithms work
out the probability to decide which data would be most frequently needed. This probability is
worked out on the basis of past observations. It acts as a high speed buffer between CPU and
main memory and is used to temporary store very active data and action during processing
since the cache memory is faster than main memory, the processing speed is increased by
making the data and instructions needed in current processing available in cache. The cache
memory is very expensive and hence is limited in capacity.
126
Unit 8: Memory
Figure 8.5: Cache Memory
Notes
Source: http://computerfuns.blogspot.in/2012/02/what-is-cache-memory.html
Self Assessment
7.
An EPROM or erasable programmable read only memory, is a type of memory chip that
does not retain its data when its power supply is switched off.
8.
The cache memory is very expensive and is limited in capacity.
8.5 Electrically Erasable Programmable Read Only Memory

(EEPROM)
Electrically Erasable Programmable Read-Only Memory (EEPROM) is a stable, non-volatile
memory storage system that is used for storing minimal data quantities in computer and electronic
systems and devices, such as circuit boards. This data may be stored, even without a permanent
power source, as device configuration or calibration tables. If storing higher volumes of data
that is static (like in USB drives), certain types of EEPROM (like flash memory) are more costeffective than conventional EEPROM devices.
8.5.1
EEPROM Structure
The EEPROM chip is physically similar to the EPROM chip. It is also composed of cells with two
transistors. The floating gate is separated from the control gate by a thin oxide layer. Unlike the
EPROM chip, however, the EEPROM chips oxide layer is much thinner. In EEPROM chips, the
insulating layer is only around 1 nanometre thick whereas in EPROM chips, the oxide layer is
around 3 nanometres thick. The thinner oxide layer means lower voltage requirements for
initiating changes in cell value
8.5.2
EEPROM Limitations
While the EEPROM can be reprogrammed, the number of times it can be altered is limited. This
is the main reason why EEPROM chips are popular for storing only configuration data such as
the computers BIOS code which doesnt require frequent reprogramming. The oxide insulating
layer can be damaged by frequent rewrite. Modern-day EEPROMs can be rewritten up to a
million times.
127
Notes
Self Assessment
Fill in the blanks:
9.
EEPROM is a ........................ memory that retains its data even if the power goes off.
10.
In EEPROM chips, the insulating layer is only around ........................ nanometer thick.
8.6 Programmable Logic Array (PLA)

A programmable logic array (PLA) is a kind of programmable logic device used to implement
combinational logic circuits. The PLA has a set of programmable AND gate planes, which link
to a set of programmable OR gate planes, which can then be conditionally complemented to
produce an output. This layout allows for a large number of logic functions to be synthesized in
the sum of products (and sometimes product of sums) canonical forms. Manufacturers can build
PLA devices that designers can use instead of building from simple gates. A PLA programming
device can permanently break fuses to implement the desired logic circuit.
Figure 8.6 : Programmable Array Block for SOP
Source: http://www.cs.washington.edu/education/courses/cse370/99au/lectures/au99-05/au99-05.pdf
Many PLAs are One Time Programmable (OTP). Each input to the AND gates goes through a
fuse that can be permanently broken or blown. If the fuse is broken, that input value does not
go to that AND gate. The OR gate inputs also go through a set of fuses.
Figure 8.7: General Form of Programmable Function Device
Inputs are available in their true as well as inverted (complementary) forms. This is an important
development since all possibilities of inputs are available readily. The user can now put links
and construct the desired function. Putting the link ( or removing it) is called as programming
the device.
128
Unit 8: Memory
Notes
Example: PLA as ROM
Figure 8.8: PLA as ROM
Advantages
A PLA can have large N and M permitting implementation of equations that are impractical
for a ROM.
A PLA has all of its product terms connectable to all outputs, overcoming the problem of
the limited inputs to the PAL.
Some PLAs have outputs that can be complemented, adding POS functions.
Disadvantages
Often, the product term count limits the application of a PLA.
Two-level multiple-output optimization is required to reduce the number of product

terms in an implementation, helping to fit it into a PLA.
Multi-level circuit capability available in PAL not available in PLA. PLA requires external
connections to do multi-level circuits.
8.6.1
Minterms
Given n variables, it would seem necessary to have 2n vertical wires (for the AND gates), one for
each possible minterm. However, 2n grows very quickly. So, sometimes there are not 2n vertical
wires.
8.6.2
Programming
Let us explain the programming through an example:

Example: Implementing a Combinational Circuit Using a PLA: 3-input, 2-output PLA
with 4 product terms.
129
F1 = m(3, 5, 6, 7)
Notes
F2 = m(1, 2, 3, 7)
Figure 8.9: K maps
Source:www1.ju.edu.jo/ecourse/abusufah/.../16-Programmable%20Logic.ppt
5 product terms:
F1 = A.B + A.C + B.C
F2 = A.B + A.C + B.C
4 product terms:
F1
= A.BC
. + A.B.C + B.C
F2 = A.B.C + A.B.C + B.C

Figure 8.10: Circuit diagram
Source: www1.ju.edu.jo/ecourse/abusufah/.../16-Programmable%20Logic.ppt
Task Draw a logic circuit for the fire alarm.
130
Unit 8: Memory
Notes
Self Assessment
11.
A programmable logic array is a kind of programmable logic device used to implement

combinational logic circuits.
12.
Multi-level circuit capability is available in PLA.
13.
A PLA has all of its product terms connectable to all outputs, overcoming the problem of
the limited inputs to the PAL.
8.7 Programmable Array Logic (PAL)

Programmable Array Logic (PAL) is a family of programmable logic device semiconductors
used to implement logic functions in digital circuits.
Did u know? PAL was introduced by Monolithic Memories, Inc. (MMI) in March 1978. MMI
obtained a registered trademark on the term PAL for use in Programmable Semiconductor
Logic Circuits. The trademark is currently held by Lattice Semiconductor.
PAL devices consisted of a small PROM (programmable read-only memory) core and additional
output logic used to implement particular desired logic functions with few components. Using
specialized machines, PAL devices were field-programmable. Each PAL device was onetime programmable (OTP), meaning that it could not be updated and reused after its initial
programming. (MMI also offered a similar family called HAL, or hard array logic, which
were like PAL devices except that they were mask-programmed at the factory.)
Figure 8.11: Simplified Programmable Logic Device
Source: http://en.wikipedia.org/wiki/File:Programmable_Logic_Device.svg
The PAL architecture consists of two main components: a logic plane and output logic macrocells.
8.7.1
Programmable Logic Plane
The programmable logic plane is a programmable read-only memory (PROM) array that allows
the signals present on the devices pins (or the logical complements of those signals) to be routed
to an output logic macrocell. PAL devices have arrays of transistor cells arranged in a fixed-OR,
programmable-AND plane used to implement sum-of-products binary logic equations for
each of the outputs in terms of the inputs and either synchronous or asynchronous feedback
from the outputs.
131
Notes
8.7.2
Output Logic
The early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be
registered or combinational. Members of the PAL family were available with various output
structures called output logic macrocells or OLMCs. Prior to the introduction of the V (for
variable) series, the types of OLMCs available in each PAL were fixed at the time of
manufacture. (The PAL16L8 had 8 combinational outputs and the PAL16R8 had 8 registered
outputs. The PAL16R6 had 6 registered and 2 combinational while the PAL16R4 had 4 of each.)
Each output could have up to 8 product terms (effectively AND gates), however the combinational
outputs used one of the terms to control a bidirectional output buffer. There were other
combinations that had fewer outputs with more product terms per output and were available
with active high outputs. The 16X8 family or registered devices had an XOR gate before the
register. There were also similar 24-pin versions of these PALs.
This fixed output structure often frustrated designers attempting to optimize the utility of PAL
devices because output structures of different types were often required by their applications.
For example, one could not get 5 registered outputs with 3 active high combinational outputs.)
So, in June 1983 AMD introduced the 22V10, a 24 pin device with 10 output logic macrocells. Each
macrocell could be configured by the user to be combinational or registered, active high or
active low. The number of product terms allocated to an output varied from 8 to 16. This one
device could replace all of the 24 pin fixed function PAL devices. Members of the PAL V
(variable) series included the PAL16V8, PAL20V8 and PAL22V10.
Self Assessment
Fill in the blanks:
14.
........................ is a family of programmable logic device semiconductors used to implement

logic functions in digital circuits.
15.
The PAL architecture consists of two main components: a ........................ and ...................... .
8.8 Use of PAL and PLA in Combinational Circuit

The elements of Boolean algebra (two-element switching algebra) and how the operations in
Boolean algebra can be represented schematically by means of gates (primitive devices). How
switching expressions can be manipulated and represented in different ways was the subject
which also presented various ways of implementing such representations in a variety of circuits
using primitive gates. With all of the tools for the purpose now in hand, The design of more
complex logic circuits. Circuits in which all outputs at any given time depend only on the inputs
at that time are called combinational logic circuits. The design procedures will be illustrated
with important classes of circuits that are now universal in digital systems. The approach taken
is to examine the tasks that a combinational logic circuit is instated to perform and then identify
one or more circuits that can perform the task. One circuit may have some specific advantages
over others, but it may also have certain deficiencies. Often one factor can be improved, but only
at the expense of others. Some important factors are speed of operation, complexity or cost of
hardware, power dissipation, and availability in prefabricated units.
8.8.1
Combinational Circuit Implementation with PLA

Example: A combinational circuit is defined by the functions
F1 (A, B, C) = 3(3, 5, 6, 7)
F2 (A, B, C) = 3(0, 2, 4, 7)
132
Unit 8: Memory
Implement the circuits with PLA having three inputs, four product terms, and two outputs.
Notes
Table 8.1: Simplification with PLA
Source: www2.southeastern.edu/Academics/Faculty/galkadi/297/.../chapter5.doc
Table 8.2 Program Table
8.8.2
Example: Using a PAL in the design of a combinational circuit, consider the following
Boolean functions given in sum of minterms:
w(A, B, C, D) = 3(2, 12, 13)
x (A, B, C, D) = 3(7, 8, 9, 10, 11, 12, 13, 14, 15)
y (A, B, C, D) = 3(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z (A, B, C, D) = 3(1, 2, 8, 12, 13)
Table 8.3 Simplification with PAL
Contd...
133
Notes
Table 8.4: PAL Programmable Table
The table is divided into 4 sections with three products in each. The first two sections need only
two product terms to implement the Boolean function. The last two sections need three product
terms. (Function w was reduced to 3 terms.) For each 1 or 0 in the table, we mark the corresponding
intersection in the diagram with the symbol for an intact fuse. For each dash, we mark the
diagram with blown fuses in both the true and complement inputs. If the AND gates is not used,
we leave its input fuses intact.
134
Unit 8: Memory
Case Study
Notes
Fine Soft Studio Memory Management
ine Soft Studio developed one of the most efficient memory manager in the world.
Applications that use our memory manager show striking improvement of runtime
performance, especially on multiprocessor platforms.
Business Description
Existing hardware is constantly improving. Multiprocessors and CPUs with more than
one core becoming usual things. From new applications are expected to use efficiently the
possibilities of coming hardware. One of the most important system components is Memory
Manager. The part of the system that manages program memory so that the program can
run most efficiently. Modern programs have object-oriented, multithreaded architectures
which put a lot of pressure on memory manager. For web applications hit processing time
is measured in milliseconds, so it is very important to have optimized each component of
the system. About 20% of CPU time is spent for managing memory. The application
memory manager must keep it up with minimum of CPU overhead, and the total memory
used. But existing memory managers have not cope with this goals adequately especially
when running on multi-CPU ore multi-core modern hardware.
Existing memory managers are not able to get most of computer hardware and substantially
limit hardware scalability. When we add new processor, or additional core to CPU
programs slow down. Instead of expected linear increase runtime performance decreases
because memory managers have memory locking problems. If two threads request a
memory at the same time, the memory manager must enqueue the requests before
processing them. One thread must wait for another threads request to be processed. This
serialization step is a large performance barrier, resulting in scaling problems. The
challenge was to build own memory manager which ensures increasing of application
runtime performance when new CPU is added and which must be memory space efficient
and very fast.
Solution and Key Benefits
We developed our own memory manager. It uses advanced memory management
algorithm.
The key benefits of our memory manager are:
it does not use critical sections (uses no-blocking algorithm)
it does not require CPU context switching
Memory Manager 100% effectively consumes all CPUs which are in system
Memory Manager does not have performance degradation when CPU count increases
(performance of other memory managers either do not increase or even decrease
when CPU count increase) optimized work with memory blocks of any size even
after long time of work memory is not fragmented.
It is very important for web applications, or for applications which should run for
long time without restart like database servers, operation systems, etc.
Memory Manager has built-in logic to capture memory leaks and do memory dumps
to see memory disposition/reallocations during application execution
Contd...
135
Notes
You do not need to make any changes in your existing code to use our Memory
Manager
Test Application
Application creates a specified number of threads. Each thread executes same actions
(emulating memory manager real usage): randomly selects pointer from an array and
allocates block of memory if pointer is not assigned or frees memory if pointer is assigned.
Size of the memory block is random within defined margins. Application calculates total
number of memory block allocations and releases in millions per sec. Resulting value is
the maximum value achieved during specified period (higher is better).
Test system configuration: CPU Inter Core 2 Quad (4 cores), OS Windows Server 2003
memory manager in .NET by default initializes allocated memory block to zeros.
In diagram we showed extrapolated values to eliminate this factor. Real values are
about 25% less.
Testing Results
Testing Results Analysis

As you may see from the table above our Memory Manager shows dramatic performance
increase even for single threaded mode and perfect scalability for multithreaded mode on
multiprocessor/multicore system. The closest competitor MS NET 2.0 shows 2 times less
performance even for single threaded mode and much less scalability. Other memory
managers shows even performance degradation when running in multithreaded mode.
Contd...
136
Unit 8: Memory
Notes
Testing Results on 16 Cores System

As a Partner in Intel Software Partner Program we got access to latest hardware platforms
and tested our Memory Manager on 16 Cores system (4 CPU Intel Xeon, 4 Cores each).
Performance increase of our application running on such system reached unbelievable
15.5 times!
Conclusion
It is just not acceptable to lose so much of hardware power just because of imperfect
software. We pay much attention to optimization of each system level component, and
this allows us to reach high level of performance and speed.
Questions:
1.
Discuss the benefits of memory manager.
2.
Discuss the concept of test application.
Source: http://finestudio.net/Projects/MemoryManager/
8.9 Summary
Memory refers to the physical devices used to store a sequences of instructions or data on
a temporary or permanent basis for use in a computer or other digital electronic device.
Primary memory is used for the information in physical systems which function at highspeed.
Secondary memory, which are physical devices for program and data storage which are
slow to access but offer higher memory capacity.
Primary memory stored on secondary memory is called virtual memory.
There are two main types of semiconductor memory: volatile and non-volatile.
Most semiconductor memory is organized into memory cells or bi stable flip-flops, each
storing one bit (0 or 1).
Each word can be accessed by a binary address of N bit, making it possible to store 2 N
words in the memory.
A random-access device allows stored data to be accessed directly in any random order.
Both static and dynamic RAM are considered volatile, as their state is lost or reset when
power is removed from the system.
The three main forms of modern RAM are static RAM (SRAM), dynamic RAM (DRAM) and
phase-change memory (PRAM).
ROM is a class of storage medium used in computers and other electronic devices. Data
stored in ROM cannot be modified, or can be modified only slowly or with difficulty.
Nonvolatile memory is used to store the initial program that runs when the computer is
powered on or otherwise begins execution (a process known as bootstrapping, often
abbreviated to booting or booting up).
Programmable read-only memory (PROM): It can be written to or programmed via a

special device called a PROM programmer.
Erasable programmable read-only memory (EPROM): It can be erased by exposure to

strong ultraviolet light.
137
Notes
Electrically erasable programmable read-only memory (EEPROM): It is based on a similar

semiconductor structure to EPROM, but allows its entire contents (or selected banks) to be
electrically erased, then rewritten electrically, so that they need not be removed from the
computer (or camera, MP3 player, etc.).
Electrically alterable read-only memory (EAROM) is a type of EEPROM that can be modified
one bit at a time.
Flash memory can be erased and rewritten faster than ordinary EEPROM.
A programmable read-only memory (PROM) is used to store programs permanently.
An EPROM or erasable programmable read only memory, is a type of memory chip that
retains its data when its power supply is switched off.
EPROM can be of two types: EEPROM and UVEPROAM.
Electrically Erasable Programmable Read-Only Memory (EEPROM) is a stable, non-volatile

memory storage system that is used for storing minimal data quantities in computer and
electronic systems and devices.
A programmable logic array (PLA) is a kind of programmable logic device used to

implement combinational logic circuits.
Programmable Array Logic (PAL) is a family of programmable logic device semiconductors

used to implement logic functions in digital circuits.
8.10 Keywords
Booting: The initial program that runs when the computer is powered on or otherwise begins
execution.
Electrically Alterable Read-only Memory (EAROM): It is a type of EEPROM that can be modified
one bit at a time.
Electrically Erasable Programmable Read-Only Memory (EEPROM): It is based on a similar
semiconductor structure to EPROM.
Erasable Programmable Read-Only Memory (EPROM): It can be erased by exposure to strong
ultraviolet light.
Primary Memory: It is used for the information in physical systems which function at highspeed.
Programmable Read-Only Memory (PROM): It can be written to or programmed via a special
device called a PROM programmer.
Secondary Memory: They are physical devices for program and data storage which are slow to
access but offer higher memory capacity.
Virtual Memory: It is Primary memory stored on secondary memory.
138
1.
Explain the concept of RAM.
2.
What are the uses of ROM?
3.
Explain the types of ROM.
4.
Differentiate between PROM and EPROM.
Unit 8: Memory
Notes
5.
Why do we need cache memory?
6.
What is EEPROM?
7.
Explain the concept of PLA.
8.
Give the advantages and limitations of PLA.
9.
What is PAL?
10.
Explain the use of PAL and PLA in Combinational Circuit with the help of an example.

1.
True
2.
False
3.
PROM
4.
EAROM
5.
True
6.
False
7.
False
8.
True
9.
Non volatile
10.
One
11.
True
12.
False
13.
True
14.
PAL
15.
Logic plane, Output logic macrocell
Books
Brian Holdsworth and Clive Woods, Digital Logic Design, 4th Edition, Newnes
publication
Nigel P. Cook, Digital Electronics with PLD Integration
R. P. Jain, Modern Digital Electronics, Tata McGraw-Hill Education
Ray Ryan, Basic Digital Electronics
Online links
http://touque.ca/EC/ICS2O/students/2010-09/ICS2O7C/ShaoZ/
culminatingassignment.html
http://www.cs.washington.edu/education/courses/cse370/99sp/lectures/03CombImpl/sld061.htm
http://www.google.com/patents/US5088060
www2.southeastern.edu/Academics/Faculty/galkadi/297/.../chapter5.doc
139
Notes
Unit 9: Flip-Flops
CONTENTS
Objectives
Introduction
9.1
Basic Flip-Flop Circuit
9.2
Types of Flip-Flop
9.2.1
Clocked SR Flip-Flop
9.2.2
JK Flip-Flop
9.2.3
T Flip-Flop (Toggle)
9.2.4
D Flip-Flop (Delay)
9.3
Master-Slave Flip-Flop
9.4
Triggering of Flip-Flop
9.4.1
High Level Triggering
9.4.2
Low Level Triggering
9.4.3
Positive Edge Triggering
9.4.4
Negative Edge Triggering
9.4.5
Clock Pulse Transition
9.5
Timing Signal
9.6
Summary
9.7
Keywords
9.8
Review Questions
9.9
Further Readings
Objectives
Explain flip-flop circuits
Elaborate upon the types of flip-flop
Discuss the master slave flip-flop
Explain triggering of flip-flops
Describe the timing signal
Introduction
Flip-flop or latch is a circuit that has two stable states and can be used to store state information.
A flip-flop is a bi stable multi vibrator. The circuit can be made to change state by signals
applied to one or more control inputs and will have one or two outputs. It is the basic storage
element in sequential logic. Flip-flops and latches are a fundamental building block of digital
140
Unit 9: Flip-Flops
electronics systems used in computers, communications, and many other types of systems. Flipflops and latches are used as data storage elements. Such data storage can be used for storage of
state, and such a circuit is described as sequential logic. When used in a finite-state machine, the
output and next state depend not only on its current input, but also on its current state (and
hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variablytimed input signals to some reference timing signal. Flip-flops can be either simple (transparent
or opaque) or clocked (synchronous or edge-triggered); the simple ones are commonly called
latches. The word latch is mainly used for storage elements, while clocked devices are described
as flip-flops.
Notes
9.1 Basic Flip-Flop Circuit

A basic Flip-Flop circuit can be constructed in two ways.
Using two NOR gates
Using two NAND gates
We know that a flip-flop circuit consists of two inputs set(S) and reset(R), two outputs Q and Q.
A cross coupled connection is given between output of one gate and the input of the other gate.
Such type of cross coupled connection constitutes the feedback path for the flip-flops. These flipflops are called direct coupled RS Flip flops (or) SR latch.
Table 9.1: Truth Table of a NOR Gate
Source: http://www.brighthubengineering.com/diy-electronics-devices/46608-an-elementary-flip-flop-circuit-explored/#imgn_0
From the truth table it is evident that the output of a NOR gate is zero if any of the input is 1 and
the output is 1 only if both the inputs of the gate is 0. Now to analyze the circuit let us assume that
the SET input = 1 and RESET input = 0. For convenience let the Set input be S and Reset input be
R. We know that if any input of NOR gate is 1 then its output is 0. Therefore when S=1, the output
of the gate corresponding to S becomes 0. So Q becomes 0. This Q is given as an input (Cross
coupled connection) along with R to the other gate. So the output of the second gate, Q becomes
1 (since both R and Q are 0).
Conclusion 1: When S=1 and R=0. The outputs Q=0 and Q=1.
Figure 9.1: Basic Flip Flop Circuit Diagram and Truth Table
Now when the set input(S) returns to 0, the output remains the same. This is because the output
of Q is 1. Now the inputs to gate 2 are S=0 and Q=1. So from the truth table of NOR gate we can
say that Q=0.
141
Notes
Conclusion 2: When S=0, R=0. The outputs Q=0 and Q=1.

Similarly let us assume S=0 and R=1.When R=1, its corresponding output Q becomes zero. Since
both S and Q are zero the output Q becomes 1.
Now when R returns to 0, the output still remains the same, because the other input to Q=1.
So from the NOR truth table we can deduce that Q=0.
Now what happens when both Set and Reset inputs are given 1. When both S and R are given a
value of 1, both the output becomes 0 which is not possible. Both the outputs cannot be 0 because
we already know that the output of flip-flops are complementary to each other, one output is the
complement of the other one. So we must ensure that this state is avoided and 1s are not applied
to both inputs simultaneously, during the normal operation of flip-flops.
So following points can be deduced:
The outputs of the Flip-Flops Q and Q are complements of each other and same value
cannot be obtained for both outputs. The value of normal output is nothing but the binary
state of the flip-flop.
Both the inputs of Flip-flop remains at 0 unless the state is changed by applying external
pulse. When a pulse is applied to set input the flip-flop enters SET state and when a
momentary pulse is applied to Reset input, the flip-flop enters CLEAR state. But we
should make sure that the momentary pulse applied to set input goes back to zero before
a pulse applied to reset input. When both the inputs are given a momentary pulse at same
time, both the outputs become zero which is an undefined state and must be avoided.
The Flip-flop consists of two useful states, The SET and The CLEAR state. When Q=1 and
Q=0, the flip-flop is said to be in SET state. Similarly when Q=0 and Q=1, the flip flop is
said to be in CLEAR state.
Similarly a flip-flop with two NAND gates can be formed. The truth table and logic diagram is
shown below:
Figure 9.2: Circuit Diagram and Truth Table of a Basic Flip Flop with NAND Gates
Did u know? The first electronic flip-flop was invented in 1918 by William Eccles and F. W.
Jordan.
142
Unit 9: Flip-Flops
Notes
Self Assessment
Fill in the blanks:
1.
A basic Flip-Flop circuit can be constructed in two ways: using two........................ gates or
using two ........................ gates.
2.
The outputs of the Flip-Flops Q and Q are ........................ of each other.
3.
Both the inputs of Flip-flop remains at ........................ unless the state is changed by applying
external pulse.
4.
The Flip-flop consists of two useful states, the ........................ and the ........................ state.
9.2 Types of Flip-Flop

Flip flops are type casted as per the number of inputs they take in and the manner in which they
affect the binary state of the flip-flop.
9.2.1
Clocked SR Flip-Flop
The clocked RS flip-flop is like an SR flip-flop but with an extra third input of a standard clock
pulse CLK.
Figure 9.3: Logic Symbol of SR Flip Flop
Source: www.goiit.com/.../5cf08ffb6b07db824ff98c9674b090d7_1302852.doc
Figure 9.4: Circuit Diagram and Truth Table of SR Flip Flop with NOR Gates
Source: http://www.circuitstoday.com/flip-flops
143
Notes
A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is
02, the outputs of both the AND Gates remain 02. As soon as a pulse is given the value of CP
turns 12. This makes the values at S and R to pass through the NOR Gate flip flop. But when the
values of both S and R values turn 12, the HIGH value of CP causes both of them to turn to 02
for a short moment. As soon as the pulse is removed, the flip flop state becomes intermediate.
Thus either of the two states may be caused, and it depends on whether the set or reset input of
the flip-flop remains a 12 longer than the transition to 02 at the end of the pulse. Thus the
invalid states can be eliminated.
It can also be implemented using NAND gates as shown below:
Figure 9.5: Circuit Diagram of SR Flip Flop with NAND Gates
Bearing in mind that the NAND implementation of an SRFF is driven by 0s then it can be seen
that the extra two NAND gates in front of the standard SRFF circuitry mean that the circuit will
function as a usual SRFF when S or R are 1 and the clock pulse is also 1 (high). Therefore this
flip-flop is synchronous. Specifically, a 0 to 1 transition on either of the inputs S or R will only be
seen at the output if the clock is 1. An example timing diagram is given below:
Figure 9.6: Timing Diagram of SR Flip
9.2.2
JK Flip-Flop
The JK type flip-flop consists of two data inputs: J and K, and one clock input. There are again
two outputs Q and Q (where Q is the reverse of Q).
Figure 9.7: Block Diagram of JK Flip
Source: http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/06-FlipFlops/
144
Unit 9: Flip-Flops
Table 9.2: Truth Table of JK Flip
Notes
A.
When J=K=0, the current output will carry through to the next state. For example Current
state Q = Next state Q
B.
When J=0 and K=1, the next state output will be put to 0. This happens regardless of the
present state output.
C.
When J=1 and K=0, the next state output will be asserted (put to 1). This happens regardless
of the present state output.
D.
When J=K=1, the next state output will be the inverse of the current state output. For
example Current state Q = Next state Q.
Knowing the above we can now construct the state change table:
Table 9.3: Truth Table of JK Flip
There actually exists two operating characteristics that satisfy every possible output combination.
This means there should be some dont care terms with each output combination (as our
diagram shows). In the list below we shall see how each of the terms:
(i)
Two conditions exist so that the next state is 0 while the present state is also 0. From the
operating characteristics diagram, we can see that condition A and B would both satisfy
this scenario. The common term to make this scenario true is J=0. We dont care about K,
as K=1 or K=0 while J=0 will work. Hence the dont care term is K.
(ii)
Operating characteristics C and D both satisfy this scenario. The common term is again J,
as the situation is solved by J=1 and either K=0 or K=1, therefore the dont care term is K
as shown on the state change table.
(iii)
When the output goes from 1 to 0, there are two characteristics that will allow this to
happen; B and D. K=1 and J can be equal to 1 or 0. Therefore in this case, J is the dont care
term.
(iv)
When the JK flip-flop remains at logic, it means that either A or C of the four operating
characteristics have been applied. K must equal 0 in either case, but J could have been
equal to 1 (A) or 0 (C). Because of this, J is the dont care term.
The JK flip-flop can actually be reconfigured so that it can perform the operation of some of the
other flip-flops that are discussed above. For example, if the two inputs J and K are tied together,
then the output characteristics are fixed to A and D. This precisely matches the characteristics of
145
Notes
a T type flip flop. Also to note, because the way a JK is made, you may replace an SR flip-flop
with a JK flip-flop without a change in operation. However you cannot replace a JK flip-flop
with an SR flip-flop as a S=1 R=1 condition is not allowed, but a J=1 K=1 condition is permitted.
9.2.3
T Flip-Flop (Toggle)
This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected together
and thus are also called a single input J-K flip flop. When clock pulse is given to the flip flop, the
output begins to toggle. Here also the restriction on the pulse width can be eliminated with a
master-slave or edge-triggered construction.
Figure 9.8: T Flip Flop
Source: http://www.circuitstoday.com/wp-content/uploads/2010/04/T-Flip-Flop.jpg
The T type flip-flop is a single input device: T (trigger). Two outputs: Q and Q (where Q is the
inverse of Q). A 0 input to T will make the next state the same as the present state (i.e. T = 0
present state = 0 therefore next state = 0). However a 1 input to T will change the next state to
the inverse of the present state (i.e. T = 1 present state = 0 therefore next state = 1). The T type flipflop is an edge driven device. Therefore you should not associate 1 and 0 with levels, but instead
1 should be considered as a pulse, and 0 as no pulse. Notice that if a clock signal was tied to T, the
output Q would be a clock signal at approximately half the frequency of T. This property makes
the T flip-flop a good candidate for applications such as frequency division.
146
Unit 9: Flip-Flops
9.2.4
Notes
D Flip-Flop (Delay)
Latch is an electronic device that can be used to store one bit of information. The D latch is used
to capture, or latch the logic level which is present on the Data line when the clock input is high.
If the data on the D line changes state while the clock pulse is high, then the output, Q, follows
the input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held
in the latch.
Figure 9.9: D Flip Flop
Source: http://www.circuitstoday.com/flip-flops
D input is connected to the S input and the complement of the D input is connected to the R input.
The D input is passed on to the flip flop when the value of CP is 12. When CP is HIGH, the flip
flop moves to the SET state. If it is 02, the flip flop switches to the CLEAR state.
Task Show how a D flip-flop can be converted to a toggle (T) flip-flop.
Self Assessment
5.
Flip flops do not depend on the number of inputs they take in and the manner in which
they affect the binary state of the flip-flop.
147
Notes
6.
The clocked RS flip-flop is like an SR flip-flop but with an extra third input of a standard
clock pulse CLK.
7.
The D latch is used to capture, or latch the logic level which is present on the Data line
when the clock input is high.
9.3 Master-Slave Flip-Flop

Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as the
master and the other as a slave. The figure of a master-slave J-K flip flop is shown below:
Figure 9.10: Master Slave Flip Flop
Source: http://www.circuitstoday.com/master-slave-flip-flop-circuit
From the above figure you can see that both the J-K flip flops are presented in a series connection.
The output of the master J-K flip flop is fed to the input of the slave J-K flip flop. The output of
the slave J-K flip flop is given as a feedback to the input of the master J-K flip flop. The clock
pulse [Clk] is given to the master J-K flip flop and it is sent through a NOT Gate and thus
inverted before passing it to the slave J-K flip flop.
When Clk=1, the master J-K flip flop gets disabled. The Clk input of the master input will be the
opposite of the slave input. So the master flip flop output will be recognized by the slave flip
flop only when the Clk value becomes 0. Thus, when the clock pulse males a transition from 1 to
0, the locked outputs of the master flip flop are fed through to the inputs of the slave flip-flop
making this flip flop edge or pulse-triggered. To understand better take a look at the timing
diagram illustrated below.
Figure 9.11: Timing Diagram of Master Slave Flip Flop
Source: http://www.circuitstoday.com/master-slave-flip-flop-circuit
148
Unit 9: Flip-Flops
Thus, the circuit accepts the value in the input when the clock is HIGH, and passes the data to the
output on the falling-edge of the clock signal. This makes the Master-Slave J-K flip flop a
Synchronous device as it only passes data with the timing of the clock signal.
Notes
Self Assessment
Fill in the blanks:
8.
In master slave flip flop the output of the ........................ J-K flip flop is fed to the input of
the ........................ J-K flip flop.
9.
Master-Slave J-K flip flop is a ........................ device as it only passes data with the timing of
the clock signal.
9.4 Triggering of Flip-Flop

The output of a flip flop can be changed by bring a small change in the input signal. This small
change can be brought with the help of a clock pulse or commonly known as a trigger pulse.
When such a trigger pulse is applied to the input, the output changes and thus the flip flop is said
to be triggered. Flip flops are applicable in designing counters or registers which stores data in
the form of multi-bit numbers. But such registers need a group of flip flops connected to each
other as sequential circuits. And these sequential circuits require trigger pulses. The number of
trigger pulses that is applied to the input of the circuit determines the number in a counter. A
single pulse makes the bit move one position, when it is applied onto a register that stores
multi-bit data.
In the case of SR Flip Flops, the change in signal level decides the type of trigger that is to be
given to the input. But the original level must be regained before giving a second pulse to the
circuit. If a clock pulse is given to the input of the flip flop at the same time when the output of
the flip flop is changing, it may cause instability to the circuit. The reason for this instability is
the feedback that is given from the output combinational circuit to the memory elements. This
problem can be solved to a certain level by making the flip flop more sensitive to the pulse
transition rather than the pulse duration.
There are mainly four types of pulse-triggering methods. They differ in the manner in which the
electronic circuits respond to the pulse. They are discussed in detail below.
9.4.1
High Level Triggering
When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is
used. It is mainly identified from the straight lead from the clock input. Take a look at the
symbolic representation shown below.
Figure 9.12: High Level Triggering
Source: http://www.circuitstoday.com/triggering-of-flip-flops
149
Notes
9.4.2
Low Level Triggering
When a flip flop is required to respond at its LOW state, a LOW level triggering method is used.
It is mainly identified from the clock input lead along with a low state indicator bubble. Take a
look at the symbolic representation shown below:
Figure 9.13: Low Level Triggering
9.4.3
Positive Edge Triggering
When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge
triggering method is used. It is mainly identified from the clock input lead along with a triangle.
Take a look at the symbolic representation shown below:
Figure 9.14: Positive Edge Triggering
9.4.4
Negative Edge Triggering
When a flip flop is required to respond during the HIGH to LOW transition state, a NEGATIVE
edge triggering method is used. It is mainly identified from the clock input lead along with a
low-state indicator and a triangle. Take a look at the symbolic representation shown below:
Figure 9.15: Negative Edge Triggering
9.4.5
Clock Pulse Transition
The movement of a trigger pulse is always from a 0 to 1 and then 1 to 0 of a signal. Thus it takes
two transitions in a single signal. When it moves from 0 to 1 it is called a positive transition and
150
Unit 9: Flip-Flops
when it moves from 1 to 0 it is called a negative transition. To understand more take a look at the
images below:
Notes
Figure 9.16: Clock Pulse Transition
The clocked flip-flops already introduced are triggered during the 0 to 1 transition of the pulse,
and the state transition starts as soon as the pulse reaches the HIGH level. If the other inputs
change while the clock is still 1, a new output state may occur. If the flip-flop is made to then the
multiple-transition problem can be eliminated. The multi-transition problem can be stopped is
the flip flop is made to respond to the positive or negative edge transition only, other than
responding to the entire pulse duration.
Self Assessment
Fill in the blanks:
10.
The output of a flip flop can be changed by bring a small change in the input signal called
a ........................ .
11.
When a flip flop is required to respond at its high state, a ........................ level triggering
method is used.
12.
When a flip flop is required to respond during the high to low transition state, a
........................ edge triggering method is used.
9.5 Timing Signal

Figure 9.17: Flip-flop Setup, Hold and Clock-to-Output Timing Parameters
Source: http://en.wikipedia.org/wiki/Flip-flop_%28electronics%29
Setup Time is the minimum amount of time the data signal should be held steady before the
clock event so that the data are reliably sampled by the clock. This applies to synchronous input
signals to the flip-flop.
Hold Time is the minimum amount of time the data signal should be held steady after the clock
event so that the data are reliably sampled. This applies to synchronous input signals to the flipflop.
151
Notes
Note: Synchronous signals (like Data) should be held steady from the set-up time to the hold
time, where both times are relative to the clock signal.
Recovery time is like setup time for asynchronous ports (set, reset). It is the time available
between the asynchronous signals going inactive and the active clock edge.
Removal time is like hold time for asynchronous ports (set, reset). It is the time between active
clock edge and asynchronous signal going inactive.
Short impulses applied to asynchronous inputs (set, reset) should not be applied completely
within the recovery-removal period, or else it becomes entirely indeterminable whether the
flip-flop will transition to the appropriate state. In another case, where an asynchronous signal
simply makes one transition that happens to fall between the recovery/removal time, eventually
the asynchronous signal will be applied, but in that case it is also possible that a very short glitch
may appear on the output, dependent on the synchronous input signal. This second situation
may or may not have significance to a circuit design.
Set and Reset (and other) signals may be either synchronous or asynchronous and therefore may
be characterized with either Setup/Hold or Recovery/Removal times, and synchronicity is
very dependent on the TTL design of the flip-flop.
Differentiation between Setup/Hold and Recovery/Removal times is often necessary when
verifying the timing of larger circuits because asynchronous signals may be found to be less
critical than synchronous signals. The differentiation offers circuit designers the ability to define
the verification conditions for these types of signals independently.
The metastability in flip-flops can be avoided by ensuring that the data and control inputs are
held valid and constant for specified periods before and after the clock pulse, called the setup
time (tsu) and the hold time (th) respectively. These times are specified in the data sheet for the
device, and are typically between a few nanoseconds and a few hundred picoseconds for modern
devices.
Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop
may be connected to a real-time signal that could change at any time, outside the control of the
designer. In this case, the best the designer can do is to reduce the probability of error to a certain
level, depending on the required reliability of the circuit. One technique for suppressing
metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds
the data input of the next, and all devices share a common clock. With this method, the probability
of a metastable event can be reduced to a negligible value, but never to zero. The probability of
metastability gets closer and closer to zero as the number of flip-flops connected in series is
increased.
So-called metastable-hardened flip-flops are available, which work by reducing the setup and
hold times as much as possible, but even these cannot eliminate the problem entirely. This is
because metastability is more than simply a matter of circuit design. When the transitions in the
clock and the data are close together in time, the flip-flop is forced to decide which event
happened first. However fast we make the device, there is always the possibility that the input
events will be so close together that it cannot detect which one happened first. It is therefore
logically impossible to build a perfectly metastable-proof flip-flop.
Propagation delay
Another important timing value for a flip-flop is the clock-to-output delay (common symbol in
data sheets: tCO) or propagation delay (tP), which is the time the flip-flop takes to change its
output after the clock edge. The time for a high-to-low transition (tPHL) is sometimes different
from the time for a low-to-high transition (tPLH).
152
Unit 9: Flip-Flops
When cascading flip-flops which share the same clock (as in a shift register), it is important to
ensure that the tCO of a preceding flip-flop is longer than the hold time (th) of the following flipflop, so data present at the input of the succeeding flip-flop is properly shifted in following the
active edge of the clock. This relationship between tCO and th is normally guaranteed if the flipflops are physically identical. Furthermore, for correct operation, it is easy to verify that the
clock period has to be greater than the sum tsu + th.
Notes
Case Study
16:1 MUX D Flip-Flop Circuit
100% Fault-Grade Vector Set

The following circuit was developed as a teaching circuit and as such has parameters and
labels beyond what would appear in an actual circuit schematic. These parameters have
nothing to do with the required Functional, AC Test or Parametric Vector sets.
A parametric gate-tree, used for VIH and VIL measurement is included and its output
signal is listed. A simulation format requires that all I/O signals and internal enable nets
be listed.
The test sequence for a 16:1 MUX was altered to allow clocking to occur between vector
steps.
The rule of one input per vector changing state is honored in that data and clock do not
change in the same vector. The sequence begins after the circuit RESET is executed.
Both the schematic set and a formatted (compacted) output vector set are shown here. The
output vectors include input, output and enable signals.
The Marquand Map
The Marquand Map for logical analysis was proposed in a mathematical paper in the late
1800s.
It is a convenient mapping method for large functions. The Karnough Map was developed
in the 1950s specifically for 4-variable circuits (for coding) and is messier to use in these
cases.
The figures given below different sizes of Marquand Maps with minterms labeled.
Figure 1: 2-Input 1-Output Marquand Map
Contd...
153
Notes
Figure 4: 5-Input 1-Output Marquand Map (Split)
Questions:
1.
Discuss the use of parametric gate tree.
2.
what is Karnough map? Discuss.
Source: http://www10.edacafe.com/book/parse_book.php?article=0127466606/CHAP_9/ASChp9B2.html&interstitial_displayed=Yes
Self Assessment
154
13.
Setup time is the minimum amount of time the data signal should be held steady after the
clock event.
14.
Hold time is the minimum amount of time the data signal should be held steady before
the clock event.
15.
Recovery time is the time between active clock edge and asynchronous signal going
inactive.
Unit 9: Flip-Flops
Notes
9.6 Summary
Flip-flop or latch is a circuit that has two stable states and can be used to store state
information.
A basic Flip-Flop circuit can be constructed in two ways-Using two NOR gates or Using
two NAND gates.
The outputs of the Flip-Flops Q and Q are complements of each other.
Both the inputs of Flip-flop remains at 0 unless the state is changed by applying external
pulse.
The Flip-flop consists of two useful states, The SET and The CLEAR state.
Flip flops are type casted as per the number of inputs they take in and the manner in which
they affect the binary state of the flip-flop.
The clocked RS flip-flop is like an SR flip-flop but with an extra third input of a standard
clock pulse CLK.
The JK type flip-flop consists of two data inputs: J and K, and one clock input. There are
again two outputs Q and Q (where Q is the reverse of Q).
This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected
together and thus are also called a single input J-K flip flop.
When clock pulse is given to the flip flop, the output begins to toggle.
The D latch is used to capture, or latch the logic level which is present on the Data line
when the clock input is high.
Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as the
master and the other as a slave.
The output of a flip flop can be changed by bring a small change in the input signal called
a trigger pulse.
When a flip flop is required to respond at its HIGH state, a HIGH level triggering method
is used.
When a flip flop is required to respond at its LOW state, a LOW level triggering method
is used.
When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge
triggering method is used.
When a flip flop is required to respond during the HIGH to LOW transition state, a
NEGATIVE edge triggering method is used.
Setup time is the minimum amount of time the data signal should be held steady before
the clock event.
Hold time is the minimum amount of time the data signal should be held steady after the
clock event.
Recovery time is the time between active clock edge and asynchronous signal going
inactive.
155
Notes
9.7 Keywords
Clocked RS Flip-Flop: It is like an SR flip-flop but with an extra third input of a standard clock
pulse CLK.
Flip-Flop or Latch: It is a circuit that has two stable states and can be used to store state
information.
Hold Time: It is the minimum amount of time the data signal should be held steady after the
clock event.
JK Type Flip-Flop: It consists of two data inputs: J and K, and one clock input. There are again
two outputs Q and Q (where Q is the reverse of Q).
Master-Slave Flip Flop: It is designed using two separate flip flops. Out of these, one acts as the
master and the other as a slave.
Recovery Time: It is the time between active clock edge and asynchronous signal going inactive.
Setup Time: It is the minimum amount of time the data signal should be held steady before the
clock event.
T Flip Flop: When clock pulse is given to the flip flop, the output begins to toggle.
The D Latch: It is used to capture, or latch the logic level which is present on the Data line when
the clock input is high.
Trigger Pulse: The output of a flip flop can be changed by bring a small change in the input
signal.

1.
What is a flip flop?
2.
Explain the ways to construct a basic flip flop.
3.
What is S-R flip flop?
4.
Give the truth table and circuit diagram of a J-K flip flop.
5.
Differentiate between D and T flip flop.
6.
Explain the working of master slave flip flop.
7.
What is trigger pulse?
8.
When do we use negative edge triggering?
9.
Differentiate between setup and hold time.
10.
What is propagation delay?
156
1.
NOR, NAND
2.
Complement
3.
Zero
4.
Set, Clear
5.
False
6.
True
7.
True
8.
Master, Slave
Unit 9: Flip-Flops
9.
Synchronized
10.
Trigger pulse
11.
High
12.
Negative
13.
False
14.
False
15.
True
Notes
Books
Publication
Morris Mano, Digital Logic Circuits & Design
R.P. Jain, Modern Digital Electronics, Tata McGraw-Hill Education
Online links
http://www.circuitstoday.com/flip-flops
http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/06FlipFlops/
http://www.facstaff.bucknell.edu/mastascu/elessonsHTML/Logic/Logic4.html
http://www.indiabix.com/digital-electronics/memory-and-storage/
157
Notes
Unit 10: Clocked Sequential Circuits

CONTENTS
Objectives
Introduction
10.1 Sequential Circuits
10.2 Analysis of Clocked Sequential Circuits
10.2.1
State Reduction
10.2.2
States Assignment
10.2.3
Design with Unused States
10.2.4
Unused States Hazard
10.3 Clocked Sequential Circuits Design

10.3.1
State Diagram
10.3.2
State Table
10.3.3
K-map
10.3.4
Circuit
10.4 State Minimization

10.4.1
State Equivalence
10.4.2
Partitioning Minimization
10.5 State Assignment

10.5.1
State Maps
10.5.2
Minimum-Bit-Change Strategy
10.5.3
Prioritized Adjacency Strategy
10.6 Summary
10.7 Keywords
Objectives
158
Explain the concept of sequential circuits
Analyze clocked sequential circuits
Explain the design of sequential circuits
Elaborate upon the concept of state minimization
Explain state assignment
Notes
Introduction
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only
on the present value of its input signals but on the past history of its inputs. This is in contrast to
combinational logic, whose output is a function of only the present input. That is, sequential
logic has state (memory) while combinational logic does not. Or, in other words, sequential
logic is combinational logic with memory. Sequential logic is used to construct finite state
machines, a basic building block in all digital circuitry, as well as memory circuits and other
devices. Virtually all circuits in practical digital devices are a mixture of combinational and
sequential logic. Digital sequential logic circuits are divided into synchronous and asynchronous
types. In synchronous sequential circuits, the state of the device changes only at discrete times in
response to a clock signal. In asynchronous circuits the state of the device can change at any time
in response to changing inputs.
10.1 Sequential Circuits

Synchronous Sequential Logic
Nearly all sequential logic today is clocked or synchronous logic. In a synchronous circuit, an
electronic oscillator called a clock generates a sequence of repetitive pulses called the clock
signal which is distributed to all the memory elements in the circuit. The basic memory element
in sequential logic is the flip-flop. The output of each flip-flop only changes when triggered by
the clock pulse, so changes to the logic signals throughout the circuit all begin at the same time,
at regular intervals, synchronized by the clock. The output of all the storage elements (flipflops) in the circuit at any given time, the binary data they contain, is called the state of the
circuit. The state of a synchronous circuit only changes on clock pulses. At each cycle, the next
state is determined by the current state and the value of the input signals when the clock pulse
occurs.
The main advantage of synchronous logic is its simplicity. The logic gates which perform the
operations on the data require a finite amount of time to respond to changes to their inputs. This
is called propagation delay. The interval between clock pulses must be long enough so that all
the logic gates have time to respond to the changes and their outputs settle to stable logic
values, before the next clock pulse occurs. As long as this condition is met (ignoring certain
other details) the circuit is guaranteed to be stable and reliable. This determines the maximum
operating speed of a synchronous circuit.
Synchronous logic has two main disadvantages:
The maximum possible clock rate is determined by the slowest logic path in the circuit,
otherwise known as the critical path. Every logical calculation, from the simplest to the
most complex, must complete in one clock cycle. So logic paths that complete their
calculations quickly are idle much of the time, waiting for the next clock pulse. Therefore
synchronous logic can be slower than asynchronous logic. One way to speed up
synchronous circuits is to split complex operations into several simple operations which
can be performed in successive clock cycles, a technique known as pipelining. This technique
is extensively used in microprocessor design, and helps to improve the performance of
modern processors.
The clock signal must be distributed to every flip-flop in the circuit. As the clock is usually
a high-frequency signal, this distribution consumes a relatively large amount of power
and dissipates much heat. Even the flip-flops that are doing nothing consume a small
amount of power, thereby generating waste heat in the chip. In portable devices which
159
Notes
have limited battery power, the clock signal goes on even when the device is not being
used, consuming power.
Figure 10.1: Synchronous Sequential Logic
Source: http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/03-Seq_Intro/Intro.html
Asynchronous Sequential Logic

Asynchronous sequential logic is not synchronized by a clock signal; the outputs of the circuit
change directly in response to changes in inputs. The advantage of asynchronous logic is that it
can be faster than synchronous logic, because the circuit doesnt have to wait for a clock signal to
process inputs. The speed of the device is potentially limited only by the propagation delays of
the logic gates used. However, asynchronous logic is more difficult to design and is subject to
problems not encountered in synchronous designs. The main problem is that digital memory
elements are sensitive to the order that their input signals arrive; if two signals arrive at a logic
gate at almost the same time, which state the circuit goes into can depend on which signal gets
to the gate first. Therefore the circuit can go into the wrong state, depending on small differences
in the propagation delays of the logic gates. This is called a race condition. This problem is not
as severe in synchronous circuits because the outputs of the memory elements only change at
each clock pulse. The interval between clock signals is designed to be long enough to allow the
outputs of the memory elements to settle so they are not changing when the next clock comes.
Therefore the only timing problems are due to asynchronous inputs; inputs to the circuit from
other systems which are not synchronized to the clock signal. Asynchronous sequential circuits
are typically used only in a few critical parts of otherwise synchronous systems where speed is
at a premium, such as parts of microprocessors and digital signal processing circuits. The design
of asynchronous logic uses different mathematical models and techniques from synchronous
logic, and is an active area of research.
Figure 10.2: Asynchronous Sequential Logic
Source: http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/03-Seq_Intro/Intro.html
Self Assessment
Fill in the blanks:
160
1.
........................ logic is a type of logic circuit whose output depends not only on the present
value of its input signals but on the past history of its inputs.
2.
The output of ........................ logic is a function of only the present input.
3.
........................ sequential logic is not synchronized by a clock signal.
10.2 Analysis of Clocked Sequential Circuits
Notes
The steps to be followed while designing a clocked sequential circuit are summarized below:
Figure 10.3: Sequential Circuit Design Steps
Source: http://osp.mans.edu.eg/cs212/Seq_circuits_design.htm
Let us explain each step through an example:

Example: We wish to design a synchronous sequential circuit whose state diagram is
shown in the figure below. The type of flip-flop to be use is J-K.
Figure 10.4: State Diagram
Source: http://osp.mans.edu.eg/cs212/Seq_circuits_state_reduction_ex_1_3.htm
161
Notes
From the state diagram, we can generate the state table shown in the table below:
Note There is no output section for this circuit.

Two flip-flops are needed to represent the four states and are designated Q0Q1. The input variable
is labelled x.
Table 10.1: State Table
We shall now derive the excitation table and the combinational structure. The table is now
arranged in a different form shown in the table below, where the present state and input variables
are arranged in the form of a truth table.
Table 10.2: Excitation Table of JK Flip Flop
Table 10.3: Excitation Table of the Circuit
In the first row of the table above, we have a transition for flip-flop Q0 from 0 in the present state
to 0 in the next state. In Table 10 we find that a transition of states from 0 to 0 requires that input
J = 0 and input K = X. So 0 and X are copied in the first row under J0 and K0 respectively. Since the
first row also shows a transition for the flip-flop Q1 from 0 in the present state to 0 in the next
state, 0 and X are copied in the first row under J1 and K1. This process is continued for each row
of the table and for each flip-flop, with the input conditions as specified in the excitation table for
JK flip-flop.
162
The simplified Boolean functions for the combinational circuit can now be derived. The input
variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and K1. The information from the
truth table is plotted on the Karnaugh maps shown in the figure below:
Notes
Figure 10.5: K maps
The flip-flop input functions are derived:

J0 = Q1 * x
K0 = Q1 * x
J1 = x
K1 = Q0' * x + Q0 * x = Q0 x
Note The symbol is exclusive-NOR.

Figure 10.6: The Logic Diagram of Sequential Circuit
10.2.1 State Reduction

Any design process must consider the problem of minimizing the cost of the final circuit. The
two most obvious cost reductions are reductions in the number of flip-flops and the number of
gates. The number of states in a sequential circuit is closely related to the complexity of the
resulting circuit. It is therefore desirable to know when two or more states are equivalent in all
aspects. The process of eliminating the equivalent or redundant states from a state table/diagram
is known as state reduction.
163
Notes
Example: Let us consider the state table given below:
Source: http://osp.mans.edu.eg/cs212/Seq_circuits_state_reduction.htm
It can be seen from the table that the present state A and F both have the same next states, B (when
x=0) and C (when x=1). They also produce the same output 1 (when x=0) and 0 (when x=1).
Therefore states A and F are equivalent. Thus one of the states, A or F can be removed from the
state table. For example, if we remove row F from the table and replace all Fs by As in the
columns, the state table is modified as shown in table below:
Table 10.5: State Table without Row F
It is apparent that states B and E are equivalent. Removing E and replacing Es by Bs results in
the reduce table shown below:
Table 10.6: Reduces State Table
The removal of equivalent states has reduced the number of states in the circuit from six to four.
Two states are considered to be equivalent if and only if for every input sequence the circuit
produces the same output sequence irrespective of which one of the two states is the starting
state.
10.2.2 States Assignment

The states in the constructed state diagram have been assigned symbolic names rather than
binary codes. It is necessary to replace these symbolic names with binary codes in order to
proceed with the design. In general, if there are m states, then the codes must contain n bits,
164
where 2n e m, and each state must be assigned a unique code. There can be many possible
assignments for our state machine. One possible assignment is show in the table below:
Notes
Table 10.7: State Assignment
The assignment of state codes to states results in state transition table as shown below:
Table 10.8: State Transition
Note The binary code of the present state at a given time t represents the values stored in
the flip-flops; and the next-state represents the values of the flip-flops one clock period
later, at time t+1.
10.2.3 Design with Unused States

Sometimes a sequential circuit created with m flip-flops, may not use all the possible 2m states.
Table 10.9: State Tables
Present
state
Input
Next
state
Flip-flop inputs
SA RA SB RB SC RC
A B
A+ B+ C+
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
Given these
0
0
0
1
0
1
X
X
0
X
X
X
X
0
X
0
0
0
1
0
0
1
X
0
0
0
0
0
0
0
X
0
0
1
1
1
X
X
X
X
X
0
1
0
X
0
1
0
X
0
Output
0
1
0
X
0
1
0
X
0
1
y
0
0
0
0
0
0
0
1
0
1
Derive these
Source: www.comp.nus.edu.sg/~cs1104/oldlect/cs1104-12.ppt
165
Notes
Table 10.10: Unused State Table
Unused state
000:
0 0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
Figure 10.7: K-maps
Figure 10.8: K-maps
Figure 10.9: Logic Diagram
166
X
X
X
X
X
X
X
X
Notes
10.2.4 Unused States Hazard

There are unused state codes when the number of states is less than the number of state variable
combinations. How to consider those unused states? In a minimal risk approach, it is assumed
that the machine may go to an unused state, due to a hardware failure, for example.
For all the unused states, an explicit transition to a safe state is made. In a minimal cost approach,
it is assumed that the machine will never enter an unused state. The next state entries of the
unused states can be marked as dont cares.
Self Assessment
4.
The process of eliminating the equivalent or redundant states from a state table/diagram
5.
Two states are considered to be equivalent if and only if for every input sequence the
circuit produces different output sequence irrespective of which one of the two states is the
starting state.
6.
If there are m states, then the codes must contain n bits, where 2n e m, and each state must
be assigned a unique code.
10.3 Clocked Sequential Circuits Design

The steps to be followed in order to create a clocked sequential circuit design are discussed in
detail below:
10.3.1 State Diagram

The first step in designing a finite state machine is to determine how many states are needed,
and what transitions are possible from one state to another. One can arbitrarily select one
particular state as a starting state; generally, this is the state that the circuit should enter when
power is first turned on or when a reset signal is applied.
Figure 10.10: State Diagram
Source: http://www.ee.umanitoba.ca/~thomas/MP/ECE2220/lectures/8.pdf
167
Notes
10.3.2 State Table

Rather than having the circuit description in the graphical form of a state diagram, we can
translate the diagram into a tabular form known as a state table. A state table contains all the
information of the state diagram: transitions, input signal, and output signals; but places them
in a form from which it is easier to simplify and implement a circuit.
10.3.3 K-map
K-maps are drawn for the inputs in a clocked sequential circuit.
Figure 10.11: K-maps
10.3.4 Circuit
The final step is to draw the circuit derived from the K-map equation.
Figure 10.12: Circuit
Self Assessment
Fill in the blanks:
7.
168
Drawing a ........................ is the first step to make a Clocked Sequential Circuits Design.
8.
A ........................ contains all the information of the state diagram: transitions, input signal,
and output signals; but places them in a form from which it is easier to simplify and
implement a circuit.
9.
........................ are used to simplify the Boolean expressions.
Notes
10.4 State Minimization

We need the minimum possible states to avoid using multiple flip flops in our circuit. For
complex FSMs, it is likely that an initial state diagram may have more states than are necessary
to perform a required function. Complexity of combinational logic may also be reduced with
less states. Instead of trying to show which states are equivalent, it is often easier to show which
states are definitely not equivalent. This can be exploited to define a minimization procedure.
10.4.1 State Equivalence

Equivalent states are states in a state machine which, for every possible input sequence, the same
output sequence will be produced no matter which state is the initial state.
Figure 10.13: Equivalent States
Source: http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/05-Implication/
10.4.2 Partitioning Minimization

We can construct a minimization procedure that involves considering the states of the machine
as a set and then breaking that set into partitions that comprise subsets that are definitely not
equivalent. The partitioning approach is a successive determination of partitions PK , K = 1, 2, 3,
..., l , in which each PK is composed of a number of blocks, each of which consists of a group of
one or more states. The states contained within a block of PK are K equivalent. That is given a
FSM with 5 states S1, ..., S5 and PK = (S1 S3) (S2 S4 ) (S5), then PK contains three blocks with state
pairs S1 S3 and S2 S4 are K-equivalent.
Procedure with three steps:
Step 1: The first partition P1 is formed by placing two or more states in the same block of
P1 if and only if their output is identical for each input.
Step 2: Successive partitions PK ,K = 2, 3, 4..., l, are derived by placing two or more states
in the same block of PK if and only if for each input value their next states all lie in a
single block of PK-1. This iterative procedure is suggested by condition 2 for equivalent
states.
Step 3: When PK+1 = PK , which means a partition repeats, the states in each block of PK
that are K-equivalent are (K+1)-equivalent, (K+2)-equivalent and so on. The last partition
169
Notes
PK is said to be an equivalence partition. Condition 2 for equivalent states is now satisfied

by PK.
Example:
Source: http://users.etech.haw-hamburg.de/users/Schwarz/En/Lecture/Ds/Notes/DigSys5.pdf
Source: http://users.etech.haw-hamburg.de/users/Schwarz/En/Lecture/Ds/Notes/DigSys5.pdf
Partition P2 is obtained by examining each block of P1. In the first block of P1 the next states for
A, B and C with X = 0 all lie in the same block of P1. For X = 1 the next state of A lies in a different
block of P1 than the next states of B and C. Therefore the block (ABC) contained in P1 is split into
the blocks (A) (BC) in P2. In the second block of P1 the next states for D and E lie in the same block
of P1 for both X values. Hence D and E will remain in the same block of P2.
P2 = (A) (BC) (DE) , the states within each block are 2-equivalent. Partition P3 is obtained by
examining each block of P2. The next states of B and C lie in the same block of P2 for each input
and hence the block (BC) remains in P3. The next states for D and E with x = 1 now lie in different
blocks of P2 and hence these two states must be separated into different blocks of P3.
P3 = (A) (BC) (D) (E), the states B and C are 3-equivalent.
170
Notes
Self Assessment
10.
The first partition P1 is formed by placing two or more states in the same block of P1 if and
only if their output is identical for each input.
11.
Complexity of combinational logic may also be reduced with more states.
12.
When PK+1 = PK implies that a partition repeats.
10.5 State Assignment

A 2n-state finite state machine has n!-different possible ways to assign state variable values to
states. The number of gates needed to implement a sequential logic network is usually dependent
upon the assignments of possible state variable values to states. But, the only way to obtain the
best possible assignment is to try every choice for encoding for small state diagrams and effectively
intractable for complex state machines.
10.5.1 State Maps

State maps are a technique of observing adjacencies in the state assignments. The squares of the
state maps are indexed by the binary values of the state bits; the state given that encoding is
placed in the map square.
Figure 10.14: State Maps
Source: http://www.ami.ac.uk/courses/ami4407_dicdes/u02/
10.5.2 Minimum-Bit-Change Strategy

Binary values will be assigned to the states in a sequence that the number of all bit changes
during state transitions becomes a minimum. This strategy supports two level logic with sum of
products representation (CPLD). For a bit change with a reset of a D-FF at least an AND-gate and
171
Notes
an extra OR-gate input is necessary in order to perform the state feedback. These gates will be
saved if a bit change is avoided.
Figure 10.15: Minimum Bit Changes
Source: http://users.etech.haw-hamburg.de/users/schubert/dsy/Notes/DigSys6.pdf
10.5.3 Prioritized Adjacency Strategy

There are two ways to arrange the ones on a K-map (based on z-rule minterm numbers) for next
state forming logic minimization:
Vertically by making the ones combine within a given column.
Horizontally by making the ones combine within a given row.
In both cases the ones are placed in adjacent K-map cells which differ only in one coordinate.
This grouping of ones can be obtained by adopting the following state assignment rules:
States that have the same next state for a given input should be given logically adjacent
assignments.
States that are the next states of a single present state under logically adjacent inputs
should be given logically adjacent assignments.
States that generate the same output for a given input should be given a logically adjacent
assignment.
Figure 10.16: State Encoding with Rules 1 and 2 with Prioritized Adjacency
Source: http://users.etech.haw-hamburg.de/users/schubert/dsy/Notes/DigSys6.pdf
172
Case Study
Notes
Electronic Flip-flop
he first electronic flip-flop was invented in 1918 by William Eccles and F. W. Jordan.
It was initially called the EcclesJordan trigger circuit and consisted of two active
elements (vacuum tubes). Such circuits and their transistorized versions were
common in computers even after the introduction of integrated circuits, though flip-flops
made from logic gates are also common now.
Early flip-flops were known variously as trigger circuits or multivibrators. A multivibrator
is a two-state circuit; they come in several varieties, based on whether each state is stable
or not: an astable multivibrator is not stable in either state, so it acts as a relaxation oscillator;
a monostable multivibrator makes a pulse while in the unstable state, then returns to the
stable state, and is known as a one-shot; a bistable multivibrator has two stable states, and this
is the one usually known as a flip-flop. However, this terminology has been somewhat
variable, historically. For example:
1942 multivibrator implies astable: The multivibrator circuit is somewhat similar

to the flip-flop circuit, but the coupling from the anode of one valve to the grid of the
other is by a condenser only, so that the coupling is not maintained in the steady
state.
1942 multivibrator as a particular flip-flop circuit: Such circuits were known as

trigger or flip-flop circuits and were of very great importance. The earliest and
best known of these circuits was the multivibrator.
1943 flip-flop as one-shot pulse generator: It should be noted that an essential

difference between the two-valve flip-flop and the multivibrator is that the flip-flop
has one of the valves biased to cutoff.
1949 monostable as flip-flop: Monostable multivibrators have also been called

flip-flops.
1949 monostable as flip-flop: a flip-flop is a monostable multivibrator and the

ordinary multivibrator is an astable multivibrator.
According to P. L. Lindley, a JPL engineer, the flip-flop types discussed below (RS, D, T, JK)
were first discussed in a 1954 UCLA course on computer design by Montgomery Phister,
and then appeared in his book Logical Design of Digital Computers. Lindley was at the time
working at Hughes Aircraft under Dr. Eldred Nelson, who had coined the term JK for a flipflop which changed states when both inputs were on. The other names were coined by
Phister. They differ slightly from some of the definitions given below. Lindley explains that
he heard the story of the JK flip-flop from Dr. Eldred Nelson, who is responsible for coining
the term while working at Hughes Aircraft. Flip-flops in use at Hughes at the time were all
of the type that came to be known as J-K. In designing a logical system, Dr. Nelson assigned
letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K.
Nelson used the notations j-input and k-input in a patent application filed in 1953.
Questions:
1.
Discuss the evolution of flip-flop.
2.
Analyze the meaning of j-input and k-input.
Source: http://mahendradhayal.wordpress.com/2012/11/22/flip-flop-electronics/
173
Notes
Self Assessment
Fill in the blanks:
13.
A 2n-state finite state machine has ........................ different possible ways to assign state
variable values to states.
14.
........................ are a technique of observing adjacencies in the state assignments.
15.
There are two ways to arrange the ones on a K-map for next state forming logic
minimization: ........................ and ........................ .
10.6 Summary
Sequential logic is a type of logic circuit whose output depends not only on the present
value of its input signals but on the past history of its inputs.
Combinational logics output is a function of only the present input.
In a synchronous circuit, an electronic oscillator called a clock generates a sequence of

repetitive pulses called the clock signal which is distributed to all the memory elements in
the circuit.
Asynchronous sequential logic is not synchronized by a clock signal; the outputs of the
circuit change directly in response to changes in inputs.
the circuit can go into the wrong state, depending on small differences in the propagation
delays of the logic gates. This is called a race condition.
The process of eliminating the equivalent or redundant states from a state table/diagram
Two states are considered to be equivalent if and only if for every input sequence the
circuit produces the same output sequence irrespective of which one of the two states is the
starting state.
A state table contains all the information of the state diagram: transitions, input signal,
and output signals; but places them in a form from which it is easier to simplify and
implement a circuit.
A 2n-state finite state machine has n!-different possible ways to assign state variable
values to states.
State maps are a technique of observing adjacencies in the state assignments.
There are two ways to arrange the ones on a K-map (based on z-rule minterm numbers)
for next state forming logic minimization: Horizontally and Vertically.
10.7 Keywords
Asynchronous Sequential Logic: It is not synchronized by a clock signal; the outputs of the
circuit change directly in response to changes in inputs.
Combinational Logic: It is when the output is a function of only the present input.
Race Condition: When the circuit can go into the wrong state, depending on small differences in
the propagation delays of the logic gates.
Sequential Logic: It is a type of logic circuit whose output depends not only on the present value
of its input signals but on the past history of its inputs.
174
State Maps: A technique of observing adjacencies in the state assignments.
Notes
State Reduction: The process of eliminating the equivalent or redundant states from a state
table/diagram.
State Table: It contains all the information of the state diagram: transitions, input signal, and
output signals; but places them in a form from which it is easier to simplify and implement a
circuit.
Synchronous Circuit: It has an electronic oscillator called a clock generates a sequence of repetitive
pulses called the clock signal which is distributed to all the memory elements in the circuit.

1.
Explain the concept of synchronized sequential logic.
2.
What are the advantages and limitations of synchronized sequential logic?
3.
Differentiate between synchronized sequential logic and asynchronized sequential logic.
4.
Give the steps to design a sequential logic circuit.
5.
What do you mean by state reduction?
6.
Explain the concept of state assignment.
7.
Give the steps to design a clocked sequential circuit design.
8.
What is the procedure for state minimization?
9.
Explain the prioritized adjacency strategy.
10.
What is the minimum bit change strategy?

1.
Sequential
2.
Combinational
3.
Asynchronous
4.
True
5.
False
6.
True
7.
State Diagram
8.
State Table
9.
K map
10.
True
11.
False
12.
True
13.
n!
14.
State Map
15.
Horizontally, Vertically
Books
Publication
175
Notes
Online links
http://filebox.ece.vt.edu/~jgtront/introcomp/clk_seq_ckt.swf
http://osp.mans.edu.eg/cs212/Seq_circuits_state_reduction_ex_1_3.htm
http://www.ece.tufts.edu/~karen/ES4/workbook/clocked_circuits.pdf
http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/03Seq_Intro/Intro.html
176
Unit 11: Registers and Counters
Notes
CONTENTS
Objectives
Introduction
11.1 Shift Registers
11.1.1
Serial-In/Serial-Out Shift Registers (SISO)
11.1.2
Serial-In/Parallel-Out Shift Registers (SIPO)
11.1.3
Parallel-In/Serial-Out Shift Registers (PISO)
11.1.4
Parallel-In/Parallel-Out Shift Registers (PIPO)
11.1.5
Bidirectional Shift Registers
11.2 Ripple Counter

11.3 Synchronous Counters
11.3.1
4-bit Synchronous Binary Up Counter
11.3.2
Binary Down Counters
11.3.3
Binary Up/Down Counters
11.3.4
MOD-N/Divide-by-N Counters
11.3.5
Binary Coded Decimal (BCD) Counters
11.3.6
Ring Counters
11.3.7
Johnson/Twisted-Ring Counters
11.3.8
Loadable/Presettable Counters
11.4 Memory Decoding

11.4.1
Block Address Decoding
11.5 Semiconductor Memories

11.5.1
Types of Semiconductor Memory
11.5.2
Semiconductor Memory Technologies
11.6 Summary
11.7 Keywords
Objectives
Explain the shift registers
Discuss the ripple counter
177
Notes
Elaborate the concept of synchronous counters
Define the memory decoding
Explain semiconductor memory and its types
Introduction
In digital circuits multi-bit data has to be stored temporarily until it is processed. A flip-flop is
able to store a single binary bit of information. Multiple bits of data are stored by using multiple
flip-flops which have their clock inputs connected together. Thus, by activating the clock signal
multiple-bits of data are stored. A register performs two basic functions. It stores data and it
moves or shifts data. The shifting of data involves shifting of bits from one flip-flop to the other
within the register or moving data in and out of the register. The shift operation of the binary
data is carried out by applying clock signals. Whereas a counter is a sequential circuit (aka.
Finite state machine) that cycles through a fixed sequence of states. The state of the counter is
stored in Flip-Flops. An n-bit counter has n Flip-Flops and can cycle through at most 2n states.
11.1 Shift Registers

It is a series of flip flops, sharing the same clock, in which the output of each flip-flop is connected
to the data input of the next flip-flop in the chain, resulting in a circuit that shifts by one position
the bit array stored in it, shifting in the data present at its input and shifting out the last bit in the
array, at each transition of the clock input. More generally, a shift register may be
multidimensional, such that its data in and stage outputs are themselves bit arrays: this is
implemented simply by running several shift registers of the same bit-length in parallel. Shift
registers can have both parallel and serial inputs and outputs. These are often configured as
serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have
both serial and parallel input and types with serial and parallel output. There are also bidirectional shift registers which allow shifting in both directions: L!R or R!L. The serial input
and last output of a shift register can also be connected to create a circular shift register.
Register
Registers are groups of flip-flops, where each flip-flop is capable of storing one bit of information.
An n-bit register is a group of n flip-flops. The basic function of a register is to hold information
in a digital system and make it available to the logic elements for the computing process.
Shift Register
Information often comes bitwise i.e. one bit at every clock pulse. Shift registers are used to store
such data.
Counter
It is a device which stores (and sometimes displays) the number of times a particular event or
process has occurred, often in relationship to a clock signal.
Storage Capacity
It is the total number of bits (1 or 0) of digital data it can retain. Each stage (flip-flop) in a shift
register represents one bit of storage capacity. Storage capacity is determined by the number of
stages in a register.
178
Figure 11.1: Shift Registers
Notes
Source: http://www.most.gov.mm/techuni/media/EcE_01031_5.pdf
11.1.1 Serial-In/Serial-Out Shift Registers (SISO)

A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The
register is first cleared, forcing all four outputs to zero. The input data is then applied sequentially
to the D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is transmitted
from left to right. Assume a data word to be 1001. The least significant bit of the data has to be
shifted through the register from FF0 to FF3.
Figure 11.2: SISO Shift Register
Source: http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/register02.html
Example: A register holds 0000 (so all storage slots are empty). As Data In presents
1,0,1,1,0,0,0,0 (in that order, with a pulse at Data Advance each timethis is called clocking or
strobing) to the register, this is the result. The left hand column corresponds to the left-most flipflops output pin, and so on.
So the serial output of the entire register is 10110000. As you can see if we were to continue to
input data, we would get exactly what was put in, but offset by four Data Advance cycles. This
arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be
set to zero by bringing the reset (R) pins high.
This arrangement performs destructive readout - each datum is lost once it has been shifted out
of the right-most bit.
179
Notes
Table 11.1: SISO Pattern
Source: http://en.wikipedia.org/wiki/Shift_register
Task Show the working of a 5-Bit Serial-In/Serial-Out Shift Register.
11.1.2 Serial-In/Parallel-Out Shift Registers (SIPO)

Data bits are entered serially (right-most bit first) into this type of register in the same manner
as in a serial in/serial out shift register. The difference is the way in which the data bits are taken
out of the register; in the parallel output register, the output of each stage is available. Once the
data are stored, each bit appears on its respective output line, and all bits are. Available
simultaneously, rather than on a bit-by-bit basis as with the serial output.
Figure 11.3: SIPO Shift Register
The 74LS164 8-Bit Serial in/Parallel Out Shift Register

It has two gated serial inputs, A and B, and a clear (CLR ) input that is active-LOW. The parallel
outputs are Q0 through Q7.
Figure 11.4: The 74LS164 8-Bit Serial in/Parallel Out Shift Register
180
11.1.3 Parallel-In/Serial-Out Shift Registers (PISO)
Notes
For a register with parallel data inputs, the bits are entered simultaneously into their respective
stages on parallel lines rather than on a bit-by-bit basis on one line as with serial data inputs.
Figure 11.5: PISO Logic Diagram and Symbol
Notice that there are four data-input lines, D0, D1, D2, and D3, and a SHIFT/LOAD input, which
allows four bits of data to be loaded in parallel into the register. When SHIFT/LOAD is LOW,
gates G1 through G3 are enabled, allowing each data bit to be applied to the D input of its
respective flip-flop. When a clock pulse is applied, the flip-flops with D = 1 will SET and those
with D = 0 will RESET, thereby storing all four bits simultaneously. When SHIFT/LOAD is
HIGH, gates G1 through G3 are disabled and gates G4 through G6 are enabled, allowing the data
bits to shift right from one stage to the next. The OR gates allow either the normal shifting
operation or the parallel data-entry operation, depending on which AND gates are enabled by
the level on the SHIFT/LOAD input.
The 74LS165 8-Bit Parallel Load Shift Register

The 74LS165 is an example of an IC shift register that has a parallel in/serial out operation (it can
also be operated serial in/serial out).
Figure 11.6: Logic Diagram for PISO
181
Notes
LOW on the SHIFT/LOAD input (SH/LD ) enables all the NAND gates for parallel loading.
When an input data bit is a 1, the flip-flop is asynchronously SET by a LOW out of the upper gate.
When an input data bit is a 0, the flip-flop is asynchronously RESET by a LOW out of the lower
gate. Additionally, data can be entered serially on the SER input. Also, the clock can be inhibited
anytime with a HIGH on the CLK INH input. The serial data outputs of the register am. Q7 and
its complement Q7. This implementation is different from the synchronous method of parallel
loading previously discussed, demonstrating that there are usually several ways to accomplish
the same function.
11.1.4 Parallel-In/Parallel-Out Shift Registers (PIPO)

PIPO supports immediate following of the simultaneous entry of all data bits, and the bits
appear on the parallel outputs.
Figure 11.7: Logic Diagram for PIPO
The 74LS195A 4-Bit Parallel Access Shift Register

The 74LS195A can be used for parallel in/parallel out operation. Since it also has a serial input,
it can be used for serial in/serial out and serial in/parallel out operations. It, can be used forparallel in/serial out operation by using Q3 as the output. When the SHIFT/LOAD input (SH/
LD ) is LOW, the data on the parallel inputs are entered synchronously on the positive transition
of the clock. When SH/LD is HIGH, stored data will shift right (Q0 to Q3) synchronously with
the clock. Inputs J and K are the serial data inputs to the first stage of the register (Q0); Q3 can be
used for serial output data. The active-LOW clear input is asynchronous.
Figure 11.8: Logic Diagram for 74LS195A 4-Bit Parallel Access Shift Register
182
11.1.5 Bidirectional Shift Registers
Notes
A bidirectional shift register is one in which the data can be shifted either left or right. It can be
implemented by using gating logic that enables the transfer of a data bit from one stage to the
next stage to the right or to the left, depending on the level of a control line. A 4-bit bidirectional
shift register is shown in Figure 11.9. A HIGH on the RIGHT/ LEFT control input allows data
bits inside the register to be shifted to the right, and a LOW enables data bits inside the register
to be shifted to the left. An examination of the gating logic will make the operation apparent.
When the RIGHT/LEFT control input is HIGH, gates G1 through G4 are enabled, and the state of
the Q output of each flip-flop is passed through to the D input of the following flip-flop. When
a clock pulse occurs, the data bits are shifted one place to the right. When the RIGHT/LEFT
control input is LOW, gates G5 through G8 are enabled, and the Q output of each flip-flop is
passed through to the D input of the preceding flip-flop. When a clock pulse occurs, the data bits
are then shifted one place to the left.
Figure 11.9: 4 bit Bidirectional Shift Register
The 74LS194A 4-Bit Bidirectional Universal Shift Register

The 74LS194A is an example of a universal bidirectional shift register in integrated circuit form.
A universal shift register has both serial and parallel input and output capability.
Figure 11.10: Block Diagram of 74LS194A 4-Bit Bidirectional Universal Shift Register
Parallel loading, which is synchronous with a positive transition of the clock, is accomplished
by applying the four bits of data to the parallel inputs and a HIGH to the S0 and S1 inputs. Shift
right is accomplished synchronously with the positive edge of the clock when S0 is HIGH and S1
is LOW. Serial data in this mode are entered at the shift-right serial input (SR SER). When S0 is
183
Notes
LOW and S1 is HIGH, data bits shift left synchronously with the clock, and new data are entered
at the shift-left serial input (SL SER). Input SR SER goes into the Q0 stage, and SL SER goes into
the Q3 stage.
Self Assessment
1.
A flip-flop is able to store multiple binary bits of information.
2.
An n-bit counter has n Flip-Flops and can cycle through at most 2n states.
3.
An n-bit register is a group of 2n flip-flops.
11.2 Ripple Counter

The external clock is connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes
state at the falling edge of each clock pulse, but FF1 changes only when triggered by the falling
edge of the Q output of FF0. Because of the inherent propagation delay through a flip-flop, the
transition of the input clock pulse and a transition of the Q output of FF0 can never occur at
exactly the same time. Therefore, the flip-flops cannot be triggered simultaneously, producing
an asynchronous operation.
Note For simplicity, the transitions of Q0, Q1 and CLK in the timing diagram above are
shown as simultaneous even though this is an asynchronous counter. Actually, there is
some small delay between the CLK, Q0 and Q1 transitions.
Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all the flipflops before counting starts. The clock pulse fed into FF0 is rippled through the other counters
after propagation delays, like a ripple on water, hence the name Ripple Counter. The 2-bit ripple
counter circuit above has four different states, each one corresponding to a count value. Similarly,
a counter with n flip-flops can have 2n states. The number of states in a counter is known as its
mod (modulo) number. Thus a 2-bit counter is a mod-4 counter. A mod-n counter may also
described as a divide-by-n counter. This is because the most significant flip-flop (the furthest
flip-flop from the original clock pulse) produces one pulse for every n pulses at the clock input
of the least significant flip-flop (the one triggers by the clock pulse).
Figure 11.11: A two-bit Asynchronous Counter
Source: http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/counter02.html
184
Notes
Self Assessment
4.
In a ripple counter the flip-flops can be triggered simultaneously.
5.
The number of states in a counter is known as its mod number.
6.
A counter with n flip-flops can have 2n states.
11.3 Synchronous Counters

In synchronous counters, the clock inputs of all the flip-flops are connected together and are
triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).
The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the
output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed
by the outputs of FF0 and FF1.
Figure 11.12: 3 bit Synchronous Counter
After the 3rd clock pulse, both outputs of FF0 and FF1 are HIGH. The positive edge of the 4th
clock pulse will cause FF2 to change its state due to the AND gate.
Figure 11.13: Timing Diagram
Table 11.2: Count Sequence
185
Notes
The most important advantage of synchronous counters is that there is no cumulative time
delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency
for this counter will be significantly higher than for the corresponding ripple counter.
11.3.1 4-bit Synchronous Binary Up Counter

Examining the four-bit binary count sequence, another predictive pattern can be seen. Notice
that just before a bit toggles, all preceding bits are high:
This pattern is also something we can exploit in designing a counter circuit. If we enable each
J-K flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are high, we
can obtain the same counting sequence as the asynchronous circuit without the ripple effect,
since each flip-flop in this circuit will be clocked at exactly the same time.
Figure 11.14: 4 bit Synchronous Up Counter
Source: http://www.vlsiencyclopedia.com/2011/07/4-bit-synchronous-down-counter.html
The result is a four-bit synchronous up counter. Each of the higher-order flip-flops are made
ready to toggle (both J and K inputs high) if the Q outputs of all previous flip-flops are high.
186
Otherwise, the J and K inputs for that flip-flop will both be low, placing it into the latch mode
where it will maintain its present output state at the next clock pulse. Since the first (LSB) flipflop needs to toggle at every clock pulse, its J and K inputs are connected to Vcc or Vdd, where they
will be high all the time. The next flip-flop need only recognize that the first flip-flops Q
output is high to be made ready to toggle, so no AND gate is needed. However, the remaining
flip-flops should be made ready to toggle only when all lower-order output bits are high, thus
the need for AND gates.
Notes
11.3.2 Binary Down Counters

To make a synchronous down counter, we need to build the circuit to recognize the appropriate
bit patterns predicting each toggle state while counting down. When we examine the four-bit
binary count sequence, we see that all preceding bits are low prior to a toggle (following the
sequence from bottom to top):
Since each J-K flip-flop comes equipped with a Q output as well as a Q output, we can use the Q
outputs to enable the toggle mode on each succeeding flip-flop, being that each Q will be high
every time that the respective Q is low.
Figure 11.15: 4 bit Synchronous Down Counter
187
Notes
11.3.3 Binary Up/Down Counters

We can build a counter circuit with selectable between up and down count modes by having
dual lines of AND gates detecting the appropriate bit conditions for an up and a down counting
sequence, respectively, then use OR gates to combine the AND gate outputs to the J and K inputs
of each succeeding flip-flop.
Figure 11.16: 4 bit Synchronous Up/Down Counter
The Up/Down control input line simply enables either the upper string or lower string of AND
gates to pass the Q/Q outputs to the succeeding stages of flip-flops. If the Up/Down control line
is high, the top AND gates become enabled, and the circuit functions exactly the same as the first
(up) synchronous counter circuit shown in this section. If the Up/Down control line is made
low, the bottom AND gates become enabled, and the circuit functions identically to the
second (down counter) circuit.
Figure 11.17: Counter in up Counting Mode
Figure 11.18: Counter in Down Counting Mode
11.3.4 MOD-N/Divide-by-N Counters

A counter with n flip-flops can have 2n states. The number of states in a counter is known as its
mod (modulo) number. Thus a 2-bit counter is a mod-4 counter. A mod-n counter may also
188
described as a divide-by-n counter. This is because the most significant flip-flop (the furthest
flip-flop from the original clock pulse) produces one pulse for every n pulses at the clock input
of the least significant flip-flop (the one triggers by the clock pulse).
Notes
Figure 11.19: Next State Table and Circuit Diagram of

3-bit Synchronous Binary MOD-6 Counter
Source:http://www.uobabylon.edu.iq/eprints/paper_1_7967_163.pdf
Figure 11.20: 3-bit Synchronous Binary MOD-6 Counter
Source: http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#mod
MOD-6 counters will count from 010 (0002) to 510(1012) and after that will recount back to 010
(0002) continuously.
11.3.5 Binary Coded Decimal (BCD) Counters

A BCD counter or decade counter can be constructed from a straight binary counter by terminating
the ripple-through counting when the count reaches decimal 9 (binary 1001). Since the next
toggle would produce 1010, that drives both X1 and X3 high, and since they are the inputs to the
NAND gate, the output of the NAND goes low. This zero output to the asynchronous clear line
will clear the registers and start the count over after 9.
11.3.6 Ring Counters

A ring counter is a type of counter composed of a type circular shift register. The output of the
last shift register is fed to the input of the first register. There are two types of ring counters:
A straight ring counter or Overbeck counter connects the output of the last shift register to
the first shift register input and circulates a single one (or zero) bit around the ring.
Example, in a 4-register one-hot counter, with initial register values of 1000, the repeating
189
Notes
pattern is: 1000, 0100, 0010, 0001, 1000... . Note that one of the registers must be pre-loaded
with a 1 (or 0) in order to operate properly.
A twisted ring counter, also called Johnson counter or Mbius counter that connects the
complement of the output of the last shift register to the input of the first register and
circulates a stream of ones followed by zeros around the ring. Example, in a 4-register
counter, with initial register values of 0000, the repeating pattern is: 0000, 1000, 1100, 1110,
1111, 0111, 0011, 0001, 0000... .
Figure 11.21: Ring Counter
Source: http://en.wikipedia.org/wiki/Ring_counter
11.3.7 Johnson/Twisted-Ring Counters

The switch-tail ring counter, also known as the Johnson counter, overcomes some of the
limitations of the ring counter. Like a ring counter a Johnson counter is a shift register fed back
on its self. It requires half the stages of a comparable ring counter for a given division ratio. If
the complement output of a ring counter is fed back to the input instead of the true output, a
Johnson counter results.
Note The difference between a ring counter and a Johnson counter is which output of the
last stage is fed back (Q or Q).
Figure 11.22: Johnson Counter
This reversed feedback connection has a profound effect upon the behavior of the otherwise
similar circuits. Recirculating a single 1 around a ring counter divides the input clock by a factor
equal to the number of stages. Whereas, a Johnson counter divides by a factor equal to twice the
number of stages. For example, a 4-stage ring counter divides by 4. A 4-stage Johnson counter
divides by 8.
190
11.3.8 Loadable/Presettable Counters
Notes
Instead of counting from 0, a counter can be made to count from a given initial value. This type
of counter is called a loadable counter.
Figure 11.23: Loadable Counter
Source: http://www.vlsiencyclopedia.com/2011/10/loadable-counters.html
Task Find out the working of a loadable counter.
Self Assessment
Fill in the blanks:
7.
The most important advantage of synchronous counters is that there is no cumulative

time delay because all flip-flops are triggered in ........................ .
8.
A 2-bit counter is a mod ........................ counter.
9.
In a ring counter the output of the ........................ shift register is fed to the input of the
........................ register.
10.
A Johnson counter divides by a factor equal to ........................ the number of stages.
191
Notes
11.4 Memory Decoding

The processor can usually address a memory space that is much larger than the memory space
covered by an individual memory chip. In order to splice a memory device into the address
space of the processor, decoding is necessary.
Example: The 8088 issues 20bit addresses for a total of 1MB of memory address space.
However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. A decoder
can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB
section of the 1MB address space.
There are some situations when all addressable memory space is not to be implemented. If only
a portion of the addressable space is going to be implemented there are two basic address
decoding strategies:
1.
Full address decoding.
2.
All the address lines are used to specify a memory location. Each physical memory location
is identified by a unique address.
Example: Lets assume the same microprocessor with 10 address lines (1KB memory).
However, this time we wish to implement only 512 bytes of memory. We still must use 128-byte
memory chips. Physical memory must be placed on the upper half of the memory map.
Figure 11.24: Full Address Decoding
Source: http://research.cs.tamu.edu/prism/lectures/mbsd/mbsd_l16.pdf
Partial Address Decoding

Since not all the address space is implemented, only a subset of the address lines are needed to
point to the physical memory locations. Each physical memory location is identified by several
possible addresses (using all combinations of the address lines that were not used).
192
Notes
Example: Lets assume the same microprocessor with 10 address lines (1KB memory).
However, this time we wish to implement only 512 bytes of memory. We still must use 128-byte
memory chips. Physical memory must be placed on the upper half of the memory map.
Figure 11.25: Partial Address Decoding
Source: http://research.cs.tamu.edu/prism/lectures/mbsd/mbsd_l16.pdf
11.4.1 Block Address Decoding

This decoding scheme divides the address space into blocks. It then fully decode each block
using high order bits. For this single-chip decoders are available.
Example: A 4 to 16-line decoder divides the address space into 16 blocks i.e. 512KB
blocks for 68000.
It can also subdivide within block by cascading decoder chips with more address inputs. To do
this, feed some low-order address bits to chip address inputs and put memory device at each
block start.
Self Assessment
Fill in the blanks:
11.
Instead of counting from 0, a counter can be made to count from a given initial value. This
type of counter is called a ........................ counter.
12.
All the address lines are used to specify a memory location. Each physical memory location
is identified by a unique address. This is called ........................ decoding.
13.
........................ address decoding is a decoding scheme divides the address space into blocks.
11.5 Semiconductor Memories

Semiconductor memory is an electronic data storage device, often used as computer memory,
implemented on a semiconductor-based integrated circuit. It is made in many different types
193
Notes
and technologies. Semiconductor memory has the property of random access, which means
that it takes the same amount of time to access any memory location, so data can be efficiently
accessed in any random order. This contrasts with data storage media such as hard disks and
CDs which read and write data consecutively and therefore the data can only be accessed in the
same sequence it was written. Semiconductor memory also has much faster access times than
other types of data storage; a byte of data can be written to or read from semiconductor
memory within a few nanoseconds, while access time for rotating storage such as hard disks
is in the range of milliseconds. For these reasons it is used for main computer memory
(primary storage), to hold data the computer is currently working on, among other uses. Shift
registers, processor registers, data buffers and other small digital registers that have no memory
address decoding mechanism are not considered as memory although they also store digital
data.
11.5.1 Types of Semiconductor Memory

Electronic semiconductor memory technology can be split into two main types or categories,
according to the way in which the memory operates:
Random Access Memory (RAM)

RAM has become a generic term for any semiconductor memory that can be written to, as well
as read from, in contrast to ROM which can only be read. It should be noted that all semiconductor
memory, not just RAM, has the property of random access.
Volatile memory loses its stored data when the power to the memory chip is turned off. However
it can be faster and less expensive than non-volatile memory. This type is used for the main
memory in most computers, since data is stored on the hard disk while the computer is off.
Read Only Memory (ROM)

This is designed to hold permanent data, and in normal operation is only read from, not
written to. Although some types can be written to, the writing process is slow and usually all
the data in the chip must be rewritten at once. It is usually used to store system software which
must be immediately accessible to the computer, such as the BIOS program which starts the
computer, and the software for portable devices and embedded computers such as
microcontrollers.
11.5.2 Semiconductor Memory Technologies

There is a large variety of types of ROM and RAM that are available. Some of them are:
PROM (Programmable Read-Only Memory)

In this type the data is written into the chip before it is installed in the circuit, but it can only be
written once. The data is written by plugging the chip into a device called a PROM programmer.
EPROM (Erasable Programmable Read-Only Memory)

In this type the data in it can be rewritten by removing the chip from the circuit board,
exposing it to an ultraviolet light to erase it, and plugging it into a PROM programmer. The IC
package has a small transparent window in the top to admit the UV light. It is often used for
prototypes and small production run devices, where the program in it must be changed at the
factory.
194
Notes
EEPROM (Electrically Erasable Programmable Read-Only Memory)

In this type the data can be rewritten electrically, while the chip is on the circuit board, but the
writing process is slow. This type is used to hold firmware, the low level microcode which runs
hardware devices, such as the BIOS program in most computers, so that it can be updated.
NVRAM (Flash Memory)

In this type the writing process is intermediate in speed between EEPROMS and RAM memory;
it can be written to, but not fast enough to serve as main memory. It is often used as a
semiconductor version of a hard disk, to store files. It is used in portable devices such as PDAs,
USB flash drives, and removable memory cards used in digital cameras and cellphones.
DRAM (Dynamic Random-Access Memory)

It uses memory cells consisting of one capacitor and one transistor to store each bit. This is the
cheapest and highest in density, so it is used for the main memory in computers. However the
electric charge that stores the data in the memory cells slowly leaks off, so the memory cells
must be periodically refreshed (rewritten), requiring additional circuitry. The refresh process is
automatic and transparent to the user.
SRAM (Static Random-Access Memory)

It relies on several transistors forming a digital flip-flop to store each bit. This is less dense and
more expensive per bit than DRAM, but faster and does not require memory refresh. It is used
for smaller cache memories in computers.
SDRAM (Synchronous Dynamic Random-Access Memory)

This was a reorganization of the DRAM memory chip, which added a clock line to enable it to
operate in synchronism with the computers memory bus clock. The data on the chip is divided
into banks so it can work on several memory accesses simultaneously, in separate banks. It
became the dominant type of computer memory by about the year 2000.
Magnetoresistive Random-Access Memory (MRAM)

It is a non-volatile random-access memory technology under development since the 1990s.
Continued increases in density of existing memory technologies notably flash RAM and
DRAM kept it in a niche role in the market, but its proponents believe that the advantages are
so overwhelming that magnetoresistive RAM will eventually become dominant for all types of
memory, becoming a universal memory.
Case Study
Semiconductor History
emory chips have been called the crude oil of the twenty-first century. They are
used in a wide variety of electronic applications from childrens toys to
sophisticated communication satellites. The current generation of memory chip
(64Mb) is capable of storing about 3,355 pages of text on a piece the size of a dime.
Contd...
195
Notes
What is a Semiconductor?
A number of elements are classified as semiconductors including silicon, zinc, and
germanium. These elements have the ability to conduct electrical current, and they can be
regulated in the amount of their conductivity. Silicon is the most widely used
semiconductor material because it is easily obtained. Silicon is basically extracted from
sand. It has been used for centuries to make cast iron, bricks, and pottery. In ultra-pure
form, the controlled addition of minute amounts of certain impurities (called dopants)
alters the atomic structure of the silicon. The silicon can then be made to act as a conductor
or a nonconductor, depending upon the polarity of an electrical charge applied to it.
Hence, the generic term semiconductor.
Early Developments
Semiconductor materials were studied in laboratories as early as 1830. The first materials
studied were a group of elements and compounds that were usually poor conductors if
heated. Shining light on some of them would generate an electrical current that could pass
through them in one direction only.
By 1874, electricity was being used not only to carry power, but to carry information. The
telegraph, telephone, and later the radio were the earliest devices in an industry that
would eventually be called electronics.
Radio receivers required a device called a rectifier to detect signals. Ferdinand Braun used
the rectifying properties of the galena crystal, a semiconductor material composed of lead
sulfide, to create the cats whisker diode for this purpose. Thus was born the first
semiconductor device.
The Integrated Circuit
Until 1959, all electronic components were discrete: that is, they performed only one
function, and many of them had to be wired together to create a functional circuit. Although
a great number of identical discrete transistors could be fabricated on a single wafer, they
then had to be cut up and individually packaged in tiny cans. Packaging each component
and hand wiring the components into circuits was extremely inefficient. The military
sought more efficient methods of making circuits.
New technologies emerged and integrated circuits were soon developed with various
components (transistors, resistors, and capacitors) formed on the same chip, but
interconnection of the various components still required tedious hand wiring.
In 1959, Jean Hoerni and Robert Noyce developed a new process called planar technology
at Fairchild Semiconductor which enabled them to diffuse various layers onto the surface
of a silicon wafer to make a transistor, leaving a layer of protective oxide on the junctions.
This process allowed metal interconnections to be evaporated onto the flat transistor
surface and replaced the hand wiring. The new process used silicon instead of germanium,
and made commercial production of ICs possible.
The initial resistance to the new IC technology gave way to enormous popularity. By the
end of the 1960s, nearly 90% of all the components manufactured were integrated circuits.
Questions:
1.
Discuss the evolution of a Semiconductor.
2.
Discuss the use of planer technology.
Source: http://www.micron.com/foundation/semiconductors
196
Notes
Self Assessment
Fill in the blanks:
14.
Semiconductor memory is broadly classified as ........................ and ........................ .
15.
Data can be rewritten electrically in a ........................ .
11.6 Summary
In digital circuits multi-bit data has to be stored temporarily until it is processed.
A flip-flop is able to store a single binary bit of information.
Counter is a sequential circuit (aka. Finite state machine) that cycles through a fixed
sequence of states.
The shift operation of the binary data is carried out by applying clock signals.
An n-bit counter has n Flip-Flops and can cycle through at most 2n states.
Shift Registers is a series of flip flops, sharing the same clock, in which the output of each
flip-flop is connected to the data input of the next flip-flop in the chain.
Registers are groups of flip-flops, where each flip-flop is capable of storing one bit of
information.
An n-bit register is a group of n flip-flops.
Storage Capacity is the total number of bits (1 or 0) of digital data it can retain.
The flip-flops cannot be triggered simultaneously, producing an asynchronous operation

resulting in what is a ripple counter.
The number of states in a counter is known as its mod (modulo) number.
In synchronous counters, the clock inputs of all the flip-flops are connected together and
are triggered by the input pulses.
A ring counter is a type of counter composed of a type circular shift register. The output of
the last shift register is fed to the input of the first register.
If the complement output of a ring counter is fed back to the input instead of the true
output, a Johnson counter results.
Instead of counting from 0, a counter can be made to count from a given initial value. This
type of counter is called a loadable counter.
Semiconductor memory is an electronic data storage device, often used as computer

memory, implemented on a semiconductor-based integrated circuit. It is of two types
RAM and ROM.
11.7 Keywords
Counter: It is a sequential circuit that cycles through a fixed sequence of states.
Flip-flop: It stores a single binary bit of information.
Mod: The number of states in a counter.
Registers: They are groups of flip-flops, where each flip-flop is capable of storing one bit of
information.
197
Notes
Ripple Counter: The flip-flops in this cannot be triggered simultaneously, producing an

asynchronous operation.
Shift Registers: It is a series of flip flops, sharing the same clock, in which the output of each flipflop is connected to the data input of the next flip-flop in the chain.
Storage Capacity: It is the total number of bits (1 or 0) of digital data it can retain.
Synchronous Counters: It has the clock inputs of all the flip-flops are connected together and are
triggered by the input pulses.

1.
What is a register? Why is it used?
2.
Explain a flip flop.
3.
What are shift registers?
4.
Differentiate between SIPO and SISO.
5.
What is a ring counter?
6.
Explain the types of ring counters.
7.
What is the major difference between a ring and a Johnson counter?
8.
Explain full address decoding.
9.
What are RAM and ROM?
10.
Elaborate upon the types of semiconductor memory.

1.
False
2.
True
3.
False
4.
False
5.
True
6.
True
7.
Parallel
8.
9.
Last, First
10.
Twice
11.
Loadable
12.
Full Addressing
13.
Block Addressing
14.
RAM, ROM
15.
EEPROM
Books
& Sons
198
Notes
Online links
http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html
http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/register07.html
http://www.electronics-tutorials.ws/counter/count_3.html
http://www.most.gov.mm/techuni/media/EcE_01031_5.pdf
199
Notes
Unit 12: A/D and D/A Converters

CONTENTS
Objectives
Introduction
12.1
Variables-Resistor Networks
12.1.1
Binary Equivalent Weight
12.1.2
Resistive Divider
12.2
Binary Ladders
12.3
D/A Converters
12.3.1
Multiple Signals
12.3.2
D/A Converter Testing
12.3.3
Available D/A Converters
12.4
D/A Accuracy and Resolution
12.5
A/D ConverterSimultaneous Conversion
12.6
A/D Converter-Counter Method
12.7
Continuous A/D Conversion
12.8
A/D Techniques
12.9
12.8.1
Successive Approximation
12.8.2
The ADC0804
12.8.3
Section Counters
Dual-Slope A/D Conversion

12.9.1
Single-Ramp A/D Converter
12.10
Single-Slope A/D Converter
12.11
Dual-slope A/D Converter
12.12
Successive Approximation A/D Converter
12.13
Flash Converters
12.14
Summary
12.15
Keywords
12.16
Review Questions
12.17
Further Readings
Objectives
200
Explain variables-resistor networks
Discuss binary ladders
Notes
Describe D/A converters
Explain A/D converters and techniques
Discuss dual-slope A/D conversion
Describe the single-slope A/D converter
Explain the dual-slope A/D converter
Describe the successive approximation A/D converter
Discuss flash converters
Introduction
Many of the electrical measurements are intrinsically analog. To take advantage of the great
capabilities available for digital data storage, processing, and computation, on the other hand,
requires the conversion of analog to digital. Hence, analog to digital (A/D) conversion techniques
have become extremely important. A great deal of technical effort has gone into producing A/
D converters (ADCs) which are fast, accurate, and cheap. D/A converters (DACs) are also very
important. Analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) are
processes that allow computers interact with analog signals. Digital information is different
from the analog counterpart in two important respects: it is sampled and it is quantized . These
operations restrict the information a digital signal can contain. Thus, it is important to understand
what information you need to retain and what information you can afford to lose. These are
information management questions. The understanding of these restrictions will allow us decide
how to select the sampling frequency, number of bits, and the type of filter for converting
between the analog and digital realms.
Example: Video monitors convert digital information generated by computers to analog
signals which are used to direct the electron beam at a specified portion of the monitor screen. DACs
are conceptually simpler than ADCs, although it is difficult in practice to build a precise DAC.
Principle of analog-to-digital conversion

Conversion from analog to digital form inherently involves comparator action where the value
of the analog voltage at some point in time is compared with some standard. A common way to
do that is to apply the analog voltage to one terminal of a comparator and trigger a binary
counter which drives a DAC. The output of the DAC is applied to the other terminal of the
comparator. Since the output of the DAC is increasing with the counter, it will trigger the
comparator at some point when its voltage exceeds the analog input. The transition of the
comparator stops the binary counter, which at that point holds the digital value corresponding
to the analog voltage.
12.1 Variables-Resistor Networks

By designing a resistive network, we can convert each digital level into an equivalent binary
weighted voltage. This is needed when we need to convert a digital signal into an equivalent
analog signal change the n digital voltage levels into one equivalent analog voltage.
12.1.1 Binary Equivalent Weight

A D/A converter using binary-weighted resistors is shown in the figure below. In the circuit, the
op-amp is connected in the inverting mode. The op-amp can also be connected in the
201
Notes
non-inverting mode. The circuit diagram represents a 4-digit converter. Thus, the number of
binary inputs is four.
Figure 12.1: D/A Converter
Source: http://www.circuitstoday.com/digital-to-analog-converters-da
A D/A Converter is used when the binary output from a digital system is to be converted into
its equivalent analog voltage or current. The binary output will be a sequence of 12s and 02s.
Thus they may be difficult to follow. But, a D/A converter help the user to interpret easily.
A D/A converter using binary-weighted resistors is shown in the figure above. In the circuit, the
op-amp is connected in the inverting mode. The op-amp can also be connected in the noninverting mode. The circuit diagram represents a 4-digit converter. Thus, the number of binary
inputs is four.
We know that, a 4-bit converter will have 24 = 16 combinations of output. Thus, a corresponding
16 outputs of analog will also be present for the binary inputs. Four switches from b0 to b3 are
available to simulate the binary inputs: in practice, a 4-bit binary counter such as a 7493 can also
be used.
The circuit is basically working as a current to voltage converter.
b0 is closed.
It will be connected directly to the +5V. Thus, voltage across R = 5V
Current through R = 5V/10kohm = 0.5mA
Current through feedback resistor, Rf = 0.5mA (Since, Input bias current, IB is negligible)
Thus, output voltage = -(1kohm)*(0.5mA) = -0.5V
b1 is closed, b0 is open
R/2 will be connected to the positive supply of the +5V.
Current through R will become twice the value of current (1mA) to flow through Rf.
Thus, output voltage also doubles.
202
Notes
b0 and b1 are closed

Current through Rf = 1.5mA
Output voltage = -(1kohm)*(1.5mA) = -1.5V
Thus, according to the position (ON/OFF) of the switches (bo-b3), the corresponding binaryweighted currents will be obtained in the input resistor. The current through Rf will be the sum
of these currents. This overall current is then converted to its proportional output voltage.
Naturally, the output will be maximum if the switches (b0-b3) are closed
V0 = -Rf *([b0/R][b1/(R/2)][b2/(R/4)][b3/(R/8)]) where each of the inputs b3, b2, b1, and b0
may either be HIGH (+5V) or LOW (0V).
The graph with the analog outputs versus possible combinations of inputs is shown below:
Figure 12.2: Graph with Analog Input Versus Output
Source: http://www.circuitstoday.com/digital-to-analog-converters-da
The output is a negative going staircase waveform with 15 steps of -).5V each. In practice, due to
the variations in the logic HIGH voltage levels, all the steps will not have the same size. The
value of the feedback resistor Rf changes the size of the steps. Thus, a desired size for a step can
be obtained by connecting the appropriate feedback resistor. The only condition to look out for
is that the maximum output voltage should not exceed the saturation levels of the op-amp.
Metal-film resistors are more preferred for obtaining accurate outputs.
Note If the number of inputs (>4) or combinations (>16) is more, the binary-weighted
resistors may not be readily available. This is why; R and 2R method is more preferred as
it requires only two sets of precision resistance values.
12.1.2 Resistive Divider

Resistive voltage divider (also known as a potential divider) is a linear circuit that produces an
output voltage (Vout) that is a fraction of its input voltage (Vin). Voltage division refers to the
partitioning of a voltage among the components of the divider.
Example: An example of voltage divider consists of two resistors in series or a
potentiometer. It is commonly used to create a reference voltage, or to get a low voltage signal
proportional to the voltage to be measured, and may also be used as a signal attenuator at low
203
Notes
frequencies. For direct current and relatively low frequencies, a voltage divider may be
sufficiently accurate if made only of resistors; where frequency response over a wide range is
required, (such as in an oscilloscope probe), the voltage divider may have capacitive elements
added to allow compensation for load capacitance. In electric power transmission, a capacitive
voltage divider is used for measurement of high voltage.
A voltage divider referenced to ground is created by connecting two electrical impedances in
series, as shown in Figure 1. The input voltage is applied across the series impedances Z1 and Z2
and the output is the voltage across Z2. Z1 and Z2 may be composed of any combination of
elements such as resistors, inductors and capacitors.
Applying Ohms Law, the relationship between the input voltage, Vin, and the output voltage,
Vout, can be found:
Vout =
Z2
.Vin
Z1 + Z 2
Proof:
Vin = I .(Z1 + Z2 )
Vout = I .Z2
I =
Vin
Z1 + Z2
Vout = Vin .
Z2
Z1 + Z2
The transfer function (also known as the dividers voltage ratio) of this circuit is simply:
H =
Vout
Z2
=
Va
Z1 + Z2
In general this transfer function is a complex, rational function of frequency.

Example: A resistive divider is the case where both impedances, Z1 and Z2, are purely
resistive (Figure 12.3 below).
Figure 12.3: RVD
Source: http://en.wikipedia.org/wiki/File:Resistive_divider.png
Substituting Z1 = R1 and Z2 = R2 into the previous expression gives:
Vout =
204
R2
.Vin
R1 + R2
Notes
If R1 = R2 then
Vout =
1
.Vin
2
If Vout=6V and Vin=9V (both commonly used voltages), then:

Vout
Vin
R2
6 2
= =
R1 + R2 9 3
and by solving using algebra, R2 must be twice the value of R1.

To solve for R1:
R1 =
R2 .Vin
R2
Vout
To solve for R2:
R2 =
R1
Vin
V 1
out
Any ratio between 0 and 1 is possible. That is, using resistors alone it is not possible to either
invert the voltage or increase Vout above Vin.
Self Assessment
1.
By designing a resistive network, we can convert each digital level into an equivalent
binary weighted voltage.
2.
Voltage division refers to the partitioning of a voltage among the components of the
divider.
12.2 Binary Ladders

A ladder is an electrical circuit made of repeating units of resistors. An R-2R Ladder is a simple
and inexpensive way to perform digital-to-analog conversion, using repetitive arrangements of
precision resistor networks in a ladder-like configuration. A string resistor ladder implements
the non-repetitive reference network.
Figure 12.4: n bit R-2R Resistor Ladder
Source: http://en.wikipedia.org/wiki/File:R2r-ladder.png
A basic R-2R resistor ladder network is shown in Figure 12.4 above. Bit an-1 MSB (most significant
bit) to Bit a0 LSB (least significant bit) are driven from digital logic gates. Ideally, the bits are
switched between 0 volts (logic 0) and Vref (logic 1). The R-2R network causes the digital bits to
be weighted in their contribution to the output voltage Vout. In this circuit 5 bits are shown (bits
4-0), giving (25) or 32 possible analog voltage levels at the output. Depending on which bits are
set to 1 and which to 0, the output voltage (out) will be a corresponding stepped value between
205
Notes
0 volts and (Vref minus the value of the minimum step, Bit0). The actual value of Vref (and 0 volts)
will depend on the type of technology used to generate the digital signals.
For a digital value VAL, of a R-2R DAC of N bits of 0 V/Vref, the output voltage Vout is:
Vout = Vref VAL / 2N
In the example shown, N = 5 and hence 2N = 32. With Vref = 3.3 V (typical CMOS logic 1 voltage),
Vout will vary between 00000, VAL = 0 and 11111, VAL = 31.
Minimum (single step) VAL = 1, we have
Vout = 3.3 1 / 32 = 0.1 volts
Maximum output (11111 VAL = 31, we have
Vout = 3.3 31 / 25 = 3.2 volts
The R-2R ladder is inexpensive and relatively easy to manufacture since only two resistor values
are required (or 1, if R is made by placing a pair of 2R in parallel, or if 2R is made by placing a pair
of R in series). It is fast and has fixed output impedance R. The R-2R ladder operates as a string of
current dividers whose output accuracy is solely dependent on how well each resistor is matched
to the others. Small inaccuracies in the higher significant bit resistors can entirely overwhelm the
contribution of the less significant bits. This may result in non-monotonic behavior at major
crossings, such as from 01111 to 10000. Depending on the type of logic gates used and design of the
logic circuits, there may be transitional voltage spikes at such major crossings even with perfect
resistor values. These can be filtered, with capacitance at the output node for instance (the consequent
reduction in bandwidth may be significant in some applications). Finally, the 2R resistance is in
series with the digital output impedance. High output impedance gates (e.g., LVDS) may be
unsuitable in some cases. For all of the above reasons (and doubtless others), this type of DAC
tends to be restricted to a relatively small number of bits, although integrated circuits may push
the number of bits to 14 or even more, 8 bits or fewer is more typical.
Self Assessment
Fill in the blanks:
3.
A ladder is an electrical circuit made of repeating units of ........................ .
4.
An R-2R Ladder is a simple and inexpensive way to perform ........................ -to-........................

conversion.
12.3 D/A Converters

A digital to analog converter (DAC) converts a digital signal to an analog voltage or current
output.
Figure 12.5: D/A Converter
Source: www.me.gatech.edu/mechatronics_course/DAC_S06.ppt
206
Figure 12.6: DAC Converter
Notes
Many types of DACs are available. Usually switches, resistors, and op-amps are used to implement
conversion. Majorly two types of DAC are used:
Binary Weighted Resistor
R-2R Ladder
We are going to start by examining a simple circuit. This circuit is an operational amplifier
circuit with three input voltages.
Figure 12.7: Circuit
Source: http://www.facstaff.bucknell.edu/mastascu/elessonsHTML/Interfaces/ConvDA.html
Each input voltage is either zero volts or five volts and represents a logical 0 or 1. The input
resistors are chosen so that they are not all equal. The resistors are related by: Rc = 2Rb = 4Ra.
To understand how this circuit works we will need to obtain a symbolic expression for the
output voltage one in which we express the output voltage in terms of the binary number that
the input represents. We already have an expression for the output voltage.
Vout = (RfVa /Ra) + (RfVb /Rb) + (RfVc /Rc)
We need to interpret this output voltage expression when the inputs represent a binary number.
Lets examine the expression for the output voltage using the relation we required for the
resistors.
Rc = 2Rb = 4Ra
Then, the output voltage expression becomes:
Vout = (RfVa /Ra) + (RfVb /Rb) + (RfVc /Rc)
Vout = (RfVa /Ra) + (RfVb /2Ra) + (RfVc /4Ra)
207
Notes
Each input voltage is either zero (0) or five (5) volts, representing either a zero or a one. Although
we shouldnt mix Boolean algebra variables and ordinary algebraic variables, we are going to.
Were going to say,
V a = 5A2
V b = 5A1
Vc = 5Ao
So ,
Vout = (Rf/4Ra)(4Va + 2Vb + Vc )
Vout = (5Rf/4Ra)(4A2 + 2A1 + Ao )
The expression - (4A2 + 2A1 + Ao ) can be regarded as the binary number represented by A2, A1
and Ao. This table shows the equivalence.
Table 12.1: Truth Table Showing Equivalence
Source: http://www.facstaff.bucknell.edu/mastascu/elessonsHTML/Interfaces/ConvDA.html
In other words, A2 is the 4 bit, A1 is the 2 bit and Ao is the 1 bit.

After all this, we reach these conclusions for this circuit:
The inputs can be thought of as a binary number, one that can run from zero (0) to seven
(7).
The output is a voltage that is proportional to the binary number input.
The circuit itself converts a digital representation of a number to an analog version of the
same number. The circuit is a digital-to-analog converter also known as a D/A converter.
What if we wanted to convert a digital signal with more bits?

More input resistances are needed.
The resistances should be chosen in ratios of 2.
The LSB has the largest resistance.
More significant bits have resistances that decrease by a factor of 2.
12.3.1 Multiple Signals

Sample and hold circuit is an analog device that samples the voltage of a continuously varying
analog signal and holds its value at a constant level for a specified minimal period of time.
Sample and hold circuits and related peak detectors are the elementary analog memory devices.
208
They are typically used in analog-to-digital converters to eliminate variations in input signal
that can corrupt the conversion process.
Notes
A typical sample and hold circuit stores electric charge in a capacitor and contains at least one
fast FET switch and at least one operational amplifier. To sample the input signal the switch
connects the capacitor to the output of a buffer amplifier. The buffer amplifier charges or
discharges the capacitor so that the voltage across the capacitor is practically equal, or proportional
to, input voltage. In hold mode the switch disconnects the capacitor from the buffer. The capacitor
is invariably discharged by its own leakage currents and useful load currents, which makes the
circuit inherently volatile, but the loss of voltage (voltage drop) within a specified hold time
remains within an acceptable error margin.
In the context of LCD screens, it is used to describe when a screen samples the input signal, and
the frame is held there without redrawing it. This does not allow the eye to refresh and leads to
blurring during motion sequences, also the transition is visible between frames because the
backlight is constantly illuminated, adding to display motion blur.
Figure 12.8: Sample and Hold Circuit
Source: http://en.wikipedia.org/wiki/Sample_and_hold
Steady-state: Sample-and-hold amplifier. When the switch is closed, the capacitor charges to
the D/A.
Accuracy Test: Converter output voltage. When the switch is opened, the capacitor holds the
voltage level until the next sampling time. The operational amplifier provides large input
impedance.
Monotonicity Test: So as not to discharge the capacitor appreciably and at the same time offers
gain to drive external circuits.
12.3.2 D/A Converter Testing

The steady-state accuracy test involves setting a known digital number in the input register,
measuring the analog output with an accurate meter, and comparing with the theoretical value.
Checking for monotonicity means checking that the output voltage increases regularly as the
input digital signal increases: This can be accomplished by using a counter as the digital input
signal and observing the analog output on an oscilloscope. For proper monotonicity, the output
waveform should be a perfect staircase waveform. The steps on the staircase waveform must be
equally spaced and of the exact same amplitude. Missing steps, steps of different amplitude, or
steps in a downward fashion indicate malfunctions.
The monotonicity test does not check the system for accuracy, but if the system passes the test, it
is relatively certain that the converter error is less than 1 LSB. A D/A converter can be regarded
as a logic block having numerous digital inputs and a single analog output It is interesting to
compare this logic block with the potentiometer. The analog output voltage of the D/A converter
is controlled by the digital input signals, while the analog output voltage of the potentiometer
is controlled by mechanical rotation of the potentiometer shaft. Considered in this fashion, it is
easy to see how a D/A converter could be used to generate a voltage waveform (saw tooth,
triangular, sinusoidal, etc.). It is, in effect, a digitally controlled voltage generator!
209
Notes
12.3.3 Available D/A Converters

The DAC0808 is an 8-bit monolithic digital-to-analog converter (DAC) featuring a full scale
output current settling time of 150 ns while dissipating only 33 mW with 5V supplies. No
reference current (IREF) trimming is required for most applications since the full scale output
current is typically 1 LSB of 255 IREF/256. Relative accuracies of better than 0.19% assure 8 bit
monotonicity and linearity while zero level output current of less than 4 A provides 8-bit zero
accuracy for IREF2 mA. The power supply currents of the DAC0808 is independent of bit codes,
and exhibits essentially constant device characteristics over the entire supply voltage range. The
DAC0808 will interface directly with popular TTL, DTL or CMOS logic levels, and is a direct
replacement for the MC1508/MC1408. For higher speed applications.
Figure 12.9: DAC0808
Source: http://www.ti.com/lit/ds/symlink/dac0808.pdf
Self Assessment
5.
The monotonicity test does not check the system for accuracy.
6.
The DAC0808 is an 8-bit monolithic analog to digital converter.
12.4 D/A Accuracy and Resolution

The accuracy is usually expressed by the error in output voltage compared with the expected
output voltage. The higher the accuracy, the lower will be the error. Due to the incremental
nature of the digital input word, an error can be tolerated but it should not exceed LSB or
resolution.
Example: The error at full-scale for an 8-bit DAC with 10V maximum output is 50mV.
Calculate the error and compare it with the resolution.
Error =
210
0.05
100% = 0.5%
10
Resolution =
1
100% = 0.391%
256
Notes
Resolution = 0.195%
The accuracy is not as good as the error = resolution, but for many applications, it is quite
satisfactory. Some commercially available DACs have their accuracy specified as worse than
resolution.
Resolution is the amount of variance in output voltage for every change of the LSB in the digital
input. How closely can we approximate the desired output signal (Higher Res. = finer
detail=smaller Voltage divisions) A common DAC has a 812 bit Resolution.
Resolution = VLSB =
VRef
2N
N = Number of bits
Figure 12.10: Resolution
Example: Calculate the resolution of an 8-bit DAC.

Resolution = 8 bits
Percentage resolution =
1
1
100% =
100% = 0.391%
28
256
Self Assessment
Fill in the blanks:
7.
The ........................ the accuracy, the ........................ will be the error.
8.
An error can be tolerated but it should not exceed ........................ LSB or ........................
resolution.
12.5 A/D ConverterSimultaneous Conversion

Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of
a series of comparators, each one comparing the input signal to a unique reference voltage.
211
Notes
The comparator outputs connect to the inputs of a priority encoder circuit, which then produces
a binary output. The following illustration shows a 3-bit flash ADC circuit:
Figure 12.11: Flash ADC circuit
Vref is a stable reference voltage provided by a precision voltage regulator as part of the converter
circuit, not shown in the schematic. As the analog input voltage exceeds the reference voltage at
each comparator, the comparator outputs will sequentially saturate to a high state. The priority
encoder generates a binary number based on the highest-order active input, ignoring all other
active inputs. When operated, the flash ADC produces an output that looks something like this:
Figure 12.12: Output of flash ADC
For this particular application, a regular priority encoder with all its inherent complexity isnt
necessary. Due to the nature of the sequential comparator output states (each comparator saturating
high in sequence from lowest to highest), the same highest-order-input selection effect may
be realized through a set of Exclusive-OR gates, allowing the use of a simpler, non-priority
encoder:
212
Figure 12.13: 8X3 Encoder
Notes
And, of course, the encoder circuit itself can be made from a matrix of diodes, demonstrating just
how simply this converter design may be constructed:
Figure 12.14: ADC flash Converter
213
Notes
Not only is the flash converter the simplest in terms of operational theory, but it is the most
efficient of the ADC technologies in terms of speed, being limited only in comparator and gate
propagation delays. Unfortunately, it is the most component-intensive for any given number of
output bits. This three-bit flash ADC requires seven comparators. A four-bit version would
require 15 comparators. With each additional output bit, the number of required comparators
doubles. Considering that eight bits is generally considered the minimum necessary for any
practical ADC (255 comparators needed!), the flash methodology quickly shows its weakness.
An additional advantage of the flash converter, often overlooked, is the ability for it to produce
a non-linear output. With equal-value resistors in the reference voltage divider network, each
successive binary count represents the same amount of analog signal increase, providing a
proportional response. For special applications, however, the resistor values in the divider
network may be made non-equal. This gives the ADC a custom, nonlinear response to the
analog input signal. No other ADC design is able to grant this signal-conditioning behavior
with just a few component value changes.
Self Assessment
9.
With each additional output bit, the number of required comparators doubles in a flash
ADC converter.
10.
An advantage of the flash converter is the ability for it to produce a linear output.
12.6 A/D Converter-Counter Method

A Counter type ADC comprises of input voltage comparator a clock generator, a gate and n-bit
counter. To begin with, the counter is reset to all 0s. Then a converted signal appears on the
start-lie, the input gate is ENABLED and the clock pulses are allowed to the counters clock input.
The counter advances through its normal binary count sequence, the staircase waveform is
generated at the output of the binary ladder constituting a DAC. This staircase waveform forms
one of the inputs of the comparator whose other input is the analog input signal. Whenever the
binary ladder output exceeds the analog input voltage, the comparator changes state, the gate is
DISABLED and the counter stops. The counter output is then the required digital output
corresponding to analog input signal.
Figure 12.15: Counter type ADC
Source: http://www.daenotes.com/electronics/digital-electronics/analog-to-digital-converters
214
The counter type ADC provides a very good method for digitizing to a high resolution. This
method is much simpler than the simultaneous method for high resolution, but the conversion
time required is longer. Since the counter always begins at zero and counts through its normal
binary sequence, it may require as many as 2n counts before conversion is complete. The average
conversion time is 2n/2 or 2n-1 counts, where n is the number of bits of the counter.
Notes
Example: Calculate the maximum conversion time of (a) a 8-bit staircase ramp ADC and
(b) a successive approximation ADC, if the clock rate is 2MHz.
(a)
For a 8-bit staircase ramp ADC, the maximum number of count is nc = 28 = 256
Therefore, the maximum conversion time is Tc =
(b)
nc
256
=
= 128 10 6 s = 128 s
f 2 10 6
For a 8-bit successive approximation ADC, the conversion time is constant and equal to
Tc =
n
8
=
= 4 10 6 s = 4 s
f 2 10 6
Note The conversion speed of successive approximation ADC is much faster than the
staircase ramp type.
Self Assessment
Fill in the blanks:
11.
A Counter type ADC comprises of input voltage comparator, a clock generator, a gate and
........................ counter.
12.
The average conversion time is ........................ counts in Counter type ADC.
12.7 Continuous A/D Conversion

Speeding up the conversion of the signal is to eliminate the need for resetting the counter each
time a conversion is made. If this were continuous type done, the counter would not begin at
zero each time, but instead would begin at the value A/D converter of the last converted point.
We must decide whether to count up or down by examining the output of the comparator. This
method is known as continuous conversion, and thus the converter is called a continuous type
A/D converter.
With the increasing number of services and wireless standards in the last decade, the next
generation of communication solutions must support fully-integrated systems on a chip (SoC)
in order to advance towards the design of multi-standard CMOS devices. Following this trend,
the emphasis of the new transceivers is to perform the broadband signal processing to
accommodate higher data throughput. A major building block in multi-standard high speed
transceivers is the ADC. For RF and high-IF solutions, Continuous-Time Bandpass RD Modulators
(CT-BP) are frequently used because at high intermediate frequencies the flicker noise is small
compared to that of the quantization noise . A major issue found in continuous-time networks is
the lack of accuracy due to process voltage temperature tolerances that may lead to over
25% variations on the time constants . To alleviate this problem, the master-slave tuning
techniques have been successfully used in continuous-time filters; this approach, however, has
215
Notes
been accompanied by additional calibration schemes since tuning the loop filter is not enough
to guarantee the best operation of the entire ADC loop .The optimally tuned ADC requires
correcting for filters center frequency deviations, excess loop delays and variations of DAC
coefficients. These issues are partially alleviated by optimizing the architecture using double
delay resonators and feed forward techniques. Another approach measures in the digital domain
the notch performance of ADC. This approach is however affected by the power of the incoming
out-of band information in online calibration schemes but it is an interesting approach for
offline calibration. Optimization of individual building blocks and use of programmable delay
lines for the optimization of the loop delay and reconfigurable filter-oscillator system fornotch
tuning were also reported. This approach tunes the ADC parameters at the powering up. The offline software based loop calibration technique introduced in this letter is intended for the
optimization of the noise transfer function in bandpass sigma-delta modulators, and can be used
during the system calibration times. The proposed approach measures the noise transfer function
in digital domain using an auxiliary and non-critical test tone; based on the response of the loop
to the strategically applied tone, the loop parameters are sequentially adjusted until the noise
transfer function presents its best possible performance.
Figure 12.16: Continuous-Time Bandpass RD Modulators
Source: http://amesp02.tamu.edu/~jsilva/Projects%20Going-on/NSF/Digital%20Calibration.pdf
12.8 A/D Techniques

The reason for checking other methods of conversion is to determine ways to reduce the
conversion time. We now discuss some of them in detail.
12.8.1 Successive Approximation

One method of addressing the digital ramp ADCs shortcomings is the so-called successiveapproximation ADC. The only change in this design is a very special counter circuit known as a
successive-approximation register. Instead of counting up in binary sequence, this register counts
by trying all values of bits starting with the most-significant bit and finishing at the leastsignificant bit. Throughout the count process, the register monitors the comparators output to
see if the binary count is less than or greater than the analog signal input, adjusting the bit values
accordingly. The way the register counts is identical to the trial-and-fit method of decimal-tobinary conversion, whereby different values of bits are tried from MSB to LSB to get a binary
number that equals the original decimal number. The advantage to this counting strategy is
much faster results: the DAC output converges on the analog signal input in much larger steps
than with the 0-to-full count sequence of a regular counter.
Without showing the inner workings of the successive-approximation register (SAR), the circuit
looks like this:
216
Figure 12.17: Successive Approximation Register
Notes
It should be noted that the SAR is generally capable of outputting the binary number in serial
(one bit at a time) format, thus eliminating the need for a shift register. Plotted over time, the
operation of a successive-approximation ADC looks like this:
Figure 12.18: Successive-approximation ADC
12.8.2 The ADC0804

The ADC 0804 A/D Converter is an 8bit A/D converter that uses successive approximation to
convert the analog inputs to the digital output. The basic block diagram of the function of the
successive approximation A/D Converter is shown in the figure below. The ADC0804 has four
major sections namely the Comparator, the control logic, the digital counter and a 256R ladder
D/A converter. For any analog input, the control logic will trigger the digital counter to start
incrementing from zero count and these digital values are converted to analog form through a
256R ladder network. This 256R network consists of a number of resistors of fixed incremental
resistance that produce a representative staircase type waveform based on the output of the
digital counter. The output of the ladder network then enters the comparator which has the role
of comparing the input analog to the analog output of the D/A Converter. When the staircase
wave form exceeds the input voltage, the comparator sends a signal to the control logic to stop
counting. The value of the digital counter at the time when the comparator sends the stop count
signal is the digital representation of the input voltage.
217
Notes
Figure 12.19: ADC block diagram
Source: http://openbookproject.net/electricCircuits/Digital/DIGI_13.html
12.8.3 Section Counters

To lessen the total conversion time of a simple counter converter, we divide the counter into
sections. This is the concept of a section counter. It is quite often used for digital voltmeters,
since it is very convenient to divide the counters by counts of 10. Each counter is then used to
represent one of the digits of the decimal number appearing at the output of the voltmeter.
Self Assessment
13.
SAR is generally capable of outputting the binary number in parallel format.
14.
The ADC 0804 A/D Converter is an 16 bit A/D converter.
12.9 Dual-Slope A/D Conversion

The dual-slope converter, an integrator circuit is driven positive and negative in alternating
cycles to ramp down and then up, rather than being reset to 0 volts at the end of every cycle. In
one direction of ramping, the integrator is driven by the positive analog input signal (producing
a negative, variable rate of output voltage change, or output slope) for a fixed amount of time,
as measured by a counter with a precision frequency clock. Then, in the other direction, with a
fixed reference voltage (producing a fixed rate of output voltage change) with time measured by
the same counter. The counter stops counting when the integrators output reaches the same
voltage as it was when it started the fixed-time portion of the cycle. The amount of time it takes
for the integrators capacitor to discharge back to its original output voltage, as measured by the
magnitude accrued by the counter, becomes the digital output of the ADC circuit. The dual-slope
method can be thought of analogously in terms of a rotary spring such as that used in a mechanical
clock mechanism. Imagine we were building a mechanism to measure the rotary speed of a
shaft. Thus, shaft speed is our input signal to be measured by this device. The measurement
cycle begins with the spring in a relaxed state. The spring is then turned, or wound up, by the
rotating shaft (input signal) for a fixed amount of time. This places the spring in a certain amount
of tension proportional to the shaft speed: a greater shaft speed corresponds to a faster rate of
winding and a greater amount of spring tension accumulated over that period of time. After
that, the spring is uncoupled from the shaft and allowed to unwind at a fixed rate, the time for it
to unwind back to a relaxed state measured by a timer device. The amount of time it takes for the
spring to unwind at that fixed rate will be directly proportional to the speed at which it was
wound (input signal magnitude) during the fixed-time portion of the cycle. This technique of
218
analog-to-digital conversion escapes the calibration drift problem of the single-slope ADC
because both the integrators integration coefficient (or gain) and the counters rate of speed
are in effect during the entire winding and unwinding cycle portions. If the counters clock
speed were to suddenly increase, this would shorten the fixed time period where the integrator
winds up (resulting in a lesser voltage accumulated by the integrator), but it would also mean
that it would count faster during the period of time when the integrator was allowed to unwind
at a fixed rate. The proportion that the counter is counting faster will be the same proportion as
the integrators accumulated voltage is diminished from before the clock speed change. Thus,
the clock speed error would cancel itself out and the digital output would be exactly what it
should be. Another important advantage of this method is that the input signal becomes averaged
as it drives the integrator during the fixed-time portion of the cycle. Any changes in the analog
signal during that period of time have a cumulative effect on the digital output at the end of that
cycle. Other ADC strategies merely capture the analog signal level at a single point in time
every cycle. If the analog signal is noisy (contains significant levels of spurious voltage
spikes/dips), one of the other ADC converter technologies may occasionally convert a spike or
dip because it captures the signal repeatedly at a single point in time. A dual-slope ADC, on the
other hand, averages together all the spikes and dips within the integration period, thus providing
an output with greater noise immunity. Dual-slope ADCs are used in applications demanding
high accuracy.
Notes
12.9.1 Single-Ramp A/D Converter

The single ramp architecture appears to be the easier to design and the most adapted to multichannel circuits. It has been widely used in front-end ASIC [1, 2, 3] for two decades. Several
implementations of this architecture are possible. In the most efficient one, the voltage-todigital conversion is performed by measuring the time between the start of a voltage ramp and
its crossing, detected by a comparator, of the voltage to be converted.
Figure 12.20: Single Ramp ADC
Source: http://matacq.free.fr/Publis/WILKY_tns.pdf
The time measurement is achieved by a counter started synchronously with the ramp. To avoid
metastability effects, a resynchronization of the comparator output by the clock of the counter is
219
Notes
required to stop or memorize the counter state. The main advantage of this particular
implementation is that, the counter and the ramp generator can be shared between the channels
so that the ADC part replicated in each channel can be reduced to a comparator and a memory
used to copy and memorize the counter state when the discriminator triggers. Therefore, the
power consumption and the area used can be very small even for high dynamic range, and the
linearity, mainly dominated by that of the ramp generator, can easily be very good. But,
unfortunately, the use of this kind of ADC is limited by its long conversion time. Actually, for
an N bit conversion, it requires 2N/Fck, where Fck is the clock frequency of the counter. So for a
12-bit conversion, making use of a 100 MHz clock, which appears to be a maximum for reasonable
power consumption, 40 s are required. This time is prohibitive for a lot of applications.
12.10 Single-Slope A/D Converter

It is possible to avoid using a DAC if we substitute an analog ramping circuit and a digital
counter with precise timing. The is the basic idea behind the so-called single-slope, or integrating
ADC. Instead of using a DAC with a ramped output, we use an op-amp circuit called an integrator
to generate a sawtooth waveform which is then compared against the analog input by a
comparator. The time it takes for the sawtooth waveform to exceed the input signal voltage
level is measured by means of a digital counter clocked with a precise-frequency square wave
(usually from a crystal oscillator). The basic schematic diagram is shown here:
Figure 12.21: Single Slope ADC
The IGFET capacitor-discharging transistor scheme shown here is a bit oversimplified. In reality,
a latching circuit timed with the clock signal would most likely have to be connected to the
IGFET gate to ensure full discharge of the capacitor when the comparators output goes high.
The basic idea, however, is evident in this diagram. When the comparator output is low (input
voltage greater than integrator output), the integrator is allowed to charge the capacitor in a
linear fashion. Meanwhile, the counter is counting up at a rate fixed by the precision clock
frequency. The time it takes for the capacitor to charge up to the same voltage level as the input
depends on the input signal level and the combination of -Vref, R, and C. When the capacitor
reaches that voltage level, the comparator output goes high, loading the counters output into
the shift register for a final output. The IGFET is triggered on by the comparators high output,
discharging the capacitor back to zero volts. When the integrator output voltage falls to zero,
the comparator output switches back to a low state, clearing the counter and enabling the
integrator to ramp up voltage again. This ADC circuit behaves very much like the digital ramp
ADC, except that the comparator reference voltage is a smooth sawtooth waveform rather than
a stairstep.
220
Figure 12.22: Time Diagram of Single Step ADC
Notes
The single-slope ADC suffers all the disadvantages of the digital ramp ADC, with the added
drawback of calibration drift. The accurate correspondence of this ADCs output with its input is
dependent on the voltage slope of the integrator being matched to the counting rate of the
counter (the clock frequency). With the digital ramp ADC, the clock frequency had no effect on
conversion accuracy, only on update time. In this circuit, since the rate of integration and the rate
of count are independent of each other, variation between the two is inevitable as it ages, and
will result in a loss of accuracy. The only good thing to say about this circuit is that it avoids the
use of a DAC, which reduces circuit complexity.
12.11 Dual-slope A/D Converter

Figure 12.23: Dual Slope Converter
Source: http://www.upscale.utoronto.ca/GeneralInterest/Drummond/Micro/ln_a_d.pdf
In operation the integrator is first zeroed (close SW2), then attached to the input (SW1 up) for a
fixed time M counts of the clock (frequency 1/t). At the end of that time it is attached to the
reference voltage (SW1 down) and the number of counts N which accumulate before the integrator
reaches zero volts output and the comparator output changes are determined.
The equations of operation are therefore:
Vx =
Vin ( Mt ) Vref ( Nt )
=
RC
RC
Vin = Vref
N
M
The unknown voltage is then just Vref*N/M and is reasonably independent of everything else.
The main problem with a simple dual slope ADC is in returning the converter to an exact zero
before the start of each conversion as interpreted by an imperfect comparator. This may be
221
Notes
circumvented by changing the comparison level from zero volts to a small, stable, but not
necessarily known, voltage (V), which in our example must be more positive than any
combination of imperfections in the comparison. The first timing interval then starts when the
voltage crosses the level and the second interval finishes when the level is re-crossed at the end.
Figure 12.24: Full Circuit of Dual Slope
In order to circumvent that a small bias current is added to the integrator (using -Vref and RN) to
force the output to go positive even with an input of zero. Of course this means that zero volts
is not zero output counts anymore and a calibration step is required where a zero is established.
Notice however that despite the increase in complexity, all that is required out of all components
except the reference voltage is stability over one measurement sequence, not accuracy.
Task Find out about the problems of polarity of input.
12.12 Successive Approximation A/D Converter

A successive approximation A/D converter consists of a comparator, a successive approximation
register (SAR), output latches, and a D/A converter. The circuit diagram is shown below:
Figure 12.25: Successive Approx. ADC
Source: http://www.circuitstoday.com/analog-to-digital-converters-ad
222
This type of converter is used to convert analog voltage to its corresponding digital output. The
function of the analog to digital converter is exactly opposite to that of a DAC. Like a D/A
converter, an A/D converter is also specified as 8, 10, 12 or 16 bit. A successive approximation
A/D converter consists of a comparator, a successive approximation register (SAR), output
latches, and a D/A converter. The main part of the circuit is the 8-bit SAR, whose output is given
to an 8-bit D/A converter. The analog output Va of the D/A converter is then compared to an
analog signal Vin by the comparator. The output of the comparator is a serial data input to the
SAR. Till the digital output (8 bits) of the SAR is equivalent to the analog input Vin, the SAR
adjusts itself. The 8-bit latch at the end of conversation holds onto the resultant digital data
output.
Notes
At the start of a conversion cycle, the SAR is reset by making the start signal (S) high. The MSB
of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is introduced. The output
is given to the D/A converter which produces an analog equivalent of the MSB and is compared
with the analog input Vin. If comparator output is LOW, D/A output will be greater than Vin
and the MSB will be cleared by the SAR.
If comparator output is HIGH, D/A output will be less than Vin and the MSB will be set to the
next position (Q7 to Q6) by the SAR. According to the comparator output, the SAR will either
keep or reset the Q6 bit. This process goes on until all the bits are tried. After Q0 is tried, the SAR
makes the conversion complete (CC) signal HIGH to show that the parallel output lines contain
valid data. The CC signal in turn enables the latch, and digital data appear at the output of the
latch. As the SAR determines each bit, digital data is also available serially. As shown in the
figure above, the CC signal is connected to the start conversion input in order to convert the
cycle continuously. The biggest advantage of such a circuit is its high speed. It may be more
complex than an A/D converter, but it offers better resolution.
12.13 Flash Converters

Every converter has its advantages and the flash converter, converts in a flash, i.e. very fast.
It is a brother to the successive approximation converter but whereas the successive approximation
converter compares to a guess each time, the flash converter compares to all guesses
simultaneously and then decides the best value from the results.
Note A flash converter is very extravagant in hardware but if you have to convert at
10Msamples/Sec you have to give up something!
A Flash ADC (also known as a Direct conversion ADC) is a type of analog-to-digital converter
that uses a linear voltage ladder with a comparator at each rung of the ladder to compare the
input voltage to successive reference voltages. Often these reference ladders are constructed of
many resistors; however modern implementations show that capacitive voltage division is also
possible. The output of these comparators is generally fed into a digital encoder which converts
the inputs into a binary value (the collected outputs from the comparators can be thought of as
a unary value). Flash ADCs have been implemented in many technologies, varying from silicon
based bipolar (BJT) and complementary metal oxide FETs (CMOS) technologies to rarely used
III-V technologies. Often this type of ADC is used as a first medium sized analog circuit
verification. The earliest implementations consisted of a reference ladder of well matched resistors
connected to a reference voltage. Each tap at the resistor ladder is used for one comparator,
possibly preceded by an amplification stage, and thus generates a logical 0 or 1 depending if
the measured voltage is above or below the reference voltage of the resistor tap. The reason to
223
Notes
add an amplifier is twofold: it amplifies the voltage difference and therefore suppresses the
comparator offset, and the kick-back noise of the comparator towards the reference ladder is
also strongly suppressed. Typically designs from 4-bit up to 6-bit, and sometimes 7-bit are
produced. Designs with power-saving capacitive reference ladders have been demonstrated. In
addition to clocking the comparator(s), these systems also sample the reference value on the
input stage. As the sampling is done at a very high rate, the leakage of the capacitors is negligible.
Recently, offset calibration has been introduced into flash ADC designs. Instead of high precision
analog circuits (which increase component size to suppress variation) comparators with relatively
large offset errors are measured and adjusted. A test signal is applied and the offset of each
comparator is calibrated to below the LSB size of the ADC. Another improvement to many flash
ADCs is the inclusion of digital error correction. When the ADC is used in harsh environments
or constructed from very small integrated circuit processes, there is a heightened risk a single
comparator will randomly change state resulting in a wrong code. Bubble error correction is a
digital correction mechanism that will prevent a comparator that has, for example, tripped high
from reporting logic high if it is surrounded by comparators that are reporting logic low.
Figure 12.26: Flash Converter
224
Case Study
Notes
TRX Systems
lobal Positioning System (GPS) technology has had a transformative impact on

our navigation and tracking capabilities, but there are many environments
indoors, underground, urban centers where GPS is unavailable or degraded. In
these environments, teams responding to emergency situations cannot rely on GPS location
and status monitoring to help ensure the safety and security of first responders.
TRX Systems Sentrix Tracking System overcomes this challenge, enabling 3D
infrastructure-free personnel tracking in office buildings, warehouses, caves, mines, urban
canyons and other GPS-denied environments. Utilizing advanced sensor and map fusion
technology, motion classification algorithms, and data analysis engines, the Sentrix
Tracking System affords first responders the ability to navigate unfamiliar terrain and
track personnel with motion-capture precision in even the harshest conditions.
Within each body-mounted Sentrix tracking unit, an ADI iSensor ADIS16365 inertial
sensor provides the high-performance gyroscope and accelerometer sensing functionality
required to compute user motion and orientation in real-time. ADIS16365 inertial sensors
utilize ADIs advanced iMEMS technology to enable dynamic, multiaxis sensing precision
in conjunction with TRXs proprietary Inertial Engine algorithms, providing the ability to
track a users movement and posture, and classify user motions such as walking, running,
side stepping and crawling.
Contd...
225
Notes
Sentrix tracking units are typically worn under users uniforms, and are ruggedized to
withstand high body heat and environmental temperature. Where the performance of
competing sensors is compromised under these conditions, ADIs ADIS16365 inertial
sensors are designed to sustain consistent operation in temperatures up to 105 degrees.
ADIs integration of multiple axis of accelerometer and gyroscope in a single package
enabled TRXs design team to conserve valuable board space and achieve a highly compact
form factor so as not to impede users agility in the field. ADIS16365 inertial sensors also
help to minimize power consumption, ensuring that users can work a full 8+ hour shift
between system re-charges.
Questions:
1.
Discuss the advantages of TRX systems.
2.
What are sentrix tracking units.
Source: http://www.analog.com/en/content/trx_case_study/fca.html
Self Assessment
Fill in the blanks:
15.
........................ error correction is a digital correction mechanism that will prevent a

comparator that has tripped high from reporting logic high if it is surrounded by
comparators that are reporting logic low.
16.
A Flash ADC uses a ........................ voltage ladder.
12.14 Summary
226
To take advantage of the great capabilities available for digital data storage, processing,
and computation, on the other hand, requires the conversion of analog to digital.
Conversion from analog to digital form inherently involves comparator action where the
value of the analog voltage at some point in time is compared with some standard.
By designing a resistive network, we can convert each digital level into an equivalent
binary weighted voltage.
A D/A Converter is used when the binary output from a digital system is to be converted
into its equivalent analog voltage or current.
Resistive voltage divider (also known as a potential divider) is a linear circuit that produces
an output voltage (Vout) that is a fraction of its input voltage (Vin).
A ladder is an electrical circuit made of repeating units of resistors.
An R-2R Ladder is a simple and inexpensive way to perform digital-to-analog conversion
Majorly two types of DAC are used: Binary Weighted Resistor and R-2R Ladder.
Sample and hold circuit is an analog device that samples the voltage of a continuously
varying analog signal and holds its value at a constant level for a specified minimal
period of time.
In a Steady-state Sample-and-hold amplifier, when the switch is closed, the capacitor

charges to the D/A.
Accuracy test: Converter output voltage. When the switch is opened, the capacitor holds
the voltage level until the next sampling time. The operational amplifier provides large
input impedance.
Monotonicity test: So as not to discharge the capacitor appreciably and at the same time
offers gain to drive external circuits.
The accuracy is usually expressed by the error in output voltage compared with the expected
output voltage.
Resolution is the amount of variance in output voltage for every change of the LSB in the
digital input.
Parallel A/D converter is formed of a series of comparators, each one comparing the input
signal to a unique reference voltage.
A Counter type ADC comprises of input voltage comparator a clock generator, a gate and
n-bit counter.
A successive-approximation register. Instead of counting up in binary sequence, this register

counts by trying all values of bits starting with the most-significant bit and finishing at
the least-significant bit.
The dual-slope converter, an integrator circuit is driven positive and negative in alternating
cycles to ramp down and then up, rather than being reset to 0 volts at the end of every
cycle.
A successive approximation A/D converter consists of a comparator, a successive

approximation register (SAR), output latches, and a D/A converter.
A Flash ADC (also known as a Direct conversion ADC) is a type of analog-to-digital

converter that uses a linear voltage ladder with a comparator at each rung of the ladder
to compare the input voltage to successive reference voltages.
Notes
12.15 Keywords
Accuracy: It is usually expressed by the error in output voltage compared with the expected
output voltage.
Accuracy Test: Converter output voltage. When the switch is opened, the capacitor holds the
voltage level until the next sampling time. The operational amplifier provides large input
impedance.
Counter Type ADC: It comprises of input voltage comparator a clock generator, a gate and n-bit
counter.
DAC: It is used when the binary output from a digital system is to be converted into its
equivalent analog voltage or current.
Ladder: It is an electrical circuit made of repeating units of resistors.
Monotonicity Test: So as not to discharge the capacitor appreciably and at the same time offers
gain to drive external circuits.
Parallel A/D Converter: It is formed of a series of comparators, each one comparing the input
signal to a unique reference voltage.
R-2R Ladder: It is a simple and inexpensive way to perform digital-to-analog conversion.
227
Notes
Resistive Voltage Divider: It is a linear circuit that produces an output voltage (Vout) that is a
fraction of its input voltage (Vin).
Resolution: It is the amount of variance in output voltage for every change of the LSB in the
digital input.

1.
What is the use of variable resistor network?
2.
What is a binary ladder?
3.
Explain the concept of resistor divider.
4.
Explain binary weighted register with example.
5.
What is a R-2R ladder?
6.
Explain the use of sample and hold circuit.
7.
Explain the working of DAC0808.
8.
Calculate the resolution of a 16 bit ADC.
9.
What is ADC flash converter?
10.
Differentiate between single slope ADC and digital ramp ADC.

1.
True
2.
True
3.
Resistors
4.
Digital, Analog
5.
True
6.
False
7.
Higher, Lower
8.
+- , +1/2
9.
True
10.
False
11.
n bit
12.
2n-1 or 2n/2
13.
False
14.
False
15.
Bubble
16.
Linear
Books
Banerjee Gopal Krishna, Electrical and Electronic Measurements

David and Ken Martin, Data Converter Fundamentals, Johns
Friedel Gerfers and Maurits Ortmanns, Continuous-Time Sigma-Delta A/D Conversion:
Fundamentals, Performance Limits and Robust Implementations
Goericke, Fabian, Keunhan Park and Geoffrey Williams, Digital to Analog Converter
228
Notes
Online links
http://en.wikipedia.org/wiki/Digital-to-analog_converter#DAC_types
http://www.circuitstoday.com/digital-to-analog-converters-da
http://www.daenotes.com/electronics/digital-electronics/analog-to-digitalconverters
http://www.me.gatech.edu/mechatronics_course/DAC_F05.ppt
229

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Digital Circuits and Logic Designs - Shrivastava - Ibrg

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DIGITAL CIRCUITS AND

Copyright 2013, Dr Krishna Raj

Directorate of Distance Education

in terms of no. of students in a single campus

Boolean Algebra: Complement arithmetic, Boolean theorems of Boolean algebra.

Minimization of Boolean Algebra

Implementation of Combinational Logic Circuit

Standard Integrated Circuits (ICs)

Clocked Sequential Circuits

Registers and Counters

A/D and D/A Converters

Unit 1: Number Systems

Unit 1: Number Systems

Decimal Number System

Binary Number System

Hexadecimal Number System

Octal Number System

Conversion from One Number System to Another

Converting from Another Base to Decimal

Converting from Decimal to Another Base (Division-remainder Technique)

Converting from a Base Other Than 10 to Another Base Other Than 10

Short-cut Method for Binary to Octal Conversion

Short-cut Method for Octal to Binary Conversion

Short-cut Method for Binary to Hexadecimal Conversion

Short-cut Method for Hexadecimal to Binary Conversion

Discuss the decimal number system

Explain about binary number system

Discuss the hexadecimal number system concept

Discuss the octal number system

Elaborate upon the conversions between number system concept

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We will now discuss two kinds of number systems:

Non-positional number systems

Positional number systems

(sk 1 ...s1s0 .s1s2 ...s l )b

1.1 Decimal Number System

Note n0 = 1, or any number raised to the zero power is equal to 1.

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Unit 1: Number Systems

The decimal number system is a positional number system.

1.2 Binary Number System

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Digital Circuits and Logic Designs

Task Convert (1100110)2 to decimal number.

Radix of the Binary Number System is 10.

The decimal equivalent of (1101010) 2 is (106)10

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Unit 1: Number Systems

1.3 Hexadecimal Number System

The hexadecimal number system is a ........................ number system.

The radix value of hexadecimal number system is ........................ .

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Digital Circuits and Logic Designs

From ........................ to ........................, the successive positions of the hexadecimal number

1.4 Octal Number System

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Unit 1: Number Systems

Therefore, 10101111002 = 12748.