KSZ8041NL: General Description

KSZ8041NL
10Base-T/100Base-TX
Physical Layer Transceiver
Data Sheet Rev. 1.2
General Description
The KSZ8041NL is a single supply 10Base-T/100Base-TX
Physical Layer Transceiver, which provides MII/RMII
interfaces to transmit and receive data. An unique mixed
signal design extends signaling distance while reducing
power consumption.
HP Auto MDI/MDI-X provides the most robust solution for
eliminating the need to differentiate between crossover
and straight-through cables.
The KSZ8041NL represents a new level of features and

performance and is an ideal choice of physical layer
transceiver for 10Base-T/100Base-TX applications.
The KSZ8041NL comes in a 32-pin, lead-free MLF (QFN

per JDEC) package (See Ordering Information).
Data sheets and support documentation can be found on
Micrels web site at: www.micrel.com.
Functional Diagram
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
July 2008
M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Features
Applications
Single-chip 10Base-T/100Base-TX physical layer

solution
Fully compliant to IEEE 802.3u Standard
Low power CMOS design, power consumption of
<180mW
HP auto MDI/MDI-X for reliable detection and
correction for straight-through and crossover cables
with disable and enable option
Robust operation over standard cables
Power down and power saving modes
MII interface support
RMII interface support with external 50MHz system
clock
MIIM (MDC/MDIO) management bus to 6.25MHz for
rapid PHY register configuration
Interrupt pin option
Programmable LED outputs for link, activity and
speed
ESD rating (6kV)
Single power supply (3.3V)
Built-in 1.8V regulator for core
Available in 32-pin (5mm x 5mm) MLF package
Printer
LOM
Game Console
IPTV
IP Phone
IP Set-top Box
Ordering Information
Part Number
KSZ8041NL
KSZ8041NLI
Temp. Range
0C to 70C
(1)
-40C to 85C
(1)
KSZ8041NL AM
-40C to 85C
Package
Lead Finish
Description
32-Pin MLF
Pb-Free
Commercial Temperature Device
32-Pin MLF
Pb-Free
Industrial Temperature Device
32-Pin MLF
Pb-Free
Automotive Qualified Device
Note:
1.
Contact factory for lead time.
July 2008
M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Revision History
Revision
Date
Summary of Changes
1.0
10/13/06
Data sheet created.
1.1
4/27/07
Added maximum MDC clock speed.

Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pulldowns.
Changed Model Number in Register 3h PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h Auto-Negotiation Advertisement bits [8, 6].
Set Disable power saving as the default for Register 1Fh bit [10].
Corrected LED1 (pin 31) definition for Activity in LED mode 01.
Added Symbol Error to MII/RMII Receive Error description and Register 15h RXER Counter.
Added a 100pF capacitor on REXT (pin 10) in Pin Description table.
1.2
7/18/08
Added Automotive Qualified part number to Ordering Information.

Added maximum case temperature.
Added thermal resistance (JC).
Added chip maximum current consumption.
July 2008
M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Contents
Pin Configuration .................................................................................................................................................................. 8
Pin Description ...................................................................................................................................................................... 9
Strapping Options ............................................................................................................................................................... 12
Functional Description ....................................................................................................................................................... 13
100Base-TX Transmit....................................................................................................................................................... 13
100Base-TX Receive........................................................................................................................................................ 13
PLL Clock Synthesizer...................................................................................................................................................... 13
Scrambler/De-scrambler (100Base-TX only).................................................................................................................... 13
10Base-T Transmit ........................................................................................................................................................... 13
10Base-T Receive ............................................................................................................................................................ 13
SQE and Jabber Function (10Base-T only)...................................................................................................................... 14
Auto-Negotiation ............................................................................................................................................................... 14
MII Management (MIIM) Interface .................................................................................................................................... 16
Interrupt (INTRP) .............................................................................................................................................................. 16
MII Data Interface ............................................................................................................................................................. 16
MII Signal Definition.......................................................................................................................................................... 17
Transmit Clock (TXC) ................................................................................................................................................... 17
Transmit Enable (TXEN) .............................................................................................................................................. 17
Transmit Data [3:0] (TXD[3:0]) ..................................................................................................................................... 17
Receive Clock (RXC).................................................................................................................................................... 17
Receive Data Valid (RXDV).......................................................................................................................................... 18
Receive Data [3:0] (RXD[3:0]) ...................................................................................................................................... 18
Receive Error (RXER) .................................................................................................................................................. 18
Carrier Sense (CRS) .................................................................................................................................................... 18
Collision (COL) ............................................................................................................................................................. 18
Reduced MII (RMII) Data Interface................................................................................................................................... 18
RMII Signal Definition ....................................................................................................................................................... 19
Reference Clock (REF_CLK) ....................................................................................................................................... 19
Transmit Enable (TX_EN) ............................................................................................................................................ 19
Transmit Data [1:0] (TXD[1:0]) ..................................................................................................................................... 19
Carrier Sense/Receive Data Valid (CRS_DV).............................................................................................................. 19
Receive Data [1:0] (RXD[1:0]) ...................................................................................................................................... 19
Receive Error (RX_ER) ................................................................................................................................................ 19
Collision Detection ........................................................................................................................................................ 20
HP Auto MDI/MDI-X.......................................................................................................................................................... 20
Straight Cable ............................................................................................................................................................... 20
Crossover Cable ........................................................................................................................................................... 21
Power Management.......................................................................................................................................................... 22
Power Saving Mode ..................................................................................................................................................... 22
Power Down Mode ....................................................................................................................................................... 22
Reference Clock Connection Options .............................................................................................................................. 22
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KSZ8041NL
Reference Circuit for Power and Ground Connections .................................................................................................... 23

Register Map........................................................................................................................................................................ 24
Register Description ........................................................................................................................................................... 24
(1)
Absolute Maximum Ratings ............................................................................................................................................ 31

(2)
Operating Ratings ............................................................................................................................................................ 31

(4)
................................................................................................................................................ 31
(6)
................................................................................................................................................ 32
Electrical Characteristics
Electrical Characteristics
Timing Diagrams ................................................................................................................................................................. 33

MII SQE Timing (10Base-T) ............................................................................................................................................. 33
MII Transmit Timing (10Base-T) ....................................................................................................................................... 34
MII Receive Timing (10Base-T) ........................................................................................................................................ 35
MII Transmit Timing (100Base-TX) .................................................................................................................................. 36
MII Receive Timing (100Base-TX) ................................................................................................................................... 37
RMII Timing....................................................................................................................................................................... 38
Auto-Negotiation Timing ................................................................................................................................................... 39
MDC/MDIO Timing ........................................................................................................................................................... 40
Reset Timing..................................................................................................................................................................... 41
Reset Circuit ........................................................................................................................................................................ 42
Reference Circuits for LED Strapping Pins...................................................................................................................... 43
Selection of Isolation Transformer.................................................................................................................................... 44
Selection of Reference Crystal .......................................................................................................................................... 44
Package Information ........................................................................................................................................................... 45
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KSZ8041NL
List of Figures
Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 15
Figure 2. Typical Straight Cable Connection ....................................................................................................................... 20
Figure 3. Typical Crossover Cable Connection ................................................................................................................... 21
Figure 4. 25MHz Crystal / Oscillator Reference Clock for MII Mode ................................................................................... 22
Figure 5. 50MHz Oscillator Reference Clock for RMII Mode............................................................................................... 22
Figure 6. KSZ8041NL Power and Ground Connections ...................................................................................................... 23
Figure 7. MII SQE Timing (10Base-T) ................................................................................................................................. 33
Figure 8. MII Transmit Timing (10Base-T) ........................................................................................................................... 34
Figure 9. MII Receive Timing (10Base-T) ............................................................................................................................ 35
Figure 10. MII Transmit Timing (100Base-TX)..................................................................................................................... 36
Figure 11. MII Receive Timing (100Base-TX)...................................................................................................................... 37
Figure 12. RMII Timing Data Received from RMII ............................................................................................................ 38
Figure 13. RMII Timing Data Input to RMII ....................................................................................................................... 38
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 39
Figure 15. MDC/MDIO Timing.............................................................................................................................................. 40
Figure 16. Reset Timing....................................................................................................................................................... 41
Figure 17. Recommended Reset Circuit.............................................................................................................................. 42
Figure 18. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 42
Figure 19. Reference Circuits for LED Strapping Pins......................................................................................................... 43
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KSZ8041NL
List of Tables
Table 1. MII Management Frame Format ............................................................................................................................ 16
Table 2. MII Signal Definition ............................................................................................................................................... 17
Table 3. RMII Signal Description.......................................................................................................................................... 19
Table 4. MDI/MDI-X Pin Definition ....................................................................................................................................... 20
Table 5. KSZ8041NL Power Pin Description ....................................................................................................................... 23
Table 6. MII SQE Timing (10Base-T) Parameters ............................................................................................................... 33
Table 7. MII Transmit Timing (10Base-T) Parameters......................................................................................................... 34
Table 8. MII Receive Timing (10Base-T) Parameters.......................................................................................................... 35
Table 9. MII Transmit Timing (100Base-TX) Parameters .................................................................................................... 36
Table 10. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 37
Table 11. RMII Timing Parameters ...................................................................................................................................... 38
Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 39
Table 13. MDC/MDIO Timing Parameters ........................................................................................................................... 40
Table 14. Reset Timing Parameters .................................................................................................................................... 41
Table 15. Transformer Selection Criteria ............................................................................................................................. 44
Table 16. Qualified Single Port Magnetics........................................................................................................................... 44
Table 17. Typical Reference Crystal Characteristics ........................................................................................................... 44
July 2008
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Micrel, Inc.
KSZ8041NL
Pin Configuration
32-Pin (5mm x 5mm) MLF
July 2008
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Micrel, Inc.
KSZ8041NL
Pin Description
Pin Number
1
Pin Name
Type
(1)
Pin Function
GND
Gnd
Ground
VDDPLL_1.8
1.8V analog VDD
VDDA_3.3
3.3V analog VDD
RX-
I/O
Physical receive or transmit signal (- differential)
RX+
I/O
Physical receive or transmit signal (+ differential)
TX-
I/O
Physical transmit or receive signal (- differential)
TX+
I/O
Physical transmit or receive signal (+ differential)
XO
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode is selected.
XI /
REFCLK
10
REXT
I/O
Crystal / Oscillator / External Clock Input

MII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
RMII Mode:
50MHz +/-50ppm (oscillator, or external clock only)
Set physical transmit output current

Connect a 6.49K resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041NL reference schematics.
11
MDIO
I/O
Management Interface (MII) Data I/O

This pin requires an external 4.7K pull-up resistor.
12
MDC
Management Interface (MII) Clock Input

This pin is synchronous to the MDIO data interface.
13
RXD3 /
Ipu/O
PHYAD0
14
RXD2 /
Ipd/O
PHYAD1
15
16
RXD1 /
Ipd/O
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[0] during

power-up / reset. See Strapping Options section for details.
MII Mode:
Receive Data Output[2]
Config Mode:

MII Mode:
(2)
(3)
(2)
RXD[1] /
RMII Mode:
PHYAD2
Config Mode:

MII Mode:
(2)
(3)
RXD0 /
Ipu/O
RXD[0] /
RMII Mode:
DUPLEX
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /

reset. See Strapping Options section for details.
VDDIO_3.3
3.3V digital VDD
18
RXDV /
Ipd/O
MII Mode:
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17
19
(2)
MII Mode:
Receive Data Valid Output /
CRSDV /
RMII Mode:
Carrier Sense/Receive Data Valid Output /
CONFIG2
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 during

MII Mode:
Receive Clock Output
RXC
M9999-071808-1.2
Micrel, Inc.
Pin Number
20
21
KSZ8041NL
Pin Name
RXER /
Type
Pin Function
MII Mode:
Receive Error Output /
RX_ER /
RMII Mode:
Receive Error Output /
ISO
Config Mode:
The pull-up/pull-down value is latched as ISOLATE during

INTRP
Ipd/O
(1)
Opu
Interrupt Output: Programmable Interrupt Output

Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt
output to active low (default) or active high.
22
TXC
MII Mode:
Transmit Clock Output
23
TXEN /
MII Mode:
Transmit Enable Input /
RMII Mode:
Transmit Enable Input
MII Mode:
Transmit Data Input[0]
(4)
RMII Mode:
(5)
MII Mode:
(4)
RMII Mode:
(5)
MII Mode:
(4)
(4)
TX_EN
24
TXD0 /
TXD[0]
25
TXD1 /
TXD[1]
26
TXD2
27
TXD3
28
COL /
Ipd/O
CONFIG0
29
CRS /
Ipd/O
CONFIG1
30
LED0 /
NWAYEN
Ipu/O
MII Mode:
MII Mode:
Collision Detect Output /
Config Mode:

MII Mode:
Carrier Sense Output /
Config Mode:

LED Output:
Programmable LED0 Output /
Config Mode:
Latched as Auto-Negotiation Enable (register 0h, bit 12) during

The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Link/Activity
Pin State
LED Definition
No Link
OFF
Link
ON
Activity
Toggle
Blinking
Pin State
LED Definition
LED mode = [01]

Link
No Link
OFF
Link
ON
LED mode = [10]

Reserved
LED mode = [11]
Reserved
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KSZ8041NL
Pin Number
31
Pin Name
LED1 /
Type
(1)
Ipu/O
SPEED
Pin Function
LED Output:
Programmable LED1 Output /
Config Mode:
Latched as SPEED (register 0h, bit 13) during power-up / reset.

See Strapping Options section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Speed
Pin State
LED Definition
10BT
OFF
100BT
ON
LED mode = [01]

Activity
Pin State
LED Definition
No Activity
OFF
Activity
Toggle
Blinking
LED mode = [10]

Reserved
LED mode = [11]
Reserved
32
RST#
Chip Reset (active low)
PADDLE
GND
Gnd
Ground
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII.
RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered
data are sent from the PHY.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
received by the PHY from the MAC.
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KSZ8041NL
Strapping Options
Pin Number
Pin Name
Type
(1)
Pin Function
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
13
PHYAD0
Ipu/O
The default PHY Address is 00001.
18
CONFIG2
Ipd/O
29
CONFIG1
Ipd/O
28
CONFIG0
Ipd/O
PHY Address bits [4:3] are always set to 00.
20
ISO
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0]
Mode
000
MII (default)
001
RMII
010
Reserved not used
011
Reserved not used
100
PCS Loopback
101
Reserved not used
110
Reserved not used
111
Reserved not used
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable

Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
1.
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case,
it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE or
PCS Loopback mode, or is not configured with an incorrect PHY Address.
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KSZ8041NL
Functional Description
The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u Specification.
On the media side, the KSZ8041NL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of
and correction for straight-through and crossover cables.
The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management
bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an
interrupt pin eliminates the need for the processor to poll for PHY status change.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output.
The output current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4
ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The waveshaped 10Base-T output drivers are also incorporated into the 100Base-TX drivers.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8041NL generates 125Mz, 25Mz and 20Mz clocks for system timing. Internal clocks are generated from an
external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50MHz oscillator
or system clock.
Scrambler/De-scrambler (100Base-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude
of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency
when driven by an all-ones Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and
RX- inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming
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KSZ8041NL
signal and the KSZ8041NL decodes a data frame. The receive clock is kept active during idle periods in between data
reception.
SQE and Jabber Function (10Base-T only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required
as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10BaseT transmitter is re-enabled and COL is de-asserted (returns to low).
Auto-Negotiation
The KSZ8041NL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Autonegotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 12).
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link
partners advertise their capabilities to each other, and then compare their own capabilities with those they received from
their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode
of operation.
The following list shows the speed and duplex operation mode from highest to lowest.
Priority 1: 100Base-TX, full-duplex
Priority 2: 100Base-TX, half-duplex
Priority 3: 10Base-T, full-duplex
Priority 4: 10Base-T, half-duplex

If auto-negotiation is not supported or the KSZ8041NL link partner is forced to bypass auto-negotiation, the KSZ8041NL
sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the
KSZ8041NL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement
protocol.
The auto-negotiation link up process is shown in the following flow chart.
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KSZ8041NL
Start Auto Negotiation
Force Link Setting
N
o
Parallel
Operation
Yes
Bypass Auto Negotiation

and Set Link Mode
Attempt Auto
Negotiation
Listen for 100BASE-TX

Idles
Listen for 10BASE-T

Link Pulses
No
Join
Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 1. Auto-Negotiation Flow Chart
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KSZ8041NL
MII Management (MIIM) Interface

The KSZ8041NL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output
(MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8041NL. An
external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Additional details
on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with one or more KSZ8041NL devices. Each KSZ8041NL device is assigned a PHY address
between 1 and 7 by the PHYAD[2:0] strapping pins.
An internal addressable set of thirteen 16-bit MDIO registers. Register [0:6] are required, and their functions are
defined by the IEEE 802.3u Specification. The additional registers are provided for expanded functionality.
The KSZ8041NL supports MIIM in both MII mode and RMII mode.
The following table shows the MII Management frame format for the KSZ8041NL.
Preamble
Start of
Frame
Read/Write
PHY
REG
OP Code
Address
Address
Bits [4:0]
Bits [4:0]
TA
Data
Idle
Bits [15:0]
Read
32 1s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Write
32 1s
01
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Table 1. MII Management Frame Format
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ8041NL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to enable
and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are
used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
By default, the KSZ8041NL is configured in MII mode after it is power-up or reset with the following:
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
CONFIG[2:0] (pins 18, 29, 28) set to 000 (default setting).
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KSZ8041NL
MII Signal Definition

The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information.
MII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
TXC
Output
Input
Description
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data [3:0]
RXC
Output
Input
Receive Clock
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data [3:0]
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXER
Output
Input, or (not required)
Receive Error
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
Table 2. MII Signal Definition
Transmit Clock (TXC)

TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is 00 to indicate idle when TXEN is de-asserted. Values other than 00 on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHYs reference
clock when the line is idle, or link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHYs
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
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Receive Data Valid (RXDV)

RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), 5D, and remains
asserted until the end of the frame.
In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data [3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable
of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame
presently being transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is
used to inform the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
Supports 10Mbps and 100Mbps data rates.
Uses a single 50MHz reference clock provided by the MAC or the system board.
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
The KSZ8041NL is configured in RMII mode after it is power-up or reset with the following:
A 50MHz reference clock connected to REFCLK (pin 9).
CONFIG[2:0] (pins 18, 29, 28) set to 001.
In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground.
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KSZ8041NL
RMII Signal Definition

The following table describes the RMII signals. Refer to RMII Specification for detailed information.
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
REF_CLK
Input
Input, or Output
Synchronous 50 MHz clock reference for

receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Receive Error
Description
Table 3. RMII Signal Description
Reference Clock (REF_CLK)

REF_CLK is sourced by the MAC or system board. It is a continuous 50MHz clock that provides the timing reference for
TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is 00 to indicate idle when TX_EN is de-asserted. Values other than 00 on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the
frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other
than 00 on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
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KSZ8041NL
Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8041NL and its link partner. This feature allows the KSZ8041NL to use either type of cable to connect
with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from
the link partner, and then assigns transmit and receive pairs of the KSZ8041NL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1F bit 13. MDI and MDI-X mode is
selected by register 1F bit 14 if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
The IEEE 802.3u Standard defines MDI and MDI-X as follow:
MDI
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
TD+
RD+
TD-
RD-
RD+
TD+
RD-
TD-
Table 4. MDI/MDI-X Pin Definition
Straight Cable
A straight cable connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. The following diagram
depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Transmit Pair
Receive Pair
Straight
Cable
Receive Pair
Transmit Pair
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Modular Connector
(RJ-45)
NIC
Figure 2. Typical Straight Cable Connection
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KSZ8041NL
Crossover Cable
A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. The
following diagram depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).
10/100 Ethernet
1
Receive Pair
10/100 Ethernet
Crossover
Cable
1
Receive Pair
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)

HUB
Modular Connector (RJ-45)

HUB
Figure 3. Typical Crossover Cable Connection
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KSZ8041NL
Power Management
The KSZ8041NL offers the following power management modes:
Power Saving Mode
This mode is used to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode
is enabled, cable is disconnected, and register 1F bit 10 is set to 1. Under power saving mode, the KSZ8041NL shuts
down all transceiver blocks, except for transmitter, energy detect and PLL circuits. Additionally, in MII mode, the RXC
clock output is disabled. RXC clock is enabled after the cable is connected and link is established.
Power saving mode is disabled by writing a zero to register 1F bit 10.
Power Down Mode
This mode is used to power down the entire KSZ8041NL device when it is not in use. Power down mode is enabled by
writing a one to register 0 bit 11. In the power down state, the KSZ8041NL disables all internal functions, except for the
MII management interface.
Reference Clock Connection Options
A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041NL. The reference
clock is 25MHz for MII mode and 50MHz for RMII mode. The following two figures illustrate how to connect the reference
clock to XI / REFCLK (pin 9) and XO (pin 8) of the KSZ8041NL.
Figure 4. 25MHz Crystal / Oscillator Reference Clock for MII Mode
Figure 5. 50MHz Oscillator Reference Clock for RMII Mode
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KSZ8041NL
Reference Circuit for Power and Ground Connections

The KSZ8041NL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground
connections are shown in the following figure and table.
Figure 6. KSZ8041NL Power and Ground Connections
Power Pin
Pin Number
Description
VDDPLL_1.8
Decouple with 10uF and 0.1uF capacitors-to-ground.
VDDA_3.3
Connect to boards 3.3V supply through ferrite bead.
VDDIO_3.3
17
Connect to boards 3.3V supply.
Table 5. KSZ8041NL Power Pin Description
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Register Map
Register Number (Hex)
Description
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
Link Partner Next Page Ability
9h 14h
Reserved
15h
RXER Counter
16h 1Ah
Reserved
1Bh
Interrupt Control/Status
1Ch 1Dh
Reserved
1Eh
PHY Control 1
1Fh
PHY Control 2
Register Description
Address
Name
(1)
Description
Mode
1 = Software reset
RW/SC
RW
RW
Set by SPEED strapping pin.
Default
Register 0h Basic Control

0.15
Reset
0 = Normal operation
This bit is self-cleared after a 1 is written to it.
0.14
Loop-back
0.13
Speed Select
(LSB)
1 = Loop-back mode
1 = 100Mbps
0 = 10Mbps
See Strapping Options section

for details.
This bit is ignored if auto-negotiation is enabled

(register 0.12 = 1).
0.12
0.11
AutoNegotiation
Enable
1 = Enable auto-negotiation process
Power Down
1 = Power down mode
RW
0 = Disable auto-negotiation process
Set by NWAYEN strapping pin.

for details.
If enabled, auto-negotiation result overrides

settings in register 0.13 and 0.8.
RW
RW
Set by ISO strapping pin.
0.10
Isolate
1 = Electrical isolation of PHY from MII and

TX+/TX-

for details.
0.9
Restart AutoNegotiation
1 = Restart auto-negotiation process
RW/SC
0 = Normal operation.
This bit is self-cleared after a 1 is written to it.
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Address
Name
Description
Mode
0.8
Duplex Mode
1 = Full-duplex
RW
(1)
0 = Half-duplex
0.7
Collision Test
Default
Set by DUPLEX strapping pin.
for details.
1 = Enable COL test
RW
RO
000_000
RW
RO
RO
RO
RO
RO
RO
0000
RO
RO
RO/LH
RO
RO/LL
RO/LH
1 = Supports extended capabilities registers
RO
Assigned to the 3rd through 18th bits of the

Organizationally Unique Identifier (OUI).
Kendin Communications OUI is 0010A1 (hex)
RO
0022h
0 = Disable COL test

0.6:1
0.0
Reserved
Disable
0 = Enable transmitter
Transmitter
1 = Disable transmitter
Register 1h Basic Status

1.15
100Base-T4
1 = T4 capable
0 = Not T4 capable
1.14
100Base-TX
Full Duplex
1 = Capable of 100Mbps full-duplex
1.13
100Base-TX
Half Duplex
1 = Capable of 100Mbps half-duplex
10Base-T Full
Duplex
1 = Capable of 10Mbps full-duplex
1.11
10Base-T Half
Duplex
1 = Capable of 10Mbps half-duplex
1.10:7
Reserved
1.6
No Preamble
1.5
AutoNegotiation
Complete
1 = Auto-negotiation process completed
Remote Fault
1 = Remote fault
1.12
0 = Not capable of 100Mbps full-duplex

0 = Not capable of 100Mbps half-duplex
0 = Not capable of 10Mbps full-duplex
0 = Not capable of 10Mbps half-duplex
1 = Preamble suppression
0 = Normal preamble
1.4
0 = Auto-negotiation process not completed
0 = No remote fault
1.3
1.2
AutoNegotiation
Ability
1 = Capable to perform auto-negotiation
Link Status
1 = Link is up
0 = Not capable to perform auto-negotiation
0 = Link is down
1.1
Jabber Detect
1 = Jabber detected
0 = Jabber not detected (default is low)
1.0
Extended
Capability
Register 2h PHY Identifier 1

2.15:0
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PHY ID
Number
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Address
KSZ8041NL
Name
Description
Mode
(1)
Default
Register 3h PHY Identifier 2

3.15:10
PHY ID
Number
Assigned to the 19th through 24th bits of the

Organizationally Unique Identifier (OUI).
Kendin Communications OUI is 0010A1 (hex)
RO
0001_01
3.9:4
Model Number
Six bit manufacturers model number
RO
01_0001
3.3:0
Revision
Number
Four bit manufacturers model number
RO
0010
RW
RO
RW
RO
00
RW
RO
Register 4h Auto-Negotiation Advertisement

4.15
Next Page
4.14
Reserved
4.13
Remote Fault
4.12:11
Reserved
4.10
Pause
4.9
100Base-T4
1 = Next page capable

0 = No next page capability.
1 = Remote fault supported
0 = No remote fault
1 = PAUSE function supported
0 = No PAUSE function supported
1 = T4 capable
0 = No T4 capability
4.8
4.7
4.6
4.5
4.4:0
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
10Base-T
Full-Duplex
10Base-T
Half-Duplex
Selector Field
[00001] = IEEE 802.3
RW
0 = No 100Mbps full-duplex capability

for details.
RW
0 = No 100Mbps half-duplex capability

for details.
RW
RW
RW
0_0001
RO
RO
RO
RO
RO
00
RO

Register 5h Auto-Negotiation Link Partner Ability

5.15
Next Page
1 = Next page capable

0 = No next page capability
5.14
Acknowledge
1 = Link code word received from partner

0 = Link code word not yet received
5.13
Remote Fault
5.12
Reserved
5.11:10
Pause
1 = Remote fault detected

0 = No remote fault
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
5.9
100Base-T4
1 = T4 capable
0 = No T4 capability
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(1)
Address
Name
Description
Mode
5.8
100Base-TX
Full-Duplex
RO
5.7
100Base-TX
Half-Duplex
RO
10Base-T
Full-Duplex
RO
10Base-T
Half-Duplex
RO
Selector Field
[00001] = IEEE 802.3
RO
0_0001
RO
0000_0000_000
RO/LH
RO
RO
RO/LH
RO
RW
RO
RW
RW
RO
RW
000_0000_0001
RO
RO
RO
5.6
5.5
5.4:0
Default

Register 6h Auto-Negotiation Expansion

6.15:5
Reserved
6.4
Parallel
Detection Fault
1 = Fault detected by parallel detection
Link Partner
Next Page
Able
1 = Link partner has next page capability
Next Page
Able
1 = Local device has next page capability
Page Received
1 = New page received
6.3
6.2
6.1
0 = No fault detected by parallel detection.

0 = Link partner does not have next page
capability
0 = Local device does not have next page
capability
0 = New page not received yet
6.0
Link Partner
AutoNegotiation
Able
1 = Link partner has auto-negotiation capability

0 = Link partner does not have auto-negotiation
capability
Register 7h Auto-Negotiation Next Page

7.15
Next Page
1 = Additional next page(s) will follow

0 = Last page
7.14
Reserved
7.13
Message Page
1 = Message page
0 = Unformatted page
7.12
Acknowledge2
1 = Will comply with message

0 = Cannot comply with message
7.11
Toggle
1 = Previous value of the transmitted link code

word equaled logic one
7.10:0
Message Field
11-bit wide field to encode 2048 messages
0 = Logic zero
Register 8h Link Partner Next Page Ability

8.15
Next Page
1 = Additional Next Page(s) will follow

0 = Last page
8.14
Acknowledge
1 = Successful receipt of link word
8.13
Message Page
1 = Message page
0 = No successful receipt of link word

0 = Unformatted page
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KSZ8041NL
(1)
Address
Name
Description
Mode
Default
8.12
Acknowledge2
1 = Able to act on the information
RO
8.11
Toggle
1 = Previous value of transmitted link code

word equal to logic zero
RO
RO
000_0000_0000
RO/SC
0000h
RW
RW
RW
RW
RW
RW
RW
RW
RO/SC
RO/SC
RO/SC
RO/SC
RO/SC
RO/SC
0 = Not able to act on the information
0 = Previous value of transmitted link code

word equal to logic one
8.10:0
Message Field
Register 15h RXER Counter

15.15:0
RXER Counter
Receive error counter for Symbol Error frames
Register 1Bh Interrupt Control/Status

1b.15
Jabber
Interrupt
Enable
1 = Enable Jabber Interrupt
Receive Error
Interrupt
Enable
1 = Enable Receive Error Interrupt
Page Received
Interrupt
Enable
1 = Enable Page Received Interrupt
Parallel Detect
Fault Interrupt
Enable
1 = Enable Parallel Detect Fault Interrupt
Link Partner
Acknowledge
Interrupt
Enable
1 = Enable Link Partner Acknowledge Interrupt
Link Down
Interrupt
Enable
1= Enable Link Down Interrupt
Remote Fault
Interrupt
Enable
1 = Enable Remote Fault Interrupt
Link Up
Interrupt
Enable
1 = Enable Link Up Interrupt
Jabber
Interrupt
1 = Jabber occurred
Receive Error
Interrupt
1 = Receive Error occurred
Page Receive
Interrupt
1 = Page Receive occurred
1b.4
Parallel Detect
Fault Interrupt
1 = Parallel Detect Fault occurred
1b.3
Link Partner
Acknowledge
Interrupt
1= Link Partner Acknowledge occurred
Link Down
Interrupt
1= Link Down occurred
1b.14
1b.13
1b.12
1b.11
1b.10
1b.9
1b.8
1b.7
1b.6
1b.5
1b.2
July 2008
0 = Disable Jabber Interrupt
0 = Disable Receive Error Interrupt
0 = Disable Page Received Interrupt
0 = Disable Parallel Detect Fault Interrupt
0 = Disable Link Partner Acknowledge

Interrupt
0 = Disable Link Down Interrupt
0 = Disable Remote Fault Interrupt
0 = Disable Link Up Interrupt
0 = Jabber did not occurred

0 = Receive Error did not occurred
0 = Page Receive did not occurred
0 = Parallel Detect Fault did not occurred
0= Link Partner Acknowledge did not occurred
0= Link Down did not occurred
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KSZ8041NL
(1)
Address
Name
Description
Mode
Default
1b.1
Remote Fault
Interrupt
1= Remote Fault occurred
RO/SC
1b.0
Link Up
Interrupt
1= Link Up occurred
RO/SC
RW
00
0= Remote Fault did not occurred

0= Link Up did not occurred
Register 1Eh PHY Control 1

1e:15:14
LED mode
[00] =
LED1 : Speed
LED0 : Link/Activity
[01] =
LED1 : Activity
LED0 : Link
[10] =
Reserved
[11] =
Reserved
1e.13
Polarity
1e.12
Reserved
1e.11
MDI/MDI-X
State
0 = Polarity is not reversed
RO
1 = Polarity is reversed
1e:10:8
Reserved
1e:7
Remote
loopback
1e:6:0
RO
0 = MDI
RO
1 = MDI-X
0 = Normal mode
RW
RW
RW
RW
RO
1 = Remote (analog) loop back is enable
Reserved
Register 1Fh PHY Control 2

1f:15
HP_MDIX
0 = Micrel Auto MDI/MDI-X mode

1 = HP Auto MDI/MDI-X mode
1f:14
MDI/MDI-X
Select
When Auto MDI/MDI-X is disabled,

0 = MDI Mode
Transmit on TX+/- (pins 7,6) and
Receive on RX+/- (pins 5,4)
1 = MDI-X Mode
Transmit on RX+/- (pins 5,4) and
Receive on TX+/- (pins 7,6)
1f:13
Pairswap
Disable
1 = Disable auto MDI/MDI-X
1f.12
Energy Detect
1 = Presence of signal on RX+/- analog wire

pair
0 = Enable auto MDI/MDI-X
0 = No signal detected on RX+/-
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Micrel, Inc.
KSZ8041NL
(1)
Address
Name
Description
Mode
Default
1f.11
Force Link
1 = Force link pass
RW
RW
RW
RW
RW
RO
RO
RO
000
RW
RW
0 = Normal link operation

This bit bypasses the control logic and allow
transmitter to send pattern even if there is no
link.
1f.10
Power Saving
1 = Enable power saving

0 = Disable power saving
If power saving mode is enabled and the cable
is disconnected, the RXC clock output (in MII
mode) is disabled. RXC clock is enabled after
the cable is connected and link is established.
1f.9
Interrupt Level
1 = Interrupt pin active high

0 = Interrupt pin active low
1f.8
Enable Jabber
1 = Enable jabber counter
1f.7
AutoNegotiation
Complete
1 = Auto-negotiation process completed
1f.6
Enable Pause
(Flow Control)
1 = Flow control capable
1f.5
PHY Isolate
1 = PHY in isolate mode
0 = Disable jabber counter

0 = Auto-negotiation process not completed
0 = No flow control capability

0 = PHY in normal operation
1f.4:2
Operation
Mode
Indication
[000] = still in auto-negotiation

[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = reserved
1f.1
Enable SQE
test
1 = Enable SQE test
1f.0
Disable Data
Scrambling
1 = Disable scrambler
0 = Disable SQE test

0 = Enable scrambler
Note:
1.
RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
(VDDPLL_1.8) ............................................... -0.5V to +2.4V
(VDDIO_3.3, VDDA_3.3) ................................... -0.5V to +4.0V
Input Voltage (all inputs) ............................... -0.5V to +4.0V
Output Voltage (all outputs) .......................... -0.5V to +4.0V
Lead Temperature (soldering, 10sec.) ....................... 260C
Storage Temperature (Ts) ..........................-55C to +150C
(3)
ESD Rating .................................................................. 6kV
Supply Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
Ambient Temperature (TA) .............................. 0C to +70C
Maximum Junction Temperature (TJ Max) ................. 125C
Maximum Case Temperature (TC Max)...................... 150C
Thermal Resistance (JA) .........................................34C/W
Thermal Resistance (JC) ...........................................6C/W
Electrical Characteristics(4)
Symbol
Parameter
Condition
Min
Typ
Max
Units
53
58.3
mA
38
41.8
mA
(5)
Supply Current
IDD1
100Base-TX
IDD2
10Base-T
Chip only (no transformer);

Full-duplex traffic @ 100% utilization
Chip only (no transformer);
Full-duplex traffic @ 100% utilization
IDD3
Power Saving Mode
Ethernet cable disconnected (reg. 1F.10 = 1)
32
35.2
mA
IDD4
Power Down Mode
Software power down (reg. 0.11 = 1)
4.4
mA
TTL Inputs
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
2.0
VIN = GND ~ VDDIO
V
0.8
10
-10
TTL Outputs
VOH
Output High Voltage
IOH = -4mA
VOL
Output Low Voltage
IOL = 4mA
|Ioz|
Output Tri-State Leakage
2.4
V
0.4
10
100Base-TX Transmit (measured differentially after 1:1 transformer)

VO
Peak Differential Output Voltage
VIMB
Output Voltage Imbalance
tr , tf
Rise/Fall Time
Rise/Fall Time Imbalance
100 termination across differential output
0.95
1.05
ns
0.5
ns
+ 0.25
ns
Duty Cycle Distortion

Overshoot
VSET
0.65
Reference Voltage of ISET

Output Jitter
0.7
Peak-to-peak
V
1.4
ns
Notes:
1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification
is not implied. Maximum conditions for extended periods may affect reliability.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. TA = 25C. Specification for packaged product only.
5. Current consumption is for the single 3.3V supply KSZ8041NL device only, and includes the 1.8V supply voltage (VDDPLL_1.8) that is provided by the
KSZ8041NL. The PHY ports transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T.
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Electrical Characteristics(6)
10Base-T Transmit (measured differentially after 1:1 transformer)
VP
tr , tf
Peak Differential Output Voltage
Jitter Added
Peak-to-peak
Rise/Fall Time
2.2
2.8
3.5
ns
25
ns
400
mV
10Base-T Receive
VSQ
Squelch Threshold
5MHz square wave
Notes:
6. TA = 25C. Specification for packaged product only.
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Timing Diagrams
MII SQE Timing (10Base-T)
Figure 7. MII SQE Timing (10Base-T)
Timing Parameter
Description
Min
Typ
Max
Unit
tP
TXC period
400
ns
tWL
TXC pulse width low
200
ns
tWH
TXC pulse width high
200
ns
tSQE
COL (SQE) delay after TXEN de-asserted
2.5
us
tSQEP
COL (SQE) pulse duration
1.0
us
Table 6. MII SQE Timing (10Base-T) Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
MII Transmit Timing (10Base-T)
Figure 8. MII Transmit Timing (10Base-T)
Timing Parameter
Description
Min
Typ
Max
Unit
tP
TXC period
400
ns
tWL
TXC pulse width low
200
ns
tWH
200
ns
tSU1
TXD[3:0] setup to rising edge of TXC
10
tSU2
TXEN setup to rising edge of TXC
10
ns
tHD1
TXD[3:0] hold from rising edge of TXC
ns
tHD2
TXEN hold from rising edge of TXC
ns
tCRS1
TXEN high to CRS asserted latency
Bit
Time
tCRS2
TXEN low to CRS de-asserted latency
Bit
Time
ns
Table 7. MII Transmit Timing (10Base-T) Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
MII Receive Timing (10Base-T)
Figure 9. MII Receive Timing (10Base-T)
Timing Parameter
Description
Min
Typ
tP
RXC period
400
ns
tWL
RXC pulse width low
200
ns
tWH
RXC pulse width high
200
ns
tOD
(RXD[3:0], RXER, RXDV) output

delay from rising edge of RXC
tRLAT
CRS to (RXD[3:0], RXER, RXDV)

latency
182
Max
225
6.5
Unit
ns
us
Table 8. MII Receive Timing (10Base-T) Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
MII Transmit Timing (100Base-TX)
Figure 10. MII Transmit Timing (100Base-TX)
Timing Parameter
Description
Min
Typ
Max
Unit
tP
TXC period
40
ns
tWL
TXC pulse width low
20
ns
tWH
20
ns
tSU1
TXD[3:0] setup to rising edge of TXC
10
ns
tSU2
TXEN setup to rising edge of TXC
10
ns
tHD1
TXD[3:0] hold from rising edge of TXC
ns
tHD2
TXEN hold from rising edge of TXC
ns
tCRS1
TXEN high to CRS asserted latency
Bit
Time
tCRS2
TXEN low to CRS de-asserted latency
Bit
Time
Table 9. MII Transmit Timing (100Base-TX) Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
MII Receive Timing (100Base-TX)
Figure 11. MII Receive Timing (100Base-TX)
Timing Parameter
Description
tP
RXC period
Min
Typ
40
Max
ns
tWL
RXC pulse width low
20
ns
tWH
RXC pulse width high
tOD
(RXD[3:0], RXER, RXDV) output

delay from rising edge of RXC
19
tRLAT
CRS to (RXD[3:0], RXER, RXDV)

latency
20
Unit
ns
25
ns
Bit
Time
Table 10. MII Receive Timing (100Base-TX) Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
RMII Timing
Figure 12. RMII Timing Data Received from RMII
Figure 13. RMII Timing Data Input to RMII
Timing Parameter
Description
Min
Typ
Max
tcyc
Clock cycle
t1
Setup time
ns
t2
Hold time
ns
tod
Output delay
20
2.8
Unit
ns
10
ns
Table 11. RMII Timing Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Auto-Negotiation Timing
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing
Timing Parameter
Description
Min
Typ
Max
Units
tBTB
FLP Burst to FLP Burst
16
24
ms
tFLPW
FLP Burst width
tPW
Clock/Data Pulse width
tCTD
Clock Pulse to Data Pulse
55.5
64
69.5
tCTC
Clock Pulse to Clock Pulse
111
128
139
Number of Clock/Data Pulse per

FLP Burst
17
ms
100
ns
33
Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
MDC/MDIO Timing
Figure 15. MDC/MDIO Timing
Timing Parameter
Description
Min
tP
MDC period
t1MD1
MDIO (PHY input) setup to rising edge of MDC
10
tMD2
MDIO (PHY input) hold from rising edge of MDC
10
tMD3
MDIO (PHY output) delay from rising edge of MDC
Typ
400
Max
Unit
ns
ns
ns
222
ns
Table 13. MDC/MDIO Timing Parameters
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Reset Timing
The KSZ8041NL reset timing requirement is summarized in the following figure and table.
Figure 16. Reset Timing
Parameter
Description
Min
Max
Units
tsr
Stable supply voltage to reset high
10
ms
tcs
Configuration setup time
ns
tch
Configuration hold time
ns
trc
Reset to strap-in pin output
ns
Table 14. Reset Timing Parameters
After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on the MIIM
(MDC/MDIO) Interface.
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Reset Circuit
The following reset circuit is recommended for powering up the KSZ8041NL if reset is triggered by the power supply.
Figure 17. Recommended Reset Circuit
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA).
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041NL device. The RST_OUT_n
from CPU/FPGA provides the warm reset after power up.
Figure 18. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.
July 2008
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Micrel, Inc.
KSZ8041NL
Reference Circuits for LED Strapping Pins

The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins.
Figure 19. Reference Circuits for LED Strapping Pins
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Selection of Isolation Transformer

A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes
is recommended for exceeding FCC requirements.
The following table gives recommended transformer characteristics.
Parameter
Value
Turns ratio
1 CT : 1 CT
Test Condition
Open-circuit inductance (min.)
350H
100mV, 100kHz, 8mA
Leakage inductance (max.)
0.4H
1MHz (min.)
Inter-winding capacitance (max.)
12pF
D.C. resistance (max.)
0.9
Insertion loss (max.)
1.0dB
HIPOT (min.)
1500Vrms
0MHz 65MHz
Table 15. Transformer Selection Criteria
Magnetic Manufacturer
Part Number
Auto MDI-X
Number of Port
Bel Fuse
S558-5999-U7
Yes
Bel Fuse (Mag Jack)
SI-46001
Yes
Bel Fuse (Mag Jack)
SI-50170
Yes
Delta
LF8505
Yes
LanKom
LF-H41S
Yes
Pulse
H1102
Yes
Pulse (low cost)
H1260
Yes
Transpower
HB726
Yes
TDK (Mag Jack)
TLA-6T718
Yes
Table 16. Qualified Single Port Magnetics
Selection of Reference Crystal

Characteristics
Value
Units
Frequency
25
MHz
Frequency tolerance (max)
50
ppm
Load capacitance (max)
20
pF
Series resistance
40
Table 17. Typical Reference Crystal Characteristics
July 2008
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M9999-071808-1.2
Micrel, Inc.
KSZ8041NL
Package Information
32-Pin (5mm x 5mm) MLF Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user.
A Purchasers use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchasers own risk and Purchaser agrees to
fully indemnify Micrel for any damages resulting from such use or sale.
2006 Micrel, Incorporated.
July 2008
45
M9999-071808-1.2

KSZ8041NL: General Description

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KSZ8041NL

The KSZ8041NL represents a new level of features and

The KSZ8041NL comes in a 32-pin, lead-free MLF (QFN

MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

Single-chip 10Base-T/100Base-TX physical layer

Available in 32-pin (5mm x 5mm) MLF package

Commercial Temperature Device

Industrial Temperature Device

Automotive Qualified Device

Contact factory for lead time.

Data sheet created.

Added maximum MDC clock speed.

Added Automotive Qualified part number to Ordering Information.

Reference Circuit for Power and Ground Connections .................................................................................................... 23

Absolute Maximum Ratings ............................................................................................................................................ 31

Operating Ratings ............................................................................................................................................................ 31

Timing Diagrams ................................................................................................................................................................. 33

32-Pin (5mm x 5mm) MLF

1.8V analog VDD

3.3V analog VDD

Physical receive or transmit signal (- differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (- differential)

Physical transmit or receive signal (+ differential)

Crystal / Oscillator / External Clock Input

25MHz +/-50ppm (crystal, oscillator, or external clock)

50MHz +/-50ppm (oscillator, or external clock only)

Set physical transmit output current

Management Interface (MII) Data I/O

Management Interface (MII) Clock Input

The pull-up/pull-down value is latched as PHYADDR[0] during

Receive Data Output[2]

The pull-up/pull-down value is latched as PHYADDR[1] during

Receive Data Output[1]

Receive Data Output[1]

The pull-up/pull-down value is latched as PHYADDR[2] during

Receive Data Output[0]

Receive Data Output[0]

Latched as DUPLEX (register 0h, bit 8) during power-up /

3.3V digital VDD

Receive Data Output[3]

Receive Data Valid Output /

Carrier Sense/Receive Data Valid Output /

The pull-up/pull-down value is latched as CONFIG2 during

Receive Clock Output

Receive Error Output /

Receive Error Output /

The pull-up/pull-down value is latched as ISOLATE during

Interrupt Output: Programmable Interrupt Output

Transmit Clock Output

Transmit Enable Input /

Transmit Enable Input

Transmit Data Input[0]

Transmit Data Input[0]

Transmit Data Input[1]

Transmit Data Input[1]

Transmit Data Input[2]

Transmit Data Input[3]

Collision Detect Output /