Ch06b Functions of Combinational Logic PDF
Ch06b Functions of Combinational Logic PDF
Ch06b Functions of Combinational Logic PDF
Lecture 8
Topic Outlines
Encoder
Decoder
Multiplexers (MUX)
Demultiplexers (DEMUX)
Topic Outlines
Encoder
Decoder
Multiplexers (MUX)
Demultiplexers (DEMUX)
Decoders Expansion
When a certain decoder size is needed, but only smaller
number of sizes is available.
Combine 2 or more decoders in a hierarchy, i.e. cascade the
smaller decoders to form a larger decoder size.
Decoder Expansion
Example:
Decoder Expansion
The Operation
The MSB input, A2, functions:
As enable, EN, of one decoder
As its complement, EN to the other decoder
When A2=0,
When A2=1,
Decoder Expansion
The function of EN input
Very useful and convenient way to interconnect 2 or
more functional blocks
For the purpose of expanding digital functions into:
and
Decoder Expansion
Example:
Implementing a Binary Adder Using a Decoder
For an addition of X, Y, and Z (as Cin), the S and Cout
expression are as follows:
S(X,Y,Z) = m (1, 2, 4, 7)
C(X,Y,Z) = m (3, 5, 6, 7)
Decoder Expansion
Implementing a Binary Adder Using a Decoder
- The logic circuit
Multiplexers (MUX)
MUX is a device that allows
digital information from
several sources to be routed
onto a single line for
transmission
It is made up of several datainput lines and a single output
line. It also has data-select
inputs which permits digital
data on any one of the inputs
to be switched to the output
line.
MUX is also known as data
selectors
n select
inputs
1 data
output
2n data
inputs
Multiplexers (MUX)
2:1 MUX
Data selector
SELECT input code determines
which input is transmitted to
output Z.
Multiplexers (MUX)
4:1 MUX
DATA-SELECT
INPUTS
D0
D1
D2
D0
D1
D3
D3 S
1
4-to-1 Z
D2 MUX
S0
INPUT
SELECTED
S0
S1
D0
D1
D2
D3
S1 S0
If a binary 0 (S0=0 and S1=0) is applied to the data-select lines,
the data on input D0 appear on the data-output line
Multiplexers (MUX)
4:1 MUX
Logic diagram
for 4:1 MUX
Y D0 S1 S 0 D1 S1 S 0 D2 S1 S 0 D3 S1 S 0
Multiplexers (MUX)
Question 3
Construct an 8:1 multiplexer using block diagram.
Multiplexers (MUX)
Another design option for 8:1 mux
Using construction of larger multiplexers from smaller ones.
8-to-1-Line Multiplexer
16-to-1-Line Multiplexer
Multiplexers (MUX)
Implementing a Boolean Function with a MUX
A multiplexer is basically a decoder that includes the OR
gate within the block.
To implement a Boolean function of n variables with a
mux having n selection inputs and 2n data inputs, one for
each minterm.
The minterms are generated in a mux by the circuit associated
with the selection inputs.
Individual minterms can be selected by the data inputs.
Multiplexers (MUX)
Implementing a Boolean Function with a MUX
Another method (more efficient way)
Implementing a Boolean function of n variables with a mux
having only n-1 selection inputs and 2n-1 data inputs.
Multiplexers (MUX)
Implementing a Boolean Function with a MUX
General procedure:
1.
2.
3.
4.
5.
Multiplexers (MUX)
Example
Implement F (X,Y,Z) = m (1, 2, 6, 7) using
4:1 MUX
Multiplexers (MUX)
Example
Implement F (A, B, C, D) = m (1, 3, 4, 11,
12, 13, 14, 15) using 8:1 MUX
Content-selector Display
Demultiplexers (DEMUX)
DEMUX reverse the multiplexing functions
It takes digital information from one line and distributes it
to a given number of output lines
DEMUX is also known as data distributor
1 data
input
2n data
outputs
n select
inputs
1-line-to-8-line multiplexer
Demultiplexers (DEMUX)
1:4 DEMUX
Demultiplexers (DEMUX)
Question 4:
Construct a 1:4 DEMUX using block diagram. Show the
equivalent Truth-Table.
I0
1 -4
DEMUX
Q0
Q1
Q2
Q3
S 1 S 0 Block diagram
S1
S0
I0
Q0
Truth-table
S1 S0
I1 Q3 Q2 Q1 Q0
Q1
Q2
Q3
Logic circuit
Solve this..
Design the following:
16-line-to-4-line encoder using the 8-line-to-3-line
encoder in cascade
A 4:1 MUX using 2:1 MUXes
A 8:1 MUX using 4:1 MUXes
A 1:4 DeMUX using 1:2 DeMUX
A 1:8 DeMUX using 1:4 DeMUX