4-/6-Channel Digital Potentiometers:, 50 K, 100 K 2.7 V Dual Supply
4-/6-Channel Digital Potentiometers:, 50 K, 100 K 2.7 V Dual Supply
4-/6-Channel Digital Potentiometers:, 50 K, 100 K 2.7 V Dual Supply
FEATURES
256 Position
Multiple Independently Programmable Channels
AD52044-Channel
AD52066-Channel
Potentiometer Replacement
10 k, 50 k, 100 k
3-Wire SPI-Compatible Serial Data Input
+2.7 V to +5.5 V Single Supply; 2.7 V Dual Supply
Operation
Power ON Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
GENERAL DESCRIPTION
4-/6-Channel
Digital Potentiometers
AD5204/AD5206
FUNCTIONAL BLOCK DIAGRAMS
AD5204
CS
CLK
EN
SDO
A2
A1
A0
D7
DO
VDD
A1
D7
W1
RDAC
LATCH
#1
ADDR
DEC
D0
B1
SER
REG
A4
D7
W4
SDI
DI
RDAC
LATCH
#4
D0
8
GND
D0
POWERON
PRESET
VSS
PR
AD5206
CS
CLK
EN
A2
A1
A0
D7
B4
SHDN
A1
D7
W1
RDAC
LATCH
#1
ADDR
DEC
D0
VDD
B1
SER
REG
A6
D7
W6
SDI
DI
RDAC
LATCH
#6
D0
8
GND
POWERON
PRESET
D0
B6
R
VSS
An optional reset (PR) pin forces all the AD5204 wipers to the
midscale position by loading 80H into the VR latch.
The AD5204/AD5206 is available in both surface mount
(SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All
parts are guaranteed to operate over the extended industrial
temperature range of 40C to +85C. For additional single,
dual, and quad channel devices, see the AD8400/AD8402/
AD8403 products.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD5204/AD5206SPECIFICATIONS
(V = +5 V 10% or +3 V 10%, V
DD
Symbol
SS
Conditions
Min
Typ1
Max
Units
1
2
30
1/4
1/2
+1
+2
+30
LSB
LSB
%
ppm/C
%
700
0.25
50
8
1
2
2
0
1/4
1/2
15
1
+1
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
Capacitance6 Wx
Shutdown Current 7
Common-Mode Leakage
VA, VB, VW
CA, C B
CW
IA_SD
ICM
VIH
VIL
VOH
VOL
IIL
CIL
VDD = +5 V/+3 V
VDD = +5 V/+3 V
RPULLUP = 1 k to +5 V
IOL = 1.6 mA, VLOGIC = +5 V
VIN = 0 V or +5 V
POWER SUPPLIES
Power Single Supply Range
Power Dual Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation 8
Power Supply Sensitivity
VDD Range
VDD/SS Range
IDD
ISS
PDISS
PSS
VSS = 0 V
VIH = +5 V or V IL = 0 V
VSS = 2.5 V, VDD = +2.7 V
VIH = +5 V or V IL = 0 V
VDD = +5 V 10%
0.0002
BW_10K
BW_50K
BW_100K
THDW
tS
e N_WB
RAB = 10 k
RAB = 50 k
RAB = 100 k
VA = 1.414 V rms, V B = 0 V dc, f = 1 kHz
VA = 5 V, VB = 0 V, 1 LSB Error Band
RWB = 5 k, f = 1 kHz, PR = 0
721
137
69
0.004
2/9/18
9
DYNAMIC CHARACTERISTICS
Bandwidth 3 dB
VSS
f = 1 MHz, Measured to GND, Code = 40H
f = 1 MHz, Measured to GND, Code = 40H
+1
+2
0
+2
VDD
45
60
0.01
1
1.5
100
2.4/2.1
0.8/0.6
4.9
0.4
1
5
2.7
2.3
12
12
5.5
2.7
60
60
0.3
0.005
Bits
LSB
LSB
ppm/C
LSB
LSB
V
pF
pF
A
nA
V
V
V
V
A
pF
V
V
A
A
mW
%/%
6, 9
20
5
5
1
15
40
90
0
0
10
kHz
kHz
kHz
%
s
nV/Hz
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
REV. 0
AD5204/AD5206
5
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5204/AD5206 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
WARNING!
ESD SENSITIVE DEVICE
AD5204/AD5206
1
SDI
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
tRS
PR
0
1
CLK
tS
VDD
61 LSB
VOUT
0V
CS
VDD
VOUT
0V
SDI
(DATA IN)
Ax OR Dx
Ax OR Dx
tDH
tDS
SDO
(DATA OUT)
1
Ax OR Dx
Ax OR Dx
tPD_MAX
tCH
tCS1
1
CLK
0
CS
tCSH0
tCSS
tCL
tCSH1
tCSW
tS
VOUT
61 LSB
VDD
61 LSB ERROR BAND
0V
ORDERING GUIDE
Model
Temperature Range
Package Descriptions
Package Options
AD5204BN10
AD5204BR10
AD5204BRU10
AD5204BN50
AD5204BR50
AD5204BRU50
AD5204BN100
AD5204BR100
AD5204BRU100
AD5206BN10
AD5206BR10
AD5206BRU10
AD5206BN50
AD5206BR50
AD5206BRU50
AD5206BN100
AD5206BR100
AD5206BRU100
10
10
10
50
50
50
100
100
100
10
10
10
50
50
50
100
100
100
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
N-24
R-24/SOL-24
RU-24
N-24
R-24/SOL-24
RU-24
N-24
R-24/SOL-24
RU-24
N-24
R-24/SOL-24
RU-24
N-24
R-24/SOL-24
RU-24
N-24
R-24/SOL-24
RU -24
The AD5204/AD5206 contains 5,925 transistors. Die size; 92 mil 114 mil, 10,488 sq. mil.
REV. 0
AD5204/AD5206
AD5206 PIN CONFIGURATION
NC 1
24
B4
A6 1
24
B4
NC 2
23
W4
W6 2
23
W4
GND 3
22
A4
B6 3
22
A4
CS 4
21
B2
GND 4
21
B2
PR 5
20
W2
CS 5
20
W2
AD5204
19
A2
AD5206
19
A2
(NOT TO
SCALE)
VDD 6
(NOT TO
SCALE)
VDD 6
SHDN 7
18
A1
SDI 7
18
A1
17
W1
CLK 8
17
W1
CLK 9
16
B1
VSS 9
16
B1
SDO 10
15
A3
B5 10
15
A3
VSS 11
14
W3
W5 11
14
W3
NC 12
13
B3
A5 12
13
B3
SDI
NC = NO CONNECT
Pin
No.
Name
1, 2,
12
3
4
NC
GND
CS
PR
VDD
SHDN
8
9
10
SDI
CLK
SDO
11
VSS
13
14
15
16
17
18
19
20
21
22
23
24
B3
W3
A3
B1
W1
A1
A2
W2
B2
A4
W4
B4
REV. 0
Description
Not Connected.
Ground.
Chip Select Input, Active Low. When CS
returns high, data in the serial input register
is decoded based on the address bits and
loaded into the target RDAC latch.
Active low preset to midscale; sets RDAC
registers to 80H.
Positive power supply, specified for
operation at both +3 V or +5 V. (Sum of
|VDD| + |VSS| <5.5 V.)
Active low input. Terminal A open-circuit.
Shutdown controls Variable Resistors #1
through #4.
Serial Data Input. MSB First.
Serial Clock Input, positive edge triggered.
Serial Data Output, Open Drain transistor
requires pull-up resistor.
Negative Power Supply, specified for
operation at both 0 V or 2.7 V. (Sum of
|VDD| + |VSS| <5.5 V.)
B Terminal RDAC #3.
Wiper RDAC #3, addr = 0102.
A Terminal RDAC #3.
B Terminal RDAC #1.
Wiper RDAC #1, addr = 0002.
A Terminal RDAC #1.
A Terminal RDAC #2.
Wiper RDAC #2, addr = 0012.
B Terminal RDAC #2.
A Terminal RDAC #4.
Wiper RDAC #4, addr = 0112.
B Terminal RDAC #4.
Pin
No.
Name
Description
1
2
3
4
5
A6
W6
B6
GND
CS
VDD
7
8
9
SDI
CLK
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B5
W5
A5
B3
W3
A3
B1
W1
A1
A2
W2
B2
A4
W4
B4
NORMALIZED GAIN dB
SWITCH RESISTANCE V
VDD/VSS = 2.7V/0V
100
90
80
70
60
VDD/VSS = 5.5V/0V
VDD/VSS = 62.7V
10kV
0
VDD = 62.7V
VSS = 2.7V
VA = 100mV rms
DATA = 80H
2
4
50kV
VA
100kV
OP42
50
40
30
3.0
2.0
1.0
0
1.0
2.0
3.0
COMMON MODE V
4.0
5.0
6.0
6.00
6.01
12
6.02
18
10kV
24
6.05
6.06
GAIN dB
GAIN dB
6.03
6.04
50kV
100kV
30
6.07
54
1k
10k
FREQUENCY Hz
DATA = 20H
DATA = 10H
DATA = 08H
DATA = 02H
OP42
VB = 0V
DATA = 40H
DATA = 04H
48
6.08
DATA = 80H
36
42
VA
6.09
100
1M
5.99
VDD = 2.7V
VSS = 2.7V
VA = 100mV rms
DATA = 80H
TA = +258C
10k
100k
FREQUENCY Hz
1k
DATA = 01H
VDD = 2.7V
VSS = 2.7V
VA = 100mV rms
TA = +258C
60
1k
100k
VA
OP42
10k
100k
FREQUENCY Hz
1M
10kV
0
2
4
VDD = 2.7V
VSS = 0V
VA = 100mV rms
DATA = 80H
TA = +258C
DATA = 80H
12
DATA = 40H
18
DATA = 20H
24
GAIN dB
NORMALIZED GAIN dB
0
6
50kV
2.7V
30
36
100kV
42
48
+1.5V
54
10k
100k
FREQUENCY Hz
DATA = 08H
DATA = 04H
DATA = 02H
DATA = 01H
OP42
1k
DATA = 10H
60
1k
1M
VDD = 2.7V
VSS = 2.7V
VA = 100mV rms
TA = +258C
VA
OP42
10k
100k
FREQUENCY Hz
1M
REV. 0
AD5204/AD5206
0
8
7
DATA = 40H
12
SUPPLY CURRENT mA
DATA = 10H
24
DATA = 08H
30
DATA = 04H
36
DATA = 02H
42
DATA = 01H
48
54
60
1k
VDD = 2.7V
VSS = 2.7V
VA = 100mV rms
TA = +258C
DATA = 20H
18
GAIN dB
TA = +258C
DATA = 80H
VA
1
OP42
10k
100k
FREQUENCY Hz
0
10k
1M
100k
1M
FREQUENCY Hz
10M
2.5
60
TA = +258C
50
2.0
SINGLE SUPPLY
VDD = VSS
1.0
PSRR dB
TRIP POINT V
40
DUAL SUPPLY
VSS = 0V
0.1
30
VDD = 3.0V 6 10%
20
0.5
10
0.0
1.0
2.0
3.0
4.0
5.0
SUPPLY VOLTAGE VDD Volts
0
10
6.0
100
100
1k
FREQUENCY Hz
10k
100k
1.0
TA = +258C
10
0.1
THD + NOISE %
SUPPLY CURRENT mA
1
IDD AT VDD/VSS = 62.7V
0.1
VDD = +2.7V
VSS = 2.7V
TA = +258C
RAB = 10kV
0.01
NONINVERTING TEST CIRCUIT
0.001
0.01
0.001
0
1
2
3
4
5
INCREMENTAL INPUT LOGIC VOLTAGE Volts
1k
FREQUENCY Hz
10k
100k
REV. 0
100
AD5204/AD5206
OPERATION
data 00H . This B terminal connection has a wiper contact resistance of 45 . The second connection (10 k part) is the first
tap point located at 84 [= RBA (nominal resistance)/256 + RW
= 84 + 45 ] for data 01 H. The third connection is the next
tap point representing 78 + 45 = 123 for data 02H. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10006 . The wiper does not
directly connect to the A terminal. See Figure 16 for a simplified
diagram of the equivalent RDAC circuit.
ADDR
B10 B9 B8
DATA
B7 B6
A2 A1
MSB
210
D7 D6
MSB
27
A0
LSB
28
The general transfer equation determining the digitally programmed output resistance between Wx and Bx is:
B5
B4
B3
B2
B1
B0
D5
D4
D3
D2
D1
D0
LSB
20
R WB (Dx) = (Dx)/256 R BA + R W
SHDN
D7
D6
D5
D4
D3
D2
D1
D0
Table II.
D
(DEC)
RWB-
Output State
255
128
1
0
10006
5045
84
45
Full Scale
Midscale (PR = 0 Condition)
1 LSB
Zero Scale (Wiper Contact Resistance)
Ax
RS
RS
Wx
R WA (Dx) = (256Dx)/256 R BA + R W
RDAC
LATCH
&
DECODER
RS
(1)
(2)
Bx
Table III.
D
(DEC)
RWA-
Output State
255
128
1
0
84
5045
10006
10045
Full Scale
Midscale (PR = 0 Condition)
1 LSB
Zero Scale
REV. 0
AD5204/AD5206
The typical distribution of RBA from channel-to-channel matches
within 1%. However, device-to-device matching is process lot
dependent, having a 30% variation. The change in RBA with
temperature has a 700 ppm/C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
(3)
CS
CLK
EN
SDO
(AD5204
ONLY)
VDD
W1
RDAC
LATCH
#1
D0
L
P
L
L
H
H
H
H
X
X
H
X
H
L
H
H
X
X
H
H
P
H
H
L
A1
D7
ADDR
DEC
A2
A1
DO A0
D7
transfer data to the next packages SDI pin. The pull-up resistor
termination voltage may be larger than the VDD supply of the
AD5204 SDO output device, e.g., the AD5204 could operate at
VDD = 3.3 V and the pull-up for interface to the next device
could be set at +5 V. This allows for daisy chaining several
RDACs from a single processor serial-data line. Clock period
needs to be increased when using a pull-up resistor to the SDI
pin of the following device in the series. Capacitive loading at
the daisy chain node SDO-SDI between devices must be accounted for to successfully transfer data. When daisy chaining is
used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that
the address bits and data bits are in the proper decoding location. This would require 22 bits of address and data complying
to the word format provided in Table I if two AD5204 fourchannel RDACs are daisy chained. During shutdown (SHDN)
the SDO output pin is forced to the off (logic high state) to
disable power dissipation in the pull-up resistor. See Figure 19
for equivalent SDO output circuit schematic.
B1
SER
REG
A4/A6
D7
W4/W6
SDI
DI
RDAC
LATCH
#4/#6
D0
D0
B4/B6
GND
PR
(AD5204 ONLY)
REV. 0
A2
A1
A0
Latch Decoded
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
RDAC#1
RDAC#2
RDAC#3
RDAC#4
RDAC#5 AD5206 Only
RDAC#6 AD5206 Only
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder enabling one of four or six positive edge triggered RDAC
latches, see Figure 18 detail.
AD5204/AD5206
AD5204/AD5206
CS
IMS
RDAC 1
RDAC 2
ADDR
DECODE
DUT
A
W
V+
RDAC 4/6
IW = 1V/RNOMINAL
VW
CLK
SDI
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. Four separate 8bit data words must be clocked in to change all four VR settings.
VA
V+ = VDD 10%
V+
SHDN
VDD
DVMS%
PSS (%/%) =
DVDD%
VMS
SDO
SERIAL
REGISTER
DV
CS
SDI
VMS
SERIAL
REGISTER
V+ < VDD
V W2 [VW1 + IW (R AWII RBW)]
RW =
IW
MS
(
)
DV
DD
Q
GND
CK RS
CLK
PR
DUT B
+5V
W
VIN
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 20. Applies to
digital pins CS, SDI, SDO, PR, SHDN, CLK
OP279
OFFSET
GND
VOUT
+
OFFSET BIAS
340kV
LOGIC
VSS
+5V
DUT
V+ = VDD
1LSB = V+/256
+15V
V+
OFFSET BIAS
DUT
VSS
VOUT
VIN
VMS
DUT
B
OFFSET
GND
+
OP42
VOUT
2.5V
15V
NO CONNECT
DUT
A
W
RSW = 0.1V
ISW
DUT
IW
CODE = H
B
VMS
0.1V
ISW
VSS TO VDD
10
REV. 0
AD5204/AD5206
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C367789/99
13
12
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.015 (0.381)
0.008 (0.204)
24-Lead SOIC
(R-24/SOL-24)
0.6141 (15.60)
0.5985 (15.20)
24
13
0.2992 (7.60)
0.2914 (7.40)
1
0.4193 (10.65)
0.3937 (10.00)
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
3 458
0.0098 (0.25)
88
08
0.0192 (0.49) SEATING
0.0125 (0.32)
PLANE
0.0138 (0.35)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
24
13
PRINTED IN U.S.A.
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
11
88
08
0.028 (0.70)
0.020 (0.50)