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    This document lists 7 projects related to VLSI design and implementation using hardware description languages like VHDL and Verilog. The projects include improving error detection capabilities of orthogonal codes using FPGA implementation, designing a convolutional code encoder and decoder using VHDL along with the Viterbi algorithm, designing a 16-bit microprocessor with memory interface using VHDL, implementing the I2C protocol for inter-IC communication using Verilog, designing CMOS circuits using adiabatic logic, implementing an elevator control system using a state machine in VHDL, and designing basic digital components like counters, RAM, adders and ALUs in Verilog/VHDL. The document provides a brief description of each project and estimates

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    Includes Report, Presentation,: Synopsys

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    This document lists 7 projects related to VLSI design and implementation using hardware description languages like VHDL and Verilog. The projects include improving error detection capabilities of orthogonal codes using FPGA implementation, designing a convolutional code encoder and decoder using VHDL along with the Viterbi algorithm, designing a 16-bit microprocessor with memory interface using VHDL, implementing the I2C protocol for inter-IC communication using Verilog, designing CMOS circuits using adiabatic logic, implementing an elevator control system using a state machine in VHDL, and designing basic digital components like counters, RAM, adders and ALUs in Verilog/VHDL. The document provides a brief description of each project and estimates

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    This document lists 7 projects related to VLSI design and implementation using hardware description languages like VHDL and Verilog. The projects include improving error detection capabilities of orthogonal codes using FPGA implementation, designing a convolutional code encoder and decoder using VHDL along with the Viterbi algorithm, designing a 16-bit microprocessor with memory interface using VHDL, implementing the I2C protocol for inter-IC communication using Verilog, designing CMOS circuits using adiabatic logic, implementing an elevator control system using a state machine in VHDL, and designing basic digital components like counters, RAM, adders and ALUs in Verilog/VHDL. The document provides a brief description of each project and estimates

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    11 views2 pages

    Includes Report, Presentation,: Synopsys

    Uploaded by

    asit
    This document lists 7 projects related to VLSI design and implementation using hardware description languages like VHDL and Verilog. The projects include improving error detection capabilities of orthogonal codes using FPGA implementation, designing a convolutional code encoder and decoder using VHDL along with the Viterbi algorithm, designing a 16-bit microprocessor with memory interface using VHDL, implementing the I2C protocol for inter-IC communication using Verilog, designing CMOS circuits using adiabatic logic, implementing an elevator control system using a state machine in VHDL, and designing basic digital components like counters, RAM, adders and ALUs in Verilog/VHDL. The document provides a brief description of each project and estimates

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    List of projects on VLSI

    1.Improvement of the Orthogonal Code Convolution


    Capabilities Using FPGA Implementation.
    (VHDL/VERILOG) (includes report, presentation,
    synopsys) Rs 6000-7000
    When data is stored, compressed, or communicated through a media such as cable or air, sources of
    noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability
    of these data. Error detection and correction techniques are therefore required. Orthogonal Code is
    one of the codes that can detect errors and correct corrupted data. An n-bit orthogonal code has n/2 1s
    and n/2 0s. In a previous work these properties have been exploited to detect
    and correct errors. In this project we present a new methodology to enhance error detection
    capabilities of the orthogonal code. The technique was implemented experimentally using Field
    Programmable Gate Arrays (FPGA). The results show that the proposed technique improves the
    detection capabilities of the orthogonal code by approximately 50%, resulting in 99.9% error
    detection, and corrects as predicted up to (n/4-1) bits of error in the received impaired code with
    bandwidth efficiency.

    2. Implementation of power efficient


    convolution codes encoder decoder on
    VHDL (Generation and decoding by
    MLD,Viterbi algorithm). includes report, presentation,
    synopsys ) Rs 9,000-10,000
    The objective of this project is to design a convolutional code encoder and
    decoder using vhdl,also to show the benefits of using convolutional code and
    viterbi algorithm and their error correcting capabilities.
    A convolutional code is a type of error-correcting code in which

    each m-bit information symbol (each m-bit string) to be encoded is transformed into
    an n-bit symbol, where m/n is the code rate (n m) and

    the transformation is a function of the last k information symbols, where k is the


    constraint length of the code.
    The Viterbi algorithm is a dynamic programming algorithm for finding the
    most likely sequence of hidden states called the Viterbi path.

    3. 16 bit Microprocessor design using VHDL. With


    memory interface :- (includes material) Rs-4000-5000
    4. Implementation of I2C Protocol using VERILOG HDL.
    (includes ppt and material) Rs 8,000-9,000.
    Its a inter ic communication protocol works on two wires only, reducing the number of
    connections and is widely used in microcontrollers, mobile etc, one master and upto 8 slaves
    are implemented.

    5. CMOS Circuit Designing using Adiabatic Logic (with


    material):- Rs (4000-5000)
    designing of different gates and full adder using adiabatic logics (low power consumption
    than conventional circuits) on 0.35 um technology simulation with HSPICE.

    6. Elevator control chip using State machine


    implementation on VHDL. Rs (3000)
    Describes how different floors can be used as states and their circuitry can
    be implemented on a single chip.

    7.Jhonson Counter,LFSR,Ring
    counters,single/dual port RAM,full
    adder,ALU,Ripple counter in VERILOG/VHDL
    (RS 3000).

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