4468 20 Zynq Architecture
4468 20 Zynq Architecture
4468 20 Zynq Architecture
Zynq
14.2 Version
This material exempt per Department of Commerce license exception TSU
Objectives
Outline
The ARMv7 ISA includes the following types of instructions (for backwards
compatibility)
Thumb instructions: 16 bits; Thumb-2 instructions: 32 bits
NEON: ARMs Single Instruction Multiple Data (SIMD) instructions
Outline
Speculative execution
Supports virtual renaming of ARM physical registers to remove pipeline stalls due to data
dependencies
Increased processor utilization and hiding of memory latencies
Increased performance by hardware unrolling of code loops
Reduced interrupt latency via speculative entry to Interrupt Service Routine (ISR)
PS Components
Memory interfaces
PS interconnect
DMA
Timers
Public and private
Central interconnect
Enables other interconnects to
communicate
Peripheral master
USB, GigE, SDIO connects to DDR and PL
via the central interconnect
Peripheral slave
CPU, DMA, and PL access to IOP
peripherals
Memory Map
PS Boots First
CPU0 boots from OCM ROM; CPU1 goes into a sleep state
On-chip boot loader in OCM ROM (Stage 0 boot)
Processor loads First Stage Boot Loader (FSBL) from external flash memory
NOR
NAND
Quad-SPI
SD Card
JTAG; not a memory deviceused for development/debug only
Boot source selected via package bootstrapping pins
Optional secure boot mode allows the loading of encrypted software from the flash boot
memory
Configuring the PL
Outline
Input/Output Peripherals
Two GigE
Two USB
Two SPI
Two SD/SDIO
Two CAN
Two I2C
Two UART
Four 32-bit GPIOs
Static memories
NAND, NOR/SRAM, Quad SPI
Trace ports
PS-PL Interfaces
PS-PL Interfaces
One 64-bit accelerator coherence port (ACP) AXI slave interface to CPU memory
DMA, interrupts, events signals
Processor event bus for signaling event information to the CPU
PL peripheral IP interrupts to the PS general interrupt controller (GIC)
Four DMA channel RDY/ACK signals
Extended multiplexed I/O (EMIO) allows PS peripheral ports access to PL logic and
device I/O pins
Clock and resets
Four PS clock outputs to the PL with enable control
Four PS reset outputs to the PL
Outline
PL Clocking Sources
PS clocks
PS clock source from external package pin
PS has three PLLs for clock generation
PS has four clock ports to PL
Synchronizing the clock between PL and PS is taken care of by the architecture of the
PS
PL cannot supply clock source to PS
Clocking the PL
Zynq Resets
Internal resets
Power-on reset (POR)
Watchdog resets from the three watchdog timers
Secure violation reset
PS resets
External reset: PS_SRST_B
Warm reset: SRSTB
PL resets
Four reset outputs from PS to PL
FCLK_RESET[3:0]
Outline
AMBA
AMBA 3.0
APB
AXI
AHB
Older
Performance
Newer
(2003)
AHB
AXI
ATB
AMBA 3.0
(2003)
Same Spec
AXI-4
Memory Map
Interface
AXI-4
Stream
AMBA 4.0
AXI-4
Lite
(2010)
Features
Traditional Address/Data Burst
Similar to
Streaming
Data-Only, Burst
Lite
PLBv46-single
(AXI4-Lite)
OPB
(AXI4-Stream)
PLBv46, PCI
No burst
Data width 32 or 64 only
AXI4-Lite Read
AXI4-Lite Write
AXI4 Read
1024 bits
AXI4-Stream Transfer
Streaming Applications
Outline
Summary
I/O peripherals
External memory interfaces
Summary
Tightly coupled AXI ports interface the PL and PS for maximum performance
The PS boots from a selection of external memory devices
The PL is configured by and after the PS boots
The PS provides clocking resources to the PL
The PL may not provide clocking to the PS
Zynq Architecture 12-40