ICCAS2005

June 2 -5, KINTEX, Gyeonggi-Do, Korea

Design of Programmable Logic Controller and I/O Expansions

Suphan Gulpanich, Ajin Numsomran, Prapas Roengruen, Viriya Kongratana
and Kitti Tirasesth
*Department of Instrumentation Engineering , Faculty of Engineering.
Kings Mongkut Institute of Technology Ladkrabang , 10520 Bangkok , Thailand.
(Tel : 66-2739-2407 Ext 110 E-mail: [email protected])
Abstract. This paper presents a design of Programmable logic Controllers which are well known for a long time that can be
applied to be a controller for an automatic machine in industries. However, most of them have been imported from oversea
country. This research focuses on the development of PLC by KMITL staff. This PLC system is consists of CPU unit, Digital I/O
RTU unit, ANALOG RTU unit. The implementation of the CPU scan time and I/O refresh are principle to PLC. In this article,
there are many benefits to industries especially in order to support SME that can use local technology. Therefore, we can apply this
research to the manufacturing process in Thailand for the future.
Keywords: PLC, RTU, Scan time

1. INTRODUCTION
Programmable Logic Controller in Thailand has been
applied commonly around year 1985 King Mongkut's Institute
of Technology, Chaokhuntaharn Ladkrabang (KMITL),
Instrumentation Engineering Department get some supports
from UNDP. (UNITED NATIONS DEVELOPMENT
PROGRAM) for 2 years in sponsoring Thai lecturers aboard
to learn technology in Europe and sending consultants to the
institute. During the beginning period, PLC laboratory is one
the laboratory that get funding from UNDP. in this project.
Most equipments, especially PLC, were imported. The
department realized this importance, so this research was
initiated. The development has been continued, sometimes has
some difficulty the causes delayed project. However, the
attempt make this project success in 1990, from that period,
there are some improvements, tests continuously until now.
The development will focus on the research that can serve
local needs for small industries and study test kits. So the
HARD WARE will be designed to served industries objectives

series Z84C11 which is 100 pin CPU, the input/output ports

can be connected to external devices 4 ports and serial
communication 2 ports, speed of crystal 10 MHz. 32 Kbytes
ROM is an operating system (OS). 32 Kbytes RAM is user
program and executed memory. All of systems are designed to
meet local industry objectives. There are various sizes of IO
matched with machines, so its economical in order to support
small and medium industries.

This research will describe that designed PLC

structure consists of base units, remote terminal units,
memory maps, instruction command and Operating
System as well as system testing
2. PLC STRUCTURE
PLC structure consists of parts that can be put in diagram in
fig.1
1. Central processing units (CPU)
2. Input/output units
3. Remote terminal units (RTU)
2.1 Central Processing Unit
Central Processing Unit or base unit is designed by
microprocessor. Its function is to control process by receiving
input status from device, computing program according to
written program and sending the computed result to output
device that operated by Operating System. Input will get
status from push button switch, sensor from machine. For
the PLC command, there are many command groups e.g. logic,
movement, arithmetic, timer/counter commands etc
this
research report is designed by microprocessor 8 bits/ 16 bits

fig. 1 PLC Structure

2.2 Input/output Units
Input/output units are built in Base Unit, Input terminal is
connected to input devices in fig.2, e.g. proximity switch are
used for non-contact object detection. They integrate a sensing
element and a transistor NPN switch output which connected
to DC. Voltage Digital sink input circuit of PLC.(1)

Output terminal is connected to output devices in

fig.3, it shows a typical opto-isolated NPN transistor
switch output circuit.

ICCAS2005

June 2 -5, KINTEX, Gyeonggi-Do, Korea

memory is determined again by the design of the unit.
However, all PLC memories can be subdivided into at least
five major areas. A typical memory utilization map for a PLC
is depicted in table 1.

Fig.2 DC. Voltage Digital sink input circuit

Fig.3 DC. Voltage Digital NPN transistor output circuit

2.3 Remote terminal Units (RTU)
Remote terminal units are distributed through network
device group, centralized by PLC control and communicated
with similar protocol through serial bus in IEC fieldbus RS485
standards. These networks, often referred to as data
highways, utilize twisted shielded-pair to carry high speed.
Communications data between the various Controller and
RTUs microprocessor - based devices connected to the
network. The RTU network devices consisted of three models,
Remote terminal Input 16 (RTI16), Remote terminal output 16
(RTO16) and Remote terminal AD/DA (RTAD). The number
of RTUs that can connected to data highway network varies
with the network design. The maximum of modules are able to
expand to 32 units. RTU designed by microcontroller MSC51
is CPU that operated with Crystal frequency 11.0592 MHz.
RAM size 4 Kbytes, ROM size 256 bytes. Max 192 A/D chip
support 10 bits 8 channel and 2 Chips 0800 D/A 8bits 1
channel depict fig.4

Table1 CPU memory

Memory
Executive Memory
User Memory
System Memory
Data Memory
I/O Status Memory
Stack Memory

Address Range(Hex)
0000-7FFFh
8000-9C00h
9C01-F100h
F101-FF00h

Size
32 K
7K
21K
3.9K

FF01-FFFFh

256byte

3.1 Operating system

Operating system or executive memory for the PLC is
always placed in ROM since, once developed, it rarely needs
changing. The executive of a PLC performs several functions.
It is the one that actually does the Scanning in a PLC. The
PLC user programs the PLC in high-level language composed
of relay symbols. These symbols are stored in the user portion
of the memory in binary format. The executive causes the
microprocessor to examine each user instruction, then
instructs the microprocessor through the actual conversion of
the high-level instruction into its equivalent series of machine
language instruction for further action by the microprocessor.
Often a user program will contain instructions that require data
from other areas of the memory. In this case the executive
programming must instruct the microprocessor to gather these
data along with the proper machine language for further use
by the microprocessor
3.2 I/O memory
Its the memory that can be referred to I/O statuses in order
to connect with I/O devices. Whenever the executive program
instructs the microprocessor to read the current statuses of the
inputs to the PLC, it stores this information in the input status
or image area. As the executive instructs the microprocessor to
scan the user program and interpret the user commands,
various output device statuses are generated. These output
states and conditions are stored by the microprocessor in the
output status or image area until the end of the logic scan
when the output modules get updated to this previously stored
information. These status areas of memory are always
available for user monitoring and use
3.3 System memory
This memory is reserved for program data manipulation.
When timers, counters, math, and/or data functions are
available, an area of memory must be set aside for data storage.
The data storage portion of memory is allocated for storage of
such items as timer or counter preset and accumulated values,
math instruction data and results, and miscellaneous data and
information which will be sued by any data manipulation
functions programmed in the user memory area Its placed in
RAM.

fig.4 :block diagram of RTU units

3. PLC MEMORY ARCHITECTURE(2)

All PLCs contain both RAM and ROM in varying amounts
depending upon the design of the PLC. The use of PLCs

3.4 User memory.

This memory is allocated to the storage of the user program.
It is the memory area that the executive program instructs the
microprocessor to examine or scan to find the user
instructions. The user program are may be subdivided if the
processor allocates a portion of this memory area for the
storage of ASCII messages, subroutine programs, or other
special programming functions or routines. Its placed in RAM

ICCAS2005

June 2 -5, KINTEX, Gyeonggi-Do, Korea

3.5 Stack memory

This memory is served for storage of stack pointer index in
order to execute in subroutine program. Its placed in RAM.
Table2 PLC visual memory
Area
Size
Digital Input
32 bits
Digital Output
16 bits
Remote Digital Input
16 bits
Remote Digital Output 16 bits
Remote Analog
4Ch.ADC
Input/Output
2Ch.DAC
Internal Relay
1,120 bits
Holding Relay
1,600 bits
Link Relay
1,024 bits
Timer
512 Points
Counter
512 Points

Range(word)
000-001
007
00-15
00-15
00-15
008-0078
HR00-HR99
LR00-LR63
T000-T511
C000-C511

B3

ROR(28)

Table7 BCD Calculation

CodeNo.
C0
C1
C2
C3

Statement1
ADD(30)
SUB(31)
MUL(32)
DIV(33)

Word

--

--

instruction code assignment

Statement2
Source
Source
Source
Source

Statement3
Add
Su
Mu
Dv

Statement4
Result
Result
Result
Result

Table8 Remote I/O instruction code assignment

CodeNo.
D0
D1

Statement1
RDI(70)
WRO(71)

Statement2
#Unit No.
#Unit No.

Statement3
Source
Destination

Statement4
---

Example of programs in operating system that write for

microprocessor to operate according to Subroutine LD, LD
NOT, OUT and OUT NOT are followings
Instruction routine procedure

Table2 is classified and adapted from table 1 by OS. developer.

Objectives of this re-classification is easy to use. The memory
in table 2 is called Visual Memory
4.

COMMAND AND INTERPRETER

These are important parts of operating systems. They

cause the microprocessor to examine each user instruction,
then instructs the microprocessor through the actual
conversion of the high-level instruction into its equivalent
series of machine language instruction for further action by the
microprocessor. User instruction in PLC designs memory
units to RECORD. There are 2 fields in the record, the
first one is code number (instruction code), the second one is
statement as following table 3
Table 3 interpreter record
Record No.
Code No.
Statement
Record format
Record of code command
Code Number :1 Byte;
Statement : 4 By te;
End.

0001

Code1

Statement A

0002

Code2

Statement B

0003

Code3

Statement C

End record

Code

Statement..

There are some samples of Logic, Movement ,Arithmetic

Shift , BCD Calculation and Remote I/O instruction code
assignments, refer to table 4 to 8 respectively
Table4 Sample of Logic instruction code assignment
Code No. Statement
Code No. Statement
80
82
84
86
88
8A

LD
LD HR
LD LR
AND
AND HR
AND LR

81
83
85
87
89
8B

Procedure LD command
Subroutine LD_SUB;
Begin
Result:=Datatable (IOassign);
IF Result>0 then
Result:=$FF else
Result:=$00;
Push result to stack;
End;
Procedure OUT command
Subroutine OUT_SUB;
Begin
Pop result from stack;
Data table(IOassign) :=
Result;
Push result to stack;
End;

Procedure LD NOT command

Subroutine LD NOT_SUB;
Begin
LD_SUB(IOassign);
Pop result from stack;
Complement result;
Push result to stack;
End
Procedure OUT NOT command
Subroutine OUT NOT_SUB;
Begin
Pop result from stack;
Data table(IOassign) :=
Result;
Complement result;
Push result to stack;
End;

5. HARDWARE CONFIGULATION
Hardware configuration are consisted of CPU
Unit(84PROsf) ,RTU1(RTI16) 16 bits digital input / station
#00 and RTU2(RTO16) 16 bits digital output /station #01 as
depicted in fig. 5
In one scan time of PLC, starting from reading input status
from RTI16, manipulate data or condition according to user
program, then update output data to RTO16, the end of scan
time depicted in fig. 6

LD NOT
LD NOT HR
LD NOT LR
AND NOT
AND NOT HR
AND NOT LR

Table5 Movement instruction code assignment

CodeNo.
A0
A1
A2

Statement1
MOV(21)
MVN(22)
MOVD(83)

Statement2
Source
Source
Source

Table6 Arithmetic Shift

CodeNo.
B0
B1
B2

Statement1
ASL(25)
ASR(26)
ROL(27)

Statement3
Destination
Destination
Designation

Statement4
--Destination

instruction code assignment

Statement2
Word
Word
Word

Statement3
----

Statement4
----

Fig. 5 CPU and Remote I/O Expansion Unit

ICCAS2005

June 2 -5, KINTEX, Gyeonggi-Do, Korea

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Fig. 6 I/O Respond time diagram

The overall flow of PLC operation is as shown in the
following flowchart depicted in fig. 7 [3]

Fig.8 scan time measuring by oscilloscope

Testing procedures consisted of 3 tests as followings

Case test 1,2

One CPU Unit
Read input then compute Read input then compute and
write to output
and write to output

Program1
Ladder program I/P and O/P
Program2
Ladder program logic 20 INS.

Ch.1
Ch.2
Input signal output signal
delay time
4 msec.
? msec.
Fig. 7 Operation flow chart in one scan time of PLC

6. IMPLEMENTATION
Response to system in term of PLC scan time is very
important. The PLC that have fast scan time can response to
the system effectively. This test can measure scan time by
using oscilloscope. Testing procedure can be done by pulse
signal input at PLC from pulse generator. Range of pulse
generator is 1to10 KHz in order to be input signal simulator,
then ladder programming to operate test program and write
data to output. The oscilloscope has 2 channels, channel 1 and
2, measuring signal from input and output of PLC respectively,
as depicted in fig.8

Ch.1
Input signal
4 msec.

Ch.2
output signal
delay time
? msec.

These tests are used for measuring scanned time of CPU

Unit, the processes are as followings
1. Input signal from pulse generator to PLC input
address 0000
2. Probe for measuring input signal address 0000 and
output signal address 0700 of PLC by Oscilloscope
(OSC) in channel 1 and 2 respectively
3. Write the ladder program1 to PLC and selected
switch to run mode.
From result of case test 1, The PLC is able to respond
pulsed input signal 250 Hz or 4 mSec. and output signal delay
time is 0.25 mSec. In case test 2, The processes are similar to
case test1 but rewrite the ladder program2 to PLC. In ladder
program2, there are 20 logic instructions. The PLC is able to
respond pulsed signal input 250 Hz or 4 mSec. and output
signal delay time is 0.5 mSec. When compare output delay
times of these two tests, the output delay time of case test 1 is
shorter than case test2s 0.25 mSec. in execution of 20
instructions.

ICCAS2005

June 2 -5, KINTEX, Gyeonggi-Do, Korea

Case Test 3
CPU +RTI16+RTO16 Unit

Ch.1
Input signal
Program3
Ladder program and
RDI&WRO command

100msec.

Ch.2
output signal
delay time
10 msec.

This test consists of CPU Unit , RTI16 and RTO16,

measures scanned time. The processes are as followings
1. Input signal from pulse generator to RTI16 address
0800,
2. Probe for measuring input signal RTI16 address
0800 and output signal RTO16 address 0900 by
Oscilloscope(OSC) in channel 1 and 2 respectively
3. Write the ladder program3 to PLC and selected
switch to run mode.
From result of case test 3, The PLC is able to respond
pulsed input signal 10 Hz or 100 mSec. and output signal
delay time is 10 mSec. So the input respond time is relatively
long since most time spending to communicate data.

CONCLUSION
Even result of PLC research can response to scanned time
speed not as fast as imported PLC, its meet the departments
objective that to depend on our own local technology in order
to serve local need in small and medium industries.
In
testing, the department cooperates with private organization to
research and testing by installing with various machines e.g.
Screen painting machine of plastic can filling color and oil,
small paper cutting machine, KFC. sauce pack filling machine,
Reverse Osmosis water production rate 5,000 lits/day for ice
industry etc. The testing result is good at one level and will
be developed to higher efficacy and better capacity in the
future
REFERENCES
(1) Alan J.Crispin, Programmable Logic Controller and
their Engineering Application, Second Edition, the
McGraw-Hill Companies.1997.
(2) Robert E.Wilhelm,JR. Programmable Controller

Handbook , Copyright.1985
(3) SYSMAC CQM1/CPM1Programmable Controllers
Programming Manual , OMRON,Revised June 1998