Ultra-Low-Power Adiabatic Flip-flops and Sequential

Circuits Using Three-phase AC Power Supply

Hu Jianping, Wu Yangbo, and Li Hong
Faculty of Information Science and Technology,Nmgbo University, Ningbo 3 15211, P.R. CHINA
Email: nhhjp@yaboo,com.cn

Abstract
We propose a new dual transmission gate adiabatic logic
(DTGAL) for ultra-low-power design, whch is driven by
three-phase AC power supply. DTGAL has more
efficient energy transfer and recovery, because it hasn't
the non-adiabatic energy loss. We also discuss the
design of adiabatic sequential circuits. For the
energy-efficient design, we explained how to design an
adiabatic D flip-flop with DTGAL A. practical
sequential svsteiii was designed and demonstrated using
MOSIS 0.2Spm CMOS process pavameters. SPICE
simulation results show that the adiabatic flip-flop
based on DTGAL is 3 to 4.5 times more energy
efficient than 2N-2N2P for clock rates ranging from
50 to ZOOMhz. In conclusion, DTGAL has better
energy saving advantage, and adiabatic D flip-flop based
on DTGAL is suitable for the applications in the
low-power sequential system
Key words: VLSI design, Low-power, Adiabatic logic,
Flip-flop, Sequential circuit

lntroductiou
The power dissipation is a critical concem in the design
of VLSI circuits, especially in the po,mble and
battery-operated ASIC systems. Adiabatic circuits (or
energy-recovery logic circuits), which utilize ac power
supplies to recycle the energy of node capacitances, is an
attractive way to obtain low power level whch
conventional CMOS circuit can't reach.
The current adiabatic circuits can be classified into two
types: full-adiabatic logic and quasi-adiabatic logic. The
full-adiabatic circuits, the non-adiabatic loss of wluch is
eliminated completely by using reversible logic, are
much more complex than quasi-adiabatic circuits. For
example, the complexity of a 16-bit cany-lookahead
adder (CLA) in a fully reversible manner is about 32
times that of static CMOS CLA [l]. Quasi-adiabatic
logic circuits, such as SCAL, ECRL, and ZN-ZNZP etc,
have simple architecture and power clock system [2-61.
The typical adiabatic logic, such as the 2N-2N2P as

showed in Fig. 1, uses cross-coupled PMOS transistors

for energy-recovery [SI.Although they consume. lower
power than the conventional CMOS, the charge of output
loads can't be completely recovered, and their energy
loss is highly dependent on the output load capacitance.

Fig. 1 2N-2N2P inverter, inverter chain, and power clock

. ,

At present, studies on adiabatic computing have been

grown for some applications such as CLA, ALU, and
processor. However, we can't build adiabatic sequential
circuits by simply using conventional method. In Fig.1,
the output signal of the inverter is fixedly set to OV
When 4 falls from the peak voltage to ground. In this
way, a signal can never be,stored.

On the foundation of the past studies, we propose a dual

transmission gate adiabatic logic (DTGAL), which uses
transmission gates for evaluation and energy-recovery,
to realize utmost-low-power design. Finally, t h s paper
also explores the design of adiabatic synchronous
sequential circuits, which adopt the D flip-flop with
three-phase AC power supply.
Operation of DTGAL and adiabatic flip-flop
The basic DTGAL inverter (buffer) is illustrated in
Fig.Z(a). It is composed of two main parts: the logic
evaluation and energy-iecovery circuit. The logic
evaluation circuit consists of transmission gates (NI,PI)
and (Nib.P2). The energy-recovery circuit consists of
transmission gates (NI, PI) and (N2, PI). The

0-7803-7889-X/03/$17.00@2003 IEEE.

1209

.. P

cross-coupled transistors (N3 and N4) make the undriven

output node grounded. The power-clock dcharges the
output OCT (or OD'T ) through N, and PI (or Nib and
). The energy of output
P!) by the inputs ( IlV and
nodes is recovered to 9 through N, and PI (or N2 and
P2)by the inputs (FZN and FIN ), which are from the
output of nest-stage buffer.

'

(a) Schematic of DTGAL

6,
D

(b) Adiabatic,D flip-flop using three-phase power clock

-6,
-D

Fig.Z(c) illustrates The SPICE simulation results using

MOSIS 0.25 P ni CMOS process. These simulation
results were obtained when the input D = ' I 1010.'"'. The
frequency of the power-clock is IOOMHz, and the peak
voltage PbDis 2.5V. The nh4OS transistors are all of size
W'/L = 3 A /2 A , and PMOS transistors are all of size W/L
=hA/?X,\vith A=0.12~111.

3
-1

z,

output out? of the second-stage

DTGAL buffer is PbDand NI is tumed on. When fall
from the peak voltage to. ground, the charge on the node
mill is recovered through N, and P, in the full-adiabatic
nianner. The siinilar discussion can be made for the
second-stage and third-stage DTGAL buffers with
power-clock 4* and b3.The ZN-ZNZP buffer in Fig.Z(b)
is driven by @I> and it uses only two cross-coupled
pMOS transistors both for precharge and recover, thus it
has non-adiabatic loss in the outputs( FQ a n d m ) [ j ] .
fdr the

...... ......

'

iin

.....E

+________
..'_.....,._
.., --Fe .....

-I-+k.+$-------I I :'I
I
in0

at ground. During

To establish complex systems, such as D flip-flop, an

inverter (huffer) chain driven by three-phase power-clock
is shown in Fig.2 (b). In Fig.2 (h), the upper buffers are
first-stage, second-stage, and third-stage DTGAL one,
respecti\,ely from left to right. The lower buffer is a
2N-ZN2P one, and its outputs FQ and
control
energyrecovery of the third-stage DTGAL buffer. A
clocking mle must be followed to form a chain of logic
circuits: Each clock is followed by the next clock with a
120" phase lag. The three-phase power clock can be
sinusoidal wavefomis. They can be obtained from an
efficient single-inductor LC oscillator [ 7 ] . For
convenience, we use trapezoidal wavefomis to analyze
the operation of the DTGAL.

We first discuss the working process of the first-stage

DTGAL buffer by referring the schematic shown in
Fig.2ja) and the waveforms in Fig.2(c). During the time
intend f, and t2, the input D goes hgh and Ni is tumed
o n During I,. as the clock 9 ,go up, the voltage of the
node mf,go high via N
i hv the rising 4,. When the
rises above l,+p, Pi will he tumed o n , so the node out,
is charged through transmission gate (Ni, PI) without
non-adiabatic loss, and the fully-swing is obtained.
During l4 and 15; thc node ouf,is IfDD, and
is still

FIN

120

130

Time (ns)

(c) Siinulation wavefonns of adiabatic D flip-flop

Fig. 2 DTGAL buffer and adiabatic flip-flop
The simulation wavefomis of Fig.2(c) show that the
output of each DTGAL buffer is followed by the input
with a 120' phase lag. The input D is just shifted to the
output terminal 0 through three-stage DTGAL chain by
one clock period, i.e. one-bit shifting. Thus the function
ofFig.2 (b) is corresponding to a traditionalD flip-flop.

'

Energy dissipation

The energy dissipation of logic circuits is compared in

this section. The energy loss per cycle in ZN-ZNZP is [j]
%N",lN.,,,

c ~ r c , , v &+C,,VA

= 2R,CIO,

(1)

where C
,I
is the load capacitance of the 2N-2N2P, Rp is
the lum-on resistance of PMOS, T is the transition time

1210

of the power-clock, and P;p is the threshold of PMOS. In

Eq. (1); the first tenn represents the full-adiabatic energy
loss, and the second tenn represents the non-adiabatic
energy loss. The adiabatic D flip-flop based on 2N-2N2P,
as shown in Fig.1, consists of three-stage 2N-2N2P
buffers, thus its energy loss per cycle is
E m w w-

ZR V'
~

DD

(c;+c;+Cb)+(C, +c,+C&

dissipative than the static D flip-flop, assuming a

100% energy-efficient power-clock generator,

(2)

where C,, C?and CQare separately the capacitance of the

nodes oifij, out?, and Q shown in Fig.1. Because the
operation of the DTGAL buffer on output loads is a
full-adiabatic process, its energy dissipation per cycle
can be witten as

(3)

Lvhere CLis the load capacitance of the DTGAL, R is the

tum-on resistance of transniission gate (N;, PI) or (NI,
P?). Energy dissipntion of the DTGAL is lowered
significantly; because it hasn't non-adiabatic loss. If the
transition time T is much greater than RCL, the energy
loss is almost zero. The adiabatic D flip-flop based on
DTGAL consists of three-stage DTGAL buffers and one
2N-2N2P buffer, thus its energy loss per cycle can be
uTitten as
E,Dm

= 2R1,;D ( C j + C j
~

0.2

Interconnection capacitance at output node (e)

ZRC

= (++CLG
T

E,.

2
+0.4

+C;)+%c;,+c'

Fig. 3 Energy loss coiuparison of adiabatic flip-flop

Adiabatic synchronous sequential circuit

' Based on the adiabatic D flip-flop, coniplex sequential

circuits can be designed. We have design an adiabatic
BCD code upcounter. It consists of four flip-flops and
the cany circuit, as shown in Fig.4 (a).

m,

4,

6,
I

?I

w v?
r p [4)

where C,; C2;CQ and Cpuare separately the capacitance

ofthe nodes m f , , mi2,0; and FQ shown in Fig.l(b).

Fig. 3 illustrates the SPICE siinulation results of energy

consumption comparison of adiabatic D flip-flop based
on DTGAL and 2N-2N2P circuits. We used the sues of
lV1L =0.36 P in 10.24 P ni for nMOS transistor and W/L =
0.72 P in 10.24 P in for pMOS transistor in all circuits It
is obvious that the energv dissipation of adiabatic
flip-flop based on DTGAL is much lower than 2N-2N2P,
especially when driving the large load capacitance in the
output temiinal Q. Compared to 2N-2N2P. the DTGAL
dissipates less energy at all operation frequencies and is
insensitivity to power-clock frequency. We have also
simulated the conventional static D flip-flop adopting
DC power supply using the same process parameter and
transistor size, and the energy consumption' of the
adiabatic D flip-flop has been compared with static D
flip-flop. The static D flip-flop consists offour CMOS
transiuissioll gate's and five invelters [SI. F~~clock rates
ranging from 50 to ZOOMhz, the adiabatic flip-flop
based on DTGAL is 3 to 4.5 times more energy
efficient than 2N-2N2P and 4.5 to 9 times less

Fig.4 (a) Adiabatic 8421 BCD code up-counter using

three-phase

121 1

power

Conclusion

We have proposed a new dual transmission gate adiabatic

logic using three-phase AC power supply. The energy
dissipation of the adiabatic D flip-flop based on DTGAL
is very low. Moreover, this paper also explores the
design of adiabatic sequential circuits. Currently, we
are designing several complex circuits with DTGAL and
simulating them with parameters extracted from layout.
Fuiher study on how to design an efficient power-clock
generator is required.

Acknowledgments
91

m:

This project is supported by Scientific Research Fund of

Zhejiang Provincial Education Department (No.
20010238) and Ningbo Scientific Research Key
ResearchFunds (No. OlJ20100-I).
References

Fig.4 (b) DTGAL logic cells in Adiabatic counter

2.5

0
2.5
0

2.5
0
2.5
0

2.5
0
0

10

20

30

40 50 60 70
lim IW

80 90 100.110

FIG. 4(c) Simulation for output waveform of Adiabatic

8421 BCD code up-counter

In Fig.4 (a), each flip-flop consists of three-stage

DTGAL and one 2N-2N2P inverter, and the first-stage
DTGAL is used to realize the combinatorial logic
function. The transition function of each flip-flop can
he expressed as: Q;=Q, ; Q; = ( Q , ~ Q , Q , ;

.e,)W,

Q1 = tQ,
; Q; = tQ, -Q,M
+Q,Q. . Therefore,
this is an 8421 BCD,code up-counter. The first-stage
DTGAL logic cells can be realized by using nMOS
function blocks to replace the input nMOS 0.r; and Nib)
ofthe DTGAL buffer, and they are shown in Fig. 4@).
The simulation results for the output waveform of the
adiabatic counter are shown in Fig. 4(c).

1212

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