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    Ecen 248 Prelab 5

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    Rebecca Sontheimer
    This document contains information for an upcoming lab: 1) It discusses overflow detection in an addition/subtraction circuit and provides a truth table and minimized expression for a 1-bit 2:1 multiplexer. 2) It includes gate-level schematics for an addition/subtraction unit, 1-bit and 4-bit 2:1 multiplexers, and a final ALU design. 3) It lists the operations of a multiplexer within an ALU and suggests a design modification.

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    Ecen 248 Prelab 5

    Uploaded by

    Rebecca Sontheimer
    984 views3 pages
    This document contains information for an upcoming lab: 1) It discusses overflow detection in an addition/subtraction circuit and provides a truth table and minimized expression for a 1-bit 2:1 multiplexer. 2) It includes gate-level schematics for an addition/subtraction unit, 1-bit and 4-bit 2:1 multiplexers, and a final ALU design. 3) It lists the operations of a multiplexer within an ALU and suggests a design modification.

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    tamu ecen 248 lab report

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    This document contains information for an upcoming lab: 1) It discusses overflow detection in an addition/subtraction circuit and provides a truth table and minimized expression for a 1-bit 2:1 multiplexer. 2) It includes gate-level schematics for an addition/subtraction unit, 1-bit and 4-bit 2:1 multiplexers, and a final ALU design. 3) It lists the operations of a multiplexer within an ALU and suggests a design modification.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    984 views3 pages

    Ecen 248 Prelab 5

    Uploaded by

    Rebecca Sontheimer
    This document contains information for an upcoming lab: 1) It discusses overflow detection in an addition/subtraction circuit and provides a truth table and minimized expression for a 1-bit 2:1 multiplexer. 2) It includes gate-level schematics for an addition/subtraction unit, 1-bit and 4-bit 2:1 multiplexers, and a final ALU design. 3) It lists the operations of a multiplexer within an ALU and suggests a design modification.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    Rebecca Sontheimer

    ECEN 248-511
    Pre-lab: Lab 5
    1. Examples demonstrating how the circuit in Figure 5 adds and subtracts and how
    the overflow detection circuit works.
    2. Truth table and minimized boolean expression for a 1-bit wide, 2:1 multiplexer.
    Truth Table for 2:1 Multiplexor:
    S
    A
    B
    F
    0
    0
    0
    0
    0
    0
    1
    0
    0
    1
    0
    1
    0
    1
    1
    1
    1
    0
    0
    0
    1
    0
    1
    1
    1
    1
    0
    0
    1
    1
    1
    1
    K-Map for 2:1 Multiplexor:
    AB\S
    00
    01
    11
    10

    0
    0
    0
    1
    1

    1
    0
    1
    1
    0

    Minimized expression:
    F = S * A + S * B
    3. Gate-level schematics for the Addition/Subtraction unit, 1-bit and 4-bit 2:1
    multiplexers, and final ALU design.
    1-bit 2:1 MUX

    4-bit addition/subtraction circuit

    Rebecca Sontheimer
    ECEN 248-511

    4-bit 2:1 MUX

    Final ALU design

    Rebecca Sontheimer
    ECEN 248-511

    4. Table of ALU operations and suggested design modification.


    Operations of the MUX within the ALU:
    c0 c1 Op
    0 0 Add
    0 1 Sub
    1 0 AND
    1 1 AND

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