74AC11032

QUADRUPLE 2-INPUT POSITIVE-OR GATE

SCAS007C JULY 1987 REVISED APRIL 1996

D
D
D
D

D, DB, OR N PACKAGE
(TOP VIEW)

Center-Pin VCC and GND Configurations

Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at
125C
Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, and Standard Plastic
300-mil DIPs (N)

1A
1Y
2Y
GND
GND
3Y
4Y
4B

16

15

14

13

12

11

10

1B
2A
2B
VCC
VCC
3A
3B
4A

description
This device contains four independent 2-input OR gates. It performs the Boolean function
Y

+ A ) B or Y + A B

in positive logic.

The 74AC11032 is characterized for operation from 40C to 85C.

FUNCTION TABLE
(each gate)
INPUTS
A

OUTPUT
Y

logic symbol
1A
1B
2A
2B
3A
3B
4A
4B

1
16

1Y

15
3

14

2Y

11
6

10

3Y

9
7

4Y

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C JULY 1987 REVISED APRIL 1996

logic diagram (positive logic)

1A
1B
2A
2B
3A
3B
4A
4B

16
15
14
11

10
9
8

1Y

2Y

3Y

4Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Maximum power dissipation at TA = 55C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W
DB package . . . . . . . . . . . . . . . . . . 0.55 W
N package . . . . . . . . . . . . . . . . . . . . 1.1 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.

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74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C JULY 1987 REVISED APRIL 1996

recommended operating conditions

VCC

Supply voltage

VIH

High-level input voltage

VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V

MIN

NOM

MAX

5.5

0.9

VI
VO

Input voltage

Output voltage

IOH

High-level output current

t/v

Input transition rise or fall rate

TA

Operating free-air temperature

3.85

Low-level input voltage

Low-level output current

2.1
3.15

VIL

IOL

UNIT

VCC = 4.5 V
VCC = 5.5 V

1.35

1.65
VCC
VCC

VCC = 3 V
VCC = 4.5 V

V
V

4
24

VCC = 5.5 V
VCC = 3 V

24

VCC = 4.5 V
VCC = 5.5 V

24

mA

12
mA

24
0

10

ns/V

40

85

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER

TEST CONDITIONS

IOH = 50 A
VOH

MIN

3V

2.9

2.9

4.5 V

4.4

4.4

5.4

5.4

3V

2.58

2.48

4.5 V

3.94

3.8

IOH = 24
24 mA
A

5.5 V

4.94

IOH = 75 mA

5.5 V

IOL = 12 mA
IOL = 24 mA

II
ICC

TA = 25C
MIN
TYP
MAX

5.5 V
IOH = 4 mA

IOL = 50 A
VOL

VCC

MAX

UNIT

4.8
3.85

3V

0.1

0.1

4.5 V

0.1

0.1

5.5 V

0.1

0.1

3V

0.36

0.44

4.5 V

0.36

0.44

5.5 V

0.36

0.44

IOL = 75 mA

5.5 V

VI = VCC or GND
VI = VCC or GND,

5.5 V

0.1

5.5 V

40

IO = 0

Ci
VI = VCC or GND
5V
3.5
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

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1.65

pF

74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C JULY 1987 REVISED APRIL 1996

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tPLH
tPHL

A or B

MIN

TA = 25C
TYP
MAX

MIN

MAX

1.5

6.3

8.7

1.5

9.7

1.5

5.4

7.4

1.5

UNIT
ns

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tPLH
tPHL

A or B

MIN

TA = 25C
TYP
MAX

MIN

MAX

1.5

4.3

6.2

1.5

6.7

1.5

3.8

5.5

1.5

5.9

UNIT
ns

operating characteristics, VCC = 5 V, TA = 25C

PARAMETER
Cpd

TEST CONDITIONS

Power dissipation capacitance per gate

CL = 50 pF,

TYP

f = 1 MHz

24

UNIT
pF

PARAMETER MEASUREMENT INFORMATION

Input
(see Note B)

From Output
Under Test
CL = 50 pF
(see Note A)

VCC
50%

50%
0V

tPLH

tPHL

500
Output

50% VCC

VOH
50% VCC
VOL

VOLTAGE WAVEFORMS

LOAD CIRCUIT

NOTES: A. CL includes probe and jig capacitance.

B. Input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

www.ti.com

12-Jan-2006

PACKAGING INFORMATION
Orderable Device

Status (1)

Package
Type

Package
Drawing

Pins Package Eco Plan (2)

Qty

74AC11032D

ACTIVE

SOIC

16

74AC11032DBLE

OBSOLETE

SSOP

DB

16

74AC11032DBR

ACTIVE

SSOP

DB

16

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74AC11032DBRE4

ACTIVE

SSOP

DB

16

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74AC11032DE4

ACTIVE

SOIC

16

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74AC11032DR

ACTIVE

SOIC

16

2500 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74AC11032DRE4

ACTIVE

SOIC

16

2500 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74AC11032N

ACTIVE

PDIP

16

25

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

74AC11032NE4

ACTIVE

PDIP

16

25

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

74AC11032NSR

ACTIVE

SO

NS

16

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74AC11032NSRE4

ACTIVE

SO

NS

16

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

40

Green (RoHS &

no Sb/Br)
TBD

40

Lead/Ball Finish
CU NIPDAU
Call TI

MSL Peak Temp (3)

Level-1-260C-UNLIM
Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN
0,38
0,22

0,65
28

0,15 M

15

0,25
0,09
8,20
7,40

5,60
5,00

Gage Plane
1

14

0,25

08

0,95
0,55

Seating Plane
2,00 MAX

0,10

0,05 MIN

PINS **

14

16

20

24

28

30

38

A MAX

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30

DIM

4040065 /E 12/01
NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.

This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150

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