Remiting For Clockperiod Minimization

Retiming for clock period
minimization
ArunachalamV
AP SG, SENSE
Minimum feasible clock period
Minimizing the clock period of a synchronous circuit, G.
For any circuit G, the minimum feasible clock period is the
computation time of the critical path.
Mathematically the minimum feasible clock period (G), is
defined as
( ) ( ) ( ) { } 0 : max = = p w p t G
Description of W and D matrix
The algorithm finds a retiming solution r
0
such that
for any other retiming solution r.
Let W(U,V) is the minimum number of registers on any path
from node U to node V.
Let D(U,V) is the maximum computation time among all paths
from node U to node V with weight W(U,V).
( ) ( ) G G
r
s
0
( ) ( )
)
`
= V U p w V U W
p
: min ,
( ) ( ) ( )
)
`
= = ) , ( : max , V U W p w and V U p t V U D
p
Algorithm steps 1 to 3
1. Let M=t
max
.n,
t
max
= maximum computation time of the nodes in G.
n = number of nodes in G.
2. Form a new graph G which is same as G except the edge
weights are replaced by
3. Solve the all-pairs shortest path problem on G . Let be
the shortest path from U to V.
( ) ( ) ( ) V U edges all for U t e w M e w
e
= . '
'
UV
S
Algorithm step 4
4. If , then and
If , then and
is the ceiling of x, which is the smallest integer greater
than or equal to x.
V U = ( )
(
(
(
=
M
S
V U W
UV
'
,
( ) ( )
V UV
t S V U W M V U D + =
'
, . ,
V U =
( ) 0 , = V U W ( ) ( ) U t V U D = ,
(
x
An Example
Step 1
8 4 . 2
4 2
max
= =
= =
M
n and t
Step 2
( )
( )
( )
( )
( ) 7 1 1 8 1 2 '
2 2 0 8 2 4 '
2 2 0 8 2 3 '
15 1 2 8 4 1 '
7 1 1 8 3 1 '
= =
|
.
|
\
|

= =
|
.
|
\
|

= =
|
.
|
\
|

= =
|
.
|
\
|

= =
|
.
|
\
|

e
e
e
e
e
w
w
w
w
w
Step 3
Solve the all-pairs shortest path on G using Floyd-Warshall
algorithm.
For n=4,
'
UV
S
( )
(
(
(
(

=
= = =
2
2
7
15 7
4 1 ; 4 1 ; 0
1
R
to U to V k
( )
(
(
(
(

=
= = =
2
2
22 14 7
15 7
4 1 ; 4 1 ; 1
2
R
to U to V k
( )
(
(
(
(

=
= = =
20 12 2 5
20 12 2 5
22 14 7
15 7
4 1 ; 4 1 ; 2
3
R
to U to V k
( )
(
(
(
(
=
= = =
20 12 2 5
20 12 2 5
22 14 12 7
15 7 5 12
4 1 ; 4 1 ; 3
4
R
to U to V k
( ) ' 5
20 12 2 5
20 12 2 5
22 14 12 7
15 7 5 12
4 1 ; 4 1 ; 4
UV
S R
to U to V k
=
(
(
(
(
=
= = =
Step 4
( )
(
(
(
(
=
0 2 0 1
3 0 0 1
3 2 0 1
2 1 1 0
,V U W
V U = ( )
(
(
(
=
M
S
V U W
UV
'
,
V U =
( ) 0 , = V U W
(
(
(
(
=
20 12 2 5
20 12 2 5
22 14 12 7
15 7 5 12
'
UV
S
V U =
( ) ( ) ( ) V t S V U W M V U D
UV
+ =
'
, . ,
V U =
( ) ( ) U t V U D = ,
( )
(
(
(
(
=
2 6 3 4
6 2 3 4
4 4 1 2
3 3 4 1
,V U D
M=8
Constraints
If c be the desired clock to be achieved by the retiming, then
there is a feasible retiming solution r such that
This is ensured by the following constraints
1. Feasibility constraint : for every edge of G.
This forces the number of delays on each edge in the retimed graph to be non
negative
2. Critical path constraint: for all vertices U,V in
such that .
Enforces . If , then must hold for
the critical path to have computation time less than or equal to c.
( ) c G
r
s
( ) ( ) ( ) e w V r U r s
V U
e
( ) ( ) ( ) 1 , s + U r V r V U W
( ) c V U D > ,
( ) c G s ( ) ( ) ( ) 1 , s V U W V r U r ( ) c V U D > ,
Feasibility constraint
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( ) 0 2 4
0 2 3
1 1 2
2 4 1
1 3 1
s
s
s
s
s
r r
r r
r r
r r
r r
( ) ( ) ( ) e w V r U r s
Critical path constraint
( )
(
(
(
(
=
0 2 0 1
3 0 0 1
3 2 0 1
2 1 1 0
,V U W
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( ) 3 3 , 4 1 3 , 4 1 3 4
3 1 , 4 1 1 , 4 0 1 4
3 4 , 3 1 4 , 3 2 4 3
3 1 , 3 1 1 , 3 0 1 3
3 4 , 2 1 4 , 2 2 4 2
3 3 , 2 1 3 , 2 1 3 2
3 2 , 1 1 2 , 1 0 2 1
> s
> s
> s
> s
> s
> s
> s
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
( )
(
(
(
(
=
2 6 3 4
6 2 3 4
4 4 1 2
3 3 4 1
,V U D
( ) ( ) ( ) ( ) c V U D for V U W V r U r > s , 1 ,
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( ) 0 2 4
0 2 3
1 1 2
2 4 1
1 3 1
s
s
s
s
s
r r
r r
r r
r r
r r
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( ) 1 3 4
0 1 4
2 4 3
0 1 3
2 4 2
1 3 2
0 2 1
s
s
s
s
s
s
s
r r
r r
r r
r r
r r
r r
r r
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( ) 2 4 3
2 4 2
2 4 1
1 3 4
1 3 2
1 3 1
0 2 4
0 2 3
0 2 1
0 1 4
0 1 3
1 1 2
s
s
s
s
s
s
s
s
s
s
s
s
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
Constraint Graph will be solved for
retiming solution using Bellman-Ford
or Floyd-Warshall algorithm
r(1) = r(2) = r(3) = r(4) = 0 ; no
retiming required for c=3
Critical path constraint for c=2
( )
(
(
(
(
=
0 2 0 1
3 0 0 1
3 2 0 1
2 1 1 0
,V U W
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( )
( ) ( ) ( ) | | ( ) 2 3 , 4 1 3 , 4 1 3 4
2 2 , 4 1 2 , 4 1 2 4
2 1 , 4 1 1 , 4 0 1 4
2 4 , 3 1 4 , 3 2 4 3
2 2 , 3 1 2 , 3 1 2 3
2 1 , 3 1 1 , 3 0 1 3
2 4 , 2 1 4 , 2 2 4 2
2 3 , 2 1 3 , 2 1 3 2
2 4 , 1 1 4 , 1 1 4 1
2 3 , 1 1 3 , 1 0 3 1
2 2 , 1 1 2 , 1 0 2 1
> s
> s
> s
> s
> s
> s
> s
> s
> s
> s
> s
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
D for W r r
( )
(
(
(
(
=
2 6 3 4
6 2 3 4
4 4 1 2
3 3 4 1
,V U D
( ) ( ) ( ) ( ) c V U D for V U W V r U r > s , 1 ,
For c=2
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( ) 0 2 4
0 2 3
1 1 2
2 4 1
1 3 1
s
s
s
s
s
r r
r r
r r
r r
r r ( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( ) 2 4 3
2 4 2
1 4 1
1 3 4
1 3 2
0 3 1
1 2 4
1 2 3
0 2 1
0 1 4
0 1 3
1 1 2
s
s
s
s
s
s
s
s
s
s
s
s
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( ) 1 3 4
1 2 4
0 1 4
2 4 3
1 2 3
0 1 3
2 4 2
1 3 2
1 4 1
0 3 1
0 2 1
s
s
s
s
s
s
s
s
s
s
s
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
r r
RETIMING FOR REGISTER MINIMIZATION
Next Class

Remiting For Clockperiod Minimization

Uploaded by

Copyright:

Available Formats

Remiting For Clockperiod Minimization

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Remiting For Clockperiod Minimization

Uploaded by

Copyright:

Available Formats

Retiming for clock period

You might also like