Orcad 16.5 Signal Integrity

OrCAD 16.
5 - Signal Integrity Workshop

Toronto
August 21, 2012
OrCAD 16.5 - Signal Integrity Workshop
April 2012 5 . 6 1 n o i s r e V t c u d o r P 2
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April 2012 5 . 6 1 n o i s i v e R t c u d o r P 3
Contents
Lab 1: Impedance Mismatch and Reflections.................................................................. 4
Lab 2: Termination and Layer Stack-up ........................................................................ 15
Lab 3: Crosstalk ............................................................................................................ 27
Lab 1: Impedance Mismatch and Reflections
This module covers:
Driver Ideal Transmission Line - Receiver
Reflection Simulation and Parameter Editing
Sweeping and Ideal / Actual Transmission Line Elements
Introduction
As a signal propagates from driver to receiver, it encounters many structures in its path.
Traces, vias, connectors and component packages are all examples of the structures which
combine to form an interconnect. Each of these presents impedance to the incoming signal
derived from the effects they create on the magnetic and electric fields which surround them.
This lab starts with the most basic interconnect and adds complexity until the need for signal
integrity considerations present themselves.

1. Launch OrCAD PCB SI (SigXplorer),
and open Lab1_01.top located in the
C:\Orcad_labs\Lab1 directory.
Note: Lab directories will vary based on the location
where the material was installed at the beginning of
the class. Use the browser to locate the lab materials
at this time and the remainder of the labs should not
require additional searching.
OrCAD - Signal Integrity Training 16.5
April 2012 5 Product Revision 16.5
The open topology
represents the simplest
possible interconect , that
being a single driver
receiver pair connected
by an ideal transmission
line.
2. Click on the white
text CUSTOM of
the Driver to view
details of the
stimulus.
3. Note that a 100 MHz, 010 bit stream will be transmitted at time of simulation.

4. Click OK to close window and continue.
5. Expand the structures in the Parameters pane such that all properties can be seen.
Note: The unshaded (white background)
entries in the Value column represent
properties which can be edited. The element
INTERCONNECT has four such properties.
For this lab we will examine two of them:
Impedance and length.
This is all that is required to perform a preliminary SPICE simulation. The physical net is
constructed of two IBIS based device models, Driver (CDSDefaultOutput_1p8v) and Receiver
(CDSDefaultInput_1p8v). The interconnect model is derived from the values defined in the
parameters tab.
6. Launch Simulation from menu or tool bar icon.
Note: Upon completion, The resulting waveforms will
displayed in a popup Sigwave window and the
measurements will appear in the Results tab.

7. We will look at the results in more detail latter in the lab. The SigWave window displays the
simulated waveforms so we will look at this window in more detail. Expand the SigWave
window.
8. Like SigXplorer, the SigWave user interface is made up of several functional panes. In the
SigWave GUI, using the hints in the following image,change the display to show only the
waveform at the Receiver.
Hints:

Although not severe enough to cause a threshold crossing, clearly there is a signal integrity
issue worth investigating even on this simple topology. The ringing when the signal
transitions consumes over 60% of the available margin.
9. Minimize (but dont close) the SigWave window.
10. In the Parameters pane of
SigXplorer window, change the
length of the interconnect to
5000 mils and re simulate.
Note that when the simulation completes, the SigWave window opens automatically as
before. This time, however, two simulations are available in the navigation tree. The display
settings are automatically adjusted to leave only the current simulation visible.

Lengthening the Interconnect changes the waveform because the reflected portion has a
longer distance to travel. This can be easily visualized by displaying both simulation results
simultaneously. Notice the shape of the waveform is very similar only the x-axis (time) is
extended for the longer interconnect.
11. Repeat steps 9 and 10 two more times changing the Interconnect length to 15000 and
25000 mils.
12. Using skills from earlier in the
lab, toggle different simulation
results and observe the changes
in the waveform that result from
adjusting the Interconnect length.
In addition to the menu and tool bar
icons, frequently used functions can
be performed directly in the waveform
canvas.
13. Right click over a waveform and click
Display in the resulting popup to
hide that waveform.
The ringing behavior associated with an
impedence mismatch is most
pronounced in the waveform at the 5000
mil length (second simulation).
14. Adjust the display to show only that result and compare it to a
bounce diagram described in the lecture.
15. Close SigWave
(For Reference)

This provides pretty compelling evidence that the
distortion effects seen in simulation are the result
of an impedence mismatch.
In the following section, well use the simulation
tools to take a closer look at the effects of
impedance changes.
16. Return to the SigXplorer window and
change the Interconnect length to 5000 mils.
Well use this value as it yeilds simulation
waveforms where the reflection effects can be viewed.
17. In the Parameters pane, click on the
INTERCONNECT impedance Value
and note the arrow symbol whick
appears at the right of the entry area.
18. Click on the arrow to open a parameter
editor window.
This window makes it
possible to launch
many simulations in a
single operation and
sweep several entries
for a single variable.

19. In the parameter editor window set the sweep conditions as shown above to run five
simulations, sweeping the impedance from 30 ohm to 70 ohm in 10 ohm increments.
20. Click to close the parameter sweep editor.
April 2012 5 . 6 1 n o i s r e V t c u d o r P 0 1
21. Verify that SigWave is closed (not just minimized). When running, the icon will be
visible on the taskbar.
22. Launch the simulation as before.
23. When launching multiple simulations, a confirmation
dialog is presented. The purpose for this is to allow the
operator to do partial coverage sweeps as it is easy to
generate a large number of simulations when sweeping
multiple values for multiple variables. In this case we
will do 100% coverage so click continue.
24. When the simulation completes this time SigWave doesnt open
automatically. The results pane does however open. To expand the
viewing area for the Results pane, collapase the Parameters,
Command and Measurement panes. This is achieved by un-pinning
the panes. Pin the Results pane.
Note that each horizontal row
represents an individual simulation.
The vertical columns display the
swept variables and measurement
results obtained during simulation.
April 2012 5 . 6 1 n o i s i v e R t c u d o r P 1 1
Note that the smallest noise margin is the result of the highest impedence and the highest
noise margin cooresponds to the lowest impedence.

25. To view the waveforms, Right click anywhere on the results row then click on the
View Waveform popup. Using this method, and the skills from earlier, configure the
display to simultaneously show Sim1 (30 ohm) and Sim5 (70 ohm) at the receiver only.
Clearly the lower impedance (30 ohm)
provides greater margin.
Recall that margin
is voltage beyond
threshold.
26. Close SigWave
27. From the SigXplorer main menu, select View ->Reset UI to Cadence Default
28. Click Yes in the confirmer popup.
This action simply restores the pane
size and visibility to its origional state.

29. Select a microstrip element and place under
the ideal transmission line.
Note: Once selected from the quick pick menu bar, an
element will attach to the cursor until clicked at the
desired location.
Based on earlier simulations, we found that, although their continued to be ringing, we could
achieve acceptable margin when the interconnect impedance was 30 ohms.
The ideal transmission line allows topology exploration without regard to how (or if) it would be
constructed. Other options, such as the microstrip element, address construction aspects
(materials and dimentions) needed to achieve the target
impedances.

30. To view the specific dimention and material properties,
Right click on the canvas element and select
View Trace Parameters
from the parameters pane
The 90 ohm default microstrip element is a long way from our desired 30 ohm. Changes to
the trace width and distance from the plane are known to alter impedance. We will look at
adjusting these to correct our impedance mismatch.
31. Close the Trace Model Parameter viewer.
32. In the SigXplorer Parameters pane, expand the newly added Microstrip element TL_MS1.
33. Change the trace width from 5 to 20 Mil and observe the impedance change displayed on
the canvas. While we do see improvement, clearly a 20 mil route is not reasonable for
todays densities. Additionally, we would need nearly 50 mils for a 30 ohm trace.
Trace Width 5 mil...20 milall the way to 49.75 mil.

34. As previously mentioned, Impedance can also be altered by adjusting the distance from the
ground plane. Change the dielectric
thickness to sweep from 2 to 10 mils.
35. Note the Impedance
is no longer visible on the canvas.
36. Click OK to close the sweep parameter editor.
37. Again, open the Trace Parameter Viewer.
38. Click on the row indicator and observe the
Impedance change.
While each change helps, achieving the 30 ohm target
requires adjusting two variables, trace width and the
distance from the plane {dielectric thickness T(D1)}.
39. Close the Trace Model Parameter Viewer.
40. Delete the unconnected Microstrip model on the canvas.
Note that commands like delete mirror, and rotate act on
entities that are selected when the command is
executed. Selected elements will have stippled graphics.
41. Change the Impedance on the
INTERCONNECT element to 30
ohms and simulate as before.
42. When the simulation completes, minimize the SigWave
window.
43. Again add a microstrip element to the canvas and edit its
properties such that
d1Thickness=3.05;traceWidth=12;length=5000
44. Delete the ideal Transmission Line and
connect the recently added Microstrip
element in its place.
45. From the main menu, select
Edit -> Cleanup. This function
aligns the canvas elements. It
effectiveness decreases as the
complexity increases however.
46. Simulate

47. Set the visibility to display only
the signals at the receiver for
each simulation.
48. In the SigWave navigation tree,
Right Click on the first
simulation and select Set Name
49. Set the first simulation to
Ideal and the second to
Actual.
50. Observe the waveforms and
note the reflection amplitudes
coorelate very closely.
51. Close
The time axis coorelation could
also be tuned by adjusting signal
velocity in the ideal model.
Conclusion:
The purpose of this Lab was to introduce solution space simulation. We began by simulating a
very basic electrical net and observed the resulting waveform. Ringing, a tell-tale sign of
impedance mismatch was identified. Lengthening the net extended the signal propagation time
making the impedance mismatch more obvious. The interconnect impedance was then swept by
way of multiple simulations. An optimal Impedance was selected which resulted in an acceptable
noise margin. Efforts then shifted to determining the required materials and dimentions needed
to construct an actual trace element which coorelated to the ideal line previously determined to
yeilded acceptable noise margin.

Lab 2: Termination and Layer Stack-up
This module covers:
Termination
Importing and using Existing Layer Stack-up data
Modifying the Stack-up
Introduction
The first Lab demonstrated the importance of Impedance management and has hopefully
convinced you that mismatches are problematic. In the Lab we examined the geometry that
drives the Impedance and experimented with tools and techniques available to reduce the
mismatch to achieve an acceptable noise margin. While we were able to improve the signal
quality, we did see that conventional line widths and layer thickness resulted in a fairly narrow
impedance range. Lab 2 will examine the use of series termination. This technique is
characterized by a discrete resistor placed close enough to the driver pin so as to behave as a
single impedance.

Following the termination exercise, the Lab will
examine the process of extending the Actual
Transmission line constructed in Lab 1 to a
complete board stack-up.

1. Launch OrCAD PCB SI (SigXplorer),
and open Lab2_01.top located in the
C:\Orcad_labs\Lab2 directory.
From the File menu, open the topology Lab2_01.top
2. When the topology opens, note that the 5 30 ohm Microstrip
transmission line developed in Lab_1 has been split into two
segments (.1 and 4.9) and a resistor has been added in
series in the interconnect.
3. Simulate
4. From the knowledge gained earlier in the Lab, Hide
the wavefrom at the driver.
5. In the Parameters
tab, change the
resistance of the
R_SERIES element
to 0 ohms.
(This has the effect of removing the resistor).
6. Re-simulate and use the display controls to view the
both receiver waveforms, with and without the
series resistor.
Clearly the resistor has dramatically improved the
quality of the signal at the receiver. Recall from the
lecture material Impedence matching eliminates reflections. In this
case the Impedence of the driver is approximately 11 ohms. Adding
a 19 ohm resistor very close to the driver makes the driver appear to
have a 30 ohm impedance (11+19). A 30 ohm driver driving an 30
ohm transmission line yeilds no reflections.
So how do we know the best value of the resistor we add?
7. Close SigWave (not minimized)
8. In the the SigXplorer parameters pane, set the
resistance fo the series resistor as shown.
9. Expand the Measurement pane and tack it on the
display.
Note: It may be helpful to collapase the other panes and
reduce the topology canvas. Remember you can restore the display to the original settings from
the view menu.
10. Change the measurement settings such that only
the Noise margin and Overshoot measurements
are taken. These will be found under the
Reflection category. A check in the box indicates
that a specific measurement will be performed
and subsequently reported in the Results
spreadsheet.
11. Reset the UI to Cadence defaults and simulate.
12. Expand the Results window to display the Margin
and Overshoot measurements resulting from the
sweep of the series resistor.
13. Right click and View Waveform for both SimID 1
and SimID 5. As before, set visibility to view the
signal at the receiver.
14. Note that increasing the resistance has successfully
eliminated the ringing. In fact the step in SimID5
indicates that the 25 ohm series resistance is actually
too much. If interested, display all 5 receiver
waveforms.
15. This technique can be used to identify the optimal
resistance. In the interest of time for this lab, use
the hints below to set the following sweep
conditions.
16. Close (not minimized) SigWave
17. Simulate
18. Use the Results tab to open SigWave and display the receiver waveform at the receiver for
both simID1 and simID3.

19. Observe that the 17 Ohm termination value (blue waveform) produces a very clean transition
for the rising edge however still has nearly 200mV of negative overshoot on the falling edge.
Conversly, the 22 Ohm terminator (red waveform) is clean on the falling edge but
undershoots on the rising ede by nearly 130 mV. As with nearly all Signal Integrity
descisions, a compromised value of 19 Ohms produces reasonable results for both
transitions. Additionally, recall that the variable swept is the resistance of a discrete resistor.
Therefore, in actual practice, the values defined for the multiple value parameter sweep
should be those of actual purchasable resistors.
20. In the parameters pane, change the resistance and
length values as shown.
21. Simulate
Note that, unlike the unterminated net, the waveform is
reasonably clean over a much wider length variation.

22. Close SigWave.
Recall that the series resistor is effective when it is placed close enough to the Dirver that
the Driver and Resistor Impedances combine to look like a single lump.
23. Place the resistor near the receiver as opposed to near the driver. For simulation this can be
achieved by adjusting the net lengths of the two Microstrip transmission lines.
24. Simulate and observe the
resulting waveform. Note
that when the resistor is
placed at the opposite
end of the net, as shown
above, it becomes entirely
ineffective.
As a post Lab exercise, try
sweeping the length of the
transmission line between the
Driver and series resisitor.
25. Re-Open the original topology (From the File
menu, open the topology Lab2_01.top). It is not
necessary to save the changes made in the
previous steps.
Recall from previous exercises, that it was difficult to construct actual 30 Ohm Microstrip
transmission lines. (Required 12 Mil trace width and only 3.05 Mil dielectric thickness.) We then
learned that that the impedance match, not the specific impedance, had the most impact on the
signal quality.

26. Select Setup ->Manage LayerStacks OR Right click in any open space and select
27. In the resulting popup, observe that one stack-up has been previously loaded. Note that the
same stack-up editor available in the layout tools is used for Signal Integrity. In fact, the
stack-up from an existing OrCad layout file can be loaded simply by identifying the source file
in the browser.

28. Select pre-loaded SODIMM_1Rx8N and click
Edit.
The stack-up editor common throughtout the tool suite
opens for editing.

29. Click the checkbox to Show Single
Impedance and observe a new column
is visible.
30. Note that for the given stack-up and
materials, a 5 mil lline results in
approximately 55 Ohm trace on the TOP
layer.
31. Click OK to close the stack-up editor and
Close to exit the Stack-up manager.
32. From the topology canvas,
Right click one of the
Microstrip elements. From
the resulting popup, change
the layer to TOP.
33. Open the Parameters pane
and observe the difference
between the edit capable
parameters for a generic
microstrip and one assigned
to a layer.
Conclusion
This lab demonstrates the value of simulation
even for simple, slow switching net topologies. As
rise times and complexity increase, so does the
likelihood of unpredictability in the signal
waveform at the receiver. The lab also introduces
a basic technique for managing impedance
mismatches (series termination) and demonstrates
how simulation tools can be used as a design aide
in addition to its traditional role in verifying signal
quality at the end of the design process.

Take Home Exercises
The remainder of this lab explores different combinations of multiple receiver interconnects.
Typically, additional devices can be added to the standard Driver/Receiver simple network in
one of two ways, sequentially (aka daisy chain) or by creating branches in the path. Complex
networks often include combinations of both. It is important to understand the transmission line
implications of the following 4 types of topology constructs before attempting to rectify reflection
problems in more complex networks.
Each file illustrates a different concept and is followed by suggested areas to explore.
Lab2_2.top Daisy chain
Daisy chain topologies are commonly used as they limit reflections to a single path. It is
interesting to note that not all reflections are bad. In fact, some signals require them to
switch a signal above the threshold. Signals can plateau at a receiver as the incident
wave passes requiring the reflected waves return before the threshold voltage is reached.
Areas for consideration could be separation between receivers, and number of receivers.
Lab2_3.top Daisy chain with parallel termination
Daisy chained signals are often ended in parallel termination. A parallel terminator is
simply a resistor matching the Characteristic Impedance of the trace tied to ground or
other DC net. Simply put the parallel terminator after the last receiver dissipates the
reflection making the transmission line look infinitely long.
Areas to examine include, changing driver strength, location of the terminator (i.e. close
to or far after the last load) and placement in a location other than after the last load.
Lab2_4.top Branch
A Branch in a topology occurs in the majority of multi-receiver topologies. Poor
management of these can yield transmission lines with signals bouncing wildly over many
different paths. It is important to note that an impedance mismatch is created when 3
matched traces join. As a signal travels down one branch and encounters a fork, the
other branches appear as parallel impedances. (i.e. two joined 80 ohm lines appear as 40
ohms at the split)
Topics for test can include branches of different impedance, more than a 2 trace split, etc.
Be cautious here though as these can get very complex quickly and it will be difficult to
follow where the reflections are coming from.
Lab2_5.top Branch with parallel termination
Similar to the Daisy Chain with termination, the parallel resistor has the effect of making
the branch look infinitely long. You are still faced with the reflection at the split however.
These can be managed by altering the trace geometry to match the parallel resistance.
Things to investigate are different branch length and the effects of an improperly
terminated branch.
1. Launch SigXplorer (with GXL License), and open Lab2_2.top located in the Lab2 directory.
2. Simulate
Multiple receiver nets add complexity and can be more difficult to predict until you understand
what is happening on the transmission line.
Given that the receiver R_LAST switches approximately 2ns after the driver, estimate when
R_FIRST switches.
2. Simulate
2. Simulate
Launch SigXplorer (with GXL License), and open Lab2_5.top located in the Lab2 directory.
1. Simulate
Conclusion
The focus of this lab was to provide tools needed to implement theoretical connection
schemes in real transmission lines. The first half dealt with managing the elements along the
path whereas the second half demonstrated the methods used to divide paths and manage
the ends. Very complex topologies can be constructed utilizing these basic principles. It is
always best to start simple and build upon it as frequently it is not an intuitive as it may
initially seems. The good news is that these effects are predictable and repeatable.
Simulation will accurately predict the signal behavior. These techniques are useful in reverse
as well. Complex trace topologies can be extracted and simulated. If problems are found
potential reflection points can be removed and re-simulated until the source of the
unacceptable noise is identified.
Lab 3: Crosstalk
This module covers:
Reflection simulation with passive victim
Crosstalk simulation
Introduction
As seen in the previous exercises, the waveform seen by a receiver can be distorted by
many structures electrically connected in an interconnect. All previous work has concentrated on
the distortion in a single net. Crosstalk differs in that it is a study of the interaction between nets.
Although electrically isolated from each other (i.e. not shorted) a net can impact its neighbors by
way of magnetic interference. This magnetic relationship, called coupling, creates an
environment where a switching signal generates noise on neighboring transmission lines. As
discussed in the lecture material, the magnitude of the noise depends on the aggressor
waveform and the degree to which the interconnects are coupled.

Note that the topology now contains two distinct electrical nets. The net framed in the image
above is identical to that used in the earlier exercises except that the transmission line has
been replaced with a 3 inch coupled line. The second net is grounded at one end (near end)
and has the same receiver as the primary net, referred to as the aggressor. Simulation occurs
in the aggressor an in previous exercises. In addition to the signal sent to the receiver on the
aggressor net, a signal is also received by the victim receiver as a result of the coupled
transmission.
2. Simulate
3. In the SigWave navigation tree, right click over the sim1: folder and select Hide All
Sub items from the popup window.
4. Set the visibility for the DESIGN RECEIVER 1 to on.

5. Select Zoom in Specific Size from the SigWave toolbar.
6. Enter the values as shown in the Zoom popup.
7. Click OK to close and adjust waveform size.
8. Add a Differential Vertical Marker to the SigWave canvas.
9. Drag the markers to the points where the waveform begins and ends its transition.
10. Repeat with an additional marker on the falling edge.
11. Set display visibility to on for DESIGN VICTIM 1

Note: When the voltage at the RECEIVER is changing is there is a voltage
produced on the VICTIM due to the coupling. When the voltage is
steady no voltage is produced on the victim regardless of the
magnitude (in this case 0V or 1.8V). These areas have been highlighted.
12. Leaving the SigWave window open, return to the SigExplorer window and open
LAB3_2.top.

Observe that the only difference between the topologies is the removal of the series resistor
near the driver on the aggressor signal.
13. Simulate
The new simulation will be added to the open Sigwave window with its visibility set to on and
all others off.
14. Change the visibility as done in steps 4 and 11 to display only the RECEIVER and VICTIM
Note that the noise generated on the VICTIM is almost constant and even is significant enough
to create a threshold crossing.

15. Change the visibility so that only the VICTIM waveforms from both simulations are visible
and not how much more noise is generated when the Aggressor is allowed to oscillate
uncontrolled.
16. Change the Aggressor switching frequency to 10 MHz as shown and simulate again.
(Reminder: click on the white CUSTOM text on the Driver to open the stimulus editor)
Given a typical Signal Integrity approach, consider if
this 10MHz signal would even be evaluated. This
signal is capable of producing random 600mV spikes
in a 1.8 volt rail to rail system (30% swing) from a
single aggressor. Also remember crosstalk
accumulates thru superposition,
. m e l b o r p r e g g i b = s r o s s e r g g a e l p i t l u m
17. Exit SigWave and open LAB3_3.top
18. Answer yes to Proceed with new template confirmer.
19. Slide the mouse over the Measurements tab as shown above to open the measurements
collapsible window.
20. Click the Crosstalk radio button to select crosstalk simulation.
21. Although this is an expandable menu, currently Max Voltage report produces all needed
measurements for full crosstalk simulation.
22. Simulate
23. When the simulation completes, observe the VICTIM waveform. Note that although the
voltage is induced only when the aggressor is in transition, the signal does propagate and
exhibits the same type of reflections as it would had it been driven directly.

24. This simulation illustrates the crosstalk induced when the signal is
help low.
25. Click on the Quite_Lo text to open the stimulus editor.
26. Change the VICTIM_NEAR option to Quiet_Hi.
27. Click OK to close the Stimulus Editor
28. Simulate
29. Change the visibility to show both VICTIM NEAR
waveforms.
Note that these signals show only small ripples. This is because for typical PCB structures, the
inductive and capacitive components of crosstalk are almost equal in amplitude but are
opposite in polarity, thereby cancelling each others effects at the near end.
30. Change the visibility to show both VICTIM FAR waveforms.
31. Close all open windows.
NEAR END
FAR END
Conclusion
Crosstalk simulation is the study of a transmission lines effect on its neighbors. While this
is most often addressed in a post route environment, tools such as SigXplorer can be
used to determine acceptable parallelism constraints before routing. It is important to note
that while this exercise examines a single aggressor injecting noise on a victim, in most
situations many aggressors combine to form the total crosstalk. Users should note that
even slowly switching signals can be responsible for substantial crosstalk and should
transition to considering edge rate as opposed to frequency when looking for potential
issues.

Thank you for joining us.
To find out more about OrCAD PCB SI or other OrCAD solutions, please visit us online at
www.ema-eda.com. To have the lab files sent to your or for any questions, please contact
us at 800.813.7287 or [email protected].
Technical Support:
Telephone: 585.334.6001 Option 5
E-mail: [email protected]


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