Schem, MLB - Ldo, K6: Schematic / PCB #'S

8
2
REV ECN
1
DESCRIPTION OF REVISION CK APPD DATE
2010-03-18
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,MLB_LDO,K6
D
(.csa)
PVT, 3/18/10
Date (.csa) Date
Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
Contents
1
Sync
05/20/2009 K17_MLB 08/19/2009 K69_MLB 08/19/2009 K69_MLB 07/20/2009
Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
Contents
56
Sync
07/20/2009 K24_MLB 08/15/2009 T27_MLB 08/03/2009 T27_MLB 07/20/2009 T27_MLB 10/21/2009 T27_MLB 08/31/2009 AUDIO 07/17/2009 AUDIO 07/17/2009 AUDIO 07/17/2009 AUDIO 08/25/2009 AUDIO 08/27/2009 AUDIO 07/20/2009 K24_MLB 07/29/2009 T27_MLB 07/20/2009 K24_MLB 08/06/2009 T27_MLB 07/20/2009 K24_MLB 08/18/2009 T27_MLB 07/20/2009 K24_MLB 09/30/2009 T27_MLB 11/24/2009 T27_MLB 08/27/2009 T27_MLB 07/20/2009 K24_MLB 08/12/2009 K69_MLB 07/20/2009 K24_MLB 08/27/2009 K69_MLB 07/28/2009 T27_MLB 08/03/2009 T27_MLB 08/03/2009 T27_MLB 08/03/2009 T27_MLB 08/27/2009 T27_MLB 11/23/2009 T27_MLB 07/20/2009 T27_MLB 07/28/2009 T27_MLB 09/08/2009 T27_MLB 08/06/2009 T27_MLB
TABLE_TABLEOFCONTENTS_ITEM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Table of Contents
2
System Block Diagram

3
Power Block Diagram

4
BOM Configuration
5
K24_MLB 07/20/2009
Revision History
7
K24_MLB 07/20/2009
FUNC TEST
8
K24_MLB 07/22/2009
Power Aliases
9
K24_MLB 07/20/2009
SIGNAL ALIAS
10
K24_MLB 08/27/2009
CPU FSB
11
T27_MLB 07/20/2009
CPU Power & Ground

12
T27_MLB 11/23/2009
CPU Decoupling
13
T27_MLB 07/28/2009
eXtended Debug Port (mini-XDP)

14
T27_MLB 11/05/2009
MCP CPU Interface

15
T27_MLB 08/06/2009
MCP Memory Interface

16
T27_MLB 11/05/2009
MCP PCIe Interfaces

17
T27_MLB 11/05/2009
MCP Graphics
18
T27_MLB 11/23/2009
MCP SATA, USB & Ethernet

19
T27_MLB 11/23/2009
MCP HDA, LPC & MISC

20
T27_MLB 08/06/2009
MCP Power & Ground

23
T27_MLB 11/23/2009
MCP89 Memory Rail Gating

24
T27_MLB 11/23/2009
MCP89 GFX Core Rail Gating

25
T27_MLB 08/15/2009
MCP Standard Decoupling

26
T27_MLB 08/06/2009
MCP Graphics Support

28
T27_MLB 07/28/2009
SB Misc
29
T27_MLB 07/28/2009
DDR3 SO-DIMM Connector A

31
T27_MLB 07/28/2009
DDR3 SO-DIMM Connector B

32
T27_MLB 06/19/2009
DDR3 BYTE/BIT SWAPS-K6

33
K18_MLB 09/29/2009
FSB/DDR3 Vref Margining

34
T27_MLB 07/28/2009
RIGHT CLUTCH CONNECTOR

35
T27_MLB 09/30/2009
SecureDigital Card Reader

39
T27_MLB 08/20/2009
Ethernet PHY (Caesar II/IV)

40
T27_MLB 07/28/2009
Ethernet Connector
41
T27_MLB 07/20/2009
FireWire LLC/PHY (FW643E)

42
T27_MLB 12/15/2009
FireWire Port & PHY Power

43
T27_MLB 07/28/2009
FireWire Connector
45
T27_MLB 08/06/2009
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Fan
57
WELLSPRING 1
58
WELLSPRING 2
59
Sudden Motion Sensor (SMS)

61
SPI ROM
62
AUDIO: CODEC/REGULATOR
63
AUDIO: LINE INPUT FILTER

65
AUDIO: HEADPHONE FILTER

66
AUDI0: SPEAKER AMP

67
AUDIO: JACK
68
AUDIO: JACK TRANSLATORS

69
DC-In & Battery Connectors

70
PBus Supply & Battery Charger

72
5V/3.3V SUPPLY
73
1.5V/1.35V LVDDR3 Supply

74
IMVP6 CPU VCore Regulator

75
MCP VCore Regulator

76
CPU VTT(1.05V) SUPPLY

77
Misc Power Supplies

78
Power Sequencing
79
Power FETs
90
LVDS CONNECTOR
93
DISPLAYPORT SUPPORT
94
DisplayPort Connector
97
LCD Backlight Driver

98
LCD Backlight Support

100
CPU/FSB Constraints
101
Memory Constraints
102
MCP Constraints 1
103
MCP Constraints 2
104
Ethernet Constraints
105
FireWire Constraints
106
SMC Constraints
108
K6/K69 Specific Constraints

109
K6/K69 PCB Rule Definitions
SATA Connectors
46
T27_MLB 08/27/2009 T27_MLB 08/27/2009 T27_MLB 09/02/2009 T27_MLB 09/02/2009 T27_MLB 08/27/2009 T27_MLB 08/21/2009 T27_MLB 08/27/2009 T27_MLB 09/30/2009 T27_MLB 08/27/2009 T27_MLB
External USB Connectors

48
Internal USB Support

49
SMC
50
SMC Support
51
LPC+SPI Debug Connector

52
K6 SMBUS CONNECTIONS
53
Voltage Sensing
54
Current Sensing
55
Thermal Sensors
A
DRAWING TITLE
A
SCHEM,MLB_LDO,K6
Schematic / PCB #s
PART NUMBER
051-8563 820-2879
DRAWING
DRAWING NUMBER
SIZE
Apple Inc.
REFERENCE DES
SCH PCB
051-8563
REVISION
QTY
1 1
DESCRIPTION
SCHEM,MLB_LDO,K6 PCBF,MLB_LDO,K6
CRITICAL
CRITICAL CRITICAL
BOM OPTION
A.13.0
BRANCH PAGE
NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
LAST_MODIFIED=Thu Mar 18 17:53:39 2010
TITLE=MLB ABBREV=DRAWING
1 OF 109
SHEET
1 OF 80
6
U1000
5
J1300
INTEL CPU
2.X OR 3.X GHZ PENRYN
PG 9
XDP CONN
PG 12
FSB
D
PG 10
64-Bit 1067/1333 MHz
J6950,U7000
D
DC/BATT POWER SUPPLY
PG 58,59
J2900
GPIOs
PG 18
FSB INTERFACE
MAIN MEMORY
PG 14
2 UDIMMs DDR3-1067/1333MHZ
DIMM
U5535,U5515 PG 25,26
CPU,MCP,TEMP SENSOR
PG 45
CLK SYNTH
PG 15,18 J4501
Misc
PG 18 U6100
SATA Conn HD
J4500
SPI
1.05V/3GHZ. PG 38 PG 18
SPI Boot ROM

PG 51
POWER PGSENSE 50
J5601
FAN CONN PG AND CONTROL 46
NVIDIA
SATA Conn ODD
1.05V/3GHZ. PG 38
U4900
B,0 BSB
ADC
SATA
PG 17
MCP
LPC
SMC
PG 39 PG 18
Fan Ser Prt
J5100
LPC+SPI Conn
PG 46
C
J9000
U1400
LVDS CONN
PG 68
PWR
LVDS OUT RGB OUT DP OUT HDMI OUT DVI OUT
PG 70
CTRL
J3401 U5701 J4890 J3401 J4600, J4610 J3500 J4890
Bluetooth
PG 29
TRACKPAD/ KEYBOARD
PG 47
IR
PG 38
CAMERA
PG 29
EXTERNAL USB
Connectors PG 37
Card reader
PG30
Blue Ray dec

PG38
J9400
TMDS OUT
PG 16
J3401
AIR PORT
PG 15
PG 29
(UP TO 12 DEVICES)
DISPLAY PORT CONN
0 1 2 3 4 5 6 7 8 9 10 11
USB PCI-E MAC

PG 17
PG 17
UP TO 20 LANES3
J1300
B
PG 12
SMB
PG 18
SMB CONN
PCI
HDA
PG 18
U6201
Audio Codec
PG 52
U3900
U6880
U6633, U6623, U6613
A
J3401 J4000
BMC5764M
PG 31
GB E-NET
Line In Filter
PG 53
HEADPHONE Filter
PG 54
Mic Amp
PG 53
Speaker Amps
PG 55
SYNC_MASTER=K69_MLB
PAGE TITLE
SYNC_DATE=08/19/2009
System Block Diagram

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
PCI-E AirPort
PG 29
A.13.0
BRANCH PAGE
E-NET Conn
PG 32
J6750,6700
Audio Conns
PG 56

2 OF 109
SHEET
2 OF 80
7
PP18V5_DCIN_CONN
K6 POWER SYSTEM ARCHITECTURE

Q7080
PPDCIN_G3H_OR_PBUS
02
ENABLE
Q7085
PBUS_VSENSE
D
01
CHGR_EN (S5)
ENABLES
8A FUSE PPVBAT_G3H_CHGR_REG F7040
V
PPBUS_G3H
3.425V G3HOT LT3470 VOUT U6990 PBUS_G3H_VSENSE
PP3V42_G3H_REG 03
SMC PWRGD RN5VD30A-F
04
Q5315
02
VIN
U5010
D
PP1V05_S0 (8A MAX CURRENT)
AC DCIN(16.5V) ADAPTER IN
F6905 6A FUSE
CPUVTTS0_EN (S0)
EN_PSV
VOUT
CPUVTT
(1.05V)
A
SMC_DCIN_ISENSE
VIN
VOUT
R7050
SMC_BATT_ISENSE
TPS51117 U7600
PGOOD
MCP89
PWRBTN*
06-1
R7020
PBUS SUPPLY/ BATTERY CHARGER ISL6259 U7000

01
31
PLTRST*
A
02
LPC_RESET_L
CPUVTTS0_PGOOD
RSMRST*
CPU VCORE
VIN VOUT
SMC_CPU_VSENSE
MCP_PS_PWRGD PWRGD
J6950
IMVP_VR_ON_R 3S2P Q7055 PPVBAT_G3H_CONN
PPVBAT_G3H_CHGR_R
ISL9504B
VR_ON PGOOD
PPVCORE_S0_CPU (44A MAX CURRENT) SMC_CPU_ISENSE
29 26
U2850
CPUPWRGD(GPIO49)
CPU_RESET#
CPU_PWRGD
30
FSB_CPURST_L
U1400
28
VR_PWRGOOD_DELAY
(9 TO 12.6V)
25
C
CHGR_BGATE
U7100
CPU
4.5V AUDIO VIN MAX8840 PWRGOOD PP4V5_AUDIO_ANALOG
VOUT
PPBUS_G3H
U6200
EN
RESET*
U1000
MCP89
PM_SLP_S4_L
11
32
11-1
P3V3S3_EN
Q7940
SMC
15
PM_SLP_S3_L
11-3 P16
02 04
SMC_PM_G2_EN
PP5V_S0_FET PP5V_S3_REG
(13A MAX CURRENT)
U4900
P5VS3_EN_L 05
P3V3S5_EN_L
VIN
EN1
5V
(RT)
VOUT1
17 07
Q7910 PP3V3_S3_FET
P5VS0_EN
U1400
RC DELAY
DDRREG_EN
P60
(S5)
PP3V3_S5_REG
VOUT2
EN2
3.3V
(5.5A MAX CURRENT)
11-2
02 P5VS3_EN_L
VIN
U7840
TPS51125 U7201
PGOOD1,2
VREG3
13
Q3450 P3V3S3_EN P3V3_S3_WLAN
RC DELAY
BKLT_EN
LP8545 U9701
ENA VOUT
P5V3V3_PGOOD
PPVOUT_SW_LCDBKLT
P3V3ENET_EN_L
B
Q7890
AP_PWR_EN
PM_WLAN_EN_L VIN
EN
VOUT
24
ALL_SYS_PWRGD
SMC
RSMRST_OUT(P15)
PWRGD(P12) 99ms DLY
PM_RSMRST_L
IMVP_VR_ON_R
10
Q7930 PP3V3_S0_FET PP0V9_S5_REG P3V3S0_EN

1.8V
TPS62202 U7760
18 09
RSMRST_PWRGD SMC_ONOFF_L
16
ISL8009B U7750
PP1V8_S0_REG
05
P1V5S0_PGOOD P5V3V3_PGOOD
IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) P17(BTN_OUT) RST*
25
PM_PWRBTN_L SMC_RESET_L
1.5V
Q7890,Q7891 PM_SLP_S3_L SMC_ADAPTER_EN

04-1
ISL8009B U7710
PP1V5_S0_REG
SLP_S5_L SLP_S4_L SLP_S3_L
MCPCORES0_PGOOD CPUVTTS0_PGOOD
1.05V MCPPLLDO_PGOOD
TPS7470 U7740
SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)
Q7930
PP1V5R1V35_SW_MCP
02
VIN
21
1.2V
ST1S12G12R U7720
S0PGOOD_RST_L
PP1V05_S0_MCP_PLL_REG
U4900
PP1V2_ENET_REG
=DDRREG_EN PM_SLP_S3_L
S5 S3
1.5V
VOUT1
MCPDDROUT
=DDTVTT_EN
16-1
0.75V VOUT2
14
PP1V5_S3_REG (12A MAX CURRENT) PP0V75_S0_REG (1A MAX CURRENT)
RST*
PP3V3_S0 PP1V5_S0 PP1V05_S0 V1 V2 V3
RC DELAY
P1V8S0_EN
16-3
PBUSVSENSE_EN (S0) P5VS0_EN (S0)

RC DELAY 16-1
TPS51116 U7300 MCP_CORE

PPMCPCORE_S0_R
20
R7525 PPMCPCORE_S0_REG
VOUT
ISL88042 U7870
SYNC_MASTER=K69_MLB
PAGE TITLE
RC DELAY
P1V5S0_EN
16-4
Power Block Diagram

DRAWING NUMBER SIZE
MCPCORES0_EN
16-2
EN
(25A MAX CURRENT)

R
Apple Inc.
051-8563
REVISION
RC DELAY
CPUVTTS0_EN
16-6
P3V3S0_EN
A.13.0
BRANCH PAGE
DDRVTT_EN MCPCORES0_EN
16-5
RC DELAY
VIN
02
ISL9563A
U7500
3 OF 109
SHEET
3 OF 80
8
BOM Variants
7
BOM NAME
PCBA,MLB_LDO,BETTER,K6 PCBA,MLB_LDO,BEST,K6 K6 MLB_LDO DEVELOPMENT BOM
6
TABLE_BOMGROUP_HEAD
5
Bar Code Labels / EEE #s
4
PART NUMBER QTY
1 1
3
REFERENCE DES
[EEEE_DD23] [EEEE_DD24]
2
BOM OPTION
EEEE:DD23 EEEE:DD24
BOM NUMBER
639-1120 639-1119 085-1634
BOM OPTIONS
TABLE_BOMGROUP_ITEM
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM
CRITICAL
CRITICAL CRITICAL
K6_COMMON,CPU:2.4GHZ,MCP89M:A02,EEEE:DD24
TABLE_BOMGROUP_ITEM
826-4393 826-4393
TABLE_BOMGROUP_ITEM
K6_COMMON,CPU:2.66GHZ,MCP89M:A02,EEEE:DD23 K6_DEVEL:PVT
BOM Groups
TABLE_BOMGROUP_HEAD
BOM GROUP
K6_COMMON K6_MISC K6_PROGPARTS K6_DEVEL:ENG K6_DEVEL:PVT K6_DEBUG:ENG K6_DEBUG:PVT K6_DEBUG:PROD
BOM OPTIONS
TABLE_BOMGROUP_ITEM
COMMON,ALTERNATE,K6_MISC,K6_DEBUG:PROD,KB_BL,K6_PROGPARTS,RDRV:NO,SPI:25MHZ,CPU_CAP:15
TABLE_BOMGROUP_ITEM
DP_ESD,MIKEY,BCM5764M,GL137,ENET_ESD,VFRQ:SLPS3,LVDDR3:YES,MCPPLL_R:REG,S0PGOOD_BJT,BOOST_VOL:LOW,HDA:1.5V
TABLE_BOMGROUP_ITEM
BOOTROM:UNLOCKED,SMC:PROG,IR:PROG,WELLSPRING:PROG
TABLE_BOMGROUP_ITEM
BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,RDRV:IN_DEVEL
TABLE_BOMGROUP_ITEM
LPCPLUS,XDP_CONN
TABLE_BOMGROUP_ITEM
K6 BOARD STACK-UP
Top 2 3 SIGNAL GROUND SIGNAL(High Speed) SIGNAL(High Speed) GROUND POWER POWER GROUND SIGNAL(High Speed) SIGNAL(High Speed) GROUND SIGNAL
DEVEL_BOM,SMC_DEBUG:YES,XDP
TABLE_BOMGROUP_ITEM
DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO
TABLE_BOMGROUP_ITEM
BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO,LPCPLUS,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES
Module Parts
PART NUMBER
337S3769 337S3680 337S3756 337S3761 337S3797
QTY
1 1 1 1 1 1
DESCRIPTION
PDC,SLGVT,PRQ,2.26,25W,1066,R0,3M,BGA,P7550 PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA IC,MCP89M-A01,31X31MM,BGA1168 IC,MCP89M-A01,31X31MM,BGA1168 IC,1MBIT,SPI FLASH,K17/18
REFERENCE DES
U1000 U1000 U1000 U1000 U1400 U1400 U3990 U3900 U4100 U9701
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
BOM OPTION
CPU:2.26GHZ CPU:2.4GHZ CPU:2.53GHZ CPU:2.66GHZ MCP89M:A01 MCP89M:A02 BCM5764M BCM5764M
4 5 6 7 8 9 10 11 BOTTOM
337S3866 341S2731 343S0493 338S0753 353S2896
1 1 1 1
IC,ASIC,BCM5764M,ENET CONTROLLER, 8x8, 64QFN

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12 IC,LP8545,LED BKLT CTRLR,LLP24
Programmable Parts
338S0563 341T0240 335S0610 341T0238 341S2589 338S0633 341S2384 337S2983 341S2616
1 1 1 1 1 1 1 1 1
IC,SMC,HS8/2117,9X9MM,TLP,HF SMC EXTERNAL,K6

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U4900 U4900 U6100 U6100 U6100 U4800 U4800 U5701 U5701
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
SMC:BLANK SMC:PROG BOOTROM:BLANK BOOTROM:UNLOCKED BOOTROM:LOCKED IR:BLANK IR:PROG WELLSPRING:BLANK WELLSPRING:PROG
EFI UNLOCKED,K6/K69 IC,EFI,LOCKED,K6 IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN IC,ENCORE II,CY7C63803-LQXC IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 IC,TP PSOC,K17,K18
Alternate Parts
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
152S0693 152S0796 157S0058 104S0018 128S0093 152S0874 152S0847 152S1025 337S3769 152S1135 516-0213 516S0790 376S0699
152S0778 152S0685 157S0055 104S0023 128S0218 152S0516 152S0586 152S1024 337S3704 152S0586 516-0201 516S0706 376S0360
ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
DELTA AS ALTERNATE
TABLE_ALT_ITEM
DALE/VISHAY AS ALTERNATE
TABLE_ALT_ITEM
KEMET AS ALTERNATE
TABLE_ALT_ITEM
MAGLAYERS AS ALTERNATE
TABLE_ALT_ITEM
MAGLAYERS AS ALTERNATE
TABLE_ALT_ITEM
TOKO AS ALTERNATE
TABLE_ALT_ITEM
INTEL P7550 CPU AS ALTERNATE

TABLE_ALT_ITEM
TOKO AS ALTERNATE
TABLE_ALT_ITEM
MOLEX AS ALTERNATE
TABLE_ALT_ITEM
MOLEX AS ALTERNATE
TABLE_ALT_ITEM
SSM6P15FE AS ALTERNATE
A
DEVELOPMENT BOM
SYNC_MASTER=K24_MLB
PAGE TITLE
A
DRAWING NUMBER SIZE
BOM Configuration
Apple Inc.
PART NUMBER
085-1634
051-8563
REVISION
QTY
1
DESCRIPTION
K6 MLB_LDO DEVELOPMENT BOM
REFERENCE DES
DEVEL
CRITICAL
CRITICAL
BOM OPTION
DEVEL_BOM
A.13.0
BRANCH PAGE

4 OF 109
SHEET
4 OF 80
8
Revision History
SYNC_MASTER=K24_MLB
PAGE TITLE
A
Revision History
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

5 OF 109
SHEET
NOTE: All page numbers are .csa, not PDF.
See page 1 for .csa -> PDF mapping.
5 OF 80
Functional Test Points

DEBUG VOLTAGE
Fan Connectors
RIGHT CLUTCH CONN

(NEED 2 TP)
6 7 65 46 46
I303 I301 I302 I300 I299
I12 I15 I16
TRUE TRUE TRUE
PP5V_S0 FAN_RT_PWM FAN_RT_TACH

(NEED TO ADD 3 GND TP)
MIC FUNC_TEST
I238 I237 I239
I298 I293
TRUE TRUE TRUE
BI_MIC_LO BI_MIC_HI BI_MIC_SHIELD
55 56
I297
55 56
I294
55 56
I288 I292
I227 I226 I228 I230 I229 I231
SPEAKER FUNC_TEST SPKRAMP_L_N_OUT TRUE SPKRAMP_L_P_OUT TRUE SPKRAMP_R_N_OUT TRUE SPKRAMP_R_P_OUT TRUE SPKRAMP_SUB_N_OUT TRUE SPKRAMP_SUB_P_OUT TRUE
I296
54 55 54 55 54 55 54 55 54 55 54 55
I291 I295 I290 I271 I289
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP5V_S3_BTCAMERA_F PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N PP5V_WLAN PCIE_WAKE_L SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA USB_BT_CONN_P USB_BT_CONN_N AP_CLKREQ_Q_L AP_RESET_CONN_L
I287
29
I285
15 29 74
I414
15 29 74
I280
29 74
I281
29 74
I282
29 79
I283
29 79
I376
29 79
I278
29 79 6 29 15 24 29
I273
(NEED 2 TP)
I270
I416
6 42 78
I274
6 42 78
I275
29 79
I417
29 79
I392
29
I391
29
I390 I388
I418
IPD_FLEX_CONN
I375 I374 I372
I386 I383
LVDS FUNC_TEST
I370 I259 I258 I260 I245
I407
I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_LCDVDD_SW_F PP3V3_S0_LCD_F PPVOUT_SW_LCDBKLT BKL_VSYNC LVDS_DDC_CLK LVDS_DDC_DATA LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2> LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LED_RETURN_1 BKL_ISEN2 BKL_ISEN3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6
I371
6 67
I369
6 67
I368
67 70
I361
67 70
I366
8 67
I365
8 67
I363
8 67 74
I364
8 67 74
I362
8 67 74
I360
8 67 74
I359
8 67 74
I357
8 67 74
I358
67 79
I377
67 79
I378
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3 PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L
6 7
I419
6 48
I382
47 48
I381
47 48
I380
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PPVCORE_S0_CPU PPVCORE_S0_MCP PP1V2_ENET PP1V05_S0 PP1V5_S0 PP1V8_S0 PP3V3_S0 PP5V_S0 PP3V3_S3 PP5V_S3 PP0V9_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET PP5V_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP18V5_S3 PP3V3_S0_LCD_F PP3V3_LCDVDD_SW_F PP4V5_AUDIO_ANALOG PP1V5R1V35_S3 SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L
7 43 7 43 7 7 65 7 65 79 7 7 65 79 6 7 65 6 7 6 7 7 7 65 79 6 7 7 43 7 6 29 6 8 6 36 6 48 6 67 6 67 51 7 79 39 65 18 39 40 65 18 39 65 69
47 48 47 48 47 48 48 47 48 47 48 47 48 47 48 47 48 47 48 47 48 6 42 78 6 42 78 47 48 47 48
C
SPI DEBUG CONN
I421 I422 I423 I424 I425 I426
TRUE TRUE TRUE TRUE TRUE TRUE
PP3V42_G3H SPI_CS0_L SPI_CLK SPI_MOSI SPI_MISO SPIROM_USE_MLB
6 7 41 75 41 75 41 75 18 41 75 18 41 50
DC POWER CONN
I312 I304
67 70 70 70 67 70 67 70 67 70
I354 I355 I344 I345 I346 I347
(NEED 3 TP)
57 57
TRUE TRUE
PP18V5_DCIN_FUSE ADAPTER_SENSE
KEYBOARD CONN TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
6 7 6 7 47 47 47 47 47 47 47 47 47
SATA ODD CONN

I264
I349
I268 I269 I267 I265 I266
PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_ODD_R2D_P SATA_ODD_R2D_N

(NEED 4 TP)
36 39
I348
6 8
I350 I352
FSB SIGNALS WITH NOTEST

I396 NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE
36 79
I351
B
9 13 72 9 13 72 9 13 72 9 13 72 9 13 72 9 13 72 9 13 72 9 13 72 9 13 72 9 13 72 9 13 72
36 79
I353
47
36 74
I327
I399
47
36 74
I328 I329
I398
47
I397
47
I403
47
SATA HDD/IR/SIL
(NEED 3 TP)
I319 I314 I315 I318 I317 I307 I309 I311
I343 I342
I402
47
I400
47
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R IR_RX_OUT PP5V_S3_IR_R

I341
6 36
I339
I401
47
36 74
I340
I404
47
36 74
I338
I406
47
36 74
I336
I405
47 47 47 47 47 47 47 47
FSB_A_L<35..3> FSB_ADS_L FSB_ADSTB_L<1..0> FSB_D_L<63..0> FSB_DINV_L<3..0> FSB_DSTB_L_N<3..0> FSB_DSTB_L_P<3..0> FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L<4..0>
36 74
I337
36
I333
36 38
I335
36
I334 I332 I330 I331
BATT POWER CONN

I322 I321 I320
I305
TRUE TRUE TRUE TRUE
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L PPVBAT_G3H_CONN

(NEED 3 TP) (NEED TO ADD 4 GND TP)
6 42 78 6 42 78
I356
KBD BACKLIGHT CONN TRUE TRUE KBDLED_ANODE

SMC_KDBLED_PRESENT_L
48
57 57 58
I394
48
SYNC_MASTER=K24_MLB
PAGE TITLE
A
FUNC TEST
DRAWING NUMBER SIZE
BIL CONN
I326 I323 I324 I325 I308
T57 CONN PP3V42_G3H SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMC_BIL_BUTTON_L SMC_LID_R

6 7 6 42 78 6 42 78 39 40 57 57
TRUE TRUE TRUE TRUE TRUE
I408 I409 I410 I411 I413 I412
PP5V_S3 PP3V3_S3 T57_PWR_EN T57_RESET USB_T57_N USB_T57_P

6 7 6 7 18 18 38 75 38 75 R
Apple Inc.
051-8563
REVISION
A.13.0
BRANCH PAGE
7 OF 109
SHEET
6 OF 80
7
"S0,S0M" RAILS
4
"S3" RAILS
2
"G3H" RAILS
57 6 79
61
=PPVCORE_S0_CPU_REG
(CPU VCORE PWR)
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE
6 43
LVDDR (1.5V/1.35V) Rails

66
=PP5V_S0_FET
PP5V_S0
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE
6 65
60
=PPDDR_S3_REG
PP1V5R1V35_S3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE (OR
=PP3V42_G3H_REG
PP3V42_G3H
=PPVCORE_S0_CPU =PPCPUVTT_S0_REG PP1V05_S0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
10 11
=PP5V_S0_HDD
63 6 65
36 41 46 61 48 69 63 66 70 62 21
=PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT
=PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_PLL_UF_R =PP1V05_FW_P1V0FWFET =PP1V05_S0_FWPWRCTL
=PP5V_S0_CPU_IMVP
9 10 11 12 61 13 19 22 22 19 22 64 34 34 19 22 7 22 14 22 66 16 23 16 23
0 mA 4250 mA
=PP5V_S0_KBDLED =PP5VR3V3_S0_DPCADET =PP5V_S0_CPUVTTS0 =PP5V_S0_BKL =PP5V_S0_MCPREG =PP5V_S0_MCPFSBFET
1.35V) =PPLVDDR_S3_MEM_A =PPLVDDR_S3_MEM_B =PP1V5R1V35_S3_MCP_MEM =PP1V5R1V35_S0_MCPDDRFET =PPVIN_S0_DDRREG_LDO
=PPVIN_S5_SMCVREF
25 26 14 20 60
40 42 65 58 65 37 47 57 39 40 41 44 57 18 19 22 22
=PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PP3V42_G3H_BATT

=PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_BMON_ISNS
=PP3V3_S3_FET
PP3V3_S3
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PDCISENS
42 60 28 29 18 47 48 57 49 30 38 64
I1086
=PP3V42_G3H_ONEWIRE PP3V3_G3_RTC =PP3V42_G3H_OPA330
=PP1V05_SW_MCP_FSB =PP1V05_S0_MCP_PE_DVDD =PP1V05_S0_MCP_M2CLK_DLL =PP1V05_S0_MCP_PLL_IFP =PP1V05_S0_MCP_DP0_VDD
=PP3V3_S3_VREFMRGN =PP3V3_S0_FET PP3V3_S0

=PP3V3_S3_WLAN
6 65 79
=PP3V3_S3_MCP_GPIO =PP3V3_S3_TPAD =PP3V3_S3_SMS
=PP18V5_DCIN_CONN
PPDCIN_S5_S5
=PP3V3_S0_XDP =PP3V3_S0_MCP
62
12 19 22 64 41 36 42 42 42 59 46 51 55 56 61 67 16 17 18 22
=PP3V3_S3_CARDREADER =PP3V3_S3_T57 =PP3V3_ENET_P1V2ENET
=PPMCPCORE_S0_REG
(MCP VCORE AFTER SENSE RES)
PPVCORE_S0_MCP
6 43
=PP3V3_S0_P1V5S0 =PP3V3_S0_DEBUGROM =PP3V3_S0_ODD

19 22 21
=PPDCIN_S5_CHGR
58
=PPVCORE_S0_MCP =PPVCORE_S0_MCPGFXFET
=PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO
58
=PPBUS_G3H
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE
6 43
LVDDR VRef/VTT (0.75V/0.675V) Rails

60
=PP5V_S3_REG
PP5V_S3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE
=PPBUS_S0_LCDBKLT =PPVIN_S0_MCPCORE =PPVIN_S3_DDRREG =PPVIN_S5_3V3S5 =PPVIN_S3_5VS3 =PPBUS_S5_FWPWRSW
71 62 60 59 59 34
=PPVTT_S0_DDR_LDO
PPDDRVTT_S0
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE
=PP3V3_S0_IMVP
=PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO
=PP5V_S3_RTUSB =PP5V_S3_IR =PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED =PP5V_S3_TPAD
37 36 38 20 40 48 29 60 51 53 55 54 66 36 29 38 44
C
60 28
=PP3V3_S0_MCP_PLL_UF
=PPDDRVTT_S0_MEM_A =PPDDRVTT_S0_MEM_B
25 26
=PP3V3_S0_MCP_HVDD =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS
19 22 40 45 45 69 25 26 65 31 44 48 42 64 70 44
=PP5V_S3_WLAN
=PP5V_S3_DDRREG =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP =PP5V_S3_P5VS0FET =PP5V_S0_ODD
=PP5V_S3_BTCAMERA =PP5V_S3_T57
=PPBUS_S5_CPUREGS_ISNS_R
44
=PPVTT_S3_DDR_BUF
PPDDRVREF_S3
=PP3V3_S0_DPCONN =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL =PP3V3_S0_ENETPHY =PP3V3_S0_CPUVTTISNS
(BEFORE HIGH SIDE SENSING RES.)
=PPBUS_S5_CPUREGS_ISNS
(AFTER HIGH SIDE CPU VCORE & CPU VTT SENSING RES.)
PPBUS_S5_IMVP_VTT_ISNS
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE
64
=PP1V5_S0_REG
PP1V5_S0
6 65 79
=PP3V3_S0_TPAD =PP3V3_S0_SMBUS_MCP_1 =PP3V3_S0_P1V8S0 =PP3V3_S0_BKL_VDDIO =PP3V3_S0_MCPDDRISNS =PP3V3_S0_MCP_PLL_VLDO =PP3V3_S0_FWPWRCTL =PP3V3_S0_FWLATEVG =PP3V3_S0_SDCONN =PP3V3_S0_MCPCOREISNS =PP3V3_S0_MCP_HDA_R
=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP
63 61
=PP1V5_S0_CPU =PP1V5_S0_SATARDRVR =PP1V5_S0_MCP_PLL_VLDO =PP1V8R1V5_S0_AUDIO =PP1V5_S0_MCP_HDA_R =PP1V5_S0_AUDIO_R
10 11 36
51 8 8
34 34 35 30 44 8 8 22
"FIREWIRE" RAILS "S5" RAILS

59 34
64
=PP1V8_S0_REG
PP1V8_S0
=PP3V3_S0_AUDIO_R =PP3V3_S0_OPA333
=PP3V3_FW_FET
PP3V3_FW
=PP3V3R1V8_S0_MCP_IFP_VDD
16 23
B
64 =PP1V05_S0_MCP_PLL_OR
=PP1V8_S0_AUDIO
"ENET" RAILS
8
=PP3V3_S5_REG
PP3V3_S5
6 65 79
=PP3V3_FW_FWPHY
33 34 35
PP1V05_S0_MCP_PLL_UF
=PP3V3_ENET_FET_R 400mA
PP3V3_ENET
=PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR
17 18 50 67 19 22 24 66 66 66 69 64 34 66 65 42 34 34
=PPBUS_FW_FET
PPVP_FW
=PP1V05_S0_MCP_PLL_UF
22
300mA ~100mA
=PP3V3_ENET_MCP_RMGT 17 19 22 =PP3V3_ENET_MCP_PLL_MAC 22 =PP3V3_ENET_PHY 24 31 64 =PP3V3_ENET_PWRCTL 65
=PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET
35 35
64
(BCM5764M) =PP1V2_ENET_REG
PP1V2_ENET
=PP1V0_FW_FET_R
PP1V05_FW
=PP3V3_S5_P0V9S5 =PP3V3_FW_P3V3FWFET =PP3V3_S5_P0V9ENETFET
UNUSED MCP PE0[3:0] AVDD/DVDD

19
700 mA max output =PP1V2_ENET_PHY_REG 64 (BCM57765) ~400mA
=PP1V2_ENET_PHY
=PP1V0_FW_FWPHY
33 34
31
=PP3V3_S5_VMON =PP3V3_S5_SMBUS_SMC_MGMT
=PP1V05_S0_MCP_PE_DVDD0 =PP1V05_S0_MCP_PE_AVDD0
19
(SINCE PE0[3:0] IS NOT USED ON K6)

66
=PP0V9_ENET_FET
PP0V9_ENET
(CONNECTS TO MCP BALLS) (CONNECTS TO MCP BALLS)
19
=PP1V05_S0_MCP_PE_DVDD1 =PP1V05_S0_MCP_PE_AVDD1
=PP1V05_S0_MCP_PE_DVDD PP1V05_S0_MCP_PE_AVDD
MAKE_BASE=TRUE
7 22 22
(CONNECTS TO THE DECAPS) (CONNECTS TO THE DECAPS)
0.9V Rails
19 22 64
=PP0V9_ENET_MCP_RMGT
19
=PP0V9_S5_REG
PP0V9_S5
105 mA/241 mA 139 mA/ 0 mA
=PP0V9_S5_MCP_VDD_AUXC =PP0V9_ENET_P0V9ENETFET
19 22 66
SYNC_MASTER=K24_MLB
PAGE TITLE
Power Aliases
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

8 OF 109
SHEET
7 OF 80
7
HEATSINK STANDOFFS
Z0902 Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
1
6
PCI-E ALIASES
UNUSED GPU LANES
15
5
=PEG_D2R_N<3:0> =PEG_D2R_P<3:0> =PEG_R2D_C_N<3:0> =PEG_R2D_C_P<3:0> PEG_CLK100M_P PEG_CLK100M_N
PEG_CLKREQ_L
4
DACS ALIASES
UNUSED CRT & TV-OUT INTERFACE
74
MAKE_BASE=TRUE
3
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
MAKE_BASE=TRUE
2
CPU ALIASES
72 9
1
=MCP_BSEL<0:2> TP_CPU_PECI_MCP
MAKE_BASE=TRUE
NC_PEG_D2R_N<3:0>
NO_TEST=TRUE
MCP_TV_DAC_RSET MCP_TV_DAC_VREF MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT
15
NC_PEG_D2R_P<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
CPU_BSEL<0:2>
MAKE_BASE=TRUE
13 BSEL<2..0>
FSB MHZ 266 133 200 (166) 333 100 (400) (RSVD)
STDOFF-4.5OD.98H-1.1-3.48-TH
1
74
NC_MCP_TV_DAC_VREF
NO_TEST=TRUE
MAKE_BASE=TRUE
15
NC_PEG_R2D_C_N<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
13
CPU_PECI_MCP
NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE
MAKE_BASE=TRUE
15
NC_PEG_R2D_C_P<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_CLK27M_XTALOUT
NO_TEST=TRUE
MAKE_BASE=TRUE
LEFT OF CPU
ABOVE CPU
74 15
TP_PEG_CLK100M_P
MAKE_BASE=TRUE
74
CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC
NC_CRT_IG_R_C_PR
NO_TEST=TRUE
MAKE_BASE=TRUE
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
74 15
TP_PEG_CLK100M_N
MAKE_BASE=TRUE
Z0903
Z0904
STDOFF-4.5OD.98H-1.1-3.48-TH
1
15
74
NC_CRT_IG_G_Y_Y
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PEG_CLKREQ_L
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
1
74
NC_CRT_IG_B_COMP_PB
NO_TEST=TRUE
MAKE_BASE=TRUE
MCP89 ALIASES
TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF NC_MCP_RGB_RED
MAKE_BASE=TRUE 16
NO_TEST=TRUE
D
NO_TEST=TRUE
74
NC_CRT_IG_HSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
BELOW MCP
BELOW CPU
75 17 75 17 75 17 75 17
USB ALIASES
UNUSED USB PORTS
74
NC_CRT_IG_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
16
NC_MCP_RGB_GREEN
MAKE_BASE=TRUE
FAN STANDOFF
Z0905
STDOFF-4.5OD.98H-1.1-3.48-TH
1
75 17 75 17 75 17 75 17
USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_WM_P USB_WM_N USB_MINI_P USB_MINI_N
TP_USB_EXTCP TP_USB_EXTCN TP_USB_EXTDP TP_USB_EXTDN TP_USB_WMP TP_USB_WMN TP_USB_MINIP TP_USB_MININ
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
LVDS ALIASES
16 16 16 16
16
NC_MCP_RGB_BLUE
MAKE_BASE=TRUE
NO_TEST=TRUE
=MCP_IFPA_TXC_P =MCP_IFPA_TXC_N =MCP_IFPA_TXD_P<0..2> =MCP_IFPA_TXD_N<0..2> =MCP_IFPA_TXD_P<3> =MCP_IFPA_TXD_N<3> =MCP_IFPB_TXC_P =MCP_IFPB_TXC_N =MCP_IFPB_TXD_P<0..3> =MCP_IFPB_TXD_N<0..3> LCD_IG_BKLT_PWM LCD_IG_BKLT_EN =MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA
LVDS_IG_A_CLK_P MAKE_BASE=TRUE LVDS_IG_A_CLK_N MAKE_BASE=TRUE LVDS_IG_A_DATA_P<0..2> MAKE_BASE=TRUE LVDS_IG_A_DATA_N<0..2>

MAKE_BASE=TRUE
67 74 67 74
16
NC_MCP_RGB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
16 6 67 74 6 67 74 16
NC_MCP_RGB_VSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_DAC_RSET
MAKE_BASE=TRUE
NO_TEST=TRUE
16
MAKE_BASE=TRUE
16 16
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
ETHERNET ALIASES
PLACE_NEAR=U7980.A1:5MM
16 16 16
NC_LVDS_IG_A_DATAP<3> NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_A_DATAN<3> NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKN NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_DATAP<0..3>NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_DATAN<0..3>NO_TEST=TRUE
MAKE_BASE=TRUE
16
NC_MCP_RGB_DAC_VREF
MAKE_BASE=TRUE
NO_TEST=TRUE
5V ODD ALIASES
6
R0911
PP5V_SW_ODD
MAKE_BASE=TRUE
MLB MOUNTING (TO C. BRACKET) SCREW HOLES

OMIT OMIT
PP3V3_ENET_FET
66
16
=PP3V3_ENET_FET_R
OUT
16
LCD_BKLT_PWM LCD_BKLT_EN
LVDS_DDC_CLK LVDS_DDC_DATA
70 MAKE_BASE=TRUE 71 MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.4 MM VOLTAGE=5V
=PP5V_SW_ODD =PP5V_SW_ODD_FET
36 36
Z0906
3R2P5
1
Z0907
3R2P5
1
=PP3V3_ENET_FET
5% 1/16W MF-LF 402
16 16
6 67 MAKE_BASE=TRUE 6 67 MAKE_BASE=TRUE
BACKLIGHT CONTROLLER ALIASES

R0910
71 70
PPBUS_SW_LCDBKLT_PWR
PLACE_NEAR=L9701.1:5MM PPBUS_SW_BKL
ENET_RXD_PD
MAKE_BASE=TRUE
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_CLK125M_RXCLK ENET_RX_CTRL ENET_MDIO MCP_RGMII_VREF ENET_LOW_PWR
OUT OUT OUT OUT OUT OUT BI OUT OUT
17 76 17 76 17 76 17 76
5% 1/16W MF-LF 402
=PPBUS_SW_BKL
70
ENET_RXCLK_PD
MAKE_BASE=TRUE
17 76
17 76
DISPLAY PORT ALIASES

16 16
17 76
17 18 31
MLB MOUNTING (TO TOPCASE) SCREW HOLES

OMIT OMIT OMIT
R0980 1
10K
5% 1/16W MF-LF 402
R0981
10K
5% 1/16W MF-LF 402
R0984 1
10K
5% 1/16W MF-LF 402
NO STUFF R0986
10K
5% 1/16W MF-LF 402
Z0908
3R2P5
1
Z0909
3R2P5
1
Z0910
3R2P5
1
DP_IG_ML0_P<0..3> 74 DP_IG_ML0_N<0..3> 74 DP_IG_HPD0 16 DP_IG_AUX_CH0_P 16 DP_IG_AUX_CH0_N 16 DP_AUX_CH_C_N 68 DP_AUX_CH_C_P 68 DP_CA_DET 68
DP_IG_ML_P<0..3> DP_IG_ML_N<0..3>
DP_EXT_HPD DP_IG_AUX_CH_P DP_IG_AUX_CH_N
DP_EXT_ML_P<0..3> DP_EXT_ML_N<0..3>
69
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
69 79 69 79
68 74
MAKE_BASE=TRUE
CHARGER SIGNAL
58
68 74
MAKE_BASE=TRUE
DP_EXT_AUX_CH_C_N DP_EXT_AUX_CH_C_P
DP_EXT_CA_DET
69 79
MAKE_BASE=TRUE
IN
=CHGR_ACOK
SMC_BC_ACOK
MAKE_BASE=TRUE
OUT
39 40 57
69 79
MAKE_BASE=TRUE
69
MAKE_BASE=TRUE
R0982
10K
R0983
10K
5% 1/16W MF-LF 402
16 16 16 16
OMIT
OMIT
Z0911
3R2P5
1
Z0912
3R2P5
1
5% 1/16W MF-LF 402
DP_IG_ML1_P<0..3> DP_IG_ML1_N<0..3> DP_IG_AUX_CH1_P DP_IG_AUX_CH1_N
TP_DP_IG_ML1P<0..3> TP_DP_IG_ML1N<0..3> TP_DP_IG_AUX_CH1P TP_DP_IG_AUX_CH1N
MAKE_BASE=TRUE MAKE_BASE=TRUE
MCPCOREISNS SIGNAL
62
MCPCORES0_VO
MCPCOREISNS_N
MAKE_BASE=TRUE
=MCPCOREISNS_N =MCPCOREISNS_P
44
MAKE_BASE=TRUE MAKE_BASE=TRUE
R0920
16
62
MCPCORES0_ISP_R
MCPCOREISNS_P
MAKE_BASE=TRUE
44
DP_IG_HPD1
100K
B
EMI IO (SHORT) POGO PINS
402 5% MF-LF 1/16W
AUDIO ALIASES
HDA:1.5V
ZS0900
1
ZS0901
1
ZS0902
1
=PP1V5_S0_AUDIO_R =PP3V3_S0_AUDIO_R
R0912
HDA:3.3V
0
402
PP3V3R1V5_S0_AUDIO
MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm
51
1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24 SM SM SM

7
R0913
HDA:1.5V
5% 1/16W MF-LF 2 5% 1/16W MF-LF
=PP3V3R1V5_S0_AUDIO
402
=PP1V5_S0_MCP_HDA_R =PP3V3_S0_MCP_HDA_R
R0914
HDA:3.3V
0
402
PP3V3R1V5_S0_MCP_HDA
MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm
18 22
ZS0903
1
ZS0908
1
ZS0909
7
1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24 SM SM SM

1
R0915
5% 1/16W MF-LF 2 5% 1/16W MF-LF
=PP3V3R1V5_S0_MCP_HDA
402
A
ZS0904
SM
1 1
EMI TALL POGO PINS

ZS0905
SM
1
SYNC_MASTER=K24_MLB
PAGE TITLE
A
SIGNAL ALIAS
DRAWING NUMBER SIZE
ZS0906
SM
ZS0907
SM
1
R
2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
Apple Inc.
051-8563
REVISION
A.13.0
BRANCH PAGE
9 OF 109
SHEET
8 OF 80
8
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
7
OMIT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
6
ADS* BNR* BPRI* DEFER* DRDY* DBSY* H1 E2 G5 H5 F21 E1 F1 D20 B3
72
5
6 13 72 13 72 13 72
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_ADSTB_L<0> FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1> CPU_A20M_L CPU_FERR_L CPU_IGNNE_L CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*
U1000
PENRYN
FCBGA 1 OF 4
FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L FSB_BREQ0_L CPU_IERR_L CPU_INIT_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L FSB_HIT_L FSB_HITM_L XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L
BI BI BI
=PP1V05_S0_CPU
7 10 11 12 61
BI BI BI
13 72 13 72 13 72
R10001
54.9
1% 1/16W MF-LF 402 2
ADDR GROUP0
BR0* CONTROL IERR* INIT*
BI
13 72
D
IN
13 72
LOCK* H4
BI
6 13 72
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
BI BI BI BI BI
K3 H2 K2 J3 L1
REQ0* REQ1* REQ2* REQ3* REQ4*
RESET* RS0* RS1* RS2* TRDY*
C1 F3 F4 G3 G2
IN IN IN IN IN
12 13 72 13 72 13 72 13 72 13 72
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*
HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*
G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
BI BI
6 13 72 6 13 72 72 13 6
OMIT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI
12 72 12 72 12 72 12 72 12 72
R10011
54.9
1% 1/16W MF-LF 402 2 BI
12 72
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
IN IN OUT IN IN OUT
9 12 72 9 12 72 9 12 72 9 12 72 9 12 72 12 24
R10021
68
5% 1/16W MF-LF 402 2
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
THERMAL PROCHOT* THERMDA THERMDC THERMTRIP* ICH D21 A24 B25 C7
CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N PM_THRMTRIP_L
OUT OUT OUT

45 79 45 79
13 40 61 72
72 13 6 72 13 6
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*
U1000
PENRYN
FCBGA 2 OF 4
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>
6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72
XDP/ITP SIGNALS
ADDR GROUP1
DATA GRP 0
DATA GRP 2
72 13 72 13 72 13
IN OUT IN
A6 A20M* A5 FERR* C4 IGNNE* D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 STPCLK* LINT0 LINT1 SMI* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
OUT
13 40 72
72 13 6 72 13 6
72 28
H CLK
72 13 6 72 13 6 72 13 6
72 13 72 13 72 13 72 13
IN IN IN IN
BCLK0 BCLK1
A22 A21
FSB_CLK_CPU_P FSB_CLK_CPU_N
IN IN
13 72 13 72
72 13 6 72 13 6 72 13 6 72 13 6 72 13 6 72 13 6
RESERVED
72 13 6 72 13 6 72 13 6 72 13 6
R1005
1K PLACE_NEARs:
R1005.2: U1000.AD26:12.7 mm R1006.1: U1000.AD26:12.7 mm C1014.1: U1000.AF26:12.7 mm
72 13 6 72 13 6 72 13 6 72 13 6
B
72 12 9 72 12 9
CPU JTAG Support R1090

XDP_TMS
1
1% 1/16W MF-LF 2 402
FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1> CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2
D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
72 72 72 72
FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_DSTB_L_N<3> FSB_DSTB_L_P<3> FSB_DINV_L<3> CPU_COMP<0> CPU_COMP<1> CPU_COMP<2> CPU_COMP<3> CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L
6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72 6 13 72
DATA GRP 1
DATA GRP 3
54.9 2
1% 1/16W MF-LF 402
MISC
R1091
XDP_TDI 54.9 2 1
1% 1/16W MF-LF 402
R1006
2.0K NO STUFF
R1092
1
72 12 9
XDP_TDO
54.9 2
1% 1/16W MF-LF 402
1% 1/16W MF-LF 2 402
C1014 1
NO STUFF 0.1uF
IN IN IN IN IN OUT
13 61 72 13 72 13 72 12 13 72 13 72 61
R10231
54.9
1% 1/16W MF-LF 402 2
R10211
54.9
1% 1/16W MF-LF 402 2
PLACE_NEAR=J1300.51:12.7 mm
R1010
1
10% 16V 2 X5R 402
72 8 72 8 72 8
OUT OUT OUT
NO STUFF
R1093
72 12 9
R10111
1K
5% 1/16W MF-LF 402 2
XDP_TCK
54.9 2 1
1% 1/16W MF-LF 402
5% 1/16W MF-LF 402
NO STUFF
1
R1022
27.4
R1020
27.4
R1012
1K
R1094
72 12 9
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
XDP_TRST_L
649
PLACE_NEARs:
R1020.1: U1000.R26:12.7 mm R1021.1: U1000.U26:12.7 mm R1022.1: U1000.AA1:12.7 mm R1023.1: U1000.Y1:12.7 mm
1% 1/16W MF-LF 402
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU FSB
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

10 OF 109
SHEET
9 OF 80
A4
P6 P21 OMIT
(CPU CORE POWER) =PPVCORE_S0_CPU

7 10 11
A8 A11 A14
U1000
PENRYN
FCBGA
P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 OMIT
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18
44 41 30.4 23
A A A A
(SV (SV (SV (LV
Design Target) HFM) LFM) Design Target)
A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11
4 OF 4
U1000
PENRYN
FCBGA
3 OF 4
VCC
AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14
D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9
VCC
AF15 AF17 AF18 AF20
(CPU IO POWER 1.05V) =PP1V05_S0_CPU

7 9 11 12 61
E14 E16 E19
VSS
VSS
AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25
G21 V6 J6 K6 M6 J21 K21
4500 mA (before VCC stable) 2500 mA (after VCC stable)
E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23
VCCP
M21 N21 N6 R21 R6 T21 T6 V21 W21
(CPU INTERNAL PLL POWER 1.5V) =PP1V5_S0_CPU

7 11
G26 H3 H6
(BR1#)
B26
AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6
C26
130 mA
H21 H24
AD6 AF5 AE5 AF4 AE3 AF3 AE2
CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>
OUT OUT OUT OUT OUT OUT OUT
61 72 61 72 61 72 61 72 61 72 61 72 61 72
J2 J5 J22
=PPVCORE_S0_CPU
1
7 10 11
J25 K1
R1100
100
1% 1/16W MF-LF 402
K4 K23 K26 L3
VCCSENSE
AF7
CPU_VCCSENSE_P
OUT
61 72
L6 L21 L24
PLACE_NEAR=U1000.AF7:25.4 mm PLACE_NEAR=U1000.AE7:25.4 mm
VSSSENSE
AE7
CPU_VCCSENSE_N
OUT
1
61 72
M2 M5
R1101
100
1% 1/16W MF-LF 402
M22 M25 N1 N4 N23 N26 P3 B1
(Socket-P KEY)
AF25
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU Power & Ground

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

11 OF 109
SHEET
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
10 OF 80
CPU VCore HF and Bulk Decoupling

4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219): Place inside socket cavity on secondary side.
10 7
=PPVCORE_S0_CPU
CPU_CAP:15&CPU_CAP:12 CPU_CAP:15&CPU_CAP:12 NO STUFF NO STUFF CRITICAL CRITICAL CRITICAL CRITICAL

1
CPU_CAP:15&CPU_CAP:12 NO STUFF CRITICAL

1
D
NO STUFF CRITICAL
1
CPU_CAP:15 CRITICAL CRITICAL

1
NO STUFF CRITICAL
1
NO STUFF CRITICAL
1
C1200
22UF
C1201
22UF
C1202
22UF
C1203
22UF
C1204
22UF
C1205
22UF
C1206
22UF
C1207
22UF
C1208
22UF
C1209
22UF
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
CPU_CAP:15&CPU_CAP:12 CPU_CAP:15&CPU_CAP:12 CPU_CAP:15&CPU_CAP:12 CPU_CAP:15&CPU_CAP:12 CPU_CAP:15&CPU_CAP:12 CPU_CAP:15&CPU_CAP:12 CPU_CAP:15&CPU_CAP:12 NO STUFF CPU_CAP:15&CPU_CAP:12 CPU_CAP:15 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C1210
22UF
C1211
22UF
C1212
22UF
C1213
22UF
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
22UF
C1214
C1215
22UF
C1216
22UF
C1217
22UF
C1218
22UF
C1219
22UF
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
PLACEMENT_NOTE (C1240-C1243): CPU_CAP:15&CPU_CAP:12 NO STUFF CPU_CAP:15 CRITICAL CRITICAL CRITICAL

1
C1220
22UF
C1221
22UF
C1222
22UF
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
20% 6.3V 2 X5R-CERM 603
C
Place on secondary side. CRITICAL NO STUFF
1
C
CRITICAL
1
CRITICAL
1
CRITICAL
1
C1240
470UF-4MOHM
3
C1241
470UF-4MOHM
3
C1242
470UF-4MOHM
3
C1243
470UF-4MOHM
20% 3 2 2.0V POLY-TANT D2T-SM
20% 2 2.0V POLY-TANT D2T-SM
VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF
10 7
=PP1V5_S0_CPU BYPASS=U1000.B26::4 mm
C1250 1
10uF
C1251
0.01UF
20% 6.3V X5R 2 603
10% 16V 2 CERM 402
VCCP (CPU I/O) DECOUPLING

1x 330uF, 6x 0.1uF 0402
61 12 10 9 7
=PP1V05_S0_CPU CRITICAL
PLACEMENT_NOTE=Place C1260 between CPU & NB.

1 1
C1260
330UF
C1261
0.1UF
C1262
0.1UF
C1263
0.1UF
C1264
0.1UF
C1265
0.1UF
C1266
0.1UF
20% 2.0V 2 POLY-TANT D2T-SM2
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU Decoupling
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

12 OF 109
SHEET
11 OF 80
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
Use with 920-0620 adapter board to support CPU, MCP debugging.
MCP89-specific pinout
=PP3V3_S0_XDP =PP1V05_S0_CPU XDP CRITICAL
7 61 11 10 9 7
R1315 1
54.9
1% 1/16W MF-LF 402 2
XDP_CONN J1300
LTH-030-01-G-D-NOPEGS
F-ST-SM 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7
72
72 9 72 9
BI BI
XDP_BPM_L<5> XDP_BPM_L<4> XDP_BPM_L<3> XDP_BPM_L<2> XDP_BPM_L<1> XDP_BPM_L<0> TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1 TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1 TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3
OBSFN_A0 OBSFN_A1
4 6 8
OBSFN_C0 OBSFN_C1
JTAG_MCP_TDO JTAG_MCP_TRST_L TP_XDP_OBSDATA_C0 TP_XDP_OBSDATA_C1 TP_XDP_OBSDATA_C2 TP_XDP_OBSDATA_C3 JTAG_MCP_TDI JTAG_MCP_TMS TP_XDP_OBSDATA_D0 TP_XDP_OBSDATA_D1 TP_XDP_OBSDATA_D2 TP_XDP_OBSDATA_D3 FSB_CLK_ITP_P FSB_CLK_ITP_N XDP_CPURST_L XDP_DBRESET_L XDP_TDO XDP_TRST_L XDP_TDI XDP_TMS
IN OUT
18 18
72 9 72 9
BI IN
OBSDATA_A0 OBSDATA_A1
10 12 14
OBSDATA_C0 OBSDATA_C1
72 9 72 9
IN IN
OBSDATA_A2 OBSDATA_A3
16 18 20
OBSDATA_C2 OBSDATA_C3
OBSFN_B0 OBSFN_B1
22 24 26
OBSFN_D0 OBSFN_D1
OUT OUT
18 18
OBSDATA_B0 OBSDATA_B1
28 30 32
OBSDATA_D0 OBSDATA_D1
XDP
OBSDATA_B2 OBSDATA_B3
34 36 38
OBSDATA_D2 OBSDATA_D3
R1399
72 13 9
IN
CPU_PWRGD
1K
5% 1/16W MF-LF 402
XDP_PWRGD XDP_OBS20
18 18
PWRGD/HOOK0 HOOK1 VCC_OBS_AB
40 42 44 46 48 50
IN IN
13 72 13 72
XDP
R1303
1
IN OUT
PM_LATRIGGER_L JTAG_MCP_TCK SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK XDP_TCK
1K
5% 1/16W MF-LF 402
HOOK2 HOOK3
FSB_CPURST_L
IN
9 13 72
OUT
9 24
PLACEMENT_NOTE=Place close to CPU to minimize stub.
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. TDO TRSTn TDI TMS XDP_PRESENT#
75 42 18 75 42 18
BI BI
SDA SCL TCK1
52 54
IN OUT OUT OUT
9 72 9 72 9 72 9 72
NC
56 58 60
72 9
OUT
TCK0
XDP
XDP
1 1
C1300
0.1uF
10% 16V X5R 402
998-1571
2 2
C1301
0.1uF
10% 16V X5R 402
Direction of XDP module

Please avoid any obstructions on even-numbered side of J1300
SYNC_MASTER=T27_MLB
PAGE TITLE
eXtended Debug Port (mini-XDP)

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

13 OF 109
SHEET
12 OF 80
5
OMIT
4
U1400
MCP89M-A01
FBGA (1 OF 11)
72 9 6 72 9 6 72 9 6
BI BI BI BI BI BI BI BI BI BI BI BI
FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_DINV_L<0> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_DINV_L<1> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_DINV_L<2> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_DINV_L<3> FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<0> FSB_ADSTB_L<1> FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> FSB_ADS_L FSB_BNR_L FSB_BREQ0_L FSB_DBSY_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_TRDY_L CPU_PECI_MCP CPU_PROCHOT_L
K34 K35 L37 T31 T30 P28 K33 K32 N35 C36 D36 A35 U38 U34 U35 T34 W37 W38 T37 Y38 W35 Y36 U33 W34 Y37 Y35 AF38 AB35 Y34 AE38 AC36 AF36 AC38 AB36 AB38 AB37 AC34 AE36 AF37 AC37 AC35 AE37 AE35 AE33 AE34 W36 AB34 U36 T36 U37 T38 T35 AE31 AE32 AE30 AE29 U29 W32 AB31 AC32 AC29 AH34 U28 W33 AB32 B34 C34 A34
CPU_DSTBP0* CPU_DSTBN0* CPU_DBI0* CPU_DSTBP1* CPU_DSTBN1* CPU_DBI1* CPU_DSTBP2* CPU_DSTBN2* CPU_DBI2* CPU_DSTBP3* CPU_DSTBN3* CPU_DBI3* CPU_A3* CPU_A4* CPU_A5* CPU_A6* CPU_A7* CPU_A8* CPU_A9* CPU_A10* CPU_A11* CPU_A12* CPU_A13* CPU_A14* CPU_A15* CPU_A16* CPU_A17* CPU_A18* CPU_A19* CPU_A20* CPU_A21* CPU_A22* CPU_A23* CPU_A24* CPU_A25* CPU_A26* CPU_A27* CPU_A28* CPU_A29* CPU_A30* CPU_A31* CPU_A32* CPU_A33* CPU_A34* CPU_A35* CPU_ADSTB0* CPU_ADSTB1* CPU_REQ0* CPU_REQ1* CPU_REQ2* CPU_REQ3* CPU_REQ4* CPU_ADS* CPU_BNR* CPU_BR0* CPU_DBSY* CPU_DRDY* CPU_HIT* CPU_HITM* CPU_LOCK* CPU_TRDY* CPU_PECI CPU_PROCHOT* CPU_THERMTRIP* CPU_FERR* CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_RS0* CPU_RS1* CPU_RS2*
72 9 6 72 9 6 72 9 6
72 9 6 72 9 6 72 9 6
72 9 6 72 9 6 72 9 6
72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6 72 9 6
72 9 6 72 9 6
72 9 6 72 9 6 72 9 6 72 9 6 72 9 6
BI BI BI BI BI
72 9 6 72 9
IN IN IN IN IN IN IN IN BI
B
22 19 13 7
72 9 72 9
=PP1V05_S0_MCP_FSB
72 9 72 9 6 72 9 6
CPU_D0* CPU_D1* CPU_D2* CPU_D3* CPU_D4* CPU_D5* CPU_D6* CPU_D7* CPU_D8* CPU_D9* CPU_D10* CPU_D11* CPU_D12* CPU_D13* CPU_D14* CPU_D15* CPU_D16* CPU_D17* CPU_D18* CPU_D19* CPU_D20* CPU_D21* CPU_D22* CPU_D23* CPU_D24* CPU_D25* CPU_D26* CPU_D27* CPU_D28* CPU_D29* CPU_D30* CPU_D31* CPU_D32* CPU_D33* CPU_D34* CPU_D35* CPU_D36* CPU_D37* CPU_D38* CPU_D39* CPU_D40* CPU_D41* CPU_D42* CPU_D43* CPU_D44* CPU_D45* CPU_D46* CPU_D47* CPU_D48* CPU_D49* CPU_D50* CPU_D51* CPU_D52* CPU_D53* CPU_D54* CPU_D55* CPU_D56* CPU_D57* CPU_D58* CPU_D59* CPU_D60* CPU_D61* CPU_D62* CPU_D63*
N38 N36 P36 L36 N34 L35 P37 P38 H36 L34 K37 K36 K38 N37 H37 L38 N28 U30 N29 P34 T29 T32 U32 T33 P31 P30 N30 P33 N31 T28 P35 P29 H33 G34 L30 L31 L33 P32 N32 N33 H35 K31 H34 K30 L32 G33 H32 G35 C37 D37 H38 G38 G37 G36 B35 E35 B36 E36 C35 D34 E38 D38 E34 E37
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_BPRI_L FSB_DEFER_L FSB_CLK_CPU_N FSB_CLK_CPU_P FSB_CLK_ITP_N FSB_CLK_ITP_P
72 72
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72 6 9 72
FSB
R1410
54.9
R1415
62
72 9 6 72 9
1% 1/16W MF-LF 402 2

72 40 9 72 9
5% 1/16W MF-LF 2 402
CPU_BPRI* Y31 CPU_DEFER* Y30 BCLK_OUT_CPU_N AF32 BCLK_OUT_CPU_P AF33 BCLK_OUT_ITP_N AF35 BCLK_OUT_ITP_P AF34 BCLK_OUT_NB_N AF28 BCLK_OUT_NB_P AF29 BCLK_IN_P AF30 BCLK_IN_N AF31
W30 AB30 AB28 W31 AC30 AC28 Y32 AE28 G1 Y33 AB33 U31 Y29 W29
OUT OUT
9 72 9 72
8 72 61 40 9
OUT OUT
IN IN
PM_THRMTRIP_L CPU_FERR_L =MCP_BSEL<2> =MCP_BSEL<1> =MCP_BSEL<0>

72 9
OUT OUT OUT OUT
9 72 9 72
12 72 12 72
8 8 8
IN IN IN
FSB_CLK_MCP_N FSB_CLK_MCP_P Loop-back clock for delay matching.
OUT OUT OUT
R14301
49.9
1% 1/16W MF-LF 402 2
R1435
49.9
72 9 72 9
FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2>
AB29 AC33 AC31
1% 1/16W MF-LF 2 402

72 72
MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND
AH37 AH38 AH36 AH35
BCLK_VML_COMP_VDD BCLK_VML_COMP_GND CPU_COMP_VCC CPU_COMP_GND
A
R1431
49.9
1 1
72 72
R1436
49.9
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
CPU_A20M* CPU_IGNNE* CPU_INIT* CPU_INTR CPU_NMI CPU_SMI* CPU_PWRGD CPU_RESET* CPU_DPRSLPVR CPU_SLP* CPU_DPSLP* CPU_DPWR* CPU_STPCLK* CPU_DPRSTP*
CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L PM_DPRSLPVR FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L
OUT OUT OUT OUT OUT OUT
9 72 9 72 9 72 9 72 9 72 9 72
=PP1V05_S0_MCP_FSB NO STUFF
1
7 13 19 22
R1440
150
5% 1/16W MF-LF 2 402
SYNC_MASTER=T27_MLB
OUT
9 12 72
PAGE TITLE
OUT OUT OUT OUT OUT OUT OUT
9 12 72 61 72 9 72 9 72 9 72 9 72 9 61 72
MCP CPU Interface

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

14 OF 109
SHEET
13 OF 80
7
OMIT
3
OMIT
U1400
MCP89M-A01
FBGA (2 OF 11)
73 27 73 27 73 27 73 27
U1400
MCP89M-A01
FBGA (3 OF 11) MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
AN7 AM7 AN10 AM10 AN13 AM13 AL16 AK16 AH28 AJ28 AM29 AN29 AP34 AP35 AH31 AG31
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT
73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27
73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27
73 27 73 27 73 27 73 27 73 27 73 27 73 27
MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0> MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>
AP5 AP7 AR8 AP8 AR4 AR5 AM8 AN8 AK11 AL11 AH13 AH14 AL10 AK10 AN11 AJ13 AK13 AK14 AJ16 AH16 AJ14 AL13 AM14 AN14 AK17 AL17 AN17 AJ19 AH17 AJ17 AM16 AM17 AN26 AH29 AK29 AL29 AM25 AM26 AL28 AK28 AM28 AP29 AL31 AN32 AP28 AN28 AN31 AM31 AR34 AM32 AL33 AL35 AP32 AP33 AM35 AL32 AJ35 AJ31 AH32 AH33 AJ34 AL34 AJ33 AJ32 AR7 AM11 AL14 AN16 AJ29 AP31 AM34 AJ30
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0> MEM_A_A<15> MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73
73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT

73 73
MRAS0* AN19 MCAS0* AL19 MWE0* AL20
73 27
OUT OUT OUT
25 73 73 27 25 73 73 27 25 73 73 27 73 27
MBA0_2 AL25 MBA0_1 AN20 MBA0_0 AM19 MA0_15 AK26 MA0_14 AK25 MA0_13 AJ20 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
AJ26 AH25 AM20 AH26 AN23 AJ25 AM22 AM23 AN22 AL23 AK22 AK23 AL22
OUT OUT OUT
25 73 25 73 25 73
73 27 73 27 73 27 73 27 73 27
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 25 73 73 27 7 22 73 27 73 27 73 27
+VIO_M2CLK_DLL_1 AF24 +VIO_M2CLK_DLL_2 AG25 +VIO_PLL_MEM_1 AF25 +VIO_PLL_MEM_2 AG26 +VIO_PLL_FSB_1 AF26 +VIO_PLL_FSB_2 AG28 +VIO_PLL_CPU_1 +VIO_PLL_CPU_2 +VIO_PLL_CPU_3 +VIO_PLL_CPU_4
AC26 AD26 AE26 AF27
=PP1V05_S0_MCP_M2CLK_DLL 550 mA PP1V05_S0_MCP_PLL_FSBMEM 20 mA 70 mA
22
73 27 73 27 73 27 73 27
25 mA
73 27 73 27 73 27
25 mA
73 27 73 27 73 27 73 27 73 27
MCLK0A_1_P AH23 MCLK0A_1_N AJ23 MCLK0A_0_P AJ22 MCLK0A_0_N AH22 MCS0A_1* AH19 MCS0A_0* AK20 MODT0A_1 AH20 MODT0A_0 AK19 MCKE0A_1 AL26 MCKE0A_0 AN25
MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CS_L<1> MEM_A_CS_L<0> MEM_A_ODT<1> MEM_A_ODT<0> MEM_A_CKE<1> MEM_A_CKE<0>
73 27
OUT OUT
25 73 73 27 25 73 73 27 73 27
OUT OUT
25 73 73 27 25 73 73 27
MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0> MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0> MCP_MEM_COMP_GND MCP_MEM_COMP_VDD
AP1 AR3 AV4 AU4 AP3 AP2 AU3 AT4 AT5 AT7 AU8 AR10 AV5 AU5 AP10 AT8 AT10 AU10 AR13 AR14 AR11 AP11 AT11 AP13 AV14 AU14 AR17 AP17 AP14 AT13 AP16 AR16 AU26 AT26 AU29 AT29 AV25 AV26 AV28 AV29 AT31 AR32 AT34 AU34 AR29 AR31 AU32 AT32 AV35 AT35 AR37 AP38 AV34 AU35 AR36 AR38 AM36 AM37 AJ36 AL36 AP37 AP36 AJ38 AJ37 AT2 AU7 AV10 AT14 AR28 AV32 AT37 AM38 AG23 AG22
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0 MEM_COMP_GND MEM_COMP_VDD
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
AR2 AR1 AV7 AV8 AU11 AV11 AU13 AV13 AT28 AU28 AU31 AV31 AU36 AT36 AL38 AL37
MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0> MEM_B_A<15> MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27 73
MRAS1* AR19 MCAS1* AU17 MWE1* AT17
OUT OUT OUT
26 73 26 73 26 73
MEMORY PARTITION 0
MEMORY PARTITION 1
MBA1_2 AR25 MBA1_1 AT19 MBA1_0 AR20 MA1_15 AP26 MA1_14 AR26 MA1_13 AV16 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
AP25 AT23 AP20 AU23 AV22 AV23 AT22 AU22 AP23 AR23 AP22 AR22 AT20
OUT OUT OUT
26 73 26 73 26 73
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73 26 73
=PP1V5R1V35_S3_MCP_MEM
1
R1520
1K
5% 1/16W MF-LF 2 402
MRESET0* AP4 MCLK1A_1_P AU20 MCLK1A_1_N AV20 MCLK1A_0_P AU19 MCLK1A_0_N AV19 MCS1A_1* AU16 MCS1A_0* AP19 MODT1A_1 AT16 MODT1A_0 AV17 MCKE1A_1 AU25 MCKE1A_0 AT25
MEM_RESET_L MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CS_L<1> MEM_B_CS_L<0> MEM_B_ODT<1> MEM_B_ODT<0> MEM_B_CKE<1> MEM_B_CKE<0>
OUT
25 26
OUT OUT
26 73 26 73
OUT OUT
26 73 26 73
73 27 73 27 73 27 73 27 73 27 73 27 73 27 73 27
OUT OUT
25 73 25 73
73 27 73 27
OUT OUT
26 73 26 73
22 20 19
=PP1V5R1V35_SW_MCP_MEM
73 27 73 27
OUT OUT
25 73 25 73
OUT OUT
26 73 26 73
R15101
40.2
1% 1/16W MF-LF 402 2
73 27 73 27 73 27 73 27
OUT OUT
20 25 73 20 25 73
OUT OUT
20 26 73 20 26 73
R15111
40.2
1% 1/16W MF-LF 402 2
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Memory Interface

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

15 OF 109
SHEET
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009).
K6/K69 EDP currents used.
14 OF 80
OMIT
U1400
MCP89M-A01
8
IN
PEG_CLKREQ_L AP_CLKREQ_L ENET_CLKREQ_L FW_CLKREQ_L FW_PWR_EN FW_PME_L
W4 W5 W7 W8 W6 W9
29
D
31 34 34
IN
IN
IN
OUT
FBGA (4 OF 11) PEA_CLKREQ*/GPIO_49 PE0_REFCLK_P Y1 (IPU) PE0_REFCLK_N W1 PEB_CLKREQ*/GPIO_50 (IPU) PE1_REFCLK_P W3 PE1_REFCLK_N W2 PEC_CLKREQ*/GPIO_51 (IPU) PE2_REFCLK_P U4 PED_CLKREQ*/GPIO_52 PE2_REFCLK_N U5 (IPU) PE3_REFCLK_P U7 PEE_CLKREQ*/GPIO_53 (IPU) PE3_REFCLK_N U6 PEF_CLKREQ*/GPIO_54 (IPU) PE4_REFCLK_P U9 PE4_REFCLK_N U8 PE5_REFCLK_P W10 PE5_REFCLK_N W11 PE0_TX0_P AC3 PE0_TX0_N AC2 PE0_TX1_P AB2 PE0_TX1_N AB3 PE0_TX2_P AC6 PE0_TX2_N AC7 PE0_TX3_P AC8 PE0_TX3_N AC9
PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N =PEG_R2D_C_P<0> =PEG_R2D_C_N<0> =PEG_R2D_C_P<1> =PEG_R2D_C_N<1> =PEG_R2D_C_P<2> =PEG_R2D_C_N<2> =PEG_R2D_C_P<3> =PEG_R2D_C_N<3> TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_RESET_L NO STUFF
1
OUT OUT OUT OUT OUT OUT OUT OUT
8 74 8 74
29 74 29 74
31 74 31 74
33 74 33 74
34
IN
29 24 6
IN
PCIE_WAKE_L =PEG_D2R_P<0> =PEG_D2R_N<0> =PEG_D2R_P<1> =PEG_D2R_N<1> =PEG_D2R_P<2> =PEG_D2R_N<2> =PEG_D2R_P<3> =PEG_D2R_N<3> TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN
U3 AC1 AB1 AC5 AC4 AC10 AC11 AB7 AB6 AB9 AB8 Y2 Y3 AB11 AB10 Y10 Y11
PE_WAKE* (IPU-S5) PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N
PE0 ports are Gen2-capable. PE1 ports are Gen1-only.

8 8
4 RCs: 4x, x2, x1, x1 2 RCs: x1, x1
8 8
IN IN IN IN IN IN IN IN
8 8
8 8
8 8
8 8
If PE0[3:0] are not used, +VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND
8 8
8 8
PCI EXPRESS
PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE1_RX0_P PE1_RX0_N PE1_RX1_P PE1_RX1_N
PE0_TX4_P AB4 PE0_TX4_N AB5 PE0_TX5_P Y5 PE0_TX5_N Y4 PE1_TX0_P Y7 PE1_TX0_N Y6 PE1_TX1_P Y9 PE1_TX1_N Y8 (IPD) PEX_RST* U1
74 33 74 33
IN IN
PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PP3V3_S0_MCP_PLL_HVDD 50 mA PP1V05_S0_MCP_PLL_PEXSATA 325 mA 100 mA 80 mA
OUT OUT
33 74 33 74
If PE0[4:5] and PE1[0:1] are not used, +VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND
74 29 6 74 29 6
IN IN IN IN
22
OUT OUT OUT OUT
29 74 29 74
74 31 74 31
31 74 31 74
V11 V13 AH10 AG11 AF12 AF13 AH8 AH9 AH11
+3.3V_PLL_HVDD_1 +3.3V_PLL_HVDD_2 +VIO_PLL_PE +VIO_PLL_XREF_XS_1 +VIO_PLL_XREF_XS_2 +VIO_PLL_XREF_XS_3 +VIO_PLL_SATA_1 +VIO_PLL_SATA_2 +VIO_PLL_H
OUT
18 24
22
R1600
10K
5% 1/16W MF-LF 2 402
120 mA
25 mA
PEX0_TERM_P U2
74
MCP_PEX0_TERMP
R16101
2.49K
1% 1/16W MF-LF 402 2
PLACE_NEAR=U1400.U2:12.7 mm
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP PCIe Interfaces

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

16 OF 109
SHEET
15 OF 80
OMIT
D
23
U1400
MCP89M-A01 PP3V3_S0_MCP_DAC 140 mA TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF
FBGA (5 OF 11) B29 C29 D29 +3.3V_RGBDAC RGB_DAC_RSET RGB_DAC_VREF DDC_CLK0/GPIO_38 F29 DDC_DATA0/GPIO_39 H25 RGB_DAC_RED C31 RGB_DAC_GREEN B31 RGB_DAC_BLUE A31 RGB_DAC_HSYNC D31 RGB_DAC_VSYNC E31 IFPA_TXC_P K22 IFPA_TXC_N L22 IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N C22 B22 E22 D22 F22 G22 H22 J22
D
AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC =MCP_IFPA_TXC_P =MCP_IFPA_TXC_N =MCP_IFPA_TXD_P<0> =MCP_IFPA_TXD_N<0> =MCP_IFPA_TXD_P<1> =MCP_IFPA_TXD_N<1> =MCP_IFPA_TXD_P<2> =MCP_IFPA_TXD_N<2> =MCP_IFPA_TXD_P<3> =MCP_IFPA_TXD_N<3> =MCP_IFPB_TXC_P =MCP_IFPB_TXC_N =MCP_IFPB_TXD_P<0> =MCP_IFPB_TXD_N<0> =MCP_IFPB_TXD_P<1> =MCP_IFPB_TXD_N<1> =MCP_IFPB_TXD_P<2> =MCP_IFPB_TXD_N<2> =MCP_IFPB_TXD_P<3> =MCP_IFPB_TXD_N<3> =MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA
8 8 8
IN IN
16 56 16
8 8
RGB DAC Disable: Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required Connect +3.3V_RGBDAC pin to GND. (or use as GPIOs).
RGB
8 8
NOTE: No Composite/S-Video/Component Video support on MCP89 Interface Mode

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
8 8
8 8
DP_IG_ML0_P<3> DP_IG_ML0_N<3> DP_IG_ML0_P<2> DP_IG_ML0_N<2> DP_IG_ML0_P<1> DP_IG_ML0_N<1> DP_IG_ML0_P<0> DP_IG_ML0_N<0> DP_IG_ML1_P<3> DP_IG_ML1_N<3> DP_IG_ML1_P<2> DP_IG_ML1_N<2> DP_IG_ML1_P<1> DP_IG_ML1_N<1> DP_IG_ML1_P<0> DP_IG_ML1_N<0> DP_IG_HPD0 DP_IG_HPD1 SATARDRVR_A_EN DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N DP_IG_AUX_CH1_P DP_IG_AUX_CH1_N PP3V3_S0_MCP_PLL_DP_USB 210 mA 180 mA
D26 E26 G26 F26 F25 G25 E25 D25 F28 G28 E28 D28 A28 A29 C28 B28 H26 J26 J25 L28 K28 K25 K26
DP0_3_P/TMDS0_TXC_P DP0_3_N/TMDS0_TXC_N DP0_2_P/TMDS0_TX0_P DP0_2_N/TMDS0_TX0_N DP0_1_P/TMDS0_TX1_P DP0_1_N/TMDS0_TX1_N DP0_0_P/TMDS0_TX2_P DP0_0_N/TMDS0_TX2_N DP1_3_P/TMDS0B_TXC_P DP1_3_N/TMDS0B_TXC_N DP1_2_P/TMDS0_TX3_P DP1_2_N/TMDS0_TX3_N DP1_1_P/TMDS0_TX4_P DP1_1_N/TMDS0_TX4_N DP1_0_P/TMDS0_TX5_P DP1_0_N/TMDS0_TX5_N HPLUG_DET0/GPIO_20 HPLUG_DET1/GPIO_21 HPLUG_DET2/GPIO_22 DDC_CLK2/DP_AUX_CH0_P DDC_DATA2/DP_AUX_CH0_N DDC_CLK3/DP_AUX_CH1_P DDC_DATA3/DP_AUX_CH1_N
MCP Signal =MCP_IFPA_TXC_P/N =MCP_IFPA_TXD_P/N<0> =MCP_IFPA_TXD_P/N<1> =MCP_IFPA_TXD_P/N<2> =MCP_IFPA_TXD_P/N<3> =MCP_IFPB_TXC_P/N =MCP_IFPB_TXD_P/N<0> =MCP_IFPB_TXD_P/N<1> =MCP_IFPB_TXD_P/N<2> =MCP_IFPB_TXD_P/N<3> =MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA
TMDS/HDMI TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0> TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2> (UNUSED) (UNUSED) TMDS_IG_TXD_P/N<3> TMDS_IG_TXD_P/N<4> TMDS_IG_TXD_P/N<5> (UNUSED) TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA
LVDS LVDS_IG_A_CLK_P/N LVDS_IG_A_DATA_P/N<0> LVDS_IG_A_DATA_P/N<1> LVDS_IG_A_DATA_P/N<2> LVDS_IG_A_DATA_P/N<3> LVDS_IG_B_CLK_P/N LVDS_IG_B_DATA_P/N<0> LVDS_IG_B_DATA_P/N<1> LVDS_IG_B_DATA_P/N<2> LVDS_IG_B_DATA_P/N<3> LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
8 8 8 8 8 8
8 8 8 8 8 8 8 8
8 8
FLAT PANEL
C
NOTE: 100K pull-downs required if HPLUG_DET0/HPLUG_DET1 are not used.
IFPB_TXC_P B23 IFPB_TXC_N C23 IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N L23 K23 J23 H23 G23 F23 D23 E23
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
8 8
8 8 8 8 8
8 8 8 8 8 8 8 8
LVDS: Power +VDD_IFPx at 1.8V TMDS: Power +VDD_IFPx at 3.3V
8 8 36 16
IN IN OUT
16 8 16 8
BI BI
DDC_CLK1/GPIO_40 J28 DDC_DATA1/GPIO_41 G29
OUT BI
8 8
8 8
BI BI
22
M23 N22 N21 M22 N23 L24 M25 N25 L26 M26 N24 L25 A22 A23 A26 B26 C26
+3.3V_PLL_DP0_1 +3.3V_PLL_DP0_2 +3.3V_PLL_USB_1 +3.3V_PLL_USB_2 +VIO_PLL_IFPAB_1 +VIO_PLL_IFPAB_2 +VIO_PLL_CORE_LEG +VIO_PLL_SPPLL0_1 +VIO_PLL_SPPLL0_2 +VIO_PLL_V +VIO_PLL_NV_1 +VIO_PLL_NV_2 +VDD_IFPA +VDD_IFPB +VIO_DP0_1 +VIO_DP0_2 +VIO_DP0_3
LCD_BKL_CTL/GPIO_57 A25 LCD_BKL_ON/GPIO_59 B25 LCD_PANEL_PWR/GPIO_58 C25
(GMUX_INT) LCD_IG_BKLT_PWM LCD_IG_BKLT_EN LCD_IG_PWR_EN
OUT OUT OUT
8 8 67
30 mA
23 7
=PP1V05_S0_MCP_PLL_IFP 60 mA PP1V05_S0_MCP_PLL_CORE 160 mA 40 mA 60 mA 40 mA 20 mA
22
B
23 7
B
IFPAB_VPROBE L20 IFPAB_RSET K20
MCP_IFPAB_VPROBE MCP_IFPAB_RSET
OUT OUT
23 74
23 74
=PP3V3R1V8_S0_MCP_IFP_VDD 180 mA =PP1V05_S0_MCP_DP0_VDD 160 mA
23 7
TMDS0_VPROBE H28 TMDS0_RSET F31
MCP_TMDS0_VPROBE MCP_TMDS0_RSET
OUT OUT
23 74
23 74
DDC Mode Pull-downs

NOTE: DP_AUX_CH1 also requires pull-downs if used for dual-mode DisplayPort (DP++). If unused no pulls are necessary, if used for TMDS/HDMI only then only pull-ups are necessary.
R1710 100K R1711 100K
1 1
2 2
5% 5%
1/16W MF-LF 402 1/16W MF-LF 402
DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N
8 16 8 16
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Graphics
GPIO Pull-Ups
=PP3V3_S0_MCP_GPIO
R 7 17 18
DRAWING NUMBER
SIZE
Apple Inc.
16 36 16 56 16
051-8563
REVISION
A.13.0
BRANCH PAGE
R1780 R1781 R1782
10K 10K 10K
1 1 1
2 2 2
5% 5% 5%
1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402
SATARDRVR_A_EN AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET
17 OF 109
SHEET
16 OF 80
5
OMIT
U1400
MCP89M-A01
FBGA (6 OF 11)
74 36 74 36
OUT OUT
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_D2R_N SATA_HDD_D2R_P
AH4 AH5 AJ4 AJ5
SATA_A0_TX_P SATA_A0_TX_N SATA_A0_RX_N SATA_A0_RX_P
USB0_N USB0_P USB1_P USB1_N
C20 B20 J20 H20 C19 B19 G20 F20 E20 D20 E19 D19 G19 F19 J17 H17 J19 H19 C17 B17 E17 D17 G17 F17 A17 L17 K17 K19 L19
74 36
Internal 19.5K Pull-Downs on all USB pairs
OHCI0/EHCI0
IN IN
74 36
USB2_P USB2_N USB3_P USB3_N USB4_P USB4_N USB5_P USB5_N USB6_P USB6_N USB7_P USB7_N
74 36 74 36
OUT OUT
SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_D2R_N SATA_ODD_D2R_P
AJ3 AJ2 AH2 AH3
SATA_A1_TX_P SATA_A1_TX_N SATA_A1_RX_N SATA_A1_RX_P
74 36 74 36
IN IN
TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN TP_SATA_C_D2RN TP_SATA_C_D2RP
AJ6 AJ7 AH7 AH6
SATA_B0_TX_P SATA_B0_TX_N SATA_B0_RX_N SATA_B0_RX_P
Only USB8-11 support nV USB JTAG in S3/S4/S5.
18 16 7
=PP3V3_S0_MCP_GPIO
TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN
1
AL4 AL3 AL1 AL2
SATA_B1_TX_P SATA_B1_TX_N SATA_B1_RX_N SATA_B1_RX_P
USB8_P USB8_N USB9_P USB9_N USB10_P USB10_N USB11_N USB11_P
R1800
100K
TP_SATA_D_D2RN TP_SATA_D_D2RP
5% 1/16W MF-LF 402 2
MXM_GOOD_L
74
AH1
SATA_LED*/GPIO_30 SATA_TERMP
MCP_SATA_TERMP
AJ1
External A USB_EXTA_N USB_EXTA_P AirPort (PCIe Mini-Card) USB_MINI_P USB_MINI_N T57 NC_USB_T57_P NC_USB_T57_N External C USB_EXTC_P USB_EXTC_N Watermelon USB_WM_P USB_WM_N Camera/External E USB_CAMERA_P USB_CAMERA_N SD Card/ExpressCard USB_SDCARD_P USB_SDCARD_N External D USB_EXTD_P USB_EXTD_N Geyser Trackpad/Keyboard USB_TPAD_P USB_TPAD_N External B USB_EXTB_P USB_EXTB_N IR USB_IR_P USB_IR_N Bluetooth USB_BT_N USB_BT_P
BI BI
37 75 37 75
BI BI
8 75 8 75
BI BI
BI BI
8 75 8 75
BI BI
8 75 8 75
SATA
USB
BI BI
29 75 29 75
BI BI
30 75 30 75
BI BI
8 75 8 75
OHCI1/EHCI1
=PP3V3_S5_MCP_GPIO
BI BI
47 75 47 75
7 18
1 BI BI
37 75 37 75
R1851
8.2K
R1853
8.2K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
BI BI
38 75 38 75
R18501
8.2K
5% 1/16W MF-LF 402 2
R18521
8.2K
5% 1/16W MF-LF 402 2
C
USB_EXTA_OC_L 37 USB_EXTB_OC_L 37 USB_EXTC_OC_L USB_EXTD_OC_L OC2# Also for EXTE OC3# Also for EXCARD
1
BI BI
29 75 29 75
R1805
2.49K
NC NC NC NC
G4 E7 F7 F4 NC_1 NC_2 NC_3 NC_4
1% 1/16W MF-LF 2 402
USB_OC0*/GPIO_25 USB_OC1*/GPIO_26 USB_OC2*/GPIO_27_MGPIO_0 USB_OC3*/GPIO_28_MGPIO_1 USB_RBIAS_GND
75
MCP_USB_RBIAS_GND MCP_RGMII_VREF TP_ENET_TXD<0> TP_ENET_TXD<1> TP_ENET_TXD<2> TP_ENET_TXD<3> TP_ENET_CLK125M_TXCLK TP_ENET_TX_CTRL TP_ENET_MDC ENET_MDIO TP_MCP_CLK25M_BUF0_R TP_ENET_RESET_L
IN
8
RGMII_VREF
76 8 76 8 76 8 76 8
C13 G13 H13 F14 D14 G14 E14 F13 K13 J13 J14
R1860
887
IN IN IN IN IN IN
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_CLK125M_RXCLK ENET_RX_CTRL ENET_ENERGY_DET PP3V3_ENET_MCP_PLL_MAC 20 mA MCP_MII_COMP_VDD MCP_MII_COMP_GND
B14 C14 D16 F16 E16 A14 H14
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3 RGMII_RXCLK RGMII_RXCTL RGMII_INTR/GPIO_35
RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3
1% 1/16W MF-LF 2 402
LAN
22 19 7
=PP3V3_ENET_MCP_RMGT
76 8 76 8
RGMII_TXCLK RGMII_TXCTL RGMII_MDC RGMII_MDIO BUF_25MHZ RGMII_RESET*
R18101
49.9
31
IN
22
1% 1/16W MF-LF 402 2
BI
8 76
M16 D13 E13
+3.3V_PLL_MAC_DUAL RGMII_COMP_VDD RGMII_COMP_GND
76 76
R18111
49.9
1% 1/16W MF-LF 402 2
Internal MAC Disable: Connect RGMII_RXD<0:3> together to 10K pull-down. Connect RGMII_RXCLK to 10K pull-down. Connect RGMII_RXCTL to 10K pull-down. Connect RGMII_INTR to 10K pull-down (if not used as GPIO). +3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail. RGMII_COMP_VDD/_GND must remain connected as shown. Connect RGMII_VREF to 10K pull-down. Connect RGMII_MDIO to 10K pull-down. All other pins can be left TP or NC.
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP SATA, USB & Ethernet

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

18 OF 109
SHEET
17 OF 80
4
=PP3V3_S0_MCP_GPIO OMIT
2
3
7 16 17 18
U1400
MCP89M-A01
22 8
R1961
10K
=PP3V3R1V5_S0_MCP_HDA 70 mA 70 mA
FBGA (7 OF 11) D6 +VDD_HDA HDA_SDATA_OUT E1
5% 1/16W MF-LF 1 402

75 18
R1950
HDA_SDOUT_R
1
22
HDA_SDOUT
OUT
51 75
D
R19001
49.9
1% 1/16W MF-LF 402 2
R1951
75 51
IN
HDA_SDIN0
E2
HDA_SDATA_IN0 (IPD)
HDA_BITCLK E4
75 18
HDA_BIT_CLK_R
22
5% 1/16W MF-LF 402
HDA_BIT_CLK
D
OUT
51 75
HDA
5% 1/16W MF-LF 402
R1952
1
56
OUT
E3 AUD_IPHS_SWITCH_EN Output limited to +VDD_HDA. Confirmed OK for this signal.

75
HDA_SDATA_IN1/GPIO_2 (IPD)
HDA_RESET* D1
75 18
HDA_RST_R_L
22
HDA_RST_L
OUT
51 75
R1953
HDA_PULLDN_COMP HDA_SYNC D2
75 18
MCP_HDA_PULLDN_COMP
D3
HDA_SYNC_R
22
5% 1/16W MF-LF 402
HDA_SYNC
OUT
51 75
BUF_SIO_CLK Frequency
Frequency HDA_SYNC 1 0 24 MHz 14.31818 MHz
5% 1/16W MF-LF 402

75 41 39 75 41 39 75 41 39 75 41 39
BI BI BI BI
LPC
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>
R1910 R1911 R1912 R1913
22 22 22 22
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> TP_MLB_RAM_SIZE
K1 L1 L2 L3
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
(IPU) (IPU) (IPU) (IPU)
LPC_SERIRQ L8 (IPU) LPC_FRAME* L7
LPC_SERIRQ
BI
39 41
R1960
LPC_FRAME_R_L
1
22
LPC_FRAME_L
OUT
39 41 75
K2
LPC_DRQ0*/GPIO_43 (IPU)
5% 1/16W MF-LF 402
(IPD) LPC_RESET* K7 LPC_CLK0 L5 K10 C8 A8 D8 G8 C7 H7 H6 G6 H4
LPC_RESET_L LPC_CLK33M_SMC_R MCP_CPU_VTT_EN_L MLB_RAM_VENDOR T57_PWR_EN SMC_ADAPTER_EN LPCPLUS_GPIO MCP_MEM_VDD_SEL_1V5 ODD_PWR_EN_L MEM_EVENT_L ENET_LOW_PWR SDCARD_RESET PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3> SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R MCP_SPKR MCP_THMDIODE_P MCP_THMDIODE_N SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN ARB_DETECT_L PM_CLK32K_SUSCLK_R MCP_TEST_MODE_EN NO STUFF
1 OUT OUT OUT BI OUT BI OUT
18 45 79 45 79 18 18
OUT OUT
18 24 75
BIOS Boot Select

I/F LPC SPI LPC_FRAME# 0 1
41 39
IN
PM_CLKRUN_L SMC_WAKE_SCI_L PM_LATRIGGER_L AUD_I2C_INT_L SMC_RUNTIME_SCI_L PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L RTC_RST_L
L6
LPC_CLKRUN*/GPIO_42 (IPU)
24 75
22 19 7
PP3V3_G3_RTC
39 12 56
IN OUT IN IN
R19201
R1921
49.9K
39
D11 G11 B3 H2
(IPU-S5) (IPU)
SIO_PME*/GPIO_31 EXT_SMI*/GPIO_32 A20GATE/GPIO_55 KBRDRSTIN*/GPIO_56
49.9K
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
39 24
IN IN
J10 F10
PWRBTN* (IPU-S5) RSTBTN* (IPU-S5)
MISC_VDDEN0/GPIO_47 MISC_VDDEN1/GPIO_48 MISC_VDDEN2/GPIO_17 MISC_VDDEN3/GPIO_18 MISC_VDDEN4/GPIO_19 MEM_VDD_SEL/GPIO_46
BI IN BI OUT OUT IN OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT
6 18 39 40 65 18 41 60
NOTE: MCP89 A01 has strong (~10K) pull-downs on these pins.
G16 C11 C2
RTC_RST* PWRGD_SB PWRGD
FANCTL0/GPIO_61 FANRPM0/GPIO_60/MGPIO_2 FANCTL1/GPIO_62 FANRPM1/GPIO_63/MGPIO_3
NOTE: MCP89 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override.
18 36 18 25 26 39 8 18 31 18 30
SPI Frequency Select

Frequency SPI_DO SPI_CLK 25.0 MHz 31.2 MHz 42.7 MHz 62.5 MHz 0 0 1 1 0 1 0 1
39 24
IN IN
PM_RSMRST_L MCP_PS_PWRGD MCP_WAKE_REQ_L PM_BATLOW_L MCP_MEM_VDD_EN MCP_MEM_VTT_EN SM_INTRUDER_L
NOTE: MCP89 A01 has strong (~10K) pull-downs on these pins.
(IPD) SLP_S3* C4 (IPD) SLP_RMGT* K9 (IPD) SLP_S5* D5 MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15 MCP_VID3/GPIO_16 SPI_CS0*/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_08 SPI_DO/GPIO_09 K3 K4 K5 K6 E11 D7 F11 B8
6 39 65 69 65 6 18 39 40 65
40
OUT IN OUT OUT
H16 A7 B7 G10 J16
MCP_WAKE_REQ*
18 62 18 62 18 62 18 62
65 20
For EMI Reduction on HDA interface

20
MEMVTT_EN/GPIO_45 INTRUDER*
MISC
HDA Output Caps

HDA_SDOUT_R HDA_BIT_CLK_R HDA_RST_R_L HDA_SYNC_R
18 75 18 75 18 75 18 75
39
MCP_WAKE_DIS* (IPU-S5) MCP_MEMVDD_EN/GPIO_44
41 75 41 75 6 18 41 75 41 75
40 18 18 6 21 18
OUT OUT OUT BI
C1950
10PF
C1952
10PF
50 41 18 6
SMC_IG_THROTTLE_L T57_RESET GFXVCORE_PWR_EN SPIROM_USE_MLB JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS JTAG_MCP_TRST_L JTAG_MCP_TCK MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT
G5 H5 H10 J11 C10 D10 B10 E10 A10 A11 B11 B16 C16
1
MGPU_PIO0/GPIO_6 MGPU_PIO1/GPIO_7 MGPU_PIO2/GPIO_23 MGPU_PIO3/GPIO_24 JTAG_TDI (IPU) JTAG_TDO JTAG_TMS (IPU) JTAG_TRST* (IPD) JTAG_TCK XTALIN XTALOUT XTALIN_RTC XTALOUT_RTC
NOTE: 42 & 62 MHz use FAST_READ command. Straps not provided on this page.
OUT 1
40
SPKR/GPIO_1 H3 THERM_DIODE_P G3 THERM_DIODE_N G2 SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT*/GPIO_64 A4 B4 A5 B5 C5
R1970
10K MCP_SPKR: 0 = USER mode (Normal boot mode) 1 = SAFE mode (For ROMSIP recovery) Connects to SMC for automatic recovery.
5% 50V CERM 2 402
5% 50V CERM 2 402
12 42 75 12 42 75 42 75 42 75 18 29 65
12 12 12
IN OUT IN IN IN
5% 1/16W MF-LF 2 402
C1951
10PF
C1953
10PF
12 12
5% 2 50V CERM 402
5% 2 50V CERM 402
BUF_SIO_CLK/GPIO_33 H1
24 24
IN OUT
SUS_CLK/GPIO_34 H11 TEST_MODE_EN D4 PKG_TEST L16 PKG_TEST2 K16
OUT
24 75
GPIO Pull-Ups/Downs
=PP3V3_S5_MCP_GPIO =PP3V3_S3_MCP_GPIO =PP3V3_S0_MCP_GPIO PCIE_RESET_L
7 17 7 7 16 17 18 15 24
24 24
IN OUT
R19301
10K
5% 1/16W MF-LF 402 2
R1931
100K
R1959
10K
R1966
10K
R1975
1K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
R1980 10K R1981 10K R1999 100K R1986 100K R1983 10K R1984 10K R1985 100K R1987 100K R1988 10K R1989 10K R1990 10K R1991 10K R1992 100K R1993 100K R1994 100K R1995 100K R1996 10K R1997 100K R1998 20K
1 1
1
2 2
2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2
5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
SDCARD_RESET T57_RESET GFXVCORE_PWR_EN SPIROM_USE_MLB MCP_CPU_VTT_EN_L MLB_RAM_VENDOR T57_PWR_EN LPCPLUS_GPIO ODD_PWR_EN_L MEM_EVENT_L ENET_LOW_PWR SMC_IG_THROTTLE_L MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3> AP_PWR_EN
18 30 6 18 18 21 6 18 41 50
Platform-Specific Connections
R1965
75 24 18
18 18 6 18 18 41
IN
LPC_RESET_L
33
LPC_PWRDWN_L
OUT
39 41
18 36 18 25 26 39 8 18 31 18 40 65 40 39 18 6
5% 1/16W MF-LF 402 IN
PM_SLP_S4_L
MAKE_BASE=TRUE
PM_SLP_S5_L
OUT
39
NOTE: MCP SLP_S5# signal has the behavior of Intels SLP_S4# signal.
SYNC_MASTER=T27_MLB
PAGE TITLE
18 62 18 62 18 62 18 62
MCP HDA, LPC & MISC

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
18 29 65
1/16W MF-LF 402
A.13.0
BRANCH PAGE
2 5% 2 5% 1/16W MF-LF 402 1/16W MF-LF 402
ARB_DETECT_L SPI_MISO
18

6 18 41 75
19 OF 109
SHEET
18 OF 80
5
OMIT
2
OMIT OMIT
NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.
OMIT
U1400
MCP89M-A01
22 7
U1400
MCP89M-A01
M4 M2 P4 N12 N4 N14 V20 N10 P3 P1 N11 N6 P6 N2 N9 N8 M10 N3 N1 M5 M7 P2 M8 M11 V19 N7 N16 P5 N5 N13 N15 P9 V17 V18 M14 M13 Y19 Y20 Y17 Y18 P7 P8 +VDD_COREB_1 +VDD_COREB_2 +VDD_COREB_3 +VDD_COREB_4 +VDD_COREB_5 +VDD_COREB_6 +VDD_COREB_7 +VDD_COREB_8 +VDD_COREB_9 +VDD_COREB_10 +VDD_COREB_11 +VDD_COREB_12 +VDD_COREB_13 +VDD_COREB_14 +VDD_COREB_15 +VDD_COREB_16 +VDD_COREB_17 +VDD_COREB_18 +VDD_COREB_19 +VDD_COREB_20 +VDD_COREB_21 +VDD_COREB_22 +VDD_COREB_23 +VDD_COREB_24 +VDD_COREB_25 +VDD_COREB_26 +VDD_COREB_27 +VDD_COREB_28 +VDD_COREB_29 +VDD_COREB_30 +VDD_COREB_31 +VDD_COREB_32 +VDD_COREB_33 +VDD_COREB_34 +VDD_COREB_35 +VDD_COREB_36 +VDD_COREB_37 +VDD_COREB_38 +VDD_COREB_39 +VDD_COREB_40 +VDD_COREB_41 +VDD_COREB_42
U1400
MCP89M-A01
AU24 AU15 AG5 AD35 AJ18 AL18 AR24 AA5 G18 B9 AU9 AM24 H24 B30 AR21 D24 AU30 AK5 N18 E24 K15 M19 AH27 E18 AA34 AK31 K11 AU21 V34 AL21 AA11 M34 B27 V28 C38 D27 R34 J35 AK34 E15 AR30 AU33 J34 AH30 J4 AU27 AU1 AG10 E9 E27 L21 AU38 H18 B15 AA4 AJ15 L18 A3 G15 AL27 AV37 D9 L4 N19 H27 FBGA (11 OF 11) GND_135 GND_200 E33 GND_136 GND_201 M35 GND_137 GND_202 AV2 GND_138 GND_203 AK2 GND_139 GND_204 AU6 GND_140 GND_205 F37 GND_141 GND_206 C3 GND_142 GND_207 J37 GND_143 GND_208 V35 GND_144 GND_209 G27 GND_145 GND_210 AA35 GND_146 GND_211 AU18 GND_147 GND_212 AR6 GND_148 GND_213 AV36 GND_149 GND_214 B33 GND_150 GND_215 AJ27 GND_151 GND_216 G9 GND_152 GND_217 AG35 GND_153 GND_218 AG7 GND_154 GND_219 AD8 GND_155 GND_220 AU2 GND_156 GND_221 AP9 GND_157 GND_222 AD31 GND_158 GND_223 V37 GND_159 GND_224 AA37 GND_160 GND_225 AG37 GND_161 GND_226 AL15 GND_162 GND_227 AR18 GND_163 GND_228 L14 GND_164 GND_229 K14 GND_165 GND_230 F2 GND_166 GND_231 K27 GND_167 GND_232 AL9 GND_168 GND_233 AB26 GND_169 GND_234 M29 GND_170 GND_235 G30 GND_171 GND_236 R28 GND_172 GND_237 R29 GND_173 GND_238 R31 GND_174 GND_239 U17 GND_175 GND_240 K8 GND_176 GND_241 Y21 GND_177 GND_242 V31 GND_178 GND_243 U18 GND_179 GND_244 W21 GND_180 GND_245 U19 GND_181 GND_246 W18 GND_182 GND_247 U20 GND_183 GND_248 W17 GND_184 GND_249 V21 GND_185 GND_250 AA28 GND_186 GND_251 AA29 GND_187 GND_252 N17 GND_188 GND_253 AD28 GND_189 GND_254 AD29 GND_190 GND_255 AG4 GND_191 GND_256 W19 GND_192 GND_257 W20 GND_193 GND_258 AA26 GND_194 GND_259 AB27 GND_195 GND_260 AA17 GND_196 GND_261 AA18 GND_197 GND_262 AA19 GND_198 GND_263 AA20 GND_199 GND_264 U21
U1400
MCP89M-A01
22 7
=PP1V05_SW_MCP_FSB 2000 mA
22 13 7
=PP1V05_S0_MCP_FSB 200 mA
W27 W28 Y27 Y28
NOTE: VDD_COREx_SENSE signals should NOT be used for remote sensing unless COREA/COREB are powered by separate regulators. Instead connect regulator sense point as close to COREB FET as possible. TP_MCP_VDDCOREA_SENSEP TP_MCP_VDDCOREA_SENSEN
7
POWER II
G32 K29 D32 L29 Y26 V26 P27 T27 J29 N27 P26 F32 A32 H29 W26 U27 G31 C32 E32 M28 H30 U26 T26 H31 B32 R26 N26
FBGA (8 OF 11) +VDD_MEM_1 +VTT_CPU_1 +VDD_MEM_2 +VTT_CPU_2 +VDD_MEM_3 +VTT_CPU_3 +VDD_MEM_4 +VTT_CPU_4 +VDD_MEM_5 +VTT_CPU_5 +VDD_MEM_6 +VTT_CPU_6 +VTT_CPU_7 +VDD_MEM_7 +VTT_CPU_8 +VDD_MEM_8 +VTT_CPU_9 +VDD_MEM_9 +VTT_CPU_10 +VDD_MEM_10 +VTT_CPU_11 +VDD_MEM_11 +VTT_CPU_12 +VDD_MEM_12 +VTT_CPU_13 +VDD_MEM_13 +VTT_CPU_14 +VDD_MEM_14 +VTT_CPU_15 +VDD_MEM_15 +VTT_CPU_16 +VDD_MEM_16 +VTT_CPU_17 +VDD_MEM_17 +VTT_CPU_18 +VDD_MEM_18 +VTT_CPU_19 +VDD_MEM_19 +VTT_CPU_20 +VDD_MEM_20 +VTT_CPU_21 +VDD_MEM_21 +VTT_CPU_22 +VDD_MEM_22 +VTT_CPU_23 +VDD_MEM_23 +VTT_CPU_24 +VDD_MEM_24 +VTT_CPU_25 +VDD_MEM_25 +VTT_CPU_26 +VDD_MEM_26 +VTT_CPU_27 +VDD_MEM_27 +VDD_MEM_28 +VDD_MEM_29 +VTT_CPU2_1 +VDD_MEM_30 +VTT_CPU2_2 +VDD_MEM_31 +VTT_CPU2_3 +VTT_CPU2_4
AG14 AL7 AF18 AF21 AM1 AM4 AK8 AG13 AF16 AF22 AG20 AM5 AG19 AF23 AJ9 AF19 AG17 AL6 AG16 AH12 AM2 AF15 AM3 AL5 AL8 AF17 AJ11 AJ8 AF14 AJ10 AF20
=PP1V5R1V35_SW_MCP_MEM 4300 mA
=PPVCORE_S0_MCP 8450 mA (0.85V)
FBGA (9 OF 11) T3 AB22 AB20 R13 R7 T6 T13 R11 AB17 R10 AB18 T1 T2 AB21 R4 AB19 P13 R2 T8 R8 T4 R5 T7 T5 T9 U22 V22 W22 Y22 AA22 P12 P10 P11 +VDD_COREA_1 +VDD_COREA_2 +VDD_COREA_3 +VDD_COREA_4 +VDD_COREA_5 +VDD_COREA_6 +VDD_COREA_7 +VDD_COREA_8 +VDD_COREA_9 +VDD_COREA_10 +VDD_COREA_11 +VDD_COREA_12 +VDD_COREA_13 +VDD_COREA_14 +VDD_COREA_15 +VDD_COREA_16 +VDD_COREA_17 +VDD_COREA_18 +VDD_COREA_19 +VDD_COREA_20 +VDD_COREA_21 +VDD_COREA_22 +VDD_COREA_23 +VDD_COREA_24 +VDD_COREA_25 +VDD_COREA_26 +VDD_COREA_27 +VDD_COREA_28 +VDD_COREA_29 +VDD_COREA_30 +VDD_COREA_31 +VDD_COREA_32 +VDD_COREA_33
=PPVCORE_SW_MCP_GFX 15350 mA (0.85V)
21 23
14 20 22
L10 L9
+VDD_COREA_SENSE GND_COREA_SENSE
=PP1V05_S0_MCP_PE_DVDD0 200 mA (DVDD0 & DVDD1) (PE0[3:0]) =PP1V05_S0_MCP_PE_DVDD1 200 mA (DVDD0 & DVDD1) (PE0[5:4], PE1[1:0]) =PP1V05_S0_MCP_PE_AVDD0 500 mA (AVDD0 & AVDD1) (PE0[3:0])
AF7 AF8 AE9 AE10 AE6 AE7 AE8 AC13 AB12 AC12 AD11 AD13 AB13 Y12 Y13 AA13 W12 W13
+VIO_PE_DVDD0_1 +VIO_PE_DVDD0_2 +VIO_PE_DVDD0_3 +VIO_PE_DVDD0_4 +VIO_PE_DVDD1_1 +VIO_PE_DVDD1_2 +VIO_PE_DVDD1_3 +VIO_PE_AVDD0_1 +VIO_PE_AVDD0_2 +VIO_PE_AVDD0_3 +VIO_PE_AVDD0_4 +VIO_PE_AVDD0_5 +VIO_PE_AVDD0_6 +VIO_PE_AVDD1_1 +VIO_PE_AVDD1_2 +VIO_PE_AVDD1_3 +VIO_PE_AVDD1_4 +VIO_PE_AVDD1_5
+VDD_COREB_SENSE U10 GND_COREB_SENSE T10 AE1 AE2 AE3 AE4 AE5 AF1 AF2 AF3 AF4 AF5 AF6 AF9 AF10 AF11 AE11 AE12 AE13
TP_MCP_VDDCOREB_SENSEP TP_MCP_VDDCOREB_SENSEN PP1V05_S0_MCP_SATA_AVDD 300 mA

22
+VIO_SATA_AVDD_1 +VIO_SATA_AVDD_2 +VIO_SATA_AVDD_3 +VIO_SATA_AVDD_4 +VIO_SATA_AVDD_5 +VIO_SATA_DVDD_1 +VIO_SATA_DVDD_2 +VIO_SATA_DVDD_3 +VIO_SATA_DVDD_4 +VIO_SATA_DVDD_5 +VIO_SATA_DVDD_6 +VIO_SATA_DVDD_7 +VIO_SATA_DVDD_8 +VIO_SATA_DVDD_9 +VIO_SATA_DVDD_10 +VIO_SATA_DVDD_11 +VIO_SATA_DVDD_12
=PP1V05_S0_MCP_PE_AVDD1 500 mA (AVDD0 & AVDD1) (PE0[5:4], PE1[1:0])
=PP1V05_S0_MCP_SATA_DVDD 100 mA
7 22
B
22 7
=PP3V3_S0_MCP_HVDD 30 mA
T11 T12 U13
+3.3V_HVDD_1 +3.3V_HVDD_2 +3.3V_HVDD_3
22 7
=PP3V3_S0_MCP 250 mA
U11 U12 F5 E29 E5
+3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5
+VDD_DUAL_RMGT_1 L12 +VDD_DUAL_RMGT_2 L13 +3.3V_DUAL_RMGT_1 A13 +3.3V_DUAL_RMGT_2 B13 +3.3V_DUAL_USB_1 A20 +3.3V_DUAL_USB_2 A19 +3.3V_DUAL_1 F8 +3.3V_DUAL_2 E8
=PP0V9_ENET_MCP_RMGT 140 mA =PP3V3_ENET_MCP_RMGT 300 mA =PP3V3_S5_MCP 200 mA
7 22
AP21 M37 AM21 AU37 AC27 D18 B1 AD5 J2 AT1 AM30 C1 AT3 AP24 AM33 AE27 AJ24 AH18 AA8 AM18 B6 J32 AJ21 AK35 H15 D33 B18 M32 B2 E6 J5 K18 AN34 AD10 F34 V8 R35 AR9 AA2 AA10 R32 AG29 H8 AP12 AM12 AH21 V32 AR33 J7 AA32 AG34 AK37 K24 K21 J8 AG8 AN5 V2 AD32 AD2 D15 AG2 L15 AK32 AR12 AN35 AN37
FBGA (10 OF 11) GND_1 GND_68 AD7 GND_2 GND_69 B12 GND_3 GND_70 D12 GND_4 GND_71 E12 GND_5 GND_72 G12 GND_6 GND_73 A2 GND_7 GND_74 AL12 GND_8 GND_75 AM6 GND_9 GND_76 AD37 GND_10 GND_77 AG32 GND_11 GND_78 H12 GND_12 GND_79 AR35 GND_13 GND_80 H9 GND_14 GND_81 G24 GND_15 GND_82 V10 GND_16 GND_83 V5 GND_17 GND_84 AL30 GND_18 GND_85 G7 GND_19 GND_86 V29 GND_20 GND_87 AP15 GND_21 GND_88 AN2 GND_22 GND_89 AJ12 GND_23 GND_90 AR15 GND_24 GND_91 N20 GND_25 GND_92 D21 GND_26 GND_93 E21 GND_27 GND_94 G21 GND_28 GND_95 H21 GND_29 GND_96 AR27 GND_30 GND_97 AM27 GND_31 GND_98 AP27 GND_32 GND_99 AM15 GND_33 GND_100 AA31 GND_34 GND_101 AM9 GND_35 GND_102 AH24 GND_36 GND_103 K12 GND_37 GND_104 J31 GND_38 GND_105 E30 GND_39 GND_106 AK7 GND_40 GND_107 V7 GND_41 GND_108 M31 GND_42 GND_109 AU12 GND_43 GND_110 AP6 GND_44 GND_111 B37 GND_45 GND_112 A36 GND_46 GND_113 F35 GND_47 GND_114 L27 GND_48 GND_115 D35 GND_49 GND_116 AL24 GND_50 GND_117 AP30 GND_51 GND_118 AH15 GND_52 GND_119 B21 GND_53 GND_120 AV3 GND_54 GND_121 AT38 GND_55 GND_122 B38 GND_56 GND_123 AA21 GND_57 GND_124 AD4 GND_58 GND_125 A37 GND_59 GND_126 AP18 GND_60 GND_127 AN4 GND_61 GND_128 B24 GND_62 GND_129 D30 GND_63 GND_130 V4 GND_64 GND_131 AA7 GND_65 GND_132 AD34 GND_66 GND_133 AK4 GND_67 GND_134 R37
POWER I
GND
GND
7 17 22
22 7
=PP0V9_S5_MCP_VDD_AUXC 150 mA
L11 M17 M20
+VDD_DUAL_AUXC_1 +VDD_DUAL_AUXC_2 +VDD_DUAL_AUXC_3
7 22
240 mA
22 18 7
PP3V3_G3_RTC ?? uA (G3) 5 mA (S0)
40 mA
A16
+3.3V_VBAT
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Power & Ground

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

20 OF 109
SHEET
19 OF 80
C2300 helps reduce input rail droop during Q2300 turn-on.

7
=PP1V5R1V35_S0_MCPDDRFET
PLACE_NEAR=Q2300.9:2 mm
CRITICAL
C2300
100UF
Q2300
1
20% 6.3V CERM-X5R 2 1206-1
CRITICAL
9
Part Type Rds(on) Loading

NC
STMFS4854N N-Channel 10 mOhm @3.2V 4.3 A (EDP)
STMFS485NST1G
DFN
NC 8
Q2300
D
20 7
=PP5V_S3_MCPDDRFET
4 G
SENSE S
KELVIN 6
MCPDDRFET_KELVIN
OUT
44
C
65 18
VCC
C2305
0.1UF
K1
SLG5AP031
IN
U2305
TDFN
20% 2 10V CERM 402
2 3
C
MCPDDRFET_SENSE PP1V5R1V35_SW_MCP
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE (OR 1.35V)
OUT
44
NC
MCP_MEM_VDD_EN MCPMEM_CNFG
1
EN
D 5 G S
7 6 8
CRITICAL
3
CNFG
MCPMEM_GATE (G driven to VCC) TP_MCPMEM_DONE
R2305
4
1% 1/16W MF 2 402
560K
GND
DONE THRM PAD
=PP1V5R1V35_SW_MCP_MEM 4250 mA
14 19 22
<R1>
Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)
NV Requirements: - Min Ramp-Up Time: 20 uS (10% to 90%) - Max Ramp-Up Time: 65 uS (ENABLE to 90%) - FET Ron <= 3.8 mOhms NOTE: nVidia recommends Infineon BSC030N03MS for Q2300. Gated Rail Savings: 120mW
DIMM CKE Clamps

B
20 7
CRITICAL
=PP5V_S3_MCPDDRFET
Q2355
NTUD3170NZXXG
SOT-963 3 D
CKE must be held low to keep memory in self-refresh. Clamps enable before MCP89 MEMVDD rail switched off. Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89. Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM. Q2355/Q2356 chosen for low output capacitance. MEM_A_CKE<0>
BI
14 25 73
R23501
10K
5% 1/16W MF-LF 402 2
MEMVTT_EN_L
G S
Q2350
SSM3K15FV
SOD-VESM-HF
D 3
4 6 D
MEM_A_CKE<1>
BI
14 25 73
1
18
S 2
G S
IN
MCP_MEM_VTT_EN
NO STUBS on CKE signals!

CRITICAL
Q2356
NTUD3170NZXXG
SOT-963 3 D
MEM_B_CKE<0>
BI
14 26 73
G S
SYNC_MASTER=T27_MLB
PAGE TITLE
4 6 D
MCP89 Memory Rail Gating

MEM_B_CKE<1>
DRAWING NUMBER BI
14 26 73
SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE
G S

23 OF 109
SHEET
20 OF 80
C2400 helps reduce input rail droop during Q2400 turn-on.

PLACE_NEAR=C2400.1:1 mm
7
=PPVCORE_S0_MCPGFXFET
XW2400 SM
1 2
MCPCORES0_VSEN_P
OUT
62 79
CRITICAL
1
C2400
100UF
20% 2 6.3V CERM-X5R 1206-1
XW2401 SM
1 2
MCPCORES0_VSEN_N
OUT
62 79
7
=PP5V_S0_MCPFSBFET
5 1 6 7 8
Q2400
Part CRITICAL
D
Si4838BDY N-Channel 3.2 mOhm @2.5V 15.35 A (EDP)
C
18
VCC
C2405
0.1UF
4
G
Type Rds(on) Loading
SLG5AP033
IN
U2405
TDFN
20% 2 10V CERM 402
Q2400
SI4838BDY
SO-8
GFXVCORE_PWR_EN MCPGFX_CNFG
1
EN
D 5 G S
7 6 8
CRITICAL
3
CNFG
MCPGFX_GATE (G driven to VCC) TP_MCPGFX_DONE
PPVCORE_SW_MCP_GFX
C2406
820PF
GND
4
10% 50V 2 CERM 402
DONE THRM PAD

9
=PPVCORE_SW_MCP_GFX
19 23
<C1>
Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)
NV Requirements: - Min Ramp-Up Time: 100 uS (10% to 90%) - Max Ramp-Up Time: 1500 uS (ENABLE to 90%) - FET Ron <= 2.5 mOhms NOTE: nVidia recommends Infineon BSC020N03MS for Q2400. Gated Rail Savings: 860mW
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP89 GFX Core Rail Gating

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

24 OF 109
SHEET
21 OF 80
8
MCP Non-GFX Core Power
19 7
5
7
4
=PP1V05_S0_MCP_AVDD_UF 800 mA 30-OHM-5A
1 0603 2
3
L2560
1
MCP 1.05V PCIe Analog Power
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
=PPVCORE_S0_MCP 8450 mA (0.85V)
PP1V05_S0_MCP_PE_AVDD 500 mA
C2500 1
10UF
20% 6.3V X5R 2 603-1
C2501
4.7UF
C2502
1UF
C2503
0.22UF
C2504
0.1UF
C2505
0.1UF
C2506
0.1UF
C2507
0.1UF
C2508
0.1UF
C2560 1
10UF
20% 6.3V X5R 2 603-1
C2561
4.7UF
C2562
1UF
C2563
1UF
C2564
0.1UF
C2565
0.1UF
C2566
0.1UF
20% 4V 2 X5R 402
10% 10V 2 X5R 402-1
20% 6.3V 2 X5R 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 4V 2 X5R 402
10% 10V 2 X5R 402-1
10% 10V 2 X5R 402-1
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
D
20 19 14
MCP Memory Power =PP1V5R1V35_SW_MCP_MEM 4300 mA (1.5V)
30-OHM-5A
1 0603 2
L2567
MCP 1.05V SATA Analog Power PP1V05_S0_MCP_SATA_AVDD 19 MIN_LINE_WIDTH=0.4 MM 300 mA MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V
1
C2567 1
1
C2510 1
4.7UF
20% 4V X5R 2 402
C2511
0.1UF
C2512
0.1UF
C2513
0.1UF
C2514
0.1UF
C2515
0.1UF
C2516
0.1UF
C2517
0.1UF
C2518
0.1UF
C2519
0.1UF
10UF
C2568
4.7UF
C2569
0.1UF
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 6.3V X5R 2 603-1
20% 4V 2 X5R 402
20% 10V 2 CERM 402
CRITICAL MCP CPU FSB (VTT) Power

19 7
MCP S0 FSB (VTT) Power

19 13 7
=PP1V05_SW_MCP_FSB 2000 mA
=PP1V05_S0_MCP_FSB 200 mA
=PP1V05_S0_MCP_PLL_UF 555 mA
220-OHM-2.2A
1 0603 2
L2570
MCP 1.05V CPU/FSB/MEM PLL Power

1 1
PP1V05_S0_MCP_PLL_FSBMEM 70 mA
14
C2570
4.7UF
1 1
C2571
0.1UF
C2572
0.1uF
C2573
0.1UF
C2520
10UF
C2521
4.7UF
C2522
1UF
C2523
1UF
C2524
4.7UF
C2525
1UF
20% 6.3V X5R 2 603-1
20% 4V 2 X5R 402
10% 10V 2 X5R 402-1
10% 10V 2 X5R 402-1
20% 4V X5R 2 402
10% 10V 2 X5R 402-1
20% 4V 2 PLACE_NEAR=R2570.1:50 mil X5R 402
R2570
1
CRITICAL MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=0V 220-OHM-2.2A

1 0603 2
GND_MCP_PLL_FSB
0.33 2
5% 1/16W MF 0402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
MCP 1.05V PCIe/SATA PLL Power PP1V05_S0_MCP_PLL_PEXSATA

15
L2575
MCP 0.9V AUX Core Power

19 7
MCP 0.9V MAC/SMU Power

19 7
=PP0V9_S5_MCP_VDD_AUXC 150 mA
1
=PP0V9_ENET_MCP_RMGT 140 mA
C2579
1
325 mA
C2575 1
4.7UF
1
C2576
0.1UF
C2577
0.1uF
C2578
0.1UF
0.1UF
20% 10V CERM 402
C2526
0.1uF
C2527
0.1uF
C2528
4.7uF
C2529
0.1uF
20% 4V
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 4V X5R 2 402
20% 10V 2 CERM 402
PLACE_NEAR=R2575.1:50 mil X5R 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
CRITICAL 220-OHM-2.2A MCP 1.05V PCIE Digital Power

7
L2580
0603
MCP 1.05V SATA Digital Power

19 7
MCP 1.05V Core/Misc PLL Power PP1V05_S0_MCP_PLL_CORE 16 160 mA
=PP1V05_S0_MCP_PE_DVDD 200 mA
=PP1V05_S0_MCP_SATA_DVDD 100 mA
C2584
0.1UF
20% 10V CERM 402
C2580 1
4.7UF
20% 402
C2581
0.1UF
C2582
0.1uF
C2583
0.1UF
C2530 1
4.7UF
20% 4V X5R 2 402
C2531
1UF
C2532
1UF
C2533
0.1uF
C2534
0.1uF
C2535
0.1uF
C2536
4.7UF
C2537
0.1uF
4V 2 PLACE_NEAR=R2580.1:50 mil X5R
20% 10V 2 CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
10% 10V 2 X5R 402-1
10% 10V 2 X5R 402-1
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 4V X5R 2 402
20% 10V 2 CERM 402
=PP3V42_G3H_OPA330
1
MCP 3.3V PCIe/SATA I/O PLL Power MCP 1.05V Memory DLL Power
19 7 14 7
=PP1V05_S0_MCP_M2CLK_DLL 550 mA
=PP3V3_S0_MCP_HVDD 30 mA
C2599
2
HTOL_SENSE:YES HTOL_SENSE:YES
SMC_N_MIRROR
4 2
0.1UF
20% 10V CERM 402
R2597
1K
3 -IN
1% 1/16W MF-LF 402
VV+
5
C2540 1
4.7UF
20% 4V X5R 2 402
C2541
4.7UF
C2542
0.1uF
4
5
1 +IN
SC70-5
HTOL_SENSE:YES SOT-563-HF NTZD3152P
G D
3
Q2592
20% 6.3V CERM 2 603
20% 10V 2 CERM 402
OPA330
B
MCP 3.3V I/O Power
19 7
MCP 3.3V/1.5V HDA Power 18 8 =PP3V3R1V5_S0_MCP_HDA 70 mA
C2543 1
4.7uF
20% 6.3V CERM 2 603
C2544
0.1uF
C2545
0.1uF
C2546
0.1uF
C2547
0.1uF
C2548 1
4.7UF
20% 6.3V CERM 2 603
C2549
0.1uF
MCPHVDD:P3V3 R2593 R2596 =PP3V3_S0_MCP_PLL_UF 0 1K 2 PP3V3_S0_LDO_R 1 2 1 260 mA MIN_LINE_WIDTH=0.4 MM CRITICAL 5% 1% MIN_NECK_WIDTH=0.2 MM 1/16W 1/16W MCPHVDD:P2V5 VOLTAGE=3.3V Q2592 MF-LF MF-LF MCPHVDD:P2V5 NTZD3152P 1 C2593 402 402 1 SOT-563-HF R2592 1UF LDO:ADJ HTOL_SENSE:YES 10K 10% CRITICAL 1 10V 5% R2594 2 OMIT_TABLE X5R MCPHVDD:P2V5 1/16W
7
=PP3V3_S0_OPA333 HTOL_SENSE:YES
7
CRITICAL HTOL_SENSE:YES HTOL_SENSE:YES
U2593
CRITICAL
R2590
1
100K 2
1% 1/16W MF-LF 402
HTOL_SENSE:YES CRITICAL U2594 PLACEMENT_NOTEs: OPA330 Place close to SMC SC70-5 (For R and C) HTOL_SENSE:YES
SMC_P_FOLLOW
1 3
+IN -IN
V+ V2
R2598
4
1
4.53K 2
1% 1/16W MF-LF 402
SMC_NB_MISC_ISENSE
OUT 1
HTOL_SENSE:YES
2
C2598
0.22UF
20% 6.3V X5R
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
MF-LF 402 2
402
U2592
GND 2
10K
MIC5365-2.5V 1 VIN SC70 VOUT 5
5% 1/16W MF-LF 402 2
C2592
1UF
C2594
0.1UF
20% 10V CERM 402
MCP_PLL_LD0_EN
3 EN
NC 4 LDO_ADJ
10% 10V 2 X5R 402
CRITICAL
2 402
FERR-240-OHM-200MA
PP3V3_S0_MCP_HVDD
L2590
0402
SMC_N_FOLLOW
MCP 3.3V AUX/USB Power

19 7
LDO:ADJ
10K
5% 1/16W MF-LF 402
MCP 2.0V-3.3V RTC Power

19 18 7
R2591
C2550 1
4.7uF
20% 6.3V CERM 2 603
C2551
0.1uF
20% 10V 2 CERM 402
PP3V3_G3_RTC ? uA (G3) 5 mA (S0) C2552 4.7UF
SMC_P10 HTOL_SENSE:YES
39
IN
C2590
4.7UF
20% 6.3V CERM 603
43 GND_SMC_AVSS 39 40 44 MCP 3.3V PLL Power PP3V3_S0_MCP_PLL_HVDD 15 MIN_LINE_WIDTH=0.4 MM 50 mA MIN_NECK_WIDTH=0.2 MM
C2591
2 2
VOLTAGE=3.3V
R2599
100K
5% 1/16W MF-LF 402
0.1UF
20% 10V CERM 402
CRITICAL 220-OHM-2.2A
1 0603 2
20% 6.3V CERM 2 603
L2595
MCP 3.3V DP & USB PLL Power PP3V3_S0_MCP_PLL_DP_USB MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 210 mA
VOLTAGE=3.3V
1
C2595 1
MCP 3.3V MAC/SMU Power
C2596
0.1UF
C2597
0.1uF
SYNC_MASTER=T27_MLB
PAGE TITLE
19 17 7
=PP3V3_ENET_MCP_RMGT 300 mA
MCP 3.3V MAC PLL Power

7
CRITICAL FERR-240-OHM-200MA
1 0402 2
L2555
20% 6.3V 2 PLACE_NEAR=R2595.1:50 mil CERM 603
4.7UF
=PP3V3_ENET_MCP_PLL_MAC 20 mA
C2553 1
4.7uF
20% 6.3V CERM 2 603
C2554
0.1uF

1
PP3V3_ENET_MCP_PLL_MAC 20 mA
R2595
1
20% 10V 2 CERM 402
20% 10V 2 CERM 402
39
HTOL_SENSE:YES
17
GND_MCP_PLL_DP_USB
0.33 2
5% 1/16W MF 0402
MCP Standard Decoupling

DRAWING NUMBER SIZE
20% 10V 2 CERM 402
C2555 1
4.7UF
20% 6.3V 2 CERM 603
C2556
0.1UF
20% 2 10V CERM 402
Apple Inc.
PART NUMBER
353S2971 353S2979 116S0004
051-8563
REVISION
QTY
1 1 1
DESCRIPTION
IC,LDO,MIC5365,2.5V,150MA,2%,SC70-5,HFLF
REFERENCE DES
U2592 U2592 R2596
CRITICAL
CRITICAL CRITICAL CRITICAL
BOM OPTION
LDO:FIXED LDO:ADJ HTOL_SENSE:NO
A.13.0
BRANCH PAGE

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF RES,0402,0,5%,1/16W
25 OF 109
SHEET
22 OF 80
8
MCP GFX Core Power
21 19
=PPVCORE_SW_MCP_GFX 15350 mA (0.85V)
C2600 1
10UF
20% 6.3V X5R 2 603-1
C2601
4.7UF
C2602
1UF
C2603
1UF
C2604
0.22UF
C2605
0.22UF
C2606
0.1UF
C2607
0.1UF
C2608
0.1UF
C2609
0.1UF
C2610
0.1UF
C2611
0.1UF
C2612
0.1UF GND_MCP_DAC_P3V3
MCP 3.3V RGBDAC Power

1 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V MAKE_BASE=TRUE
20% 4V 2 X5R 402
10% 10V 2 X5R 402-1
10% 10V 2 X5R 402-1
20% 6.3V 2 X5R 402
20% 6.3V 2 X5R 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
R2670
0
PP3V3_S0_MCP_DAC 140 mA
16
D
MCP 3.3V/1.8V IFP Interface Power
16 7
5% 1/16W MF-LF 402 2
If RGBDAC is used, requires ferrite (155S0382) plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap. If RGBDAC is not used, tie to GND.
MCP 1.05V IFP PLL Power

16 7
=PP3V3R1V8_S0_MCP_IFP_VDD 180 mA (1.8V LVDS)
=PP1V05_S0_MCP_PLL_IFP 60 mA
C2620 1
4.7uF
20% 6.3V 2 CERM 603
C2621
0.1uF
C2630 1
4.7uF
20% 4V X5R 2 402
C2631
0.1uF
20% 2 10V CERM 402
20% 2 10V CERM 402
MCP 1.05V DisplayPort Power

16 7
=PP1V05_S0_MCP_DP0_VDD 160 mA
C2640 1
4.7UF
20% 4V X5R 2 402
C2641
0.1uF
20% 10V 2 CERM 402
74 16 74 16
MCP_TMDS0_RSET MCP_TMDS0_VPROBE NO STUFF
74 16 74 16
C2650
0.1UF
R2650
1K
MCP_IFPAB_RSET MCP_IFPAB_VPROBE NO STUFF
NO STUFF
1
20% 10V CERM 2 402
1% 1/16W MF-LF 2 402
C2655
0.1UF
R2655
1K
20% 10V CERM 2 402
1% 1/16W MF-LF 2 402
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Graphics Support

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

26 OF 109
SHEET
23 OF 80
RTC Crystal
R2810
18
Platform Reset Connections

C2810
12pF
LPC Reset (Unbuffered)

R2881
75 18
IN
RTC_CLK32K_XTALOUT NO STUFF
0
5% 1/16W MF-LF 402
RTC_CLK32K_XTALOUT_R CRITICAL
4
1 5% 50V CERM 402
R2811 1
IN
LPC_RESET_L
PLACEMENT_NOTE=Place close to U1400
33
5% 1/16W MF-LF 402
LPCPLUS_RESET_L
OUT
41
D
18
10M
5% 1/16W MF-LF 402 2
Y2810
32.768K
7X1.5X1.4-SM 1
R2883
1
D
39
C2811
12pF
1 5% 50V CERM 402 2
33
5% 1/16W MF-LF 402
SMC_LRESET_L
OUT
OUT
RTC_CLK32K_XTALIN
MCP 25MHz Crystal

R2815
18
C2815
12pF MCP_CLK25M_XTALOUT_R CRITICAL
1 5% 50V CERM 402 2
PCIE Reset (Unbuffered)
IN
MCP_CLK25M_XTALOUT NO STUFF
0
1 5% 1/16W MF-LF 402 2
R2816
1M
5% 1/16W MF-LF 402
18
18 15
IN
PCIE_RESET_L
MAKE_BASE=TRUE
=FW_RESET_L
OUT
34
Y2815
25.0000M
2 1 SM-3.2X2.5MM
4 2
NC NC
C2816
12pF
1 5% 50V CERM 402 2
R2891
1
0
5% 1/16W MF-LF 402
PCA9557D_RESET_L
OUT
28
OUT
MCP_CLK25M_XTALIN
R2893
1
0
5% 1/16W MF-LF 402
BKLT_PLT_RST_L
OUT
71
Caesar II (ENET) 25MHz Crystal

C
R2820
31
R2894
0
1 2 5% 1/16W MF-LF 402
AP_RESET_L
OUT
29
C2820
27pF BCM5764_CLK25M_XTALO_R CRITICAL
1 5% 50V CERM 402 2 1
IN
BCM5764_CLK25M_XTALO NO STUFF
200
1 5% 1/16W MF-LF 402 2
R2895
0
2 5% 1/16W MF-LF 402 1
C
SDCARD_PLT_RST_L
OUT
30
R2821
10M
5% 1/16W MF-LF 402 2

31
Y2820
25.0000M
1 SM-3.2X2.5MM
NC NC
R2892
0
5% 1/16W MF-LF 402 2
ENET_RESET_L
C2821
27pF
1 5% 50V CERM 402 2
OUT
31 76
OUT
BCM5764_CLK25M_XTALI
R2825
75 18
IN
LPC_CLK33M_SMC_R
33
5% 1/16W MF-LF 402
LPC_CLK33M_SMC
OUT
39 75
R2826
33
1 5% 1/16W MF-LF 402 2
LPC_CLK33M_LPCPLUS
OUT
41 75
Ethernet WAKE# Isolation

B
1
=PP3V3_ENET_PHY
B
7 31 64
Q2830
G
SSM3K15FV
SOD-VESM-HF
2
R2830
10K
5% 1/16W MF-LF 402
75 18
R2829
IN
PM_CLK32K_SUSCLK_R
22
1 PLACEMENT_NOTE=Place close to U1400 5% 1/16W MF-LF 402 2
PM_CLK32K_SUSCLK
OUT
39 75
29 15 6
OUT
PCIE_WAKE_L
3
ENET_WAKE_L
MAKE_BASE=TRUE
=ENET_WAKE_L
IN
31
MCP S0 PWRGD & CPU_VLD

7
=PP3V3_S5_MCPPWRGD
System Reset Circuit

1
C2850
0.1UF
20% 10V CERM 402
39
IN
PM_SYSRST_L XDP
A
5
65 39
R2896
12 9
R2899
1
10K pull-up to 3.3V S0 inside MCP PM_SYSRST_DEBOUNCE_L NO STUFF

1
IN
XDP_DBRESET_L
0
5% 1/16W MF-LF 402
33
5% 1/16W MF-LF 402
SYNC_MASTER=T27_MLB
OUT
18
PAGE TITLE
OMIT
IN
ALL_SYS_PWRGD VR_PWRGOOD_DELAY
74LVC1G08GW
SOT353 4 MCP_PS_PWRGD OUT
18
R2897 1
0
5% 1/16W MF-LF 402
C2899
1UF
10% 10V X5R 402
SB Misc
DRAWING NUMBER SIZE
B A
3
61
IN
U2850 Y
2 2
Apple Inc.
R
051-8563
REVISION
SILK_PART=SYS RST PLACEMENT_NOTE=Place R2897 on BOTTOM
A.13.0
BRANCH PAGE

28 OF 109
SHEET
24 OF 80
8 Page Notes
Power aliases required by this page: - =PPLVDDR_S3_MEM_A - =PPDDRVTT_S0_MEM_A - =PPSPD_S0_MEM_A (2.5 - 3.3V) Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA BOM options provided by this page: (NONE)
=PPLVDDR_S3_MEM_A
DDR3 Plane Stitching Caps (Space evenly across plane split)

1
C2900
10UF
20% 6.3V X5R 603
C2901
10UF
20% 6.3V X5R 603
C2910
0.1UF
20% 10V CERM 402
C2911
0.1UF
20% 10V CERM 402
C2912
0.1UF
20% 10V CERM 402
C2913
0.1UF
20% 10V CERM 402
C2914
0.1UF
20% 10V CERM 402
C2915
0.1UF
20% 10V CERM 402
C2916
0.1UF
20% 10V CERM 402
C2917
0.1UF
20% 10V CERM 402
C2918
0.1UF
20% 10V CERM 402
C2919
0.1UF
20% 10V CERM 402
C2920
0.1UF
20% 10V CERM 402
C2921
0.1UF
20% 10V CERM 402
C2922
0.1UF
20% 10V CERM 402
C2923
0.1UF
20% 10V CERM 402
D
7
=PPDDRVTT_S0_MEM_A
"Factory" (top) slot

28 73 20 14
PPVREF_S3_MEM_VREFDQ_A
1 3
IN
MEM_A_CKE<0>
73 75
KEY
NC
73 14
77 79 81
IN
MEM_A_BA<2> MEM_A_A<12> MEM_A_A<9> MEM_A_A<8> MEM_A_A<5> MEM_A_A<3> MEM_A_A<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_A<10> MEM_A_BA<0> MEM_A_WE_L MEM_A_CAS_L MEM_A_A<13> MEM_A_CS_L<1>
73 14 73 14
IN IN
83 85 87
73 14 73 14
IN IN
89 91 93
73 14 73 14
IN IN
95 97 99
73 14
IN IN
101 103 105
73 14
73 14 73 14
IN IN
107 109 111
73 14 73 14
IN IN
113 115 117
73 14 73 14
IN IN
119 121 123
NC
27 27
125 127
BI BI
=MEM_A_DQ<32> =MEM_A_DQ<33> =MEM_A_DQS_N<4> =MEM_A_DQS_P<4> =MEM_A_DQ<34> =MEM_A_DQ<35> =MEM_A_DQ<40> =MEM_A_DQ<41> =MEM_A_DM<5> =MEM_A_DQ<42> =MEM_A_DQ<43> =MEM_A_DQ<48> =MEM_A_DQ<49> =MEM_A_DQS_N<6> =MEM_A_DQS_P<6> =MEM_A_DQ<50> =MEM_A_DQ<51> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DM<7> =MEM_A_DQ<58> =MEM_A_DQ<59> MEM_A_SA<0> MEM_A_SA<1>
129 131 133
27 27
BI BI
135 137 139
27 27
BI BI
141 143 145
27 27
BI BI
147 149 151
27
IN
153 155
27 27
BI BI
157 159 161
27 27
BI BI
163 165 167
27 27
BI BI
169 171 173
27 27
BI BI
175 177 179
27 27
BI BI
181 183 185
27
IN
187 189
27 27
BI BI
191 193 195
=PPSPD_S0_MEM_A
197 199 201 203
CKE0 CKE1 VDD CRITICAL VDD NC A15 J2900 BA2 A14 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 RAS* BA0 VDD VDD WE* S0* CAS* ODT0 VDD VDD ODT1 A13 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DM4 DQS4* DQS4 VSS DQ38 VSS DQ39 DQ34 DQ35 VSS VSS DQ44 DQ45 DQ40 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 VSS DQS6 DQ54 VSS DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SCL SA1 VTT VTT DDR3-SODIMM-DUAL-M97-3 (SYMBOL 2 OF 2)
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
MEM_A_CKE<1> MEM_A_A<15> MEM_A_A<14> MEM_A_A<11> MEM_A_A<7> MEM_A_A<6> MEM_A_A<4> MEM_A_A<2> MEM_A_A<0> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_BA<1> MEM_A_RAS_L MEM_A_CS_L<0> MEM_A_ODT<0> MEM_A_ODT<1>
IN
14 20 73
IN IN
14 73 14 73
C2930
2.2UF
20% 6.3V CERM 402-LF
C2931
0.1UF
20% 10V CERM 402
27 27
BI BI
=MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DM<0> =MEM_A_DQ<2> =MEM_A_DQ<3> =MEM_A_DQ<8> =MEM_A_DQ<9> =MEM_A_DQS_N<1> =MEM_A_DQS_P<1> =MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<16> =MEM_A_DQ<17> =MEM_A_DQS_N<2> =MEM_A_DQS_P<2> =MEM_A_DQ<18> =MEM_A_DQ<19> =MEM_A_DQ<24> =MEM_A_DQ<25> =MEM_A_DM<3> =MEM_A_DQ<26> =MEM_A_DQ<27>
5 7 9
IN IN
14 73 14 73
27
IN
11 13
27
BI BI
15 17 19
IN IN
14 73 14 73
27
27
BI BI
21 23 25
IN IN
14 73 14 73
27
27
BI BI
27 29 31
IN IN
14 73 14 73
27
27
BI BI
33 35 37
IN IN
14 73 14 73
27
27
BI BI
39 41 43
IN IN
14 73 14 73
27
27
BI BI
45 47 49
IN
14 73
27
NC
PPVREF_S3_MEM_VREFCA_A
28 27 27
BI BI
51 53 55
=MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DM<4> =MEM_A_DQ<38> =MEM_A_DQ<39> =MEM_A_DQ<44> =MEM_A_DQ<45> =MEM_A_DQS_N<5> =MEM_A_DQS_P<5> =MEM_A_DQ<46> =MEM_A_DQ<47> =MEM_A_DQ<52> =MEM_A_DQ<53> =MEM_A_DM<6> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<60> =MEM_A_DQ<61> =MEM_A_DQS_N<7> =MEM_A_DQS_P<7> =MEM_A_DQ<62> =MEM_A_DQ<63> MEM_EVENT_L =I2C_SODIMMA_SDA =I2C_SODIMMA_SCL
BI BI
27 27
C2936
0.1UF
20% 10V CERM 402
C2935
2.2UF
20% 6.3V CERM 402-LF
27 27
BI BI
57 59 61
IN
27
27
IN
63 65
BI BI
27 27
27 27
BI BI
67 69 71
VREFDQ VSS VSS DQ4 DQ0 DQ5 DQ1 CRITICAL VSS DQS0* VSS J2900 DM0 DQS0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 RESET* DQS1 VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ16 DQ20 DQ17 DQ21 VSS VSS DQS2* DM2 VSS DQS2 VSS DQ22 DQ23 DQ18 VSS DQ19 DQ28 VSS DQ24 DQ29 VSS DQ25 DQS3* VSS DQS3 DM3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS VSS DDR3-SODIMM-DUAL-M97-3 (SYMBOL 1 OF 2)
KEY
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
=MEM_A_DQ<4> =MEM_A_DQ<5> =MEM_A_DQS_N<0> =MEM_A_DQS_P<0> =MEM_A_DQ<6> =MEM_A_DQ<7> =MEM_A_DQ<12> =MEM_A_DQ<13> =MEM_A_DM<1> MEM_RESET_L =MEM_A_DQ<14> =MEM_A_DQ<15> =MEM_A_DQ<20> =MEM_A_DQ<21> =MEM_A_DM<2> =MEM_A_DQ<22> =MEM_A_DQ<23> =MEM_A_DQ<28> =MEM_A_DQ<29> =MEM_A_DQS_N<3> =MEM_A_DQS_P<3> =MEM_A_DQ<30> =MEM_A_DQ<31>
BI BI
27 27
BI BI
27 27
BI BI
27 27
BI BI
27 27
IN IN
27 14 26
BI BI
27 27
BI BI
27 27
IN
27
BI BI
27 27
BI BI
27 27
BI BI
27 27
BI BI
27 27
BI BI
27 27
516-0201
BI BI
27 27
BI BI
27 27
BI BI
27 27
IN
27
BI BI
27 27
BI BI
27 27
BI BI
27 27
BI BI
27 27
OUT BI IN
18 26 39 42 42
C2940
R2940
10K
R2941
10K
2.2UF
20% 6.3V CERM 402-LF 2
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
516-0201
SYNC_MASTER=T27_MLB
PAGE TITLE
DDR3 SO-DIMM Connector A

SPD Addr: 0xA0(Wr)/0xA1(Rd)
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

29 OF 109
SHEET
25 OF 80
8 Page Notes
Power aliases required by this page: - =PPLVDDR_S3_MEM_B - =PPDDRVTT_S0_MEM_B - =PPSPD_S0_MEM_B (2.5 - 3.3V) Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA BOM options provided by this page: (NONE)
=PPLVDDR_S3_MEM_B
DDR3 Plane Stitching Caps (Space evenly across plane split)

1
C3100
10UF
20% 6.3V X5R 603
C3101
10UF
20% 6.3V X5R 603
C3110
0.1UF
20% 10V CERM 402
C3111
0.1UF
20% 10V CERM 402
C3112
0.1UF
20% 10V CERM 402
C3113
0.1UF
20% 10V CERM 402
C3114
0.1UF
20% 10V CERM 402
C3115
0.1UF
20% 10V CERM 402
C3116
0.1UF
20% 10V CERM 402
C3117
0.1UF
20% 10V CERM 402
C3118
0.1UF
20% 10V CERM 402
C3119
0.1UF
20% 10V CERM 402
C3120
0.1UF
20% 10V CERM 402
C3121
0.1UF
20% 10V CERM 402
C3122
0.1UF
20% 10V CERM 402
C3123
0.1UF
20% 10V CERM 402
D
7
=PPDDRVTT_S0_MEM_B
"Expansion" (bottom) slot

28 73 20 14
PPVREF_S3_MEM_VREFDQ_B
1 3
IN
MEM_B_CKE<0>
73 75
KEY
NC
73 14
77 79 81
IN
MEM_B_BA<2> MEM_B_A<12> MEM_B_A<9> MEM_B_A<8> MEM_B_A<5> MEM_B_A<3> MEM_B_A<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_A<10> MEM_B_BA<0> MEM_B_WE_L MEM_B_CAS_L MEM_B_A<13> MEM_B_CS_L<1>
73 14 73 14
IN IN
83 85 87
73 14 73 14
IN IN
89 91 93
73 14 73 14
IN IN
95 97 99
73 14
IN IN
101 103 105
73 14
73 14 73 14
IN IN
107 109 111
73 14 73 14
IN IN
113 115 117
73 14 73 14
IN IN
119 121 123
NC
27 27
125 127
BI BI
=MEM_B_DQ<32> =MEM_B_DQ<33> =MEM_B_DQS_N<4> =MEM_B_DQS_P<4> =MEM_B_DQ<34> =MEM_B_DQ<35> =MEM_B_DQ<40> =MEM_B_DQ<41> =MEM_B_DM<5> =MEM_B_DQ<42> =MEM_B_DQ<43> =MEM_B_DQ<48> =MEM_B_DQ<49> =MEM_B_DQS_N<6> =MEM_B_DQS_P<6> =MEM_B_DQ<50> =MEM_B_DQ<51> =MEM_B_DQ<56> =MEM_B_DQ<57> =MEM_B_DM<7> =MEM_B_DQ<58> =MEM_B_DQ<59> MEM_B_SA<0> MEM_B_SA<1>
129 131 133
27 27
BI BI
135 137 139
27 27
BI BI
141 143 145
27 27
BI BI
147 149 151
27
IN
153 155
27 27
BI BI
157 159 161
27 27
BI BI
163 165 167
27 27
BI BI
169 171 173
27 27
BI BI
175 177 179
=PPSPD_S0_MEM_B
27 27
BI BI
181 183 185
27
R3140
10K
5% 1/16W MF-LF 402
27 27
IN
187 189
BI BI
191 193 195 197 199 201 203
CKE0 CKE1 VDD VDD NC A15 CRITICAL A14 BA2 J3100 VDD VDD F-RT-BGA3 A11 A12/BC* A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 RAS* BA0 VDD VDD S0* WE* CAS* ODT0 VDD VDD ODT1 A13 S1* NC VDD VDD TEST VREFCA VSS VSS DQ36 DQ32 DQ37 DQ33 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ34 DQ39 DQ35 VSS DQ44 VSS DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS DQS7* VSS DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS EVENT* SA0 VDDSPD SDA SA1 SCL VTT VTT
DDR3-SODIMM
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212
MEM_B_CKE<1> MEM_B_A<15> MEM_B_A<14> MEM_B_A<11> MEM_B_A<7> MEM_B_A<6> MEM_B_A<4> MEM_B_A<2> MEM_B_A<0> MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_BA<1> MEM_B_RAS_L MEM_B_CS_L<0> MEM_B_ODT<0> MEM_B_ODT<1>
IN
14 20 73
IN IN
14 73 14 73
C3130
2.2UF
20% 6.3V CERM 402-LF
C3131
0.1UF
20% 10V CERM 402
27 27
BI BI
=MEM_B_DQ<0> =MEM_B_DQ<1> =MEM_B_DM<0> =MEM_B_DQ<2> =MEM_B_DQ<3> =MEM_B_DQ<8> =MEM_B_DQ<9> =MEM_B_DQS_N<1> =MEM_B_DQS_P<1> =MEM_B_DQ<10> =MEM_B_DQ<11> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQS_N<2> =MEM_B_DQS_P<2> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<24> =MEM_B_DQ<25> =MEM_B_DM<3> =MEM_B_DQ<26> =MEM_B_DQ<27>
5 7 9
IN IN
14 73 14 73
27
IN
11 13
27
BI BI
15 17 19
IN IN
14 73 14 73
27
27
BI BI
21 23 25
IN IN
14 73 14 73
27
27
BI BI
27 29 31
IN IN
14 73 14 73
27
27
BI BI
33 35 37
IN IN
14 73 14 73
27
27
BI BI
39 41 43
IN IN
14 73 14 73
27
27
BI BI
45 47 49
IN
14 73
27
NC
PPVREF_S3_MEM_VREFCA_B
28 27 27
BI BI
51 53 55
=MEM_B_DQ<36> =MEM_B_DQ<37> =MEM_B_DM<4> =MEM_B_DQ<38> =MEM_B_DQ<39> =MEM_B_DQ<44> =MEM_B_DQ<45> =MEM_B_DQS_N<5> =MEM_B_DQS_P<5> =MEM_B_DQ<46> =MEM_B_DQ<47> =MEM_B_DQ<52> =MEM_B_DQ<53> =MEM_B_DM<6> =MEM_B_DQ<54> =MEM_B_DQ<55> =MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQS_N<7> =MEM_B_DQS_P<7> =MEM_B_DQ<62> =MEM_B_DQ<63> MEM_EVENT_L =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL
BI BI
27 27
C3136
0.1UF
20% 10V CERM 402
C3135
2.2UF
20% 6.3V CERM 402-LF
27 27
BI BI
57 59 61
IN
27
27
IN
63 65
BI BI
27 27
27 27
BI BI
67 69 71
VREFDQ VSS VSS DQ4 DQ5 DQ0 DQ1 CRITICAL VSS VSS DQS0* J3100 DQS0 DM0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ10 DQ14 DQ11 DQ15 VSS VSS DQ16 DQ20 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS VSS DQ22 DQ18 DQ23 VSS DQ19 VSS DQ28 DQ29 DQ24 VSS DQ25 DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS
DDR3-SODIMM
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
=MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQS_N<0> =MEM_B_DQS_P<0> =MEM_B_DQ<6> =MEM_B_DQ<7> =MEM_B_DQ<12> =MEM_B_DQ<13> =MEM_B_DM<1> MEM_RESET_L =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DM<2> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<28> =MEM_B_DQ<29> =MEM_B_DQS_N<3> =MEM_B_DQS_P<3> =MEM_B_DQ<30> =MEM_B_DQ<31>
BI BI
27 27
BI BI
27 27
(2 OF 2)
(1 OF 2)
BI BI
27 27
BI BI
27 27
IN IN
27 14 25
BI BI
27 27
BI BI
27 27
IN
27
BI BI
27 27
BI BI
27 27
BI BI
27 27
BI BI
27 27
BI BI
27 27
KEY
516s0706
BI BI
27 27
BI BI
27 27
BI BI
27 27
IN
27
BI BI
27 27
BI BI
27 27
BI BI
27 27
BI BI
27 27
OUT BI IN
18 25 39 42 42
C3140
R3141
10K
205 207 209 211
MTG PINS
2.2UF
20% 6.3V CERM 402-LF 2
5% 1/16W MF-LF 2 402
MTG PIN MTG PIN MTG PIN MTG PIN
MTG PIN
MTG PIN
MTG PIN
MTG PIN
SYNC_MASTER=T27_MLB
PAGE TITLE
DDR3 SO-DIMM Connector B

SPD Addr: 0xA2(Wr)/0xA3(Rd)
DRAWING NUMBER SIZE
516s0706
R
Apple Inc.
051-8563
REVISION
A.13.0
BRANCH PAGE
31 OF 109
SHEET
26 OF 80
8
73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
7
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
6
MCP CHANNEL B DQS 0 -> DIMM B DQS 0
25 25 25 25 25 25 25 25 25 25 25 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
5
=MEM_B_DQ<5> =MEM_B_DQ<4> =MEM_B_DQ<3> =MEM_B_DQ<7> =MEM_B_DQ<1> =MEM_B_DQ<0> =MEM_B_DQ<6> =MEM_B_DQ<2> =MEM_B_DM<0> =MEM_B_DQS_N<0> =MEM_B_DQS_P<0> =MEM_B_DQ<21> =MEM_B_DQ<20> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DM<2> =MEM_B_DQS_N<2> =MEM_B_DQS_P<2> =MEM_B_DQ<14> =MEM_B_DQ<11> =MEM_B_DQ<12> =MEM_B_DQ<8> =MEM_B_DQ<10> =MEM_B_DQ<15> =MEM_B_DQ<13> =MEM_B_DQ<9> =MEM_B_DM<1> =MEM_B_DQS_N<1> =MEM_B_DQS_P<1> =MEM_B_DQ<28> =MEM_B_DQ<24> =MEM_B_DQ<26> =MEM_B_DQ<30> =MEM_B_DQ<25> =MEM_B_DQ<29> =MEM_B_DQ<31> =MEM_B_DQ<27> =MEM_B_DM<3> =MEM_B_DQS_N<3> =MEM_B_DQS_P<3> =MEM_B_DQ<32> =MEM_B_DQ<37> =MEM_B_DQ<34> =MEM_B_DQ<35> =MEM_B_DQ<36> =MEM_B_DQ<33> =MEM_B_DQ<39> =MEM_B_DQ<38> =MEM_B_DM<4> =MEM_B_DQS_N<4> =MEM_B_DQS_P<4> =MEM_B_DQ<42> =MEM_B_DQ<44> =MEM_B_DQ<41> =MEM_B_DQ<40> =MEM_B_DQ<47> =MEM_B_DQ<45> =MEM_B_DQ<46> =MEM_B_DQ<43> =MEM_B_DM<5> =MEM_B_DQS_N<5> =MEM_B_DQS_P<5> =MEM_B_DQ<49> =MEM_B_DQ<53> =MEM_B_DQ<50> =MEM_B_DQ<51> =MEM_B_DQ<52> =MEM_B_DQ<48> =MEM_B_DQ<55> =MEM_B_DQ<54> =MEM_B_DM<6> =MEM_B_DQS_N<6> =MEM_B_DQS_P<6>
26 26 26 26 26 26 26 26 26 26 26
MCP CHANNEL A DQS 0 -> DIMM A DQS 0

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DM<0> MEM_A_DQS_N<0> MEM_A_DQS_P<0> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DM<1> MEM_A_DQS_N<1> MEM_A_DQS_P<1> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DM<2> MEM_A_DQS_N<2> MEM_A_DQS_P<2> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DM<3> MEM_A_DQS_N<3> MEM_A_DQS_P<3> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DM<4> MEM_A_DQS_N<4> MEM_A_DQS_P<4> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DM<5> MEM_A_DQS_N<5> MEM_A_DQS_P<5> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DM<6> MEM_A_DQS_N<6> MEM_A_DQS_P<6> =MEM_A_DQ<7> =MEM_A_DQ<2> =MEM_A_DQ<3> =MEM_A_DQ<5> =MEM_A_DQ<1> =MEM_A_DQ<0> =MEM_A_DQ<6> =MEM_A_DQ<4> =MEM_A_DM<0> =MEM_A_DQS_N<0> =MEM_A_DQS_P<0> =MEM_A_DQ<8> =MEM_A_DQ<9> =MEM_A_DQ<14> =MEM_A_DQ<10> =MEM_A_DQ<13> =MEM_A_DQ<12> =MEM_A_DQ<15> =MEM_A_DQ<11> =MEM_A_DM<1> =MEM_A_DQS_N<1> =MEM_A_DQS_P<1> =MEM_A_DQ<17> =MEM_A_DQ<20> =MEM_A_DQ<18> =MEM_A_DQ<19> =MEM_A_DQ<21> =MEM_A_DQ<16> =MEM_A_DQ<23> =MEM_A_DQ<22> =MEM_A_DM<2> =MEM_A_DQS_N<2> =MEM_A_DQS_P<2> =MEM_A_DQ<29> =MEM_A_DQ<26> =MEM_A_DQ<31> =MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<25> =MEM_A_DQ<24> =MEM_A_DQ<30> =MEM_A_DM<3> =MEM_A_DQS_N<3> =MEM_A_DQS_P<3>
73 14
MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DM<0> MEM_B_DQS_N<0> MEM_B_DQS_P<0> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DM<1> MEM_B_DQS_N<1> MEM_B_DQS_P<1> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DM<2> MEM_B_DQS_N<2> MEM_B_DQS_P<2> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DM<3> MEM_B_DQS_N<3> MEM_B_DQS_P<3> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DM<4> MEM_B_DQS_N<4> MEM_B_DQS_P<4> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DM<5> MEM_B_DQS_N<5> MEM_B_DQS_P<5> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DM<6> MEM_B_DQS_N<6> MEM_B_DQS_P<6>

73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14

25 25 25 25 25 25 25 25 25 25 25 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
26 26 26 26 26 26 26 26 26 26 26

73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14

25 25 25 25 25 25 25 25 25 25 25 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
26 26 26 26 26 26 26 26 26 26 26

73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14

25 25 25 25 25 25 25 25 25 25 25 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
26 26 26 26 26 26 26 26 26 26 26

73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14

73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
=MEM_A_DQ<38> 25 =MEM_A_DQ<39> 25 =MEM_A_DQ<35> 25 =MEM_A_DQ<32> 25 =MEM_A_DQ<36> 25 =MEM_A_DQ<34> 25 =MEM_A_DQ<33> 25 =MEM_A_DQ<37> 25 =MEM_A_DM<4> 25 =MEM_A_DQS_N<4> 25 =MEM_A_DQS_P<4> 25 =MEM_A_DQ<44> =MEM_A_DQ<45> =MEM_A_DQ<47> =MEM_A_DQ<43> =MEM_A_DQ<42> =MEM_A_DQ<40> =MEM_A_DQ<41> =MEM_A_DQ<46> =MEM_A_DM<5> =MEM_A_DQS_N<5> =MEM_A_DQS_P<5> =MEM_A_DQ<51> =MEM_A_DQ<53> =MEM_A_DQ<50> =MEM_A_DQ<54> =MEM_A_DQ<48> =MEM_A_DQ<49> =MEM_A_DQ<55> =MEM_A_DQ<52> =MEM_A_DM<6> =MEM_A_DQS_N<6> =MEM_A_DQS_P<6>
25 25 25 25 25 25 25 25 25 25 25
26 26 26 26 26 26 26 26 26 26 26

73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
26 26 26 26 26 26 26 26 26 26 26

73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14

25 25 25 25 25 25 25 25 25 25 25 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
26 26 26 26 26 26 26 26 26 26 26

25 25 25 25 25 25 25 25 25 25 25 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14 73 14
MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63> MEM_A_DM<7> MEM_A_DQS_N<7> MEM_A_DQS_P<7>
=MEM_A_DQ<56> =MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<59> =MEM_A_DQ<57> =MEM_A_DQ<60> =MEM_A_DQ<63> =MEM_A_DQ<58> =MEM_A_DM<7> =MEM_A_DQS_N<7> =MEM_A_DQS_P<7>
MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63> MEM_B_DM<7> MEM_B_DQS_N<7> MEM_B_DQS_P<7>
=MEM_B_DQ<62> =MEM_B_DQ<63> =MEM_B_DQ<56> =MEM_B_DQ<60> =MEM_B_DQ<59> =MEM_B_DQ<58> =MEM_B_DQ<57> =MEM_B_DQ<61> =MEM_B_DM<7> =MEM_B_DQS_N<7> =MEM_B_DQS_P<7>
26 26 26 26 26 26 26 26 26 26 26 R
SYNC_MASTER=K18_MLB
PAGE TITLE
DDR3 BYTE/BIT SWAPS-K6

DRAWING NUMBER SIZE
Apple Inc.
051-8563
REVISION
A.13.0
BRANCH PAGE
32 OF 109
SHEET
27 OF 80
8
7
=PP3V3_S3_VREFMRGN OMIT
NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.
R3300
1
VREFMRGN:YES PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
60 7
SHORT 2
NONE NONE NONE 402
=PPVTT_S3_DDR_BUF 10mA max load
R3321
1
200
PLACE_NEAR=J2900.1:2.54mm
VREFMRGN:YES
VREFMRGN:YES
1
C3300 1
2.2UF
20% 6.3V 2 CERM 402-LF
C3301
0.1UF CRITICAL VREFMRGN:YES
8 VDD
VREFMRGN:YES
1% 1/16W MF-LF 402 A2 B1

V+
D
42
20% 2 10V CERM 402
C3320 1
0.1UF
20% 10V CERM 2 402
MAX4253
UCSP A1 A4
U3320
VREFMRGN_DQ_SODIMMA_BUF VREFMRGN:YES
VREFMRGN:YES
PPVREF_S3_MEM_VREFDQ_A
25
U3300
VOUTB 2 VOUTC 4 VOUTD 5
R3322
1
133
2 PLACE_NEAR=R3321.2:1mm
IN BI
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
6 SCL 7 SDA 9 A0
MSOP VOUTA 1
VREFMRGN_SODIMMA_DQ VREFMRGN_SODIMMB_DQ VREFMRGN_SODIMMS_CA VREFMRGN_MEMVREG_FBVREF NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable both at the same time! VREFMRGN:YES
1
A3
V-
42
Addr=0x98(WR)/0x99(RD)
10 A1
DAC5574
B4
1% 1/16W MF-LF 402
VREFMRGN:YES
R3323
1
GND 3
200
R3320
100K
C2 B1
V+
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402
MAX4253
UCSP C1 C4
U3320
VREFMRGN_DQ_SODIMMB_BUF VREFMRGN:YES
VREFMRGN:YES
PPVREF_S3_MEM_VREFDQ_B
26
OMIT
R3324
1
133
R3310
SHORT 1 2
NONE NONE NONE 402
PP3V3_S3_VREFMRGN_CTRL
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 16
C3
V-
B4
1% 1/16W MF-LF 402
VREFMRGN:YES
C3310 1
0.1UF
20% 10V CERM 2 402 3 A0 4 A1 5 A2
CRITICAL VREFMRGN:YES VREFMRGN:YES

1
VREFMRGN:YES
VCC
U3310
PCA9557
QFN (OD) P0 6 P1 7 P2 9 P3 10 P4 11 P5 12 P6 13 P7 14
R3325
100K VREFMRGN:YES
R3331
1
200
NC
Addr=0x30(WR)/0x31(RD)
42 42
IN BI
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
1 SCL 2 SDA
THRM
VREFMRGN_DQ_SODIMMA_EN VREFMRGN_DQ_SODIMMB_EN VREFMRGN_CA_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN VREFMRGN_MEMVREG_EN (RSVD for FBVREF) NC VREFMRGN_CPUGTLREF_EN
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402 A2 B1

V+
C3330 1
0.1UF
20% 10V CERM 2 402
MAX4253
UCSP A1 A4
U3330
VREFMRGN_CA_SODIMMA_BUF VREFMRGN:YES
VREFMRGN:YES
PPVREF_S3_MEM_VREFCA_A
25
R3332
1
133
A3
V-
B4
1% 1/16W MF-LF 402
RESET* 15 GND
8
VREFMRGN:YES
PAD 17
R3333
1
200
VREFMRGN:YES
1
R3330
100K
C2 B1
V+
1% 1/16W MF-LF 402
24
IN
PCA9557D_RESET_L
RST* on platform reset so that system watchdog will disable margining. NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.
5% 1/16W MF-LF 2 402
MAX4253
UCSP C1 C4
U3330
VREFMRGN_CA_SODIMMB_BUF VREFMRGN:YES
VREFMRGN:YES
PPVREF_S3_MEM_VREFCA_B
26
R3334
1
133
C3
V-
B4
1% 1/16W MF-LF 402
Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER
116S0004 116S0004
VREFMRGN:YES
1
R3335
100K VREFMRGN:YES
QTY
2 2
DESCRIPTION
RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF
REFERENCE DES
R3321,R3323 R3331,R3333
CRITICAL
CRITICAL CRITICAL
BOM OPTION
VREFMRGN:NO VREFMRGN:NO
5% 1/16W MF-LF 2 402
C3340 1
0.1UF
20% 10V CERM 2 402 C2
B1
V+
MAX4253
UCSP C1 C4
U3340
VREFMRGN_MEMVREG_BUF VREFMRGN:YES
VREFMRGN:YES
R3342
1
22.6K 2
1% 1/16W MF-LF 402
DDRREG_FB
PLACE_NEAR=R7320.2:1mm
OUT
60
C3
V-
B4
Page Notes
Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PPVTT_S3_DDR_BUF Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA BOM options provided by this page: VREFMRGN:YES - Stuffs VREF Margining Circuitry. VREFMRGN:NO - Bypasses VREF Margining Circuitry.
VREFMRGN:YES
1
R3340
100K
A2 B1
V+
5% 1/16W MF-LF 2 402
MAX4253
UCSP A1 A4
U3340
VREFMRGN_CPUGTLREF_BUF VREFMRGN:YES
VREFMRGN:YES
R3344
1
267
CPU_GTLREF
PLACE_NEAR=R1005.2:1mm
OUT
9 72
A3
V-
B4
1% 1/16W MF-LF 402
VREFMRGN:YES
1
R3345
100K
5% 1/16W MF-LF 2 402
A
DAC Channel: PCA9557D Pin: Nominal value Margined target: DAC range: VRef current: DAC step size:
MEM A VREF DQ A 1
MEM B VREF DQ B 2
MEM A VREF CA
MEM B VREF CA C 4
MEM VREG D 5 1.5V (DAC: 0x3A) 1.998V - 1.002V (+/- 498mV) 0.000V - 1.501V (0x00 - 0x74) +33uA - -33uA (- = sourced) 8.59mV / step @ output
CPU GTLREF (FSB) D 7 0.7V (DAC: 0x8B) 0.200V - 1.050V (+/- 500mV) 0.000V - 1.191V (0x00 - 0x5C) +750uA - -528uA (- = sourced) 9.24mV / step @ output
SYNC_MASTER=T27_MLB
PAGE TITLE
C 3 0.75V (DAC: 0x3A) 0.300V - 1.200V (+/- 450mV) 0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced) 7.69mV / step @ output
FSB/DDR3 Vref Margining

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

33 OF 109
SHEET
28 OF 80
3
5V S3 WLAN FET
MOSFET CHANNEL RDS(ON) LOADING TPCP8102 P-TYPE 26 mOhm @4.5V 0.8 A (EDP)
D
C3431
1 1
10%
CRITICAL
Q3450
1000 mA peak 750 mA nominal max
IN IN
15 74 15 74 6
7 8
0.1uF
16V X5R 402
4 G
20347-325E-12
F-RT-SM
31
10%
16V X5R 402
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V 1
5 6
J3401
0.1uF
29
PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N
PP5V_WLAN
PP5V_WLAN_F
2 3
CRITICAL 518S0610
PLACEMENT_NOTE=Place close to J3401.
FERR-120-OHM-1.5A
0402-LF
L3404
TPCP8102
23V1K-SM
=PP5V_S3_WLAN
1
C3430
C3422
0.1uF
20% 10V CERM 402
C3421
0.1uF
20% 10V CERM 402
C3420
10UF
20% 10V X5R 805
C3451
0.033UF
10% 16V X5R 402
R3451
10K
C3450
0.1UF
1 10% 16V X5R 402 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
74 6 74 6
PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_AP_R2D_P PCIE_AP_R2D_N
OUT OUT
6 15 74 6 15 74
CRITICAL
90-OHM-100MA DLP11S
SYM_VER-1
AIRPORT
R3450
33K
1 5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
P5VWLAN_SS
PM_WLAN_EN_L
IN
65
L3401
4
79 6 79 6
PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N
PLACEMENT_NOTE=Place close to Q3450.
IN
15 74
PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N
PLACEMENT_NOTE=Place close to Q3450.
IN
15 74
(AP_CLKREQ_Q_L)
PCIE_WAKE_L
OUT
6 15 24
(AP_RESET_CONN_L)
15 16 17 18 19 20 21 22 23 24 25
NC NC
6
PP5V_S3_BTCAMERA_F I2C_ALS_SDA I2C_ALS_SCL USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_CONN_P USB_BT_CONN_N
275 mA peak 206 mA nominal max

BI IN
42 42
L3405
2 0402-LF
1
C
1
=PP5V_S3_BTCAMERA
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
FERR-120-OHM-1.5A
79 6 79 6
CRITICAL
79 6 79 6
L3402 90-OHM
DLP0NS
SYM_VER-1
ALS CAMERA
USB_CAMERA_P USB_CAMERA_N
OUT OUT
C3452
0.1uF
20% 10V CERM 402
4 26 27 1 28 29 30
17 75
17 75
CRITICAL
32
L3403 90-OHM
DLP0NS
SYM_VER-1
BLUETOOTH
3
USB_BT_P USB_BT_N
BI
17 75
2
BI
17 75
B
PP5V_WLAN_F
29
B
Supervisor & CLKREQ# Isolation
=PP3V3_S3_WLAN
7
R34401
100K
5% 1/16W MF-LF 402 2
R3453
392K
CRITICAL
C3440
0.1uF
VDD
1% 1/16W MF-LF 2 402
U3440
SLG4AP016V
TDFN 2 SENSE + 0.7V DLY 4 RESET*
20% 10V 2 CERM 402
WF: Need pull-up?
P3V3WLAN_VMON
AP_RESET_CONN_L
DLY = 60 ms +/- 20%

6
MR* 3 EN 6 OUT 8
(OD)
AP_RESET_L AP_PWR_EN AP_CLKREQ_L
IN
24
IN OUT
18 65 15
AP_CLKREQ_Q_L
7 IN THRM PAD 9
1
GND 5
R3454
97.6K
1% 1/16W MF-LF 2 402
SYNC_MASTER=T27_MLB
PAGE TITLE
RIGHT CLUTCH CONNECTOR

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

34 OF 109
SHEET
29 OF 80
Caesar IV Support
76 31
BI
SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4..7> SDCONN_CLK SDCONN_CMD SDCONN_WP SDCONN_CD
R3550 R3551 R3552 R3553 R3554 R3556
BCM57765 0 0 0 0
1 2
SD_D<0>
5% 5% 5% 5% 1/16W MF-LF 402
30 76
BCM57765
1 2
D
7
GL137 =PP3V3_S3_CARDREADER
76 31
BI
SD_D<1>
1/16W MF-LF 402
30 76
R3511
1
5% 1/16W MF-LF 402
PP3V3_S3_CARDREADER_DVDD MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM GL137

VOLTAGE=3.3V
2
BYPASS=U3500.15:16:5 mm BYPASS=U3500.26:27:5 mm BYPASS=U3500.35:34:5 mm
BCM57765
1 2
76 31
BI
SD_D<2>
1/16W MF-LF 402
30 76
BCM57765
1 2
GL137
1
GL137
1
GL137
1
76 31
C3500 1
10UF
6.3V 2 X5R
603 20%
C3501
0.1UF
C3502
0.1UF
C3503
0.1UF
76 31 76 31
BI
SD_D<3>
1/16W MF-LF 402
30 76
GL137
L3500
0.22UH
0805-1 1
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
BI
SD_D<4..7> BCM57765 0
1 2
30 76
MAKE_BASE=TRUE
IN
SD_CLK
5% 1/16W MF-LF 402
30 76
76 31
OUT
0 BCM57765 1 2
5% 1/16W MF-LF402
SD_CMD
MAKE_BASE=TRUE
30 76
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
PP3V3_S3_CARDREADER_AVDD GL137
BYPASS=U3500.6:5:5 mm BYPASS=U3500.11:12:5 mm
31
OUT
SD_WP
MAKE_BASE=TRUE
30
GL137
1
GL137
1
31
OUT
SD_CD_L
MAKE_BASE=TRUE
30
C3514 1
10UF
20% 603
C3504
0.1UF
C3508
0.1UF
7
BCM57765 =PP3V3_S0_SDCONN
6.3V 2 X5R
20% 2 10V CERM 402
20% 2 10V CERM 402
R3555
1
Keep this net short!

BYPASS=U3500.4:5:5 mm
5% 1/10W MF-LF 603
PP3V3_SW_SD_PWR
PP1V8_S3_CARDREADER
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=1.8V 6 AVDD 11 15 26 35 4
GL137
C3506 1
0.1UF
20% 402
NC
25 36 VDD18O VDD5V PMOSO DVDD
C3507 1
GL137 2.2UF
C3505
0.1UF
R3505
39K
CRITICAL
J3500
SD-CARD-K19-K24
F-RT-TH 3 6
10V CERM 2
R35121
10K
5% 1/16W MF-LF 402 2
20% 6.3V CERM1 2 603
20% 10V 2 CERM 402
5% 1/16W MF-LF 2 402
MAX CURRENT = 800 MA
GL137
NO STUFF
1
R35071
10K
5% 1/16W MF-LF 402 2
R3508
10K
75 17 75 17
76 30 76 30
5% 1/16W MF-LF 2 402
BI BI
USB_SDCARD_N USB_SDCARD_P GL137_GPIO1 GL137_GPIO2
7 DM 8 DP 48 GPIO1 47 GPIO2 46 GPIO3 19
U3500
GL137A
LQFP
NO STUFF
GL137
1
CRITICAL GL137
R35091
10K
5% 1/16W MF-LF 402 2
NC
R3510
10K
5% 1/16W MF-LF 2 402
SK NC 20 CS NC 21 DO NC 22 DI (IPD) NC
D0 D1 D2 D3 D4 D5 D6 D7
40 43 37 29 28 30 32 38
76 30 76 30 76 30 76 30 76 30 76 30 76 30 76 30
SD_CLK SD_CMD SD_D<0> SD_D<1> SD_D<2> SD_D<3> SD_D<4> SD_D<5> SD_D<6> SD_D<7> SD_WP
5 2 7 8 9 1 10 11 12 13 14 15 16 4
VSS VSS CLK CMD DAT0 DAT1 DAT2 CD/DAT3 DAT4 DAT5 DAT6 DAT7 CARD_DETECT_SW CARD_DETECT_GND WRITE_PROTECT_SW VDD SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
CLK 39 76
SD_CLK_R
30
NO STUFF
GL137_CLK12M_X1 GL137_CLK12M_X2 GL137_RREF GL137_TESTMOD GL137 GL137

1
13 X1 14 X2 10 RREF 17 TESTMOD (IPD)
R3503
1
(IPD) SD_WP (IPD) SD_CMD (IPU) PDMOD (IPU) SD_CDZ (IPU) XD_CDZ XD_CE (IPD) XD_WEZ (IPD) XD_RBZ (IPD) XD_WPZ
3 41 2 23 1
GL137_PDMOD
30
SD_CD_L
17 18 19 20
1M
NO STUFF
GL137
5% 1/16W MF-LF 402
R35061
715
1% 1/16W MF-LF 402 2
R3502
0
CRITICAL GL137
GL137_RESET_L NO STUFF
18 EXTRSTZ* (IPU)
Y3500
12.000M-100PPM
1 2
5% 1/16W MF-LF 2 402
C3513 1
0.1UF
10V CERM 2
402 20%
NC 31 NC 42 NC 44 NC 45 NC NC NC
R3513
10K
R3504
1
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402
NO STUFF
1
C3515
10PF
516-0225
(IPU) MS_INS 24 (IPD) MS_BS 33

GND 12 16 27 34 5 9
5% 2 50V CERM 402-1
8X4.5X1.4-SM
GL137
GL137
C3511
33PF
1 5% 2
C3512
33PF
1 5% 2
PDMOD: POWER DOWN MODES NC = DISABLE (DEFAULT) 10K LOW = POWER SAVING MODE ENABLE 10K HIGH = REMOTE WAKE UP ENABLE
GL137
Q3500
SSM6N15FEAPE
SOT563
D 3
50V
CERM 402
50V
CERM 402
5
18
S 4
IN
SDCARD_RESET
SDCARD_PLT_RST GL137
Q3500
SSM6N15FEAPE
SOT563
D 6
2
24
S 1
IN
SDCARD_PLT_RST_L
SYNC_MASTER=T27_MLB
PAGE TITLE
SecureDigital Card Reader

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

35 OF 109
SHEET
ADDED SERIES RESISTOR TO SD_CMD, MAX CURRENT NUMBER CHANGED TO 800MA
30 OF 80
5
TP_BCM57765_SR_VDDP BCM57765_SR_VDD BCM57765_VDDO_PIN20
4
BCM57765_SR_LX BCM57765_SR_VFB
BCM57765 SR pins are internal 1.2V switching regulator. If unused: Okay to float all 4 pins. (Broadcom not so sure now) If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY BCM57765 =PP3V3_ENET_PHY 86mA (1000base-T, Caesar II)
64 31 24 7 64 64 31 31 64 31 64
CRITICAL FERR-600-OHM-0.5A
R3915
1
L3920
SM
31
CRITICAL
PP1V2_ENET_PHY_AVDDL
FERR-600-OHM-0.5A 1 2 31 PP3V3_ENET_PHY_XTALVDDH
SM
L3900
5% 1/16W MF-LF 402
BCM57765
R3900
1
C3921 1
31
=PP1V2_ENET_PHY 7 31 396mA (1000base-T, Caesar II)
BCM57765_XTALVDDH
D
CRITICAL
C3900 1
10% 16V X7R-CERM 2 402
0.1UF
5% 1/16W MF-LF 402
10% 16V X7R-CERM 2 402
0.1UF
C3920
4.7UF
10% 2 6.3V X5R-CERM 603
CRITICAL FERR-600-OHM-0.5A 1 2 PP1V2_ENET_PHY_PCIEPLL
L3925
SM
FERR-600-OHM-0.5A 1 2 PP3V3_ENET_PHY_BIASVDDH
SM MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 1
L3905
C3926 1 C3905
0.1UF
10% 2 16V X7R-CERM 402 10% 16V X7R-CERM 2 402
C3925
4.7UF
0.1UF
10% 2 6.3V X5R-CERM 603
CRITICAL FERR-600-OHM-0.5A 1 2 PP3V3_ENET_PHY_AVDDH

SM MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
CRITICAL FERR-600-OHM-0.5A 1 2 PP1V2_ENET_PHY_GPHYPLL
L3910
L3930
SM
R3910
4.7K
C3910
0.1UF
C3911
0.1UF
C3931
0.1UF
C3930
4.7UF
5% 1/16W MF-LF 402 2
10% 2 16V X7R-CERM 402
10% 2 16V X7R-CERM 402
10% 16V X7R-CERM 2 402
10% 2 6.3V X5R-CERM 603
BCM57765
BCM57765
1
R39401
4.7K
R3941
4.7K
C3915 1
10% 6.3V X5R-CERM 2 603
42 48
BIASVDDH 37
VDDC 17
7 20 56 62
VDDC 14
REGCTL12 15
VDDIO 16
WAKE* 13
39 45 51
29 32
GPHY_PLLVDDL 36
VDDC 35 VDDC 61
4.7UF
C3916
0.1UF
VDDIO XTALVDDH VDDIO VDDIO AVDDH AVDDL PCIE_PLLVDDL
C3936 1
10% 16V X7R-CERM 2 402
C
74 15
31 7
=PP3V3_S0_ENETPHY
1
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
10% 2 16V X7R-CERM 402
0.1UF
C3935
10UF
10% 2 6.3V X5R 805
BCM57765
C3950
0.1uF
OUT
R3942
1K
PCIE_ENET_D2R_N
1 10% 16V X5R 402
5% 1/16W MF-LF 2 402
CRITICAL OMIT
31
C3951
0.1uF
1 10% 16V X5R 402 2
BCM57765_VMAIN_PRSNT PCIE_ENET_D2R_C_N PCIE_ENET_D2R_C_P PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N ENET_RESET_L ENET_CLKREQ_L BCM57765_WAKE_L
58 SMB_DATA 27 PCIE_TXD_N 28 PCIE_TXD_P 33 PCIE_RXD_P 34 PCIE_RXD_N
(IPD)
U3900
BCM5764M
QFN-8X8 VERSION 2
74 15
OUT
PCIE_ENET_D2R_P
74 74
C3955
0.1uF
74 15
74 74
IN
PCIE_ENET_R2D_C_P
1 10% 16V X5R 402
C3956
0.1uF
1 2 10% 16V X5R 402
74 15 74 15
IN IN IN OUT
31 PCIE_REFCLK_P 30 PCIE_REFCLK_N
TRD0_P TRD0_N TRD1_P TRD1_N TRD2_P TRD2_N TRD3_P TRD3_N
40 41 44 43 46 47 50 49
ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3> PP3V3R1V8_SW_SD_VIO

NC
BI BI BI BI BI BI BI BI
32 76 32 76 32 76 32 76 32 76 32 76 32 76 32 76
CR_BUS_PWR is not for SD Card power, just decoupling for BCM57765 CR I/Os. BCM57765 BCM57765
1
BCM57765
1
C3970 1
10% 6.3V X5R-CERM 2 603
C3971
0.1UF
C3972
0.1UF
10% 402
4.7UF
10% 16V 2 X7R-CERM 402
2 16V X7R-CERM
74 15
IN
PCIE_ENET_R2D_C_N
76 24
11 PERST* 12 CLKREQ*
(IPD) (OD)
(IPD)
BCM57765
R3943
1
15
GPIO_0/SERIAL_DO 5 GPIO_1/SERIAL_DI 8 GPIO_2 9 NC 1 PCIE_VDDL 26 DC0 21 25 24 23 22 52 53 54 55 59 60 57 68
BCM57765_MEDIA_SENSE BCM57765_SD_DETECT
76 31
R3972 R3973 R3974
BCM57765 0 0 0
1 2
ENET_ENERGY_DET
5% 5% 1/16W MF-LF 402
OUT
17 31
31 24
OUT
=ENET_WAKE_L (See note) WAKE#
3 LINKLED* (OD) 4 LOW_PWR
BCM57765
1 1 2 2
5% 1/16W MF-LF 402
SDCONN_CD
1/16W MF-LF 402
IN IN OUT BI BI BI BI BI BI BI BI
30
18 8
IN
31
ENET_LOW_PWR BCM57765_SMB_CLK BCM57765_SMB_DATA BCM5764_SCLK BCM5764_MISO BCM5764_MOSI BCM5764_CS_L TP_BCM5764_SPD100LED_L TP_BCM5764_TRAFFICLED_L
(IPD)
BCM57765_CR_CMD
SDCONN_CMD
5% 1/16W MF-LF 402
PLACE_NEAR=L3999.1:1 mm
30 76
(IPU)
Must isolate from PCIe WAKE# if PHY is powered-down in S3/S5. Standard N-channel FET isolation suggested. If PHY is always powered then alias =ENET_WAKE_L to PCIE_WAKE_L.
6 VDDC 10 UART_MODE 66 64 65 63 SCLK SI SO CS*
SDCONN_CLK SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6> SDCONN_DATA<7>
30 76
(IPD-BCM5764M)
31 31 31 31
2 SPD100LED* 67 TRAFFICLED* 18 XTALI 19 XTALO 38 RDAC THRM_PAD 69
DC4 DC3 DC2 DC1 NC VMAIN_PRSNT VAUX_PRSNT VDDC SMB_CLK ENERGY_DET DC5 SPD1000LED*
30 76 30 76 30 76 30 76 30 76 30 76 30 76 30 76
76 76 31 76 31 76 31
BCM57765_CR_DATA<4> BCM57765_CR_DATA<5> BCM57765_CR_DATA<6> BCM57765_CR_DATA<7> BCM57765_CE_L_MS_INS_L BCM57765_CR_LED TP_BCM57765_XD_DET
R3975 R3976 R3977 R3978

31 31
0 0 0 0
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
402 402 402 402
24 24
IN OUT
BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO BCM5764_RDAC
BCM57765
All resistors above BOMOPTIONed BCM57765 SDCONN_WP IN 30 BCM57765 supports both active-levels for WP.
PHY Non-Volatile Memory

ROM contains MAC address, PCIe config info as well as code for Bonjour proxy. Required for proper PHY operation. (Required ROM size TBD) =PP3V3_ENET_PHY
R3965
1.24K
BCM5764M Support
All parts below BOMOPTIONed BCM5764M BCM5764M R3980 0 1 2
64 31
1% 1/16W MF-LF 2 402
BCM5764M pin-function BCM57765_CR_LED 31 60-ENERGY_DET 13-WAKE* 53-VMAIN_PRSNT 59-SMB_CLK 58-SMB_DATA 54-VAUX_PRSNT 16-VDDIO 20-XTALVDDH BCM57765_SR_VFB BCM57765_CR_DATA<5>
64 31 24 7
76 31
31 31 76 31 64 31
C3990
0.1UF
VCC
U3990
AT45DB011D
SOIC-8S1
10% 2 16V X7R-CERM 402
BCM57765_CE_L_MS_INS_L BCM57765_VMAIN_PRSNT BCM57765_CR_DATA<6> BCM57765_SR_LX BCM57765_VDDO_PIN20 BCM57765_CR_DATA<7> BCM57765_XTALVDDH BCM57765_SR_VDD BCM57765_SMB_CLK
31
31
BCM5764_SCLK BCM5764_CS_L
2 4 5 3
SCK
CS*
OMIT
SI 1
BCM5764_MOSI
31
31
SO 8 WP*
RESET*
BCM57765
1
BCM5764_MISO BCM5764M
1
55-VDDC 17-VDDC 14-VDDC 06-VDDC
76 31 31 64 31 31
R3981 R3982 R3983 R3984 R3985 R3986 R3987 R3988 R3989 R3998 R3999
5% 5%
1/16W MF-LF 402 1/16W MF-LF 402
0 1K 4.7K 4.7K 1K 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
2 2 5% 2 2 2 2 2 5% 2 2 2 2 5% 5% 5% 5% 1/16W MF-LF 402 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402 5% 5% 5% 5% 1/16W MF-LF 402 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402
ENET_ENERGY_DET =ENET_WAKE_L (See note) =PP3V3_S0_ENETPHY =PP3V3_ENET_PHY
17 31
24 31
7 31
7 24 31 64
PP3V3_ENET_PHY_XTALVDDH =PP1V2_ENET_PHY
SYNC_MASTER=T27_MLB
PAGE TITLE
31
7 31
31
GND
7
R3990
4.7K
R3997
4.7K 26-PCIE_VDDL NOTE: Pull-down on SO plus internal pull-ups on other 3 SPI pins configures BCM57765 for the Atmel AT45DB011D (1Mbit) ROM. If a different ROM is used then the straps must change. NOTE: BCM5764M requires SI pull-down instead of SO.
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
FERR-600-OHM-0.5A 2 BCM57765_CR_CMD PLACE_NEAR=U3900.26:2 mm 1 76 31 SM CRITICAL Keep net short, BCM5764M BCM5764M 1 C3998 with no stubs. C3999 1 0.1UF 4.7UF
10% 16V X7R-CERM 2 402 PLACE_NEAR=U3900.26:1 mm 10% 2 6.3V X5R-CERM 603 PLACE_NEAR=L3999.1:1 mm
L3999
Ethernet PHY (Caesar II/IV)

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

39 OF 109
SHEET
31 OF 80
Page Notes
Power aliases required by this page: (NONE) Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
ENETCONN_CTAP
PLACE_NEAR=T4000.3:2.54 mm PLACE_NEAR=T4001.4:2.54 mm PLACE_NEAR=T4000.4:2.54 mm PLACE_NEAR=T4001.3:2.54 mm
C4000
0.1UF
10% 16V X5R 402
C4002
0.1UF
10% 16V X5R 402
C4004
0.1UF
10% 16V X5R 402
C4006
0.1UF
10% 16V X5R 402
CRITICAL
T4000
76 31
BI
ENET_MDI_P<0> ENET_MDI_N<0>
SM
12 79
ENETCONN_P<0> ENETCONN_N<0> CRITICAL ENET_CTAP0
76 31
BI
11 79
10
J4000
RJ45-M97-3
F-RT-TH 9
TX
C
76 31
TLA-6T213HF
4 9
ENET_CTAP1
79
10
BI
ENET_MDI_N<1> ENET_MDI_P<1>
ENETCONN_N<1> ENETCONN_P<1>
1 2
76 31
BI
79
3 4 5
RX CRITICAL
6 7
12 79
T4001
76 31
BI
SM
ENETCONN_N<2> ENETCONN_P<2> ENET_CTAP2
76 31
BI
11 79
11 12
10
TX
TLA-6T213HF
4 9
514-0636
ENET_CTAP3
79
76 31
BI
ENETCONN_N<3> ENETCONN_P<3>
76 31
BI
79
RX
2 10
2 10
NC IO NC IO NC IO NC IO
NC IO NC IO NC IO NC IO
Transformers should be mirrored on opposite sides of the board

D4000.1: D4000.5: PLACE_NEAR=T4000.6:4 mm PLACE_NEAR=T4000.1:4 mm PLACE_NEAR=T4001.6:4 mm PLACE_NEAR=T4001.1:4 mm
R4000 1
75
5% 1/16W MF-LF 402
R4001 1
75
5% 1/16W MF-LF 402
R4002
75
5% 1/16W MF-LF 402
R4003
75
5% 1/16W MF-LF 402
CRITICAL
C4008
1000PF
1 2
B
GND
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
D4000
RCLAMP0524P
SLP2510P8
D4001
RCLAMP0524P
SLP2510P8
ENET_ESD CRITICAL
ENET_ESD CRITICAL
GND
D4001.1: D4001.5:
10% 2KV CERM 1206
SYNC_MASTER=T27_MLB
PAGE TITLE
Ethernet Connector
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

40 OF 109
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4
7 mA I/O
2
=PP3V3_FW_FWPHY 138 mA
7 33 34 35
C4120
1UF
10% 6.3V CERM 402
C4121
1UF
10% 6.3V CERM 402
C4122
1UF
10% 6.3V CERM 402
C4123
1UF
10% 6.3V CERM 402
C4124
1UF
10% 6.3V CERM 402
L4130
D
C4130
1UF
10% 6.3V CERM 402 2 1
120-OHM-0.3A-EMI 114 mA FireWire PHY PP3V3_FW_FWPHY_VDDA

1 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V 1 0402-LF 2
C4131
1UF
10% 6.3V CERM 402
C4132
1UF
10% 6.3V CERM 402
L4110
34 7
L4135
120-OHM-0.3A-EMI PP1V0_FW_FWPHY_AVDD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V 2
=PP1V0_FW_FWPHY 135 mA
120-OHM-0.3A-EMI
1 0402-LF
25 mA PCIe SerDes
17 mA PCIe SerDes
PP3V3_FW_FWPHY_VP25
1 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1 0402-LF
C4110
1UF
10% 6.3V CERM 402
C4111
1UF
10% 6.3V CERM 402
C4135
1UF
10% 6.3V CERM 402
C4136
1UF
10% 6.3V CERM 402
110 mA Digital Core
0 mA VReg PWR
C4100
1UF
10% 6.3V CERM 402
C4101
1UF
10% 6.3V CERM 402
C4102
1UF
10% 6.3V CERM 402
C4103
1UF
10% 6.3V CERM 402
C4104
1UF
10% 6.3V CERM 402
C4105
1UF
10% 6.3V CERM 402
C4106
1UF
10% 6.3V CERM 402
C4141
0.1UF
20% 10V CERM 402
C4140
1UF
10% 6.3V CERM 402
C
B12 C13 E10 H12 M12 N11 C12 G12 L11 A12 L10 K12 D8 L6 A1 B1 E2 H2 K2 L1 N3 C1 F1 J1 L3 M2 D5 D6 L5 L9
PLACEMENT_NOTE=Place C4170 close to U1400 PLACEMENT_NOTE=Place C4171 close to U1400
C
IN
15 74
C4170 C4171
PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N PCIE_TXD0P REFCLKN REFCLKP
N8 N7 N5 N6
74 74 74 74
2 10% 2 10%
PCIE_FW_R2D_C_N
16V X5R 402
0.1UF
VDD10
NC NC NC
35 35 35
B13 A13 A11 F12 E12 E13 B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4 B7 C3 A2 B11 B10
ATBUSB ATBUSH ATBUSN DS0 (IPD) NT-2 DS1 (IPD) NT-3 DS2 (IPD) NT-4 TPA0N TPA0P TPA1N TPA1P TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P TPBIAS0 TPBIAS1 TPBIAS2 R0 TPCPS NAND_TREE REXT XO XI NT-9 NT-OUT NOTE: NT-xx notes show NAND tree order.
VDD33 OMIT CRITICAL
VDDH
VP
VP25
VREG_PWR PCIE_FW_R2D_N PCIE_FW_R2D_P PCIE_FW_D2R_C_N PCIE_FW_D2R_C_P PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P

15 74 15 74
PCIE_FW_R2D_C_P
16V X5R 402
IN
15 74
0.1UF
U4100
FW643E
BGA
C4175 C4176
2 10% 2 10%
PCIE_FW_D2R_N
16V X5R 402
OUT
15 74
0.1UF
1
IN IN IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
=FW_PHY_DS0 =FW_PHY_DS1 =FW_PHY_DS2 FW_P0_TPA_N FW_P0_TPA_P FW_P1_TPA_N FW_P1_TPA_P FW_P2_TPA_N FW_P2_TPA_P FW_P0_TPB_N FW_P0_TPB_P FW_P1_TPB_N FW_P1_TPB_P FW_P2_TPB_N FW_P2_TPB_P FW_P0_TPBIAS FW_P1_TPBIAS FW_P2_TPBIAS FW643_R0 FW643_TPCPS TP_FW643_NAND_TREE FW643_REXT FW_CLK24P576M_XO_R FW_CLK24P576M_XI
PCIE_FW_D2R_P
16V X5R 402
OUT
15 74
N9 N10
PCI EXPRESS PHY
IN IN
0.1UF
PLACEMENT_NOTE=Place C4175 close to U4100 PLACEMENT_NOTE=Place C4176 close to U4100
77 35 77 35 77 35 77 35 35 35 77 35 77 35 77 35 77 35
TEST CONTROLLER 1394 PHY
NT-21 (IPU) TCK NT-20 (IPU) TDI (IPU) TDO NT-18 (IPU) TMS NT-19 (IPU) TRST*
M4 N2 M1 M3 N1
TP_FW643_TCK TP_FW643_TDI TP_FW643_TDO TP_FW643_TMS FW643_LDO FW643_TRST_L
=PP3V3_FW_FWPHY
7 33 34 35
R4165
10K
R4166
10K
(OD) NT-10 (IPD)

FIXME!!! - TYPO IN SYMBOL REGCTL
35
=PPVP_FW_PHY_CPS
35 35
B
C4150
22PF
1 5% 50V CERM 402 2
R4160 1
200K
1% 1/16W MF-LF 402
35 35 34 35
POWER MANAGEMENT NT-12 (IPD) NT-13
WAKE* REGCLT VAUX_DETECT VAUX_DISABLE (OD) CLKREQN
C2 D13 E1 D2 L2
=FW_PME_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE =FW_CLKREQ_L
OUT
34
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
OUT
34
R4164
10K
5% 1/16W MF-LF 2 402
NOTE: FW_PME_L and FW_CLKREQ_L are isolated for systems that use 1394B physical plug detect. WITH PLUG DETECT: - Gate CLKREQ# based on PHY power - TP (or NC) PME# WITHOUT PLUG DETECT: - Alias both signals to drop = prefix
K1 L8 F13 G13 M13 N13 J2 L13 D12 D1 A10 H13 K13 J12
SCIF
R4150
FW_CLK24P576M_XO CRITICAL 412
1 1% 1/16W MF-LF 402 2
NT-16 (IPD) SCIFCLK NT-14 (IPD) SCIFDAIN NT-17 SCIFDOUT NT-15 (IPD) SCIFMC
G2 G1 H1 F2
TP_FW643_SCIFCLK TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT TP_FW643_SCIFMC
C4151
22PF
1 5% 50V CERM 402 2
NC NC
Y4150
24.576MHZ
SM-3.2X2.5MM
1 2 4 3
R4161 1
2.94K
1% 1/16W MF-LF 402 2
R4170
191
1% 1/16W MF-LF 402
TP_FW643_SE TP_FW643_SM TP_FW643_MODE_A TP_FW643_CE TP_FW643_FW620_L TP_FW643_JASI_EN TP_FW643_AVREG TP_FW643_VBUF FW643_PU_RST_L TP_FW643_OCR10_CTL
SE (IPD) SM (IPD) MODE_A (IPD) NT-1 CE (IPD) FW620* (IPU) JASI_EN (IPD) NT-11 AVREG VBUF FW_RESET* (IPU) NT-8 OCR_CTL_V10 OCR_CTL_V12 (Reserved)
SERIAL EEPROM CONTROLLER
NT-7 SCL NT-6 SDA
N12 M11
FW643_SCL TP_FW643_SDA
MISCELLANEOUS CHIP RESET NT-5 PERST*

N4
FW_RESET_L
1
IN
34
R4163
10K
5% 1/16W MF-LF 402
R4162 1
470K
5% 1/16W MF-LF 402
C4162
0.33UF
10% 6.3V CERM-X5R 402
NC
J13
VSS
D10 F10 G10 H10 J10 K10 B2 D4 D7 D9 E4 E5 E9 F4 F6 F7 F8 G4 G6 G7 G8 H4 H6 H7 H8 J4 J5 J9 K4 K5 K7 K8 K9 L7 K6
VREG_VSS
L12
2 2
SYNC_MASTER=T27_MLB
PAGE TITLE
FireWire LLC/PHY (FW643E)

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

41 OF 109
SHEET
33 OF 80
7
by this page: (FW VP FET Input) (FW VP FET Output) (3.3V FET Input) (3.3V FET Output) (PHY 3.3V Power)
4
FireWire Port Power Switch
CRITICAL
3
Q4260
SM
Page Notes
Power aliases required - =PPBUS_S5_FWPWRSW - =PPBUS_FW_FET - =PP3V3_FW_P3V3FWFET - =PP3V3_FW_FET - =PP3V3_FW_FWPHY - =PP3V3_S0_FWLATEVG - =PP3V3_S0_FWPWRCTL - =PP1V05_S0_FWPWRCTL - =PP1V05_FW_P1V0FWFET - =PP1V0_FW_FET_R - =PP1V0_FW_FWPHY
7
CRITICAL
FDC638P_G =PPBUS_S5_FWPWRSW
6
F4260
1.1A-24V PPBUS_FW_FWPWRSW_F
1 2
CRITICAL
D4260 SM
PPBUS_FW_FWPWRSW_D
1 2
=PPBUS_FW_FET
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

4 1
5 2
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm MINISMDC110H24 VOLTAGE=12.6V
CRS08-1.5A-30V
(5KPD Bias Rail) (1.0V FET Input) (1.0V FET Output) (PHY 1.0V)
R4262
10K
R4260
300K
C4260 1
0.1UF
10% 25V 2 X5R 402
3
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402

(SYM-VER2)
Signal aliases required by this page: - =FW_CLKREQ_L - =FW_PME_L BOM options provided by this page: (NONE)
FWPORT_FASTOFF_L_DIV
S G
SOT-363
BSS8402DW
FWPORT_PWREN_L_DIV
R4263
10
Q4262
D
3
5% 1/16W MF-LF 402 2
FWPORT_FASTOFF_L
1
6
R4261
470K
7
D
35 7
=PP3V3_S0_FWLATEVG
2
Q4262
G S
1
5% 1/16W MF-LF 2 402
Supervisor & CLKREQ# Isolation

=PP3V3_S0_FWPWRCTL
BSS8402DW
SOT-363
(SYM-VER1)
FWPORT_PWREN_L
D 3
Q4261
SSM3K15FV
SOD-VESM-HF 1
35
NO STUFF
C4290 1
0.1UF
24
CRITICAL
R4290
100K =PP1V0_FW_FWPHY
C4261 1
0.1UF
G S 2
10% 25V 2 X5R 402
IN
=FW_RESET_L
2
10% 25V 2 X5R 402
VDD
U4290
SLG4AP016V
TDFN 2 + SENSE - 0.7V DLY 3 MR* 6 EN 8 OUT
(OD)
5% 1/16W MF-LF 2 402
7 33
IN
FWPORT_PWR_EN
R4283
10K
5% 1/16W MF-LF 1 402
C
34 15 15
FW_RESET_R_L
IN OUT
RESET* 4
FW_RESET_L OUT DLY = 60 ms +/- 20% =FW_CLKREQ_L FW_CLKREQ_PHY_L

MAKE_BASE=TRUE
IN
33
FW_PWR_EN FW_CLKREQ_L
33
IN 7 GND 5 THRM PAD 9
Pull-up provided by another page.
=PP1V05_S0_FWPWRCTL
FireWire Port 5K Pull-Down Detect

All FireWire devices require 5K pull-down on TPB pair. Host can detect as load on TPBIAS signal. Current source only active when FW_PWR_EN is low. FW_PWR_EN_L
6 D 1
R42751
5% 1/16W MF-LF 402 2
1K
3.3V FW Switch
R4270
330K
CRITICAL
R42711
5% 1/16W MF-LF 402 2
=PP3V3_FW_P3V3FWFET
A2 B2
TPS22924
CSP VIN VOUT A1 B1
U4201
Q4275
DMB53D0UV
SOT-563
34 15
IN
FW_PWR_EN
2 G
5% 1/16W MF-LF 2 402
56K
FW_5KPD_DET_L
MAKE_BASE=TRUE 3
=PP3V3_FW_FET 7 EDP = 0.14A (85C)
CRITICAL
CRITICAL
FW_5KPD_DET_RC CRITICAL
S
3 5 6
5
1
Q4275
DMB53D0UV
SOT-563
C4201 1
1UF
10% 6.3V CERM 2 402
C2 ON GND C1
U4201 & U4202

Part Type R(on) TPS22924C Load Switch 18 mOhm Typ 50 mOhm Max
CRITICAL
C4270
0.1UF
Q4270
BC847CDXV6TXG SOT563
4
FWDET_MIRROR
Q4270
BC847CDXV6TXG SOT563
1
10% 16V X5R 2 402
FW_P1_TPBIAS_R
FWDET_EMIT
1.0V FW Switch
7
Max Output: 2A
R42721
5% 1/16W MF-LF 402 2 PLACE_NEAR=C4360.1:2 mm
35 33
1K
R42731
5% 1/16W MF-LF 402 2
12K
=PP1V05_FW_P1V0FWFET
A2 B2
TPS22924
CSP VIN VOUT A1 B1
U4202
PP1V05_FW_FET
CRITICAL
IN
FW_P1_TPBIAS
C4202 1
1UF
10% 6.3V 2 CERM 402
C2 ON GND C1
R4202
0.549
FireWire PHY WAKE# Support

When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
35 33 7
1% 1/16W MF 2 402
LSI FireWire PHY requires 1.0V. To avoid an extra power supply, 1.05V is used with a series R to reduce voltage.
7
=PP1V0_FW_FET_R Dual-purpose output:
=PP3V3_FW_FWPHY
R42771
5% 1/16W MF-LF 402 2
R4276
100K
1) 5K Pull-down Detect when FW_PWR_EN is low. 2) FW643 WAKE# (PME#) when PHY is powered. FW_PME_L OUT 15 Pull-up provided on another page. 3 CRITICAL
5 4
10K
5% 1/16W MF-LF 2 402
A
33
FW_WAKE NO STUFF
6 D
Q4276
DMB53D0UV
SOT-563
C4276
0.1UF
SYNC_MASTER=T27_MLB
PAGE TITLE
10% 16V X5R 2 402
FireWire Port & PHY Power

DRAWING NUMBER SIZE
IN
=FW_PME_L
FW643_WAKE_L
MAKE_BASE=TRUE
2 G
CRITICAL
Apple Inc.
R
051-8563
REVISION
Q4276
S 1
DMB53D0UV
SOT-563
A.13.0
BRANCH PAGE

42 OF 109
SHEET
TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.
34 OF 80
8 Page Notes
Power aliases required by this page: - =PPVP_FW_PORT1 - =PPVP_FW_PHY_CPS_FET (From Port) - =PPVP_FW_PHY_CPS (To PHY) - =PP3V3_FW_FWPHY - =PP3V3_S0_FWLATEVG Signal aliases required by this page: - =FW_PHY_DS0 - =FW_PHY_DS1 - =FW_PHY_DS2 NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals. BOM options provided by this page: (NONE) 1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)
6
FW643 TPCPS Leakage Protection
FW643 has internal leakage path from TPCPS pin to VDD33. FET blocks current to TPCPS until VDD33 is powered.
4
Unused FireWire Ports
Disabled per LSI instructions (All unused port signals TP/NC)
3
Configures PHY for: - Port "1" Bilingual (1394B)
35 34 33 7
2
FireWire PHY Config Straps
=PP3V3_FW_FWPHY
BSS8402DW
Q4300
(SYM-VER2)
SOT-363
33
IN BI BI BI BI
FW_P0_TPBIAS FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P2_TPBIAS FW_P2_TPA_P FW_P2_TPA_N FW_P2_TPB_P FW_P2_TPB_N
NC_FW0_TPBIAS
MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE
R4382 1
10K
1% 1/16W MF-LF 402
R4380
10K
1% 1/16W MF-LF 402
77 33
NC_FW0_TPAP
MAKE_BASE=TRUE
=PPVP_FW_PHY_CPS_FET
PPVP_FW_CPS
77 33
NC_FW0_TPAN
MAKE_BASE=TRUE
From Port
77 33
NC_FW0_TPBP
MAKE_BASE=TRUE
FWPHY_DS0
MAKE_BASE=TRUE
=FW_PHY_DS0 =FW_PHY_DS1 =FW_PHY_DS2
D
OUT OUT OUT
33 33 33
R4311
470K
5% 1/16W MF-LF 402
1 5
=PPVP_FW_PHY_CPS To FW643
77 33 33
NC_FW0_TPBN
MAKE_BASE=TRUE
FWPHY_DS1
MAKE_BASE=TRUE
33
IN BI BI BI BI
NC_FW2_TPBIAS
MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE
FWPHY_DS2
MAKE_BASE=TRUE 1
33
NC_FW2_TPAP
MAKE_BASE=TRUE
R4381
10K
1% 1/16W MF-LF 402
CPS_EN_L_DIV
33
NC_FW2_TPAN
MAKE_BASE=TRUE
R4312
330K
5% 1/16W MF-LF 402
33
NC_FW2_TPBP
MAKE_BASE=TRUE 2
33
NC_FW2_TPBN
MAKE_BASE=TRUE
CPS_EN_L
D
35 34 33 7
=PP3V3_FW_FWPHY
2
Q4300
G S
1
BSS8402DW
SOT-363
(SYM-VER1)
C
Termination
Place close to FireWire PHY
34 33 7
C
Cable Power
=PPVP_FW_PORT1
1
CRITICAL
L4310
FERR-250-OHM
2 SM 1
Note: Trace PPVP_FW_PORT1 must handle up to 5A PPVP_FW_PORT1_F

IN
FW_P1_TPBIAS
C4314
0.01UF
10% 50V X7R 402
C4360
0.33UF
10% 6.3V CERM-X5R 402
(FW_PORT1_TPA_P) (FW_PORT1_TPA_N)
"Snapback" & "Late VG" Protection

SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1 1
34 7
PORT 1
BILINGUAL CRITICAL
=PP3V3_S0_FWLATEVG
PLACE_NEAR=U4350.1:2 mm
R4360
56.2
R4361
56.2
1% 1/16W MF-LF 2 402

77 33
1% 1/16W MF-LF 402 2
0.1UF
C4350
FW_PORT1_TPA_P
MAKE_BASE=TRUE
10% 16V X5R 402
J4310
1394B-M97
F-RT-TH
VCC
2
BI BI BI BI
FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N

SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1 1
U4350
TPD4S1394
3 4 LLP
77 33
FW_PORT1_TPA_N
MAKE_BASE=TRUE
TP_FWLATEVG_VCLMP
34
VCLMP FWPWR_EN
D1+ D1D2+ D2-
8 7 6 5
(FW_PORT1_TPB_N) (FW_PORT1_BREF) (FW_PORT1_TPB_P)
1 9 2 8
TPB-
TPB(R)
TPBTPB<R>
OUTPUT
TPB+
VP
TPB+ VP
77 33
FW_PORT1_TPB_P
MAKE_BASE=TRUE
OUT
FWPORT_PWR_EN
77 33
FW_PORT1_TPB_N
MAKE_BASE=TRUE
CRITICAL
NC
(GND) (FW_PORT1_TPA_N) FW_PORT1_AREF (FW_PORT1_TPA_P)
7 6 3 5 4
B
INPUT
SC/NC TPAVG
NC VG TPATPA<R>
R4350
100K
5% 1/16W MF-LF 402
GND
2
R4362
56.2
R4363
56.2
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402 2
(PINS 5/6 AND 7/8 ARE SWAPPED FOR BETTER ROUTING)
TPA+
TPA(R)
TPA+
10 PLACE_NOTE=J4310.5:2 mm 11 12 13 2
FW_PORT1_TPB_C
C4319
0.1uF
1 10% 50V X7R 603-1
CHASSIS GND
C4364
220pF
5% 25V CERM 402
R4364
4.99K
1% 1/16W MF-LF 402
(FW_PORT1_TPB_P) (FW_PORT1_TPB_N)
2
R4319
1M
514S0605
AREF needs to be isolated from all local grounds per 1394b spec When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue) BREF should be hard-connected to logic ground for speed signaling and connection
5% 1/16W MF-LF 2 402
SYNC_MASTER=T27_MLB
PAGE TITLE
FireWire Connector
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED
43 OF 109
SHEET
35 OF 80
6
CRITICAL
5
Q4590
TPCP8102 =PP5V_SW_ODD_FET
8 6 7
8
2
FL4520
SYM_VER-1
ODD Power Control

7
=PP5V_S0_ODD
23V1K-SM 3 1 2
SATA ODD Port

CRITICAL
54722-0164
F-ST-SM 2 4 1 3 5 7 9 11 13
79 6 79 6 74 6 74 6
CRITICAL
R4596
100K
C4595 1
0.068UF
10% 10V CERM 2 402
J4500 connection separated to support debug sense resistor. Alias together if no sense R.
90-OHM-100MA DLP11S 3 4
79
J4500
SATA_ODD_R2D_UF_N SATA_ODD_R2D_UF_P
C4520 1
0.01UF
SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P
IN
17 74
10% 16V CERM 402 2

IN
17 74
5% 1/16W MF-LF 402 2
79
C4521 1
0.01UF
R4595
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.
36 7
C4596
0.01UF
1 2 10% 16V CERM 402
36 7
6
8
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_UF_N SATA_ODD_D2R_UF_P
PLACE_NEAR=J4500.5:4mm
10% 16V CERM 402
ODD_PWR_EN_LS5V_L
D 6
100K 2
5% 1/16W MF-LF 402
ODD_PWR_SS
=PP5V_SW_ODD
8 10 12 14
CRITICAL
SYM_VER-1
=PP3V3_S0_ODD
90-OHM-100MA DLP11S
4 3
74
FL4525
D
SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N
Q4596
1
R4597
100K
SSM6N15FEAPE
SOT563
=PP3V3_S0_ODD
16
15
C4525 1
0.01UF
SATA_ODD_D2R_P SATA_ODD_D2R_N
OUT
17 74
10% 16V CERM 402

2 OUT
17 74
5% 1/16W MF-LF 402 2
2 G
S 1
R45901
5% 1/16W MF-LF 402 2
39 6
516S0616
74
C4526 1
0.01UF
33K
PLACE_NEAR=J4500.9:4MM
10% 16V CERM 402
ODD_PWR_EN
Q4596
SSM6N15FEAPE
SOT563
D 3
OUT
SMC_ODD_DETECT
Indicates disc presence

36 7
PS8511A / PS8515A Straps

=PP1V5_S0_SATARDRVR NO STUFF RDRV:8515 NO STUFF
2
5 G
18
S 4
IN
ODD_PWR_EN_L
R45112
10K
R4515
10K
R4517
10K
PS8511A:
PART NUMBER 338S0769 QTY 1 DESCRIPTION
SATA 3GB/S REDRIVER, LOW POWER
REFERENCE DES U4510
CRITICAL CRITICAL
BOM OPTION RDRV:8511
C
PLACE_NEAR=J4501.9:3mm
BOMOPTIONs: - RDRV:8511 stuffs PS8511A & associated parts (STRAPS TBD!!!) - RDRV:8515 stuffs PS8515A & associated parts - RDRV:NO stuffs bypass path (neither IC or associated parts stuffed) NO STUFF
PIN 9 8 20 10
NAME A_PRE B_PRE A_BST# B_BST#
5% 1/16W MF-LF 402 1
5% 1/16W MF-LF 1 402
5% 1/16W MF-LF 1 402
(IPD) (IPD) (IPU) (IPU) NO STUFF

2
SATARDRVR_A_B_SD SATARDRVR_A_I2C_ADDR SATARDRVR_A_A_SD SATARDRVR_A_I2C_EN NO STUFF

2
36 36 36 36
RDRV:8515 NO STUFF
1
R45122
10K
5% 1/16W MF-LF 402 1
R4516
10K
R4518
10K
R45191
10K
5% 1/16W MF-LF 402 2
R4520
10K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 1 402
5% 1/16W MF-LF 1 402
CRITICAL
PLACE_NEAR=L4500.1:2mm
6
RDRV:8515
FERR-70-OHM-4A
1 0603
2
L4500
R4513
=PP5V_S0_HDD
7 42
IN
=I2C_HDD_A_SCL
19 RDRV:8515
A_EQ
(IPD)
SATARDRVR_A_I2C_SCL
36
PP5V_S0_HDD_FLT
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
PLACE_NEAR=L4500.2:2mm
2
C4501
0.1UF
C4502
0.1UF
42
5% 1/16W MF-LF 402 IN
R4514
2
=I2C_HDD_A_SDA
18
B_EQ
(IPD)
SATARDRVR_A_I2C_SDA
36
CRITICAL
J4501
20% 1 10V CERM 402
20% 1 10V CERM 402
R4531
40
54722-0224
F-ST-SM
SATA Redriver
PLACE_NEAR=U4510.16:3mm PLACE_NEAR=U4510.16:3mm
5% 1/16W MF-LF 402
SYS_LED_ANODE 2
4.7
SYS_LED_ANODE_R
1 3
2 4 6 8 10 12 14 16 18 20 22
79 79 74 6 74 6 74 6 74 6
5% 1/16W MF-LF 402
=PP1V5_S0_SATARDRVR
7 36
0.001UF
C4531
5 7 9 11 13
SATA_HDD_R2D_N SATA_HDD_R2D_P
C4516 1
0.01UF
NC
15 17
10% 16V CERM 402

2
R4510
10K
10% 6.3V CERM-X5R 2 402
10% 2 16V CERM 402
6 16
10% 50V CERM 2 402
SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P
RDRV:8511&RDRV:8515 (All 4 Cs)
RDRV:8511&RDRV:8515 (C4514, C4514 1 C4519 & R4510) 1UF
C4519
0.01UF
VDD
RDRV:IN_DEVEL CRITICAL (All 4 Cs) RDRV:8511&RDRV:8515

79
CRITICAL
90-OHM-100MA DLP11S
SYM_VER-1
FL4502
3
B
38 7
C4515 1
0.01UF
R4532
=PP5V_S3_IR 2
38 6 6
IR_RX_OUT
19 21
10% 16V CERM 402
5% 1/16W MF-LF 1 402
U4510
PS8515A-A2
1 2 4 5 7 17 10 8 19 18
SATA_HDD_D2R_RDRV_OUT_P SATA_HDD_D2R_RDRV_OUT_N
C4518 1
0.01UF
79
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_P SATA_HDD_D2R_N
OUT
17 74
10
PP5V_S3_IR_R
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm VOLTAGE=5V

1
SATA_HDD_D2R_RDRV_IN_P SATA_HDD_D2R_RDRV_IN_N SATA_HDD_R2D_RDRV_OUT_N SATA_HDD_R2D_RDRV_OUT_P SATARDRVR_A_EN 16 IN SATARDRVR_A_AUTOPWR_EN

36 36
TQFN
A_INP A_INN B_OUTN B_OUTP EN (IPU) AUTOPW_EN (IPD) I2C_EN (IPD) I2C_ADDR (IPD) SCL_CTL SDA_CTL
10% 16V CERM 402

2
79
A_OUTP 15 A_OUTN 14 B_INN 12 B_INP 11
79
C4517 1
0.01UF
SATA_HDD_D2R_UF_N
OUT
17 74
C4532
0.1UF
10% 16V CERM 402

2
CRITICAL
10% 16V 2 X7R-CERM 402
516S0687
3
79 79
FL4501 90-OHM-100MA
DLP11S
SYM_VER-1
79
SATA_HDD_R2D_RDRV_IN_N
79
C4513 1
0.01UF
SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P
16V 402
IN
17 74
10% 16V CERM 402

2 IN
17 74
79
SATA_HDD_R2D_UF_N SATA_HDD_R2D_UF_P
C4511 1
0.01UF
SATA_HDD_R2D_RDRV_IN_P
C4512 1
10% 16V CERM 402

2
79
C4510 1
0.01UF
SATARDRVR_A_I2C_EN SATARDRVR_A_I2C_ADDR SATARDRVR_A_I2C_SCL SATARDRVR_A_I2C_SDA
A_SD 20 B_SD 9
SATA HDD Port
10% 16V CERM 402
36 36
10% 0.01UF CERM SATARDRVR_A_A_SD 36 SATARDRVR_A_B_SD 36 PS8515A: x_SD pins are outputs (Signal Detect)
NOTE: Internal pulls are ~150K
GND THRM PAD 3 13 21
338S0778 (PS8515A)
Addr: 0x94(Wr)/0x95(Rd) (ALL 4 RS & CS) RDRV:NO
(All 4 Cs) RDRV:NO
Redriver Bypass Path

79
C4580 1
0.01UF
SATA_HDD_R2D_NORDRV_P SATA_HDD_R2D_NORDRV_N
R4580 1
0
10% 16V CERM 402

2
79
2 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402
C4581 1
R4581 1
0
0.01UF
10% 16V CERM 402

2
79
C4585 1
0.01UF
SATA_HDD_D2R_NORDRV_N SATA_HDD_D2R_NORDRV_P
R4585 1
34
10% 16V CERM 402

2
79
2 1% 1/16W MF-LF 402 2 1% 1/16W MF-LF 402
SYNC_MASTER=T27_MLB
PAGE TITLE
C4586 1
0.01UF
R4586 1
34
SATA Connectors
DRAWING NUMBER SIZE
10% 16V CERM 402
Apple Inc.
R
051-8563
REVISION
U4510 ADD NO STUFF IN PRODUCTION!!!!

J5401 PINOUTS ARE DIFFERENT FOR K6, DO NOT SYNC THIS PAGE FROM T27 DIRECTLY
C4587 1
47PF
A.13.0
BRANCH PAGE
5% 50V CERM 402

2

C4588 1
47PF
5% 50V CERM 402
45 OF 109
SHEET
36 OF 80
Port Power Switch

CRITICAL
7
CRITICAL
=PP5V_S3_RTUSB USB_EXTA_OC_L =USB_PWR_EN USB_EXTB_OC_L
Q4690
2 IN
TPS2064DGN
OC1* EN1 OC2* EN2 OUT2
17 65 17
OUT IN OUT
8 3 5 4
7 OUT1 MSOP 6
PP5V_S3_RTUSB_A_ILIM
FERR-220-OHM-2.5A 1 2 PP5V_S3_RTUSB_A_F
0603
L4605
Left USB Port A

CRITICAL
PP5V_S3_RTUSB_B_ILIM CRITICAL
1 1
C4605 1
0.01uF
20% 16V CERM 2 402
C4695
10UF
9
C4696
100UF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V PLACE_NEAR=J4600.1:3 mm
J4600
USB
GND TPAD
C4690 1
10UF
20% 6.3V 2 X5R 603
C4691
0.1UF
20% 6.3V 2 X5R 603
20% 2 6.3V POLY-TANT CASE-B2-SM
L4600 90-OHM-100MA
DLP11S SYM_VER-1 4 PLACE_NEAR=D4600.2:2 mm 3 79 USB_LT1_N
CRITICAL
F-RT-TH-M97-4 5 6 1 2 3 4 7 8
CRITICAL
1
79 75
USB_EXTA_MUXED_N USB_EXTA_MUXED_P
20% 10V 2 CERM 402
C4617 1
10UF
20% 6.3V 2 X5R 603
C4616
100UF
79 75
20% 2 6.3V POLY-TANT CASE-B2-SM
79
USB_LT1_P
4 3 5 2 IO NC IO NC VBUS 6 GND 1
PLACE_NEAR=D4600.3:2 mm
USB/SMC Debug Mux

7
514-0638
=PP3V42_G3H_SMCUSBMUX SMC_DEBUG:YES
D4600
RCLAMP0502N
SLP1210N6 1
D4600.4 PLACE_NEAR=J4600.3:2 mm D4600.5 PLACE_NEAR=J4600.2:2 mm
C4650 1
0.1UF
20% 10V CERM 2 402 5 M+ 4 M7 D+ 6 D8 OE* 9
R4650
10K CRITICAL
CRITICAL
CRITICAL SMC_DEBUG:YES
Y+ 1
VCC
Y- 2
5% 1/16W MF-LF 2 402
41 40 39 41 40 39
IN OUT
SMC_RX_L SMC_TX_L USB_EXTA_P USB_EXTA_N
U4650
TQFN
(USB_EXTA_MUXED_N) (USB_EXTA_MUXED_P)
FERR-220-OHM-2.5A 1 2 PP5V_S3_RTUSB_B_F
0603
L4615
Left USB Port B

CRITICAL
PI3USB102ZLE
75 17 75 17
C4615 1
0.01uF
20% 16V CERM 2 402
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V PLACE_NEAR=J4610.1:3 mm
BI BI
J4610
USB
CRITICAL 90-OHM-100MA
DLP11S
SYM_VER-1
SEL 10 GND 3 SIGNAL_MODEL=USB_MUX
USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB
L4610
IN
39
F-RT-TH-M97-4 5 6
PLACE_NEAR=D4610.2:2 mm 3
79
75 17
BI
USB_EXTB_N USB_EXTB_P
USB_LT2_N USB_LT2_P
SMC_DEBUG:NO
75 17
BI
79
R4651
1
PLACE_NEAR=D4610.3:2 mm
1 2 3 4 7 8 VBUS 6 GND 1
2 4 3 5 2 IO NC IO NC
5% 1/16W MF-LF 402
514-0638
SMC_DEBUG:NO
R4652
1
D4610
RCLAMP0502N
SLP1210N6
5% 1/16W MF-LF 402
D4610.4 PLACE_NEAR=J4610.3:2 mm D4610.5 PLACE_NEAR=J4610.2:2 mm
CRITICAL
SYNC_MASTER=T27_MLB
PAGE TITLE
External USB Connectors

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

46 OF 109
SHEET
37 OF 80
IR Support
36 7
=PP5V_S3_IR
D
10% 16V X7R-CERM 2 402
D
0.1UF
CY7C63803-LQXC QFN
75 17 75 17
U4800
BI BI
USB_IR_P USB_IR_N IR_VREF_FILTER

1
14 VCC
C4801 1
C4803
1UF
10% 2 10V X5R 402-1
NC NC NC NC NC NC NC NC NC NC NC NC
12 13 15 16 17 18 19
P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK P1.5/SMOSI P1.6/SMISO
P0.0 P0.1 INT0/P0.2 INT1/P0.3 INT2/P0.4 TIO0/P0.5 TIO1/P0.6
7 6 5 4 3 2 1
NC NC NC NC NC NC
R4800
1
IR_RX_OUT_RC 0.001UF
100
IR_RX_OUT
IN
6 36
8 9 10 20 21 NC 22 23 24
C4804 1
10% 50V CERM 2 402
5% 1/16W MF-LF 402
OMIT CRITICAL
THRML PAD 25
VSS 11
T57 Connector
T57
BS4890
STDOFF-3.6OD3.4H-SM
1
860-1287
CRITICAL T57
7
=PP3V3_S3_T57 T57
AXK720427G
J4890
C4895
0.01uF
F-ST-SM 21
B
75 6 75 6
20% 16V CERM 2 402
1 3
2 4 6 8 10 12 14 16 18 20
NC_T57_PWR_EN IN
NC NC
1
NC
BI BI
5 7
=PP5V_S3_T57 T57
USB_T57_P USB_T57_N
9 11 13 15
C4896
0.01uF
IN
NC_T57_RESET
2 5 3 4 6 VBUS 1 GND
NC
17 19
NC NC
20% 16V 2 CERM 402
22
NC IO NC IO
516S0824
T57
D4890
RCLAMP0502N
SLP1210N6
BS4891
STDOFF-3.6OD3.4H-SM
1
860-1287
T57 CRITICAL
SYNC_MASTER=T27_MLB
PAGE TITLE
Internal USB Support

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE
K6 NOTES : D4890 CONNECTION IS DIFFERENT,CANNOT DIRECTLY SYNC FROM T27
48 OF 109
SHEET
38 OF 80
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
40 40 7
PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC
D
C4902 1
22UF
1
D
C4903
0.1UF
1
C4904
0.1UF
C4905
0.1UF
C4906
0.1UF
(EXCARD_PWR_EN)
40 65 24 65
22
OUT IN IN
SMC_P10 SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L

NC
U4900
B12 A13 A12 B13 D11 C13 C12 D10 D13 E11 D12 F11 E13 E12 F13 E10 A9 D9 C8 B7 A8 D8 D7 D6 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52
20% 6.3V 2 CERM 805
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
H8S2117
LGA-HF (1 OF 3)
M12
B1 M1 H10
18 61 18
OUT OUT OUT
NC
C4920 1
0.1UF
E1
OUT
18 40 65
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE SMC_WAKE_SCI_L
5% 1/16W MF-LF 402
L11
OMIT
P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P90 P91 P92 P93 P94 P95 P96 P97
L13 K12 K11 J12 K13 J10 J11 H12 N10 M11 L10 N11 N12 M13 N13 L12 A7 B6 C7 D5 A6 B5 C6 J4 G3 H2 G1 H4 G4 F4 F1
SMC_PM_G2_EN
NC NC NC
OUT
6 65
BYPASS=U4900.E1:D2:5 mm
R4999 PLACE_NEAR=C4920.1:2
1
mm
SMC_VCL
4.7
PP3V3_S5_SMC_AVCC
SMC_ADAPTER_EN
C4907 1
0.47UF
10% 6.3V CERM-X5R 2 402
IN IN IN IN IN IN IN IN IN IN OUT
40 6 40 57
40
SMC_P20
NC NC NC NC NC
44 43 40 40 44 43 44
20% 10V CERM 2 402 BYPASS=U4900.M12:L9:5 mm
AVCC
VCC
VCL AVREF NC
H8S2117
LGA-HF (3 OF 3)
U4900
R49091
E5
NC
5% 1/16W MF-LF 402 2
10K
R4901
10K
5% 1/16W MF-LF 2 402
40
SMC_P24 SMC_BMON_MUX_SEL
OMIT
58 41 40
IN
40
SMC_RESET_L SMC_XTAL SMC_EXTAL
D3 A3 A2
RES* XTAL EXTAL
MD1 MD2
D1 H1
SMC_MD1 SMC_KBC_MDE
IN
41
44
22 40 18
NMI
E3
SMC_NMI
IN
41
75 41 18 75 41 18 75 41 18
BI BI BI BI IN IN IN BI
75 41 18 75 41 18 24 75 24 41 18
40 42 49
BI OUT
SMC_P41 SMB_MGMT_DATA SMS_ONOFF_L
NC
(OC)
NC NC
40 48
OUT OUT OUT IN BI
SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMB_0_S0_CLK
D4 A5 B4 A1 C2 B2 C1 C3 G2 F3 E4
SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK (OC) SMB_0_S0_DATA
IN IN IN IN IN IN IN BI
40 47 8 40 57 40 6 18 65 69 6 18 40 65 18 24 75 42
D2 L3 F10 B11 C5
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ
PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L (OC) SMB_MGMT_CLK
NC
OUT IN OUT IN BI
18 41 18 41 37 39 40 41 37 39 40 41 42
ETRST AVSS VSS
H3 L9 1
SMC_TRST_L NO STUFF
IN
41
R4902
10K
R4998
10K
R4903
0
XW4900 SM
2 1
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
NOTE: P94 and P95 are shorted in some platforms.
GND_SMC_AVSS
22 40 43 44
41 40 39 37 41 40 39 37 42
(OC)
(DEBUG_SW_1) (DEBUG_SW_2)
24 37 26 25 18
OUT OUT BI
B
57 18
BI OUT
SMC_PA0 SMC_PA1 PM_SYSRST_L USB_DEBUGPRT_EN_L MEM_EVENT_L SMC_PA5 40 SYS_ONEWIRE PM_BATLOW_L

40 40
U4900
(OC) (OC) (OC) (OC) (OC) (OC)
NC
N3 N1 M3 M2 N2 L1 K3 L2 B8 C9 B9 A10 C10 B10 C11 A11 G11 G13 F12 H13 G10 G12 H11 J13 M10 N9 K10 L8 M9 N8 K9 L7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
H8S2117
LGA-HF (2 OF 3)
OMIT
PE0 PE1 PE2 PE3 PE4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 PH3 PH4 PH5
K1 J3 K2 J1 K4 K5 N5 M6 L5 M5 N4 L4 M4 M8 N7 K8 K7 K6 N6 M7 L6 E2 F2 J2 A4 B3 C4
SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_G3H_POWERON_L SMC_SYS_LED SMC_LID

NC NC NC NC NC
IN IN IN OUT IN IN OUT IN
40 40 41 40 41 40 41 40 41 40
40 40 47 57
18 36 6
OUT IN
(EXCARD_CP) (EXCARD_OC_L)
40
SMC_RUNTIME_SCI_L SMC_ODD_DETECT SMC_PB3 (See below) 40 SMC_PB4 40

40
SMC_MCP_SAFE_MODE
OUT
40
IN OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN
SMC_PB6 SMC_GFX_OVERTEMP_L SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE SMC_ADC14 SMC_ADC15
NC
46 40 40 40 46 40 40 40
(OC) (OC) (OC) (OC) (OC) (OC)
=SMC_SMS_INT SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP
IN BI BI BI BI BI BI OUT OUT
40 42 42 42 42 42 42
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
40 40
NC NC NC
49 49 49 40 40
SMC_PH3
40
H8S2117-R: (SMC_PECI) (SMC_PECI_VREF) (SMC_PECI_VSTP)
40 40 40
SYNC_MASTER=T27_MLB
PAGE TITLE
SMC
DRAWING NUMBER SIZE
SMC_PB3: SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay.

R
Apple Inc.
051-8563
REVISION
A.13.0
BRANCH PAGE
49 OF 109
SHEET
39 OF 80
8
=PP3V3_S5_SMC =PPVIN_S5_SMCVREF Desktops: 5V Mobiles: 3.42V
1
3
=PP3V3_S0_SMC
1
2
SMC FSB to 3.3V Level Shifting
40 7
SMC Reset "Button", Supervisor & AVREF Supply

40 39 7 7
R5061
100K
R5060
10K
5% 1/16W MF-LF
TO SMC
C5020 1
0.47UF
10% 6.3V CERM-X5R 2 402
R5000
1K
V+
VIN
U5010
VREF-3.3V-VDET-3.0V
6 MR1* (IPU) SN0903048 7 MR2* (IPU) 4 DELAY GND 2
DFN
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
2 402
SMC_PROCHOT_3_3_L SMC_RESET_L PP3V3_S5_AVREF_SMC

OUT
39 39 41 58
OUT
39
47 47 40 39
IN IN
SMC_TPAD_RST_L SMC_ONOFF_L SMC_MANUAL_RST_L OMIT

1
RESET* 5
CPU_PROCHOT_BUF
6 D
D
Q5060
DMB53D0UV
SOT-563
REFOUT 8 THRM
PAD
R5001
0
C5001
0.01UF
TO CPU
5% 1/10W MF-LF 2 603
C5025
10uF
C5026
0.01UF
72 61 13 9
R5062
1
2 G
10% 16V CERM 2 402
BI
CPU_PROCHOT_L
3.3K 2
5% 1/16W MF-LF 402
CPU_PROCHOT_L_R
5 4
Q5060
DMB53D0UV
SOT-563
SILK_PART=SMC_RST PLACEMENT_NOTE=Place R5001 on BOTTOM side
20% 6.3V 2 X5R 603
10% 16V 2 CERM 402
S 1
6 D
GND_SMC_AVSS
Q5059
SSM6N15FEAPE
SOT563
22 39 43 44
MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.
1 S
G 2
SMC_PROCHOT
IN
39
Debug Power "Buttons"

OMIT SMC_ONOFF_L OMIT
1
OUT
39 40 47
72 13 9
OUT
PM_THRMTRIP_L
3 D
Q5059
SSM6N15FEAPE
SOT563
R50141
5% 1/10W MF-LF 603 2
R5015
0
4 S
5% 1/10W MF-LF 2 603
G 5
SILK_PART=PWR_BTN
SILK_PART=PWR_BTN PLACEMENT_NOTEs: Place R5014 on TOP side Place R5015 on BOTTOM side
SMC_THRMTRIP
IN
39
C
SMC Pull-ups
40 39 7
=PP3V3_S5_SMC
SMC Crystal Circuit

R5010
39
SMC Aliases
43
39 39 39
C5010
15pF
2 5% 50V CERM 402
SMC_MCP_VSENSE
MAKE_BASE=TRUE
SMC_ADC14 SMC_ADC15 SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE
OUT OUT OUT OUT OUT
39
39
SMC_PA0 SMC_PA1 SMC_PB4 SMC_PB6 SMC_ONOFF_L SMC_LID SMC_TX_L SMC_RX_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BIL_BUTTON_L SMC_BC_ACOK SMS_INT_L SMC_GFX_OVERTEMP_L SMC_G3H_POWERON_L
R5091 R5092 R5088 R5095 R5070 R5071 R5073 R5074 R5077 R5078 R5079 R5080 R5081 R5087 R5093 R5094 R5098
100K 100K 10K 10K 10K 100K 10K 100K 10K 10K 10K 10K 10K 470K 10K 10K 100K
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
402 402 402 402
SMC_XTAL
44
SMC_CPU_FSB_ISENSE
MAKE_BASE=TRUE
39 47 40 39 39 57 47 39 39 41 39 37 41 39 37
SMC_XTAL_R CRITICAL 20.00MHZ

5X3.2-SM
1 1
5% 1/16W MF-LF 402
44
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
Y5010
44
SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE
1 1 1 1
2 2 2 2
2
39
C5011
15pF
2 5% 50V CERM 402
39
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
402 402 402 402
TP_SMC_GPU_1V8_ISENSE
MAKE_BASE=TRUE
SMC_ANALOG_ID SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_IG_THROTTLE_L

MAKE_BASE=TRUE
OUT OUT OUT
39 41 39 39 41 39 41 39 39 41 39 57 39 6
SMC_EXTAL
TP_SMC_GPU_ISENSE
MAKE_BASE=TRUE
TP_SMC_GPU_VSENSE
MAKE_BASE=TRUE
IN
SMC_GFX_THROTTLE_L SMS_INT_L
MAKE_BASE=TRUE
OUT
18 57 39 8 40
40
=SMC_SMS_INT SMC_G3H_POWERON_L
MAKE_BASE=TRUE
39 39 40 39
B
18
IN
MCP_WAKE_REQ_L
1 1 1 1 1 1 1 1 2
2 2 2 2 2 2 2 2 1
OUT
39 40
5% 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
402 402 402 402 402 402 402 402 402
R5096
39
40 7
=PP3V3_S0_SMC
IN
SMC_MCP_SAFE_MODE
MCP_SPKR
OUT
18 39
System (Sleep) LED Circuit

7
5% 1/16W MF-LF 402
SMC_PA5
R5089
10K
2 5% 1/16W MF-LF 402
=PP5V_S3_SYSLED
SMC Pull-downs
1
R50311
1% 1/16W MF-LF 402 2
R5030
20
39
Unused Pins
IN
39 65 39 18 39 65 39 18 6
523
1% 1/16W MF-LF 2 402
SMC_FAN_1_CTL TP_SMC_FAN_1_TACH
MAKE_BASE=TRUE
TP_SMC_FAN_1_CTL
MAKE_BASE=TRUE
SMC_FAN_1_TACH NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE NO_TEST=TRUE
SMC_BS_ALRT_L SMC_ADAPTER_EN SMC_CASE_OPEN PM_SLP_S4_L
R5076 R5085 R5086 R5090
100K 10K 10K 100K
1 1 1 1
2 2 2 2
OUT
39
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
402 402 402 402
SYS_LED_ILIM
39
IN
SMC_FAN_2_CTL NC_SMC_FAN_2_TACH
SYS_LED_L_VDIV
39
SMC_FAN_2_TACH NC_SMC_FAN_3_CTL
OUT
39
IN
SMC_FAN_3_CTL NC_SMC_FAN_3_TACH
R50321
1.47K
SMC_FAN_3_TACH TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
1% 1/16W MF-LF 402 2
6 D
5 B
4 E
OUT
39
Q5030
DMB54D0UV
SOT-563
39
IN
SMC_RSTGATE_L
SYNC_MASTER=T27_MLB
PAGE TITLE
SYS_LED_L
Q1 S 1 G 2 Q2 C 3
39 39
IN IN IN IN IN
SMC_P20 SMC_P24 SMC_P41 SMC_PB3 SMC_PH3
TP_SMC_P20
MAKE_BASE=TRUE
SMC Support
DRAWING NUMBER SIZE
39
TP_SMC_P24
MAKE_BASE=TRUE
TP_SMC_P41
MAKE_BASE=TRUE
R
Apple Inc.
051-8563
REVISION
39
TP_SMC_PB3
MAKE_BASE=TRUE
A.13.0
BRANCH PAGE
39 39
TP_SMC_PH3
MAKE_BASE=TRUE
IN
SMC_SYS_LED
SYS_LED_ANODE
OUT
36
50 OF 109
SHEET
40 OF 80
LPC+SPI Connector
CRITICAL NO STUFF
D
7 7
55909-0374
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS
BI BI M-ST-SM 31 32
J5100
D
LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3> SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN BI BI
24 75 18 39 75 18 39 75
1
75 39 18 75 39 18
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
LPC_AD<0> LPC_AD<1> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
3 5 7
75 41 75 41 75 39 18 39 18 40 39 24 40 39 39 39 40 39 37
9 11 13 15 17 19 21 23 25 27 29
OUT
41 75 41 75
6 18 50
IN OUT OUT IN OUT IN OUT IN
BI IN OUT OUT OUT OUT OUT OUT
18 39 18 39 39 40 39 40 39 40 58 39 37 39 40 18
33
34
516S0573
SPI Bus Series Termination

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK SPI_ALT_CS_L LPCPLUS
1
41 75 41 75 41 75 41 75
LPCPLUS
1
LPCPLUS
1
LPCPLUS
1
R5128
0
R5127
47
R5126
47
R5125
47
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
R5110
75 18
IN
SPI_CS0_R_L
15
R5120
SPI_CS0_L
1
47
SPI_MLB_CS_L
OUT
50 75
R5111
75 18
IN
SPI_CLK_R
15
5% 1/16W MF-LF 402

75 6
R5121
SPI_CLK
1
47
5% 1/16W MF-LF 402
SPI_MLB_CLK
OUT
50 75
R5112
75 18
IN
SPI_MOSI_R
15
5% 1/16W MF-LF 402

75 6
R5122
SPI_MOSI
1
47
5% 1/16W MF-LF 402
SPI_MLB_MOSI
OUT
50 75
B
75 18 6
5% 1/16W MF-LF 402

OUT
R5123
1
SPI_MISO
15
5% 1/16W MF-LF 402
SPI_MLB_MISO
B
IN
50 75
5% 1/16W MF-LF 402
EFI Debug ROM

7
=PP3V3_S0_DEBUGROM EFI_DEBUG EFI_DEBUG

1
R51011
5% 1/16W MF-LF 402 2
R5103
0
EFI_DEBUG
C5101
0.1UF
5% 1/16W MF-LF 2 402
20% 10V CERM 2 402
EFI_DEBUG
VCC
U5101
3 E2 2 E1
NO STUFF
DEBUGROM_E2 DEBUGROM_E1 NO STUFF

1
M24M01-R
SO8N
SDA 5 6
=I2C_DEBUGROM_SDA =I2C_DEBUGROM_SCL
NC
BI IN
42
CRITICAL SCL
VSS 4
42
R51021
5% 1/16W MF-LF 402 2
R5104
0
5% 1/16W MF-LF
7 WC*
SYNC_MASTER=T27_MLB
PAGE TITLE
E0/NC0 1
LPC+SPI Debug Connector

DRAWING NUMBER SIZE
2 402
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE
Write: 0xAC/0xAE Read: 0xAD/0xAF

51 OF 109
SHEET
41 OF 80
MCP89 SMBus "0" Connections

7
SMC "0" SMBus Connections

7
SMC "Battery A" SMBus Connections

7
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V42_G3H_SMBUS_SMC_BSA
MCP89
U1400 (MASTER)
R52001
5% 1/16W MF-LF 402 2
R5201
1K
1K
SO-DIMM "A"
J2900 (Write: 0xA0 Read: 0xA1) =I2C_SODIMMA_SCL =I2C_SODIMMA_SDA
25 39
SMC
U4900 (MASTER) SMB_0_S0_CLK SMB_0_S0_DATA
78
R52501
4.7K
5% 1/16W MF-LF 402 2
R5251
4.7K
MCP Temp
EMC1412-A: U5535 (WRITE: 0X98 READ: 0X99) =I2C_MCPTHMSNS_SCL =I2C_MCPTHMSNS_SDA
45 39
SMC
U4900 (MASTER) SMB_BSA_CLK SMB_BSA_DATA
MAKE_BASE=TRUE
45 39
R52801
2.61K
1% 1/16W MF-LF 402 2
R5281
2.61K
Battery Charger
ISL6259 - U7000 (Write: 0x12 Read: 0x13) =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
58
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
75 18 12
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
25 39 78
75 18 12
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
58
MAKE_BASE=TRUE
Vref DACs
U3300 (Write: 0x98 Read: 0x99)
28
SO-DIMM "B"
J3100 (Write: 0xA2 Read: 0xA3) =I2C_SODIMMB_SCL
NBC
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
7
Battery & BIL Battery

Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91) J6950 & J6955 (See Table) =SMBUS_BATT_SCL =SMBUS_BATT_SDA
57
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
26
=PP3V3_S3_SMBUS_SMC_A_S3
28
=I2C_SODIMMB_SDA
26
57
SMC
Margin Control
U3310 (Write: 0x30 Read: 0x31)
28
R52701
5% 1/16W MF-LF 402 2
78 6
R5271
1K
Mikey U6880
(Write: 0x72 Read: 0x73) =I2C_MIKEY_SCL =I2C_MIKEY_SDA
56 39 39 56
U4900 (MASTER) SMB_A_S3_CLK SMB_A_S3_DATA

MAKE_BASE=TRUE
78 6
1K
Trackpad
J5800 (Write: 0x90 Read: 0x91) =I2C_TPAD_SCL =I2C_TPAD_SDA
48
5% 1/16W MF-LF 2 402
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA
SMC "Management" SMBus Connections

The bus formerly known as "Battery B"
7
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
MAKE_BASE=TRUE
48
=PP3V3_S5_SMBUS_SMC_MGMT
28
ALS
EFI Debug Serial
LP8545 (Bklt)
U9701 (Write: 0x58 Read: 0x59) =I2C_BKL_1_SCL =I2C_BKL_1_SDA
70
J3401 (Write: 0x52 Read: 0x53) I2C_ALS_SCL I2C_ALS_SDA

29 39
SMC
U4900 (MASTER) SMB_MGMT_CLK SMB_MGMT_DATA
78
R52901
4.7K
5% 1/16W MF-LF 402 2
R5291
4.7K
U5101 (Write: 0xAC/0xAE Read: 0xAD/0xAF) 41 =I2C_DEBUGROM_SCL

41
5% 1/16W MF-LF 2 402
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
29 39 78
MAKE_BASE=TRUE
=I2C_DEBUGROM_SDA
70
HDD Margin Ctrl.

U4510 (Write: 0x94 Read: 0x95) =I2C_HDD_A_SCL =I2C_HDD_A_SDA
36
36
MCP89 SMBus "1" Connections

B
MCP89
U1400 (Write: 0x?? Read: 0x??)
75 18 7
SMC "B" SMBus Connections

7
=PP3V3_S0_SMBUS_MCP_1 NO STUFF NO STUFF

1
=PP3V3_S0_SMBUS_SMC_B_S0
B
1
R52301
2.0K
5% 1/16W MF-LF 402 2
R5231
2.0K
SMC
U4900 (MASTER)
39
R52601
4.7K
5% 1/16W MF-LF 402 2
R5261
4.7K
CPU Temp
EMC1413: U5515 (Write: 0x98 Read: 0x99) =I2C_CPUTHMSNS_SCL =I2C_CPUTHMSNS_SDA
45
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
SMB_B_S0_CLK SMB_B_S0_DATA
78
SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
78
75 18
SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
39
MAKE_BASE=TRUE
45
R52351
MCP89 SMBus 1 is slave port to access internal thermal diodes.
5% 1/16W MF-LF 402 2
R5236
0
5% 1/16W MF-LF 2 402
NOTE:
R5280/81 WAS 2K ON K24, VALUE NEEDS TO BE CHECKED R5290/91 (VREF DAC, MARGIN CONTROL)WAS 4.7K ON K24, VALUE NEEDS TO BE CHECKED
SYNC_MASTER=T27_MLB
PAGE TITLE
K6 SMBUS CONNECTIONS
DRAWING NUMBER SIZE
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R
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REVISION
A.13.0
BRANCH PAGE

52 OF 109
SHEET
42 OF 80
CPU Voltage Sense / Filter

7 6
PPVCORE_S0_CPU
XW5309 SM
1 2
R5309
CPUVSENSE_IN
1
4.53K2
1% 1/16W MF-LF 402
SMC_CPU_VSENSE
1
OUT
39
PLACE_NEAR=L7400.2:5 MM
C5309
0.22UF
20% 2 6.3V X5R 402
GND_SMC_AVSS Place RC close to SMC
22 39 40 43 44
MCP Voltage Sense / Filter

7 6
PPVCORE_S0_MCP
XW5359 SM
1 2
R5359
MCPVSENSE_IN
1
4.53K2
1% 1/16W MF-LF 402
SMC_MCP_VSENSE
1
OUT
40
PLACE_NEAR=R7525.2:5 MM
C5359
0.22UF
20% 2 6.3V X5R 402
GND_SMC_AVSS Place RC close to SMC
22 39 40 43 44
PBUS Voltage Sense Enable & Filter

Q5315
NTUD3169CZ
SOT-963
N-CHANNEL
D
PBUSVSENS_EN_L
R53161
100K
1% 1/16W MF-LF 402 2 3
65
IN
=PBUSVSENS_EN
G S
Enables PBUS VSense divider when high.
PBUS_G3H_VSENSE
R53851
27.4K
1% 1/16W MF-LF 402 2
5
7 6
G S
PPBUS_G3H
4
RTHEVENIN = 4573 Ohms SMC_PBUS_VSENSE

OUT
39
P-CHANNEL
R53151
100K
1% 1/16W MF-LF 402 2
R5386
5.49K PBUSVSENS_EN_L_DIV
1 1
C5385
0.22UF
1% 1/16W MF-LF 402 2
20% 6.3V 2 X5R 402
GND_SMC_AVSS
22 39 40 43 44
Place RC close to SMC
SYNC_MASTER=T27_MLB
PAGE TITLE
Voltage Sensing
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

53 OF 109
SHEET
43 OF 80
MCP MEM VDD Current Sense / Filter

7
MCP VCore Current Sense Filter

R5416
7
=PP3V3_S0_MCPDDRISNS =PP3V3_S0_MCPCOREISNS
62
IN
MCPCORES0_IMON
4.53K 2
1% 1/16W MF-LF 402
SMC_MCP_CORE_ISENSE
1
OUT
40
C5400 1
D
20
0.1uF
20% 10V CERM 2 402

5
C5472
0.22UF
U5400
OPA330
SC70-5
C5420
0.1uF
D
40 43 44
V+
IN
MCPDDRFET_KELVIN MCPDDRFET_SENSE
1 3
+IN -IN
V+ V2
MCPDDR_SENSE_AMP
8
(Sense R "output")
IN
U5420
5 IN4 IN+ SC70
20
IN
=MCPCOREISNS_N =MCPCOREISNS_P (Sense R "input")
INA214
20% 2 10V CERM 402
20% 2 6.3V X5R 402
R5415
1
OUT 6
REF 1
MCPCORE_IOUT
GND_SMC_AVSS 22 39 PLACEMENT_NOTEs:
R54101
5% 1/16W MF-LF 402 2
Gain: 100x
Scale: 10A / V Max VOut: 2.48V
IN
(100V/V)
GND
2
5% 1/16W MF-LF 402
Place close to SMC (For R and C)
R54112
MCPDDR_SENSE_E
1 2 5% 1/16W MF-LF 402 1
Sense R is R7525, 1mOhm Max Vdiff = 24.8mV
NOTE: Do not stuff R5415 and R7593 at the same time!
NO STUFF
C5434
0.1UF
Q5401
SOD 1
2SA2154MFV-YAE MCPDDR_SENSE_B
10% 2 16V X5R 402
R5417
MCPDDR_SENSE_C
1
4.53K 2
1% 1/16W MF-LF 402
SMC_MCP_DDR_ISENSE
1
OUT
40
R5412
118
C5435
0.22UF
1% 1/16W MF-LF 402 2
PLACEMENT_NOTEs: Place close to SMC (For R and C)
20% 6.3V 2 X5R 402
GND_SMC_AVSS
22 39 40 43 44
MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter

7
CPU VCore Load Side Current Sense / Filter

R5471
61
=PP3V3_S0_CPUVTTISNS
IN
IMVP6_IMON
6.19K 2
1% 1/16W MF-LF 402
SMC_CPU_ISENSE
OUT
39
=PPBUS_S5_CPUREGS_ISNS_R
3 1
CRITICAL
C5417
0.1uF
R5480
17.4K
C5470
0.22UF
R5492
0.5% MF 0612-1 1W
1 3
V+
0.01
U5402
79
ISNS_CPUVTT_N ISNS_CPUVTT_P
5 IN4 IN+
INA213
SC70
20% 2 10V CERM 402
PLACEMENT_NOTEs:
R5418
1
OUT 6
REF 1
CPUVTT_IOUT
4.53K 2
1% 1/16W MF-LF 402
SMC_CPU_FSB_ISENSE
1
OUT
40
Place close to SMC (For Rs and C)
1% 1/16W MF-LF 402 2
20% 6.3V 2 X5R 402
2 4
GND_SMC_AVSS
22 39 40 43 44
79 7
=PPBUS_S5_CPUREGS_ISNS
(50V/V)
GND
2
C5436
0.22UF
20% 2 6.3V X5R 402
GND_SMC_AVSS
22 39 40 43 44
B
Battery (BMON) Current Sense, MUX & Filter
7
B
DC-IN (AMON) Current Sense Filter
R5481
BMON:ENG PLACEMENT_NOTE=Place near sense resistor Charger/Load side
78 58 58
=PP3V42_G3H_BMON_ISNS BMON:ENG
IN
CHGR_AMON
4.53K 2
1% 1/16W MF-LF 402
SMC_DCIN_ISENSE
1
OUT
39
C5418
0.1uF
C5459 1
0.1uF
20% 10V CERM 2 402
BMON:ENG NC7SB3157P6XG
1 B1 SC70
1 SEL 6
C5487
0.22UF
V+
U5403
5 IN4 IN+
IN
CHGR_CSO_R_P CHGR_CSO_R_N
INA213
SC70
20% 2 10V CERM 402
U5413
PLACEMENT_NOTEs: SMC_BMON_MUX_SEL
IN
39
OUT 6
REF 1
BMON_INA_OUT
BMON:ENG
78 58
IN
(50V/V)
GND
2
2 GND
0
VCC 5
ISL6259 Gain: 36x INA213 Gain: 50x

SMC_BATT_ISENSE
1
OUT
39
Place close to SMC (For R and C)
20% 2 6.3V X5R 402
GND_SMC_AVSS
22 39 40 43 44
Battery side NOTE: Monitoring current from battery to PBUS (battery discharge) across R7008
58
R5401
4
3
B0 A
BMON_AMUX_OUT BMON:ENG
1
45.3K 2
1% 1/16W MF-LF 402
VER 1
BMON:PROD
R5423
100K
C5490
0.022UF
R5431
IN
CHGR_BMON For engineering, stuff BMON_ENG For production, stuff BMON_PROD
From charger
5% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
10% 2 16V CERM-X5R 402
GND_SMC_AVSS
22 39 40 43 44
SYNC_MASTER=T27_MLB
PAGE TITLE
PLACEMENT_NOTE=Place R5431 next to U5413
Current Sensing
DRAWING NUMBER SIZE
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SHEET
44 OF 80
CPU T-Diode Thermal Sensor

D
7
=PP3V3_S0_CPUTHMSNS
R5515
1
D
PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 1 VDD 1
47
5% 1/16W MF-LF 402

79 9
C5515
0.1uF R5516 1
10K
1% 1/16W MF-LF 402 1
BI
CPU_THERMD_P
C5521 1
CPU Thermal Diode CPU_THERMD_N CPUTHMSNS_D2_P
3
20% 2 10V CERM 402
R5517
10K
5% 1/16W MF-LF 402
0.0022uF
U5515
EMC1413
DFN 2 DP1 THERM*/ADDR 3 DN1CRITICAL ALERT* 4 DP2/DN3 SMDATA SMCLK
THRM_PAD 11
10% 50V CERM 2 402
7 8 9 10
CPUTHMSNS_THERM_L CPUTHMSNS_ALERT_L
79 9
BI
Fin-Stack Temperature CRITICAL
=I2C_CPUTHMSNS_SDA =I2C_CPUTHMSNS_SCL
BI BI
42
Q5501
BC846BMXXH
SOT732-3 2
0.0022uF
79
C5520 1
10% 50V CERM 2 402
5 DN2/DP3 GND 6
Addr: 0x98(Wr)/0x99(Rd)
42
CPUTHMSNS_D2_N
PLACEMENT_NOTE=Place U5515 near CPU Local sensor for CPU Proximity
PLACEMENT_NOTE=Place Q5501 near Fin Stack
MCP T-Diode Thermal Sensor

7
=PP3V3_S0_MCPTHMSNS
R5535
1
47
PP3V3_S0_MCPTHMSNS_R
5% 1/16W MF-LF 402

79 18
C5535
0.1uF R5536 1
10K
1% 1/16W MF-LF 402 2 1
BI
MCP_THMDIODE_P MCP Thermal Diode 0.0022uF 10%
B
79 18
C5522
1 VDD
20% 2 10V CERM 402
R5537
10K
U5535
EMC1412-A
MSOP
2 DP 3 DN 7 SMDATA 8 SMCLK THERM*/ADDR ALERT* 4 6
5% 1/16W MF-LF 2 402
50V CERM 2 402
MCPTHMSNS_THERM_L MCPTHMSNS_ALERT_L
BI
MCP_THMDIODE_N
42 42
BI BI
=I2C_MCPTHMSNS_SDA =I2C_MCPTHMSNS_SCL
CRITICAL
GND 5
PLACEMENT_NOTE=Place U5535 near MCP Local sensor for MCP Proximity
SYNC_MASTER=T27_MLB
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE
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SHEET
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=PP5V_S0_FAN_RT =PP3V3_S0_FAN_RT
CRITICAL
C
39
R5660 1
47K 5%
SMC_FAN_0_TACH
J5601
78171-0004
NC
M-RT-SM 5
R5665 47K 2 1
5% 1/16W MF-LF 402
1/16W MF-LF 402

6
2
1 2 3 4
FAN_RT_TACH
5V DC TACH MOTOR CONTROL GND
NC
R5661 1
100K
5% 1/16W MF-LF 402
518S0521
Q5660 SSM3K15FV
SOD-VESM-HF
2 S D
3
FAN_RT_PWM
39
SMC_FAN_0_CTL
SYNC_MASTER=K24_MLB
PAGE TITLE
Fan
DRAWING NUMBER SIZE
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SHEET
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PSOC USB CONTROLLER

48 47 7
IC TMP102 3V3 LDO PSOC 18V BOOSTER
PIN NAME V+ VDD VOUT VDD VIN
CURRENT 10UA 80UA
R_SNS
V_SNS
POWER 0.255E-6 W 16.32E-6 W 36E-3 W 0.72E-3 W 96E-6 W 294E-6 W 75.2E-6 W
USB INTERFACES TO MLB SPI HOST TO Z2 TRACKPAD PICK BUTTONS KEYBOARD SCANNER
BYPASS=U5701.49:50:11 mm BYPASS=U5701.49:50:8 mm BYPASS=U5701.49:50:5 mm
2.55 KOHM 0.0255 V 0.204 V 0.6 0.012 0.012 0.021 V V V V
Keyboard Connector
48 47 7 47 7
60MA (MAX) 10 OHM 60MA (MAX) 0.2 OHM 8MA (TYP) 1.5 OHM 14MA (MAX) 4MA (MAX) 4.7 OHM
=PP3V3_S3_TPAD =PP3V42_G3H_TPAD
NC
32
=PP3V3_S3_TPAD
R5704
2
30 29
47 6 47 47 47 47 47 47
1.5
PP3V3_S3_PSOC
5% 1/16W MF-LF 402
0.0188 V
C5704
100PF
C5705
0.1UF
C5706
4.7UF
5% 2 50V CERM 402
10% 2 16V X7R-CERM 402
20% 2 6.3V X5R 603
48 6 47 48 6 47 47
PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY

NC
56 55 54 53 52 51 50 49 48 47 46 45 44 43
WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18
47 6 47 47 6 47 47 6 47 6 47 6 47 6 47 47
R5714
WS_KBD15_C
1
47 47 47 47
470
1% 1/16W MF-LF 402
R5715
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD
42 41 40 39 38 37 36 35 34 33 32 31 30 29
47 47 47 47 47 47 47
47 48 6
WS_CONTROL_KEY Z2_KEY_ACT_L TP_P4_5 Z2_DEBUG3 Z2_RESET PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK
NC
48 6 48 6 48 6 48 6
48 6 48 6 48 6 48 6 48 6 48 6
P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6
15 P1_7
16 P1_5
17 P1_3
18 P1_1
P2_3 2 P2_1 3 P4_7 4 P4_5 5 P4_3 6 P4_1 7 P3_7 8 P3_5 9 P3_3 10 P3_1 11 P5_7 12 P5_5 13 P5_3 14 P5_1
CRITICAL OMIT
U5701
CY8C24794
MLF
(SYM-VER2)
337S2983
WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3
6 47 47 47 6 47 6 47 6 47 40 39 6 47 6 47 6 47 6 47 6 47 6 47 6 47 6 47
47
WS_KBD16N
10K
1% 1/16W MF-LF 402
R5710
OUT
SMC_ONOFF_L
1 1
1K
WS_KBD1 WS_KBD2 6 WS_KBD3 6 WS_KBD4 6 WS_KBD5 6 WS_KBD6 6 WS_KBD7 6 WS_KBD8 6 WS_KBD9 6 WS_KBD10 6 WS_KBD11 6 WS_KBD12 6 WS_KBD13 6 WS_KBD14 6 6 WS_KBD15_CAP 6 WS_KBD16_NUM WS_KBD17 6 WS_KBD18 6 WS_KBD19 6 WS_KBD20 6 WS_KBD21 6 WS_KBD22 6 WS_KBD23 6 6 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
NC
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4
C5710
0.1UF
5% 1/16W MF-LF 402
47 6 47 6 47 6
3 2 1
20% 10V CERM 2 402

PLACEMENT_NOTE=NEAR J5713
31 F-RT-SM
19 VSS
22 VDD
FF14-30A-R11B-B-3H
57
20 D+
21 D-
J5713
CRITICAL
6 47 6 47 6 47
23
TP_PSOC_SCL TP_PSOC_SDA TP_PSOC_P1_3 TP_ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL
WS_KBD4 WS_KBD5 WS_KBD6 TP_ISSP_SDATA_P1_0 ISSP SDATA/I2C SDA

2
79
518S0637
R5701
75 17
USB_TPAD_P
24
USB_TPAD_R_P
Z2_CLKIN TP_P7_7
6 48
SMC Manual Reset & Isolation

Left shift, option & control keys combined with power button cause SMC RESET# assertion. Keys ANDed with PSOC power to isolate when PSOC is not powered.
47 7
5% 1/16W MF-LF 402
(PP3V3_S3_PSOC)
1
79
R5702
75 17
C5702
100PF
C5703
0.1UF
C5701
4.7UF
48 47 7
USB_TPAD_N
24
=PP3V42_G3H_TPAD
USB_TPAD_R_N
5% 1/16W MF-LF 402
5% 2 50V CERM 402
10% 2 16V X7R-CERM 402
20% 2 6.3V X5R 603
=PP3V3_S3_TPAD
CRITICAL
C5750
0.1UF
BYPASS=U5701.22:19:5 mm BYPASS=U5701.22:19:8 mm BYPASS=U5701.22:19:11
VDD mm
B
47 6
U5750
SLG4AP006
WS_LEFT_SHIFT_KBD
2 IN_A1
(IPD)
10% 2 16V X7R-CERM 402
B
47
TDFN OUT_A 4
3 IN_A2
(IPD)
WS_LEFT_SHIFT_KEY
TPAD Buttons Disable

47
7 IN_A3_B2
(IPD)
BUTTON_DISABLE
47 6
WS_LEFT_OPTION_KBD
6 IN_B1
(IPD)
OUT_B 8 THRM PAD 9
WS_LEFT_OPTION_KEY
47
Q5701
SSM3K15FV
SOD-VESM-HF
D 3
PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
GND
SMC_TPAD_RST_L NO STUFF
OUT
40
Q5702
1
57 40 39
S 2
IN
SMC_LID
CRITICAL
THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V
SSM3K15FV
SOD-VESM-HF
D 3
C5755
0.1UF
VDD
S 2
U5755
SLG4AP015V
2 IN_A1
(IPD)
10% 2 16V X7R-CERM 402
TDFN
R5720
OUT_A* 4
3 IN_A2
(IPD)
SMC_TPAD_RST
47 6
WS_CONTROL_KBD
7 IN_A3_B2
(IPD)
5% 1/16W MF-LF 402
6 IN_B1
(IPD)
OUT_B 8 THRM PAD 9
WS_CONTROL_KEY
SYNC_MASTER=T27_MLB
PAGE TITLE
47
WELLSPRING 1
DRAWING NUMBER SIZE
GND 5
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SHEET
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BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS - R5812,R5813,C5818 MODIFIED CRITICAL 3.3UH-870MA PP5V_S3_P18V5S3
7
L5801
CRITICAL
IPD Flex Connector

R5806
PP18V5_S3_R
1 1
D5802 SOD-323
P18V5S3_SW
1 2
PP18V5_S3
6 48
CRITICAL
=PP5V_S3_TPAD
R5805
2
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V
VLF3010AT-SM-HF
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE B0520WSXG
J5800
47 7
PP5V_S3_P18V5S3_VIN
5% 1/16W MF-LF 402
C5818
39PF
2 VIN
R5812
1M
5% 1/16W MF-LF 402
=PP3V3_S3_TPAD
47 6 47 6 47 6
55560-0228
M-ST-SM 2 1 3 5 7 9 11 13 15 17 19 21 4 6 8 10 12 14 16
PP18V5_S3 Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK =I2C_TPAD_SDA =I2C_TPAD_SCL
6 47 6 47 6 47 6 47 6 47 6 47 6 47 42 42
6 48
5% 50V CERM 2 402
1% 1/16W MF-LF 2 402
1 3
L DO
U5805
TPS61045
QFN
FB
4 5 8
1
P18V5S3_FB Z2_BOOST_EN
6 48
C5819
1UF
10% 603-1
47 6 47 6 48 6 47 6
NC
CTRL SW GND
R5813
71.5K
25V 2 X5R
C5816
0.1UF
10% 402
C5817
2.2UF
10% 603
CRITICAL
PGND
Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN

NC
R5811
100K
16V X7R-CERM 2
16V 2 X5R
THRML
PAD
9 7
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
18 20 22
47 6
C
516S0689
Keyboard Backlight Driver & Detection

7
=PP5V_S0_KBDLED
CRITICAL KB_BL 10UH-0.58A-0.35OHM 1 2 KBDLED_SW
B
7
BYPASS=U5850.1:2:2 MM
L5850
1098AS-SM
Keyboard Backlight Connector

CRITICAL KB_BL
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE
6
=PP3V3_S0_TPAD
470K
5% 1/16W MF-LF 402 2
39
1UF
10%
R58531
KB_BL
C5850
402-1
FF18-4A-R11AD-B-3H
F-RT-SM
J5815
1 2
VIN
SMC_KDBLED_PRESENT_L
10V 2 X5R
6 CTRL
CRITICAL KB_BL
SW 3
6
J5815 pin 1 is grounded on keyboard backlight flex
BI
SMC_SYS_KBDLED KB_BL
1
LED 5
KBDLED_ANODE
To detect Keyboard backlight, SMC will tristate and read SMC_SYS_KBDLED: If LOW, keyboard backlight present If HIGH, keyboard backlight not present R5853 always stuffed, R5854 only grounded when KB BL flex connected.
KB_BL
1
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
R5854
4.7K
U5850
LT3491
DFN
R5855
10
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
518S0691
NO STUFF
CAP 4 THRML GND 2
KBDLED_CAP
1
R58521
10K
5% 1/16W MF-LF 402 2
KB_BL
PAD
7
C5855
1UF
10% 35V 2 X5R 603
(SMC_KBDLED_PRESENT_L)
SYNC_MASTER=T27_MLB
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER SIZE
Apple Inc.
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REVISION
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K6 NOTES : C5850 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNCED FROM T27
58 OF 109
SHEET
48 OF 80
Analog SMS
7
=PP3V3_S3_SMS
R5921 pulls up SMS_PWRDN to turn off SMS when pin is not being driven by SMC
R5921 1
10K
5% 1/16W MF-LF 402 2
C5926
10UF
20% 4V X5R 603
C5922
0.1UF
10% 16V X5R 402 1
VDD
Desired orientation when placed on board top-side:

+Y 12 10 8
B
Front of system
U5920
AP344ALH
LGA
14
FS PD ST RES
VOUTX VOUTY VOUTZ
SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS
OUT OUT OUT

1
39
39
IN
SMS_ONOFF_L
SMS_PWRDN
MAKE_BASE=TRUE
+X
39
SMS_SELFTEST
+Z (up)
39
15
NC
1
4 3 6 9
RES CRITICAL NC NC NC GND

7
C5923
0.01UF
NC NC NC
11 13 16
C5924
0.01UF
10% 16V CERM 402
C5925
0.01UF
10% 16V CERM 402
R5922
10K
5% 1/16W MF-LF 402
NC NC NC
NC NC NC
10% 16V CERM 402
Circle indicates pin 1 location when placed in correct orientation
SYNC_MASTER=T27_MLB
PAGE TITLE
Sudden Motion Sensor (SMS)

DRAWING NUMBER SIZE
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SHEET
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=PP3V3_S5_ROM SPI:41MHZ&SPI:62MHZ 3.3K

5% 1/16W MF-LF 2 402
SPI:31MHZ&SPI:62MHZ
R61501
C
75 41
10K
5% 1/16W MF-LF 402 2 IN
R6101
C6100 1
0.1UF
20% 10V CERM 2 402 6 SCLK
CRITICAL
R6151
10K
VCC
U6100
32MBIT
SOP SI/SIO0 5 MX25L3205DM2I-12G
5% 1/16W MF-LF 2 402
C
IN
41 75
SPI_MLB_CLK SPI_MLB_CS_L SPI_WP_L SPIROM_USE_MLB SPI:25MHZ&SPI:41MHZ
SPI_MLB_MOSI
75 41
IN
1 CE*
OMIT
SO/SIO1 2
3 WP*/ACC
7 HOLD*
SPI_MLB_MISO
OUT
41 75
41 18 6
IN
NOTE: If HOLD* is asserted ROM will ignore SPI cycles.
R61521
10K
5% 1/16W MF-LF 402 2
GND 4
SPI:25MHZ&SPI:31MHZ
1
R6153
10K
5% 1/16W MF-LF 2 402
MCP89 SPI Frequency Select

Frequency SPI_MOSI SPI_CLK 25.0 MHz 31.2 MHz 0 0 1 1 0 1 0 1
41.7 MHz 62.5 MHz
NOTE: 42 & 62 MHz use FAST_READ command.
SYNC_MASTER=T27_MLB
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE
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AUDIO CODEC
APPLE P/N 353S2355
L6201
FERR-220-OHM
7
U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL

=PP5V_S3_AUDIO PP1V8R1V5_S0_AUDIO_DIG
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V
7 51 53 55
IN
=PP1V8R1V5_S0_AUDIO
1 0402
C6210
C6211
0.1UF
10% 16V X5R 402
=PP3V3R1V5_S0_AUDIO PP4V5_AUDIO_ANALOG
D
55 53 51 51 6
4.7UF
20% 4V X5R-1 402 2 2
D
IN
6 51
C6216 C6219
10UF
1
C6215
0.1UF
10% 16V X5R 402
1UF
C6214
0.1UF
2 10% 16V X5R 402
C6213
10UF
20% 6.3V X5R 603-1
GND_AUDIO_HP_AMP PP4V5_AUDIO_ANALOG
CRITICAL
46
24
25
20% 16V TANT-POLY 2012-LLP
C6218
2
C6217
10UF
20% 16V TANT-POLY 2012-LLP
0.1UF
10% 16V X5R 402
10% 10V X5R 402-1
CRITICAL
IN
C6221
10UF
1
C6220
10UF
20% 6.3V X5R 603-1
GND_AUDIO_HP_AMP GND_AUDIO_CODEC
51 53 55 51 52 55 56
R6210
2.67K
1% 1/16W MF-LF 402
20% 6.3V X5R 603-1
VBIAS_DAC CS4206_FP CS4206_FN
29 44 41
CRITICAL
VD VA_REF VA_HP VA VBIAS_DAC HPOUT_L VHP_FILT+ HPOUT_R VHP_FILTU6201 CS4206ACNZC HPREF

QFN
38 40 39 35 34 36 37 31 30 32 33
MIN_LINE_WIDTH=0.30MM MIN_LINE_WIDTH=0.30MM MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
AUD_HP_PORT_L AUD_HP_PORT_R AUD_HP_PORT_REF TP_AUD_LO1_P_L TP_AUD_LO1_N_L AUD_LO1_P_R AUD_LO1_N_R AUD_LO2_P_L AUD_LO2_N_L AUD_LO2_P_R AUD_LO2_N_R
OUT OUT IN
53 53
55
GPIO0 = ANALOG SW CONTROL GPIO1 = HP AMP CONTROL GPIO3 = SPKR AMP SHDN CONTROL
55 53
OUT AUD_GPIO_0 OUT AUD_GPIO_1
2 12 14 15 13
NC TP_AUD_GPIO_2
54
OUT AUD_GPIO_3 IN
GPIO0/DMIC_SDA1 GPIO1/DMIC_SDA2 /SPDIF_OUT2 GPIO2 GPIO3 SENSE_A
LINEOUT_L1+ LINEOUT_L1LINEOUT_R1+ LINEOUT_R1LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-
NC NC
OUT OUT OUT OUT OUT OUT
54 54
FR SPKR AMP. SIG. SOURCE
56
AUD_SENSE_A
=PP3V3_S0_AUDIO
54 54 54
56 55 51 7
IN
CS4206_FLYP CS4206_FLYC
45
LFT. SPKR AMP. SIG. SOURCE RT. SPKR AMP. SIG. SOURCE
C6222
1
C6223
2.2UF
20% 6.3V CERM 402-LF
43 42
C6226
0.1UF
10% 16V X5R 402
2.2UF
20% 6.3V CERM 402-LF 2 2
FLYP FLYC FLYN

CRITICAL
54
MICBIAS
3
16
AUD_CODEC_MICBIAS
OUT
56
CS4206_FLYN
VL_HD VCOM
28
C
1
CS4206_VCOM
C
AUD_LI_P_L AUD_LI_REF AUD_LI_P_R
IN IN IN
52 52 52
VL_IF LINEIN_L+ LINEIN_CLINEIN_R+

21 22 23
75 18
IN IN
HDA_BIT_CLK HDA_SYNC
BITCLK
75 18
R6211
75 18
10
SYNC SDI SDO RESET* MICIN_L+ MICIN_LMICIN_R+ MICIN_R18 17 19 20
OUT
HDA_SDIN0
22
5% 1/16W MF-LF 402
AUD_SDI_R
8 5 11
75 18 75 18
IN IN
NC
HDA_SDOUT HDA_RST_L TP_AUD_SPDIF_IN
AUD_MIC_INP_L AUD_MIC_INN_L AUD_MIC_INP_R AUD_MIC_INN_R
IN IN IN IN
56
EXT MIC CODEC INPUT

56 56 56
BI MIC CODEC INPUT
47
AUD_SPDIF_OUT_CHIP
48
SPDIF_IN SPDIF_OUT
VREF+_ADC
27
CS4206_VREF_ADC
NC NC
R6212
55
OUT
AUD_SPDIF_OUT
39
5% 1/16W MF-LF 402
DMIC_SCL
TP_AUD_DMIC_CLK
DGND THRM_PAD AGND

49 26 7
C6224
1UF
20% 16V TANT 0603-SM
C6225
10UF
20% 16V TANT-POLY 2012-LLP 1
NOSTUFF
R6213
100K
5% 1/16W MF-LF 402
B
56 55 52 51
GND_AUDIO_CODEC
4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456 NOTES ON CODEC I/O
L6200
FERR-220-OHM
55 53 51 7
U6200
TPS71745
6
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=4.5V 1
IN
=PP5V_S3_AUDIO
1 0402
4V5_REG_IN 4V5_REG_EN
IN
EN
SON
OUT
NR/FB
PP4V5_AUDIO_ANALOG 4V5_NR
OUT
6 51
CRITICAL 4 3 5
1
R6200
56 55 51 7
IN
=PP3V3_S0_AUDIO
2.21K
1 1% 1/16W MF-LF 402 2
DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS
GND
1
NC
C6200
1UF
1 10% 10V X5R 402
C6201
1UF
10% 10V X5R 402
C6202
0.1UF
10% 16V X7R-CERM 402
C6203
1UF
10% 10V X5R 402
2 2
XW6200
SM 1 2
GND_AUDIO_CODEC
51 52 55 56
NOSTUFF
R6201
1
0
5% 1/16W MF-LF 402
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: CODEC/REGULATOR
DRAWING NUMBER SIZE
XW6201
SM 1 2
Apple Inc.
051-8563
REVISION
GND_AUDIO_HP_AMP
R 51 53 55
A.13.0
BRANCH PAGE

62 OF 109
SHEET
51 OF 80
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS) FC_HP = 3.6 HZ FC_LP = 43KHZ VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
R6301
55
C6301
2.2UF AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1 2
IN
AUD_LI_L
7.87K 2
1% 1/16W MF-LF 402
AUD_LI_P_L
OUT
51
C
NOSTUFF
1
20% 10V X5R-CERM 402
C6303
820PF
R6302
21.5K CRITICAL
10% 2 50V CERM 402
1% 1/16W MF-LF 2 402
C6302
2.2UF
1 2 20% 10V X5R-CERM 402
55
IN
AUD_LI_GND
1
AUD_LI_REF
OUT
51
R6300
10 CRITICAL
1% 1/16W MF-LF 2 402
C6312
2.2UF
1 2
56 55 51
IN
GND_AUDIO_CODEC
1
NOSTUFF
C6313
820PF
1
20% 10V X5R-CERM 402
10% 50V 2 CERM 402
R6312
21.5K
1% 1/16W MF-LF 2 402
B
C6311
2.2UF
1 2
CRITICAL
R6311
55
IN
AUD_LI_R
7.87K 2
1% 1/16W MF-LF 402
AUD_LI_R_DIV
AUD_LI_P_R
OUT
51
20% 10V X5R-CERM 402
A
PAGE TITLE
A
AUDIO: LINE INPUT FILTER
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

63 OF 109
SHEET
52 OF 80
FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).
D
L6520
FERR-120-OHM-1.5A
D
=PP5V_S3_AUDIO
55 51 7
1 0402-LF
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_PP5V_F

NO STUFF
1
HP/LO AMP APN: 353S1637
C6520
0.1UF
10% 16V X7R-CERM 402
C6521
10UF
20% 6.3V X5R 603
R6521
0
5% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM
12
AUD_LO_AMP_OUTL
OUT
53 55
VDD
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6520
51
AUD_LO_AMP_INL_M
53 53
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM OUTL OUTR C1P C1N

11 10
CRITICAL
AUD_LO_AMP_OUTR
AUD_LO_AMP_INR_M
INL INR
OUT
53 55
U6500
MAX9724A
TQFN
MAX9724_C1P
1
1
CRITICAL
IN
AUD_GPIO_1
0
1
5% 1/16W MF-LF 402
AUD_GPIO_1_R
SHDN* THRM PAD SGND PGND SVSS
C6524
1UF
10% 10V X5R 402
PVSS
53 51
IN
AUD_HP_PORT_L
CRITICAL
MAX9724_C1N
R6523
2.21K
1
13
C6500
0.1UF
10% 16V X7R-CERM 402
R6522
100K
5% 1/16W MF-LF 402
1% 1/16W MF-LF 2 402
R6524
2.21K
MAX9724_SVSS
CRITICAL CRITICAL
1 1
NC
AUD_HP_ZOBEL_L
C
55 53 51
R6500
39
5% 1/16W MF-LF 402
C6522
1UF
10% 10V X5R 402 2
C6523
1UF
10% 10V X5R 402
1% 1/16W MF-LF 2 402
GND_AUDIO_HP_AMP
2
55 53 51
IN
GND_AUDIO_HP_AMP
1
R6510
39
5% 1/16W MF-LF 402
MAX9724 GAIN/FILTER COMPONENTS AV_PB = -1V/V, FC_LPF = 35.2KHZ
NC
AUD_HP_ZOBEL_R
CRITICAL
CRITICAL
1
C6510
0.1UF
10% 16V X7R-CERM 402
C6530
330PF
1 2
53 51
IN
AUD_HP_PORT_R
5% 50V COG 402
R6531
1
13.7K
1% 1/16W MF-LF 402
B
53 51
R6530
AUD_HP_PORT_L
IN
1 1% 1/16W MF-LF 402
AUD_LO_AMP_INL_M
53
13.7K
2
AUD_LO_AMP_OUTL
OUT
53 55
R6532
AUD_HP_PORT_R
53 51
13.7K
1 1% 1/16W MF-LF 402 2
AUD_LO_AMP_INR_M
53
AUD_LO_AMP_OUTR
OUT
53 55
IN
R6533
1
13.7K
1% 1/16W MF-LF 402
CRITICAL
C6531
330PF
1 2
5% 50V COG 402
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: HEADPHONE FILTER

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

65 OF 109
SHEET
53 OF 80
SATELLITE
& SUB TWEETER AMPLIFIER APN:353S2524
SATELLITE
169 HZ < FC < 282 HZ
D
SUB GAIN 80 HZ < FC < 132 HZ 6DB
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
54 7
=PP5V_S3_AUDIO_AMP
C6607
1UF
10%
10V
CRITICAL
B1
B2
C6601
47UF
20% 6.3V TANT1 2012-LLP
CRITICAL
X5R 402
VDD
PVDD
L6610
FERR-1000-OHM
51
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_N_OUT
6 55
C6610
0.0027UF SPKRAMP_INR_N
CRITICAL 1 10%
50V
SSM2315
SSM2315_R_N SSM2315_R_P C1 INA1 IN+ C2 SD* GND
1
U6610
CRITICAL
IN
AUD_LO2_N_R
1 0402
WLCSP OUT+ C3 OUT_ A3
6 55
L6611
FERR-1000-OHM
51
C6611
0.0027UF SPKRAMP_INR_P
1
10%
50V
CERM 402
IN
AUD_LO2_P_R
C
51
CERM 402
R6611
100K
5% 1/16W MF-LF 402
A2 B3
0402
R6610
0
1 5% 1/16W MF-LF 402 2 2
IN
AUD_GPIO_3
54
SPKRAMP_SHDN

54 7
=PP5V_S3_AUDIO_AMP
CRITICAL
1
C6603
100UF
20% 6.3V TANT CASE-AL1
C6608
CRITICAL
1UF
10%
10V
VDD
2
PVDD
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_N_OUT
B1
B2
6 55
L6620
FERR-1000-OHM
51
C6620
0.022UF SPKRAMP_INSUB_N
1
10%
X5R 402
SSM2315
C1 INA1 IN+ C2 SD* GND A2 B3 WLCSP OUT+ C3 OUT_ A3
CRITICAL
U6620
IN
AUD_LO1_N_R
1 0402
2
CRITICAL
SSM2315_SUB_N SSM2315_SUB_P
6 55
L6621
FERR-1000-OHM
51
25V
X7R 0402
C6621
0.022UF
1
10%
25V
IN
AUD_LO1_P_R
1 0402
SPKRAMP_INSUB_P
X7R 0402
54
SPKRAMP_SHDN
B
54 7
B
=PP5V_S3_AUDIO_AMP
CRITICAL
C6609
CRITICAL
C6605
47UF
20% 6.3V TANT1 2012-LLP
1UF
10%
10V
VDD
2
PVDD
2
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT
B1
B2
6 55
L6630
FERR-1000-OHM
51
C6630
0.0027UF SPKRAMP_INL_N
1
10%
X5R 402
SSM2315
C1 INA1 IN+ C2 SD* GND A2 B3 WLCSP OUT+ C3 OUT_ A3
CRITICAL
U6630
IN
AUD_LO2_N_L
1 0402
2
CRITICAL
SSM2315_L_N SSM2315_L_P
6 55
L6631
FERR-1000-OHM
51
50V
CERM 402
C6631
0.0027UF
1
10%
50V
IN
AUD_LO2_P_L
1 0402
SPKRAMP_INL_P
CERM 402
54
SPKRAMP_SHDN
SYNC_MASTER=AUDIO
PAGE TITLE
AUDI0: SPEAKER AMP

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

66 OF 109
SHEET
54 OF 80
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

AUD_SPDIF_OUT
IN
51
L6701
FERR-1000-OHM
1
56 51 7
=PP3V3_S0_AUDIO
0402
HS_MIC_HI
OUT
56
L6702
FERR-1000-OHM
D
APN:514-0671 J6700
SPDIF-TXRX-K24
F-RT-TH CRITICAL
HS_MIC_LO
OUT
56
0402
D
XW6702
SM
2 AUD_HP_PORT_REF
OUT
51
AUD_CONNJ1_MIC
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
CRITICAL
L6703
FERR-120-OHM-1.5A
1 0402-LF 2
XW6700
SM 1 2
GND_AUDIO_HP_AMP
51 53
AUD_CONNJ1_SLEEVE
6 5 2 1 3 4
AUD_CONN_GND
MIC DETECT SWITCH LEFT RIGHT GND
XW6701
SM 1 2
AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_TIPDET AUD_CONNJ1_TIP AUD_CONNJ1_RING
AUD_LI_GND
52
CRITICAL
L6704
FERR-220-OHM
1 0402 2
(AUD_CONN_GND)
AUD_CONN_L
BI
55
55
AUDIO
A - VIN B - VCC C - GND
7 8 9
CRITICAL
L6705
FERR-220-OHM
1 0402 2
AUD_CONN_R
BI
55
OPERATING VOLTAGE 3.3
POF
1 10
R6700 C6700
1UF
10% 2
6.3V
CRITICAL
SHELL
SHIELD PINS
CRITICAL
10K
5% 1/16W MF-LF 402
AUD_J1_SLEEVEDET_R
2
OUT
56
11 12 13
DZ6705
6.8V-100PF
402 CRITICAL
2 2
DZ6703
6.8V-100PF
402 CRITICAL
1 1 2
MIC CONNECTOR
APN:518S0520
CRITICAL
CERM 402
CRITICAL
J6701
78171-0003
M-RT-SM 4
DZ6701
6.8V-100PF
402
1 1
DZ6704
6.8V-100PF
402
R6701
4.7
1 5% 1/16W MF-LF 402 2
DZ6700
6.8V-100PF
402 1
1
AUD_J1_TIPDET_R
OUT
56
C6701
100PF
5%
50V
56 6 56 6 56 6
CERM 402
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI
1 2 3
GND_CHASSIS_AUDIO_JACK
VOLTAGE=0V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM
5
CHASSIS GND STITCHES
XW6710
SM 1 2
XW6711
SM 1 2
SPEAKER CONNECTOR
APN:518S0519
54 6 54 6
CRITICAL
J6702
78171-0002
M-RT-SM 3
R6760
0
1 5% 1/16W MF-LF 402 2
IN IN
SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT
1 2
4
54 6
53 51 7
=PP5V_S3_AUDIO
IN
SPKRAMP_SUB_P_OUT
NO STUFF 1 C6760
33PF
2 5% 50V CERM 402
B
AUD_LO_AMP_OUTL
53
CRITICAL
R6716
OUT
1
0
5% 1/16W MF-LF 402
AUD_LO_AMP_OUTL_SWITCH
2
C6710
1UF
10% 10V X5R 402
APN: 353S2803
1
J6703
78171-0004
M-RT-SM 5
MIN_LINE_WIDTH=0.2MM
NO STUFF C6761
33PF
5% 50V CERM 402
A3
MIN_NECK_WIDTH=0.15MM
AUD_CONN_L
BI
1
55
VCC
2
54 6 54 6
1 2 3
R6717
AUD_LO_AMP_OUTR
53
OUT
0
5% 1/16W MF-LF 402
U6700
AUD_LO_AMP_OUTR_SWITCH
R6712
24K
5% 1/16W MF-LF 402
IN IN
C4 NC1 C1 NC2 A4 NO1 A1 NO2
MAX14560EWC+
WLP
COM1 B4
2
SPKRAMP_SUB_N_OUT SPKRAMP_R_P_OUT
1
NO STUFF C6762
33PF
5% 50V CERM 402
COM2 B1
CRITICAL MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
2
R6718
AUD_LI_L
52
IN
0
5% 1/16W MF-LF 402
AUD_LI_L_SWITCH
SWITCH_CP
C2 CB A2 NEG
EN* B2
AUD_CONN_R
BI
55
NO STUFF C6763
33PF
5% 50V CERM 402
APN:518S0521
R6719
B3
AUD_LI_R
52
GND C3
AUD_LI_R_SWITCH
0
1 5% 1/16W MF-LF 402 2
IN
C6711
0.0033UF
10% 50V CERM 402
54 6
IN
SPKRAMP_R_N_OUT
R6713
24K
5% 1/16W MF-LF 402
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
2 2
AUD_GPIO_0
51
IN
A
R6715
AUD_CONN_GND
55
R6721
100K
5% 1/16W MF-LF 402
ANALOG AUDIO IO SWITCH

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER SIZE
0
5% 1/16W MF-LF 402
AUD_SWITCH_GND
VOLTAGE=0V
Apple Inc.
R
051-8563
REVISION
GND STUFFING OPTIONS FOR CMOS SWITCH

56 52 51
NOSTUFF
A.13.0
BRANCH PAGE
GND_AUDIO_CODEC
R6714 1
5% 1/16W MF-LF 402
R6727
1

0
5% 1/16W MF-LF 402
67 OF 109
SHEET
55 OF 80
8
CODEC OUTPUT SIGNAL PATHS
FUNCTION HP/LINE OUT LINE IN SATELLITES SUB SPDIF OUT VOLUME 0X02 (2) 0X05 (5) 0X04 (4) 0X03 (3) N/A
CONVERTER 0X02 (2) 0X05 (5) 0X04 (4) 0X03 (03) 0X08 (8)
PIN COMPLEX 0X09 (9,A) 0X0C (12) 0X0B (11) 0X0A (10) 0X10 (16)
MUTE CONTROL GPIO_0 AND GPIO_1 GPIO_0 AND GPIO_1 GPIO_3 GPIO_3 N/A
DET ASSIGNMENT 0X09 (A) 0X09 (A)AND UI ELEMENT N/A N/A 0X0D (B)
56 55 51 7
PORT B LEFT(HEADSET MIC) HP=80HZ, LP=8.82KHZ

MIKEY
L6880
FERR-1000-OHM =PP3V3_S0_AUDIO
1 2
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V PP3V3_S0_HS_RX
0402
DRC MIKEY
NOSTUFF
CODEC INPUT SIGNAL PATHS

1
FUNCTION BUILT-IN MIC HEADSET MIC
CONVERTER 0X06 (6) 0X06 (6)
PIN COMPLEX 0X0D (13,B,RIGHT) 0X0D (13,V22,B,LEFT)
VREF MIC_BIAS (80%) MIKEY
DET ASSIGNMENT N/A MIKEY
R6885
10K
CRITICAL MIKEY
APN:353S2256
1
5% 1/16W MF-LF 2 402

PULLUPS ON MCP PAGE
C6880
1UF
10%
6.3V
D
MIKEY 1 2 10 HS_MIC_BIAS MIKEY HS_SW_DET
1
AVDD
2
CERM 402
U6880
CD3275
DRC
42
IN BI OUT IN
=I2C_MIKEY_SCL =I2C_MIKEY_SDA AUD_I2C_INT_L AUD_IPHS_SWITCH_EN NOSTUFF
6 5 7 8
SCL SDA INT*
MICBIAS DETECT BYPASS
42
CRITICAL
18
HS_RX_BP
C6882
2.2UF
20% 6.3V TANT 402
PORT A DETECT (HEADPHONES)
PORT B DETECT(SPDIF DELEGATE)
18
ENABLE GND
4 9
THM
11 MIKEY
1
R6880
51
OUT AUD_SENSE_A
56 PP3V3_S0_AUDIO_F
1 1
100K
5% 1/16W MF-LF
GND_AUDIO_CODEC MIKEY MIKEY

1 1
51 52 55 56
C6881
0.01UF
2
R6806
39.2K
1% 1/16W MF-LF 402
R6805
20.0K
1% 1/16W MF-LF 402
402
16V 402
10% CERM
R6881
1K
1% 1/16W
R6882
2.2K
5% 1/16W MF-LF 402
APN:376S0613
R6801
300K
5% 1/16W MF-LF 402
GND_AUDIO_CODEC
56 55 52 51
AUD_OUTJACK_INSERT_L
2
MIKEY CRITICAL
MF-LF 402
AUD_PORTA_DET_L
NC
AUD_PORTB_DET_L
NC
Q6800
SSM6N15FEAPE
SOT563
C6883
0.1UF
51
MIKEY
R6884
2.2K HS_MIC_HI_RC MIKEY
1
1 2
Q6801
SSM6N15FEAPE
SOT563
Q6801
SSM6N15FEAPE
SOT563
OUT AUD_MIC_INP_L
MIKEY CRITICAL
HS_MIC_HI
IN
55
R6802
47K
56 55
5% 1/16W
IN
AUD_J1_TIPDET_R
1 5% 1/16W MF-LF 402
AUD_J1_DET_RC
5 1
C6886
4 5
0.1UF
10% 25V X5R 402
R6883
100K
5% 1/16W MF-LF 402
MIKEY
MF-LF 402
C6884
0.0082UF
2 10% X7R 25V 402
MIKEY
C6801
0.1UF
2 20% CERM 10V 402
2 4
51
1
OUT AUD_MIC_INN_L
C6885
27PF
2 5% CERM 50V 402
C
56 55 52 51 GND_AUDIO_CODEC 56 PP3V3_S0_AUDIO_F
1 1
10% 25V X5R 402
CRITICAL
XW6880
SM 1 2
CRITICAL
C
IN
55
56 55 52 51 GND_AUDIO_CODEC
HS_MIC_LO
R6803
220K
2 5% 1/16W MF-LF 402
AUD_J1_SLEEVEDET_INV
R6804
220K
5% 1/16W MF-LF 402
Q6800
SSM6N15FEAPE
SOT563
56 55 AUD_J1_SLEEVEDET_R
PORT B RIGHT(BUILT-IN MIC)

R6850 R6851
2.4K
2
1% 1/16W MF-LF 402
56 55
IN
AUD_J1_SLEEVEDET_R
1
C6802
0.01UF
10% 16V CERM 402
100
1
51
IN
AUD_CODEC_MICBIAS
MIC_BIAS_FILT CRITICAL
1 1% 1/16W MF 402-1
C6852
2.2UF
20% 6.3V TANT 402
CRITICAL
C6850
0.1UF
51
L6850
FERR-1000-OHM BI_MIC_HI_F
1 2
OUT AUD_MIC_INP_R
CRITICAL
BI_MIC_HI
IN
6 55
0402 10% 25V X5R 402 1
C6851
0.1UF
51
R6852
100K
5% 1/16W MF-LF 402
CRITICAL
CRITICAL
OUT AUD_MIC_INN_R
C6853
0.001UF
50V 402 10% CERM 2 2
C6854
27PF
5% CERM 50V 402
B
10% 25V X5R 402
L6851
FERR-1000-OHM
1 2
R6853
2.4K
1
1% 1/16W MF 402-1
BI_MIC_LO_F
2
BI_MIC_LO
B
IN
6 55
56 PP3V3_S0_AUDIO_F
0402
XW6851
SM
VOLTAGE=3.3V
L6862
FERR-1000-OHM
56 55 51 7
EXTRACTION NOTIFICATION CKT
BI_MIC_SHIELD
IN
6 55
HP=80HZ
2
IN
=PP3V3_S0_AUDIO
1
0402
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

1
R6864
220K
5% 1/16W MF-LF 402 1
C6861
0.1UF
10V 402 20% CERM
R6865
100K
5% 1/16W MF-LF 402
Q6802
SSM6N15FEAPE
SOT563
2 6
R6861
0
1 5% 1/16W MF-LF 402 2
AUD_PERPH_DET_R
AUD_IP_PERIPHERAL_DET
OUT
16
Q6802
1
SSM6N15FEAPE
SOT563
R6860
56 55 AUD_J1_TIPDET_R
15K
5% 1/16W MF-LF 402
TIPDET_FILT
2 5 1
A
C6860
0.1UF
20% 10V CERM 402
AUD_J1_TIPDET_INV
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: JACK TRANSLATORS

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
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BRANCH PAGE

68 OF 109
SHEET
56 OF 80
8
MagSafe DC Power Jack
CRITICAL
J6900
78048-0573
M-RT-SM 1 2 3
6 PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V 1
CRITICAL
F6905
6AMP-24V
1 2
=PP18V5_DCIN_CONN
1206-1
4 5
6 ADAPTER_SENSE
2
C6905
0.01UF
20% 50V CERM 603
=PP3V42_G3H_ONEWIRE
1
C6908
0.1UF
20% 10V CERM 402
PLACEMENT_NOTE=PLACE NEAR U6901
R6929
2
SMC_BC_ACOK_VCC
5
SOT665 TC7SZ08AFEAPE
518S0656
R6900
100K
5% 1/16W MF-LF 402
2.0K NOSTUFF
402 MF-LF 1/16W 5%
VCC
A
4
U6901
B
3 1
U6900
1
MAX9940
SC70-5 4
SMC_BC_ACOK
8 39 40
39
BI
SYS_ONEWIRE
INT
EXT 5
GND
2
NC
NC 3
1-Wire OverVoltage Protection
3.425V "G3Hot" Supply
C
R6905
1
58
Supply needs to guarantee 3.31V delivered to SMC VRef generator
C
BIL CONNECTOR
C6994
1
PPDCIN_G3H_OR_PBUS
1 5% 1/8W MF-LF 805
PPDCIN_G3H_OR_PBUS_R
P3V42G3H_BOOST
DIDT=TRUE
C6990
10UF
10% 25V X5R 805
516S0523
CRITICAL CRITICAL
VIN
2
BOOST
0.22uF
20% 6.3V X5R 402 2
J6955
CPB6312-0101F
F-ST-SM
U6990
LT3470A
8
L6995
33UH
1 CDPH4D19FHF-SM 2
=PP3V42_G3H_REG
14
13
SHDN* NC
DFN CRITICAL
SW
BIAS
4 2
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE
Vout = 3.425V
2 1 3 5 7 9 11
7
NC
250MA MAX OUTPUT <Ra>

1
GND
5
FB THRM PAD
9
57 42
BI BI
=SMBUS_BATT_SDA =SMBUS_BATT_SCL
4 6 8 10
=PP3V42_G3H_BATT
6 SMC_LID_R
R6961
100
C6995
22pF
5% 50V CERM 402
R6995
348K
1% 1/16W MF-LF 402
(Switcher limit)
TO SMC
CRITICAL
2 1
57 42 40 39 6
1
1/16W 5% MF-LF
2
402
SMC_LID
39 40 47
SMC_BIL_BUTTON_L
C6999
22UF
20% 6.3V CERM 805
C6952
47PF
1 1 5% 50V CERM 402
NC
12
NC
C6951
1
C6955
0.001UF
10% 50V CERM 402
P3V42G3H_FB
16
2
15
0.1UF
10% 25V X5R 402 2
<Rb>
R6996
200K
1% 1/16W MF-LF 402 1
C6954
0.001UF
10% 50V CERM 402
C6953
47PF
5% 50V CERM 402
Vout = 1.25V * (1 + Ra / Rb)
518-0359
CRITICAL
J6950
BAT-K24
M-RT-TH
BATTERY CONNECTOR
P1 P2 P3 P4 P5 P6 P7 P8 P9 SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 =SMBUS_BATT_SCL
6 SYS_DETECT_L 42 57
=SMBUS_BATT_SDA CRITICAL
58 6 PPVBAT_G3H_CONN
42 57
D6950
1 2
C6950
0.1UF
10% 25V X5R 402
C6960
1UF
10% 25V X5R 603-1
RCLAMP2402B
SC-75
R6950
10K
5% 1/16W MF-LF 402
SYNC_MASTER=K24_MLB
PAGE TITLE
DC-In & Battery Connectors

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

69 OF 109
SHEET
57 OF 80
6
This node is powered through body diodes: * DCIN through Q7080. * PBUS through Q7085, Charger TOP FETs and Q7055. PPDCIN_G3H_OR_PBUS
57
Reverse-Current Protection
FROM ADAPTER
7
Inrush Limiter
=PPDCIN_S5_CHGR
SI7149DPCRITICAL
S
3
Q7080 SO-8
SI7149DP
S
3
Q7085 CRITICAL SO-8

PPDCIN_G3H_INRUSH
5% 1/16W MF-LF 402
0.1UF
10% 25V X5R 402
2 2
1% 1/16W MF-LF 402
CHGR_SGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm 1
100K
470K
R7080
C7085
R7085
CHGR_AGATE_DIV
R7081
62K
5% 1/16W MF-LF 402
R7086 1
332K
1% 1/16W MF-LF 402
CRITICAL
D7005
BAT30CWFILM
SOT-323 1
R7005
3
(CHGR_SGATE) MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm (CHGR_DCIN)
(CHGR_AGATE) MIN_LINE_WIDTH=0.3
mm MIN_NECK_WIDTH=0.3 mm
CHGR_DCIN_D_R
20
5% 1/16W MF-LF 402
R7021
10
1 5% 1/16W MF-LF 402 2
ACIN pin threshold is 3.2V, +/- 50mV Divider sets ACIN threshold at 13.55V Input impedance of ~40K meets sparkitecture requirements 30mA max load PP5V1_CHGR_VDD
65 7
CRITICAL
78
C7020
0.047UF
10% 10V CERM 402
CHGR_CSI_R_P
3 1
R7020
0.020
0.5% 1W MF-LF 0612
R7022
1
78
CHGR_CSI_R_N
4 2
10
5% 1/16W MF-LF 402
R7001
1
PPDCIN_G3H_CHGR PP5V1_CHGR_VDDP
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
4.7
5% 1/16W MF-LF 402
CRITICAL
1
CRITICAL
1
=PP3V42_G3H_CHGR
C7030
22UF
20% 25V POLY-TANT CASE-D2-SM
C7031
22UF
C7035
1UF
10% 25V X5R 603-1
C7036
1UF
10% 25V X5R 603-1
C7037
0.001UF
10% 50V X7R 402
C7001
1UF
10% 10V X5R 402
C7022
0.1UF
10% 25V X5R 402
C7021
0.1UF
2 10% 25V X5R 402
R7010
30.1K
C7002
1UF
10% 10V X5R 402
1 1
1% 1/16W MF-LF 2 402
19
GND_CHGR_AGND
100K
58
R7000 R7012 1
1K
1% 1/16W MF-LF 402 2
41 40 39
5% 1/16W MF-LF 2 402
20
NO STUFF
R7002
VDD 12 13 11 10 4 6
VDDP DCIN 2 SGATE AGATE CSIP CSIN 26 1 28 78 27 78 CHGR_DCIN CHGR_SGATE CHGR_AGATE CHGR_CSI_P CHGR_CSI_N CHGR_BOOT CHGR_UGATE CHGR_PHASE CHGR_LGATE
GATE_NODE=TRUE DIDT=TRUE PLACE_NEAR=U7000.25:2mm
IN
SMC_RESET_L
0
1 2
ISL6259
5% 1/16W MF-LF 402
42 42 65
IN BI IN
CHGR_RST_L =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA CHGR_VFRQ CHGR_CELL CHGR_ACIN CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N
CRITICAL VHST SMB_RST_N SCL U7000 TQFN SDA VFRQ CELL
D
4
1
CRITICAL
Max Current = 8A f = 400 kHz
C7025
0.22UF
10% 10V CERM 402
Q7030
RJK0332DPB-01
LFPAK-SM
S
1 2 3
CRITICAL
CRITICAL
Float CELL for 1S NO STUFF 1
3 ACIN 5 ICOMP 7 VCOMP 8 VNEG 18 CSOP 17 CSON

(AGND)
BOOT 25 UGATE 24 PHASE 23 LGATE 21 BGATE AMON 36V/V BMON (OD) ACOK
20V/V
DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE
4.7UH-9.5A
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
DIDT=TRUE
L7030
F7040
8AMP-24V
1 2
TO SYSTEM
=PPBUS_G3H
7
R7013
1K
3% TOLERANCE
IHLP4040DZ-SM
1206
1% 1/16W MF-LF 402 2
R7015
220K
78 78
THRM_PAD
PGND
R7011
9.31K
5% 1/16W MF-LF 2 402
C7050
1UF
10% 16V X5R 402
16 9 15 14
CHGR_BGATE CHGR_AMON CHGR_BMON =CHGR_ACOK
NO STUFF
OUT OUT OUT
44 44 8
R7039 1
180
5% 1/10W MF-LF 603
PPVBAT_G3H_CHGR_REG
2
1% 1/16W MF-LF 2 402
CHGR_VCOMP_R
2
CRITICAL
1
C7040
22UF
C7045
0.001UF
10% 50V X7R 402
29
22
C7015
470PF
10% 50V CERM 402
353S2929
4
CRITICAL
CHGR_PHASE_RC
DIDT=TRUE
Q7035
2
RJK0305DPB
LFPAK-HF 1
NO STUFF
CRITICAL
C7039
470PF
10% 50V CERM 402
R7050
0.01
0.5% 1W MF 0612-1
Q7055
SI7137DP
SO-8
B
R7016 1
3.01K
1% 1/16W MF-LF 402
TO/FROM BATTERY
D PPVBAT_G3H_CONN
5
6 57
SM 1 2 2
(GND)
XW7000
PPVBAT_G3H_CHGR_R
CHGR_VNEG_R
1
C7016
470PF
10% 50V CERM 402
(CHGR_CSO_P) (CHGR_CSO_N) (PPVBAT_G3H_CHGR_R)
R7051 R7052
2.2 0
78 44
CHGR_CSO_R_P
1/16W MF-LF 402
5% 1 2
78 44
CHGR_CSO_R_N
1/16W MF-LF 402
5%
(PPVBAT_G3H_CHGR_R) (CHGR_BGATE)
C7042
0.033UF
10% 16V X5R 402
C7011
0.01UF
10% 16V CERM 402
C7000
1UF
10% 10V X5R 402-1
C7005
0.22UF
20% 25V X5R 603
C7026
0.001UF
10% 50V CERM 402
2
58
* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
GND_CHGR_AGND
SYNC_MASTER=T27_MLB
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
70 OF 109
SHEET
58 OF 80
5V_S3/3.3V_S5 POWER SUPPLY

D
VOUT = (2 * RA / RB) + 2 VOUT = (2 * RC / RD) + 2
<RA>
R7267
ROUTING NOTE:
<RB>
15.0K
1% 1/16W MF-LF 402
1 2
<RD>
R7268
10K
1% 1/16W MF-LF 402
1 2
<RC>
R7269
10K
1% 1/16W MF-LF 402
1 2
R7270
6.49K
1% 1/16W MF-LF 402
1 2
ROUTING NOTE:
XW7203
Place XW7203 by Pin1 OF L7260.
2
XW7204
SM
3V3S5_VFB_R7270
2 1
SM
5V_S3_VFB_XW7203
1
Place XW7204 by Pin 2 of L7220.
59
GND_5V3V3S5_SGND
XW7205
SM
65
ROUTING NOTE: Place XW7205 by C7252.
=P5V3V3_REG_EN
C
59 7
=PPVIN_S3_5VS3
ROUTING NOTE: Place XW7202 by C7292.
C
R7273
1
XW7202
SM
2 1
C7272
1UF
100K
5% 1/16W MF-LF 402 2
10% 2 25V X5R 603-1
59 7
=PPVIN_S3_5VS3
5VS3_3V3S5_VREF
5V3V3S5_REG3
=PPVIN_S5_3V3S5
1
CRITICAL
1
C7270
1UF
20% 10V 603
C7282
0.001UF
20% 50V CERM 402
C7280
39UF-0.027OHM
20% 16V POLY B1A-SM
C7281
1UF
16
CRITICAL
1
10% 25V 2 X5R 603-1
C7271
0.22UF
4
2 CERM
C7241
1UF
10% 25V X5R 603-1
C7240
39UF-0.027OHM
20% 16V POLY B1A-SM
C7242
0.001UF
20% 50V CERM 402
5 D G 4
C7260
0.1UF
10% 16V X5R 402
Q7260
SIS424DN
PWRPK-1212-8-SM
TONSEL VBST1 DRVH1 LL1 DRVL1 VO1 VFB1 ENTRIP1

CRITICAL
VREG5
17 9
PP5V_S5_LDO
R7220
402 5% 1/16W MF-LF
C7220 10% 16V

0.1UF
X5R
CRITICAL
10% 10V 2 CERM 402
VIN 14 SKIPSEL
VREF VREG3
8
5V_S3_VBST
DIDT=TRUE
22 21 20 19 24 2 1
U7200
QFN TPS51125
VBST2 DRVH2 LL2 DRVL2 VO2 VFB2
5V_S3_DRVH 5V_S3_LL 5V_S3_DRVL 5V_S3_VO1
10 3V3S5_DRVH 11 3V3S5_LL 12 3V3S5DRVL 7 3V3S5VO2
DIDT=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
3V3S5_VBST
2 3V3S5_VBST_R 2 DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
1 402
D1 1 G1 S1/D2
Q7220
WPAK 7
RJK0384DPA
CRITICAL
DIDT=TRUE
L7260
3 2 1
2
DIDT=TRUE
L7220
6 G2 S2 3 4 5
1 2
PWM FREQ. = 375 KHZ MAX CURRENT = 9.1A
MAX CURRENT = 13.3A PWM FREQ. = 300 KHZ

=PP5V_S3_REG
7
DIDT=TRUE
DIDT=TRUE
CRITICAL
4.7UH-13A-15MOHM
PCMB104E4R7-SM
5
5V_S3_VFB
5 3V3S5_VFB 6 18 23 3V3S5_ENTRIP NC
D
5V_S3_ENTRIP
CRITICAL 4.7UH-10A
PCMC063T-SM
B
=PP3V3_S5_REG CRITICAL
1
7
CRITICAL
ENTRIP2 VCLK
Q7261
1
C7293
0.001UF
20% 50V CERM 402
C7290
10UF
SIS426DN C7291
220UF
20% 6.3V ELEC D1A-SM
PWRPK-12128
G S
3 2 1
DIDT=TRUE
20% 2 6.3V X5R 603
R7271
86.6K
1% 1/16W MF-LF 402
PGOOD EN0 GND THRM_PAD

15 25
1
13 5V3V3_REG_EN
C7273
10UF
R7272
75K
1% 1/16W MF-LF 402 2
C7251
150UF
20% 6.3V POLY B1A-SM
C7250
10UF
20% 603
C7253
0.001UF
20% 50V CERM 402
2 6.3V X5R
CRITICAL
20% 6.3V 2 X5R 603
59
GND_5V3V3S5_SGND
VOLTAGE=0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
XW7201 SM
PLACE_NEAR=U7200.25:1 MM
P5V3V3_PGOOD
65
Q7221
SSM6N15FEAPE
SOT563
ROUTING NOTE:
=P5VS3_EN_L
65
IN
Q7221
D
3
Place XW7201 between Pin 15 and Pin 25 of U7200.
SSM6N15FEAPE
SOT563
A
65
=P3V3S5_EN_L
IN
SYNC_MASTER=K24_MLB
PAGE TITLE
5V/3.3V SUPPLY
DRAWING NUMBER SIZE
Apple Inc.
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

NOTE: DONT SYNC THIS PAGE FROM T27
72 OF 109
SHEET
59 OF 80
=PPVIN_S3_DDRREG
=PPVIN_S0_DDRREG_LDO
1
CRITICAL
CRITICAL
1 2
C7330
39UF-0.027OHM
20% 16V POLY B1A-SM
C7331
39UF-0.027OHM
20% 16V POLY B1A-SM
C7332
1UF
C7333
0.001UF
C7355 1
10UF
20% 6.3V X5R 2 603
10% 25V 2 X5R 603-1
10% 50V 2 X7R 402
=PP5V_S3_DDRREG
R7305
1
4.7
PP5V_S3_DDRREG_V5FILT
5% 1/16W MF-LF 402

7
R73101
10K
14 23
1% 1/16W MF-LF 402 2
5 D 4 G
=PP3V3_S3_PDCISENS
CRITICAL
R7380
100K
4.7UF
5% 1/16W MF-LF 402 2
10% 10V 2 X5R 805
10% 10V 2 X5R 402-1
1UF
15
C7300
C7305
Q7330
SIS424DN
PWRPK-1212-8-SM
V5IN 6 COMP
V5FILT
VLDOIN VDDQSNS 8
(DDRREG_DRVH) DDRREG_VDDQSNS
S 1 2 3
CRITICAL
65 65
CRITICAL 1.0UH-13A-5.6MOHM
1 PCMB065T-SM 2
IN IN OUT
=DDRVTT_EN =DDRREG_EN DDRREG_PGOOD 10mA max load Vout = VDDQSNS/2
10 S3 VTT Enable 11 S5 VDDQ/VTTREF Enable 13 PGOOD VDDQ PGOOD
MODE 4 VBST 22 DRVH 21 LL 20 DRVL 19
R7325
DDRREG_VBST
DIDT=TRUE
MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm
C7325
0.1UF
1 2
L7330
U7300
QFN
DDRREG_VBST_R
28 7
=PPVTT_S3_DDR_BUF =PPVTT_S0_DDR_LDO
TPS51116
5 VTTREF 24 VTT SYM (2 OF 2)
DDRREG_DRVH
GATE_NODE=TRUE DIDT=TRUE
5% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm 10% 16V DIDT=TRUE X5R

402
CRITICAL
1
=PPDDR_S3_REG 7 Vout = 1.501V / 1.352V 19A MAX OUTPUT

1
C7340
330UF
C7346
0.001UF f = 400 kHz
DDRREG_LL
SWITCH_NODE=TRUE DIDT=TRUE
(DDRREG_LL)
XW7360 SM
1 2
Vout = VTTREF DDRREG_VTTSNS

NC NC
2 VTTSNS 7 NC0 12 NC1 VTTGND 1 THRM_PAD GND 25 3
Q7335
4
20% 2 2.5V TANT CASE-B2-SM
10% 2 50V X7R 402
DDRREG_DRVL
GATE_NODE=TRUE DIDT=TRUE
(DDRREG_DRVL)
SIS426DN
G S
1 2 3 PWRPK-12128
CRITICAL
PLACE_NEAR=L7330.2:1 MM
CS 16 VDDQSET 9 PGND CS_GND 18 17

28
DDRREG_CS DDRREG_FB
C7341 1
330UF
20% 2.5V 2 TANT CASE-B2-SM
C7345
10UF
CRITICAL
CRITICAL
CRITICAL
1
C7360
22UF
C7361
22UF
20% 6.3V X5R 2 603
XW7345 SM
1
20% 6.3V X5R-CERM 2 603
20% 6.3V 2 X5R-CERM 603
XW7335 SM
DDRREG_CSGND (DDRREG_CSGND)
1 2
R7320
15.0K
C7320
0.001UF LVDDR3:YES
XW7300 SM
0.033UF
(DDRREG_VDDQSNS)
1% 1/16W MF-LF 2 402
C7350
(DDRREG_FB)
<Ra>
LVDDR3:YES
10% 50V 2 X7R 402
10% 16V 2 X5R 402
B
GND_DDRREG_SGND
Vout = 0.75V * (1 + Ra / Req) SEL_1V5=0: Req = Rb SEL_1V5=1: Req = Rb || Rc

LVDDR3:YES
<Rc>
R7322
75K
R73211
18.7K
1% 1/16W MF-LF 402 2
LVDDR3:YES
1% 1/16W MF-LF 2 402
<Rb>
DDRREG_P1V5_L
D 3
Q7322
SSM3K15FV
SOD-VESM-HF
1
18
S 2
IN
MCP_MEM_VDD_SEL_1V5
(GND_DDRREG_SGND)
Use LVDDR3 for 1.5V/1.35V support or LVDDR3_NOT for fixed 1.5V operation.
RES,15K,1%,1/16W,MF-LF,0402
REFERENCE DES R7321
CRITICAL
BOM OPTION LVDDR3:NO
SYNC_MASTER=T27_MLB
PAGE TITLE
1.5V/1.35V LVDDR3 Supply

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

NOTE: DONT SYNC THIS PAGE FROM T27. C7330 AND C7331 IS CHANGED TO OSCON CAPS
73 OF 109
SHEET
60 OF 80
=PP5V_S0_CPU_IMVP
1 2 1
61 7
=PPVIN_S5_CPU_IMVP
CRITICAL
PP5V_S0_IMVP6_VDD
CRITICAL
C7426
1UF
10% 16V X5R 402
R7412
10

1
5
DPRSLPVR DPRSTP* PSI* OPERATION MODE 2-PHASE CCM 1-PHASE CCM
DIDT=TRUE
C7409
D
CRITICAL
68UF
C7417
68UF
20% 16V POLY-TANT CASE-D2E-SM
C7418
1UF
10% 25V X5R 603-1
C7419
0.001UF
10% 50V CERM 402
D
61 7
5% 1/16W MF-LF 402
C7435
4.7UF
10% 10V 2 X5R 805

2
0 0 1 1
1 1 0 0
1 2
1 0 1 0
IMVP6_BOOT1_RC
DIDT=TRUE
Q7400
RJK0365DPA-02
WPAK
PWM FREQ. = 300 KHZ MAX CURRENT = 65.2A

LOAD LINE SLOPE = -2.1 MV/A
D
7
=PPVIN_S5_CPU_IMVP
PPVIN_S5_IMVP6_VIN
1
S
1-PHASE DCM
DIDT=TRUE
R7420
10
C7496
1UF
10% 16V X5R 402
VOLTAGE=12.6V
1 2 3
0.36UH-26A-1.05MOHM
(IMVP6_PHASE1)
1 MPCG1040-SM 2
L7400
=PPVCORE_S0_CPU_REG
72 13
IN
PM_DPRSLPVR
5% 1/16W MF-LF 402
1-PHASE DCM
VOLTAGE=3.3V
7
5 D
DIDT=TRUE
CRITICAL
CRITICAL
=PP3V3_S0_IMVP
PP3V3_S0_IMVP6_3V3
C7430 R7421
10
5% 1/16W MF-LF 402
61
R7424
1
Q7401
4 G
PLACE_NEAR=L7400.1:1MM SM 2 1
1
C7420
0.001UF
10% 50V CERM 402
1UF
10% 10V X5R 402
R7447
2.0K
0
5% 1/16W MF-LF 402 1 20 22 31 2 IMVP6_BOOT2_RC
DIDT=TRUE
RJK0208DPA
WPAK
XW7411
2
XW7410
IMVP_VO1 IMVP_VSUM1
2 402 MF-LF 1/16W 5% 1
1 2 1 2
GND_IMVP6_SGND
CPU_NTC:YES CPU_NTC:YES
5% 1/16W MF-LF 2 402
R7427
4.02K
1% 1/16W MF-LF 402 1 2
VIN
72 10
VDD
PVCC
DIDT=TRUE
R7426
470K
402
1
R7425
0
5% 1/16W MF-LF 402 1
C7427
0.1UF
10% 25V 2 X5R 402
C7415
1
1 2 3
(THIS NET SHOULD CONNECT TO U7400.33 WITH MIN LOOP AREA)
0.1UF
10% 25V
CPU_VID<6> CPU_VID<5> CPU_VID<4> CPU_VID<3> CPU_VID<2> CPU_VID<1> CPU_VID<0> CPU_DPRSTP_L CPU_PSI_L
43 42 41 40 39 38 37
VID6
BOOT1 36
61 61
IMVP6_BOOT1 IMVP6_BOOT2
DIDT=TRUE
R7404
CRITICAL
72 10
CRITICAL
VID5 VID4 VID3 VID2 VID1 VID0
U7400
QFN
BOOT2
26
2
1
72 10 72 10
X5R 402
ISL9504BCRZ
UGATE1 PHASE1 LGATE1 PGND1 ISEN1
35 34 32 33 24
61
IMVP6_UGATE1 IMVP6_PHASE1 IMVP6_LGATE1 (GND) (KEEP THIS NET AS SHORT AS POSSIBLE)
CPU_NTC:YES
R7445
499
R7400
10K
1% 1/16W MF-LF 402
C7403
0.22UF
10% 10V CERM 402
72 10 72 10 72 10
61
C7410
0.01uF
10% 16V CERM 402
ERT-J0EV474J
IMVP6_NTC_R
1% 1/16W MF-LF 2 402

72 13 9
61
46 45 2 3
IN
DPRSTP* DPRSLPVR PSI* IMON
72
IMVP_DPRSLPVR
9
61
IMVP6_ISEN1 IMVP6_UGATE2
61 7
(IMVP6_ISEN1)
IN OUT
C
=PPVIN_S5_CPU_IMVP
R7406
CPU_NTC:YES 0
44 IMVP6_IMON
10 9 7 12 11
=PP1V05_S0_CPU
UGATE2 27 PHASE2
28 30 29
61
CPU_PROCHOT_L
40 13 9 72
5% 1/16W MF-LF 402 2
R7499 1
68
CPU_NTC:YES
5% 1/16W MF-LF 402
48
61
IMVP6_PHASE2 IMVP6_LGATE2 (GND) IMVP6_ISEN2 IMVP6_VSUM IMVP6_OCSET (KEEP THIS NET AS SHORT AS POSSIBLE)
3V3 CLK_EN* VR_ON PGND2 PGOOD VR_TT* NTC VSUM OCSET 8 VO

19
61 61 61 61
CRITICAL
CRITICAL
5 D
CRITICAL
(NC)
FROM SMC
2
39 24
47 44 1 5 6
LGATE2
61
Q7402
RJK0365DPA-02
WPAK
DIDT=TRUE
C7401
68UF
C7408
68UF
C7411
1UF
10% 25V X5R 603-1
C7422
0.001UF
10% 50V CERM 402 1
IN OUT
IMVP_VR_ON VR_PWRGOOD_DELAY
R7401
3.65K
1% 1/16W MF-LF 402
IMVP6_VR_TT
C7405
0.015uF
10% 16V X7R 402
R7408
147K
1% 1/16W MF-LF 402 1 2
61
IMVP6_NTC IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
ISEN2 23
61
7 4
SOFT RBIAS
S
NO STUFF
1
DIDT=TRUE
61
18
IMVP6_VO
IMVP6_DROOP IMVP6_DFB
1 1 2
DROOP 16
61
1 2 3
0.36UH-26A-1.05MOHM
(IMVP6_PHASE2)
1
L7401
C7423
0.001UF
10% 50V CERM 402
C7416
0.001UF
10% 50V CERM 402 1 2
1 MPCG1040-SM
2 PLACE_NEAR=L7401.2:1MM SM 2 1
2
13
VDIFF DFB
17
61
C7406
0.001UF
10% 50V CERM 402
61 61
12 11 10 9
5 D
FB2 FB COMP VW
1 2
CRITICAL
VSEN RTN
14 15
R7418
1K
1% 1/16W MF-LF 402
R7417
4.02K
1% 1/16W MF-LF 402
C7429
180pF
5% 50V CERM 402 2
CRITICAL
R7409
1K
1% 1/16W MF-LF 402 1
R7413
1K
1% 1/16W MF-LF 402
61 61
R7416
13.7K
1% 1/16W MF-LF 402
DIDT=TRUE
Q7403
4 G
XW7413
IMVP_VO2
2 402 MF-LF 1/16W 5% 1
RJK0208DPA
WPAK
IMVP6_VDIFF_RC
NC GND
21
IMVP6_RTN
25
IMVP6_VSEN
XW7412
IMVP_VSUM2
R7411
255
1% 1/16W MF-LF 402
TPAD
49
61
C7431
0.001UF
10% 50V CERM 402
(IMVP6_VO)
1
S 1 2 3
R7407
R7430
2.61K
1% 1/16W MF-LF 402
61
(IMVP6_FB)
1
61
B
1
GND_IMVP6_SGND
VOLTAGE=0V
C7432
0.001UF
1
C7414
470PF
10% 50V CERM 402 1
C7434
0.033UF
10% 16V X5R 402
C7428
0.22UF
10% 10V CERM 402
R7415
11K
1% 1/16W MF-LF 402
(THIS NET SHOULD CONNECT TO U7400.29 WITH MIN LOOP AREA)
R7405
10K
1% 1/16W MF-LF 402 1
C7404
0.22UF
10% 10V CERM 402
(IMVP6_VW)
10% CERM 402 50V
IMVP6_VO_R
1
R7443
3.65K
1% 1/16W MF-LF 402
CRITICAL
C7413
220PF
1 5% 25V CERM 402
R7431
10KOHM-5%
0603-LF 2
C7407
0.001UF
10% 50V CERM 402
R7410
6.81K
1% 1/16W MF-LF 402
IMVP6_COMP_RC
2 1
(IMVP6_ISEN2) (IMVP6_VSUM) (IMVP6_VO)
C7433
0.001UF
50V CERM 402 10%
R7414
97.6K
1% 1/16W MF-LF 402
ERT-J1VR103J
(IMVP6_COMP)
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
PLACE_NEAR=U7400.21:1 MM
2
2 1 1
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
C7421
0.22uF
10% 6.3V CERM-X5R 402
R7423
10
R7422
10
1% 1/16W MF-LF 402
OMIT
XW7400
SM 1
1% 1/16W MF-LF 2 402
CPU_VCCSENSE_P CPU_VCCSENSE_N
10 72 10 72 61 61 61
IMVP6 CPU VCORE REGULATOR

A
MIN_LINE_WIDTH
61 61 61 61 61
61 61 61 61 61
MIN_NECK_WIDTH 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.20 MM

61 61 61 61 61
MIN_LINE_WIDTH
MIN_NECK_WIDTH 0.25 MM 0.20 MM 0.25 MM 0.25 MM 0.20 MM
61 61 61 61 61
IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1
1.5 MM 0.25 MM 1.5 MM 1.5 MM 0.25 MM
IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2
0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM
IMVP6_OCSET IMVP6_VSUM GND_IMVP6_SGND IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
MIN_LINE_WIDTH 0.25 MM 0.25 MM 0.50 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM
MIN_NECK_WIDTH 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM
R
SYNC_MASTER=K24_MLB
PAGE TITLE
IMVP6 CPU VCore Regulator

DRAWING NUMBER SIZE
Apple Inc.
051-8563
REVISION
A.13.0
BRANCH PAGE
61 61
IMVP6_RTN IMVP6_VSEN
0.25 MM 0.25 MM
0.20 MM 0.20 MM
74 OF 109
SHEET
K6 NOTES : Q7400-Q7403 CHANGED BACK TO K24 FETS DUE TO LAYOUT K6 NOTES : BOM OPTION ADDED TO NTC
61 OF 80
D
PP5V_S0_MCPREG_VDD
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
=PPVIN_S0_MCPCORE =PP5V_S0_MCPREG
D
CRITICAL MCPCORES0_BOOT_R
1
R7560
1
CRITICAL
CRITICAL
2.2
C7540 1
68UF
20% 16V 2 POLY-TANT CASE-D2E-SM
C7541 1
68UF
C7560 1
68UF
C7561
1UF
C7563
0.001UF
16
22
R7561
1K
C7550
1UF
5% 1/10W MF-LF 603 VDD PVCC
C7562
1UF
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE 2
R7565
0
C7564 1
0.22UF
5% 10V CERM-X7R 2 603
10% 2 25V X5R 603-1
10% 2 50V X7R 402
5% 1/16W MF-LF 402 2
10% 2 16V X5R 402
10% 16V 2 X5R 402
5% 1/10W MF-LF 1 603
CRITICAL
D 4 G
U7500
ISL9563B
1 RBIAS 2 SOFT 28 IMON 31 24 25 26 27 23 29 30 32 8 9 PGOOD VID0 VID1 VID2 VID3
NC
MCPCORES0_RBIAS MCPCORES0_SOFT
44
QFN
(MCPCORES0_UGATE)
VIN 14 UGATE 18 BOOT 17 PHASE 19 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE
Q7560
RJK0365DPA-02
WPAK
CRITICAL
S
OUT OUT IN IN IN IN
MCPCORES0_IMON MCPCORES0_PGOOD MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3>
R7593 R7590 R7591 R7592 R7594
NO STUFF 0 0 0 0 0
1 2
MCPCORES0_UGATE MCPCORES0_BOOT
DIDT=TRUE MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
CRITICAL 0.56UH-31A
1 FDU1040D-SM 2
R7525
0.001
1% 1W MF 0612
MCPCORES0_IMON_R
5% 1/16W MF-LF 402
1 2 3
L7560
65 18 18 18 18
MCPCORES0_PHASE
SWITCH_NODE=TRUE DIDT=TRUE
(MCPCORES0_PHASE)
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM 5
PPMCPCORE_S0_R
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
402 402 402 402
MCP_VID0_REG MCP_VID1_REG MCP_VID2_REG MCP_VID3_REG

NC
1 3
2 4 1
CRITICAL
C7566
10UF
C7565
270UF
=PPMCPCORE_S0_REG 7 MAX CURRENT: 30.4A (Q7560 Limit) f = 300 kHz
62
CRITICAL
D 4 LGATE 21 G
CRITICAL
Q7565
RJK0208DPA
WPAK
20% 2 4V X5R 603
20% 2 2V TANT CASE-B4-SM
65
IN
=MCPCORES0_EN =PPMCPCORE_S0_REG 62 7
1
MCPCORES0_FDE
R7563
100
C
R7566
79 21
MCPCORES0_VSEN MCPCORES0_RTN MCPCORES0_VW
1% 1/16W MF-LF 2 402
VR_ON AF_EN FDE VSEN RTN
CRITICAL
MCPCORES0_LGATE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE S 1 2 3
C7567 1
10UF
20% 4V X5R 2 603
C7568 1
270UF
20% 2V 2 TANT CASE-B4-SM
C7569
10% 50V 2 X7R 402
0.001UF
4 VW
IN
MCPCORES0_VSEN_P
20
(MCPCORES0_VSEN) MCPCORES0_COMP
1 5 COMP 6 FB 7 VDIFF PGND 20
1
VO 12 OCSET 3
ISP 13 ISN 11 ICOMP 10
MCPCORES0_VO MCPCORES0_OCSET MCPCORES0_ISP MCPCORES0_ISN MCPCORES0_ICOMP
(MCPCORES0_VO)
1% 1/16W MF-LF 402
R7569
9.76K 1 2
1% 1/16W MF-LF 402
C7570
0.001UF MCPCORES0_FB MCPCORES0_VDIFF
R7568
79 21
IN
MCPCORES0_VSEN_N
20
10% 2 50V X7R 402
15
33
1% 1/16W MF-LF 402
(MCPCORES0_RTN)
1
C7577
VSS
THRM_PAD
1% 1/16W MF-LF 2 402
R7573 C7573 1 10K

47PF
5% 50V CERM 2 402
R7500
1
R7571
100
R75721
150K
1% 1/16W MF-LF 402 2
C7576
0.1UF
1% 1/16W MF-LF 2 402
10% 2 16V X7R-CERM 402
10% 50V 2 X7R 402
0.001UF
100
C7578
0.001UF
MCPCORES0_ISP_R
(MCPCORES0_ISN)
1
10% 50V 2 X7R 402
R7575
22.1K
1% 1/16W MF-LF 402
C7575 1
47PF
5% 50V CERM 2 402
(MCPCORES0_VW)
XW7561 SM
GND_MCPCORES0_AGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V 1 2
1% 1/16W MF-LF 2 402
0.001UF
C7579 1
10% 50V 2 X7R 402
R7576
6.98K
(MCPCORES0_ICOMP)
PLACE_NEAR=U7500.33:1mm
C7580
330PF
1 2 5% 50V COG 402
1% 1/16W MF-LF 2 402
R7577
150K 2 1
1% 1/16W MF-LF 402
C7581
100PF
1 2 5% 50V CERM 402
B
(MCPCORES0_COMP)
MCPCORES0_COMP_C
VID<3:0>
(MCPCORES0_FB)
VOLTAGE 0.9750V 0.9625V 0.9500V 0.9375V 0.9250V 0.9125V 0.9000V 0.8875V 0.8750V 0.8625V 0.8500V 0.8375V 0.8250V 0.8125V 0.8000V 0.7875V
R7578
1
C7582
4700PF MCPCORES0_VDIF_C
1 2
200
(MCPCORES0_VDIFF)
1% 1/16W MF-LF 402
R7579
1
3.01K 2
1% 1/16W MF-LF 402
10% 100V CERM 402
1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP VCore Regulator

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE
K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27
75 OF 109
SHEET
62 OF 80
CPUVTT POWER SUPPLY
=PPVIN_S0_CPUVTTS0
CRITICAL
C7630
68UF
C7695
1UF
10% 25V X5R 603-1
C7696
0.001UF 2
20% 50V CERM 402
D1
C
=PP5V_S0_CPUVTTS0
Q7620
WPAK S1/D2 7
RJK0384DPA
1 G1
C
=PPCPUVTT_S0_REG
7
L7620
6
7
G2 S2 3 4
2.2UH-8.0A
1 2
CRITICAL
VOUT = 1.066V 15A MAX OUTPUT F = 360 KHZ
301
1 2
R7601
PP5V_S0_CPUVTTS0_V5FILT
PCMB065T-SM
PLACEMENT_NOTE=Place XW7665 next to L7620
1% 1/16W MF-LF 402
R7603 C7601
1UF
10% 10V X5R 402-1 2 1 10 4 1
226K
C7604
4.7UF
10% 10V X5R 805
1% 1/16W MF-LF 402 2 2
V5FILT
CRITICAL
V5DRV
2
C7665
10UF
20% 6.3V X5R 603
U7600
TPS51117RGY_QFN14
65
R7680
1 0
5% 1/16W MF-LF 402
DIDT=TRUE
C7603 0.1UF
CPUVTTS0_VBST_R
MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
XW7665
SM 1
C7661
0.001UF
20% 50V CERM 402
IN OUT
=CPUVTTS0_EN CPUVTTS0_PGOOD (=PPCPUVTT_S0_REG) CPUVTTS0_VFB CPUVTTS0_TRIP
EN_PSV PGOOD VOUT VFB TRIP GND

7
SYM 2 QFN
1
10% 16V X5R 402
TON VBST DRVH LL DRVL
CPUVTTS0_TON CPUVTTS0_VBST
CRITICAL
2 1
C7660
330UF
20% 2.5V TANT CASE-B2-SM
65
14
13
CPUVTTS0_DRVH
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
12
CPUVTTS0_LL
SWITCH_NODE=TRUE
DIDT=TRUE
11
CPUVTTS0_DRVL
GATE_NODE=TRUE
DIDT=TRUE
CPUVTTS0_VSNS NO STUFF
THRM_PAD
15
PGND
8
R7670
8.45K
1% 1/16W MF-LF 402
C7670
100PF
5% 50V CERM 402
R7604
8.87K
1% 1/16W MF-LF 402
1
B
2
XW7600
SM 2
<Ra>
(GND)
SM
XW7601
PLACE_NEAR=U7600.15:1MM PLACE_NEAR=U7600.7:1MM
R7671
20.0K
1% 1/16W MF-LF 402
ROUTING NOTE:
Place XW7601 by C7660.
GND_CPUVTTS0_SGND
<Rb>
Vout = 0.75V * (1 + Ra / Rb)

(CPUVTTS0_VFB) CPUVTTS0_VOUT (=PPCPUVTT_S0_REG)
SYNC_MASTER=K24_MLB
PAGE TITLE
CPU VTT(1.05V) SUPPLY

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE
K6 NOTES : Q7620 CHANGED BACK TO K24 FETS DUE TO LAYOUT
76 OF 109
SHEET
63 OF 80
1.2V ENET Switcher

7
BCM57765 Internal Switcher Support

(This may be required to use BCM57765) BCM57765
=PP3V3_ENET_P1V2ENET CRITICAL BCM5764M P1V2ENET_SW

1
CRITICAL BCM5764M 2.2UH-1.2A

2
L7720
R7730
=PP1V2_ENET_REG
1
7
PP3V3_ENET_PHY_VDD
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE PLACE_NEAR=L7735.2:2 mm
VIN
D
65
U7720
ST1S12G12R
IN
MIN_LINE_WIDTH=0.6 mm PCAA031B-SM MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE PLACE_NEAR=L7720.2:1 mm
XW7721 SM
3
1 2
Vout = 1.2V Max Current = 0.7A F = 1.7MHZ

31 24 7
5% 1/16W MF-LF 402
BCM57765_SR_VDD
=PP1V2_ENET_PHY_REG
31
BCM57765
PLACEHOLDER!
CRITICAL BCM57765 2.2UH-1.2A
31
BCM57765
R7731
1
R7735
1 2
=P1V2ENET_EN BCM5764M
1 5
TSOT23-5L
GND
PP3V3_ENET_PHY_VDDP
L7735
PP1V2_ENET_PHY_VFB
EN FB/VO
SW
=PP3V3_ENET_PHY BCM57765
BCM5764M
1
5% 1/16W MF-LF 402
BCM57765_SR_LX
1 PCAA031B-SM
TP_BCM57765_SR_VDDP
5% 1/16W MF-LF 402
31
BCM57765_SR_VFB
31
C7720
22UF
C7721
22UF
BCM57765
1 1
BCM57765
BCM57765
1 1
20% 6.3V CERM 2 805
P1V2ENET_FB
20% 6.3V 2 CERM 805
C7730
4.7UF
C7731
0.1UF
C7735
10uF
C7736
0.1UF
20% 6.3V CERM 2 603
20% 10V 2 CERM 402
20% 6.3V 2 X5R 603
20% 10V 2 CERM 402
353S2769
1.05V S0 MCP PLL LDO

MCPPLL_R:REG
7
=PP1V05_S0_MCP_PLL_UF_R
R7745
1
5% 1/16W MF-LF 402
=PP1V05_S0_MCP_PLL_OR
1.5V S0 Regulator
7
=PP3V3_S0_P1V5S0
1
CRITICAL
C7710
20% CERM 6.3V 805
22UF
CRITICAL 2.2UH-3.25A P1V5S0_SW

1 IHLP1616BZ-SM 2
L7710
=PP1V5_S0_REG
1 VIN
U7710
ISL8009B
DFN
65
C7711 1
47PF
5% 50V CERM 2 402
R7711
100K
1
IN OUT
=P1V5S0_EN P1V5S0_PGOOD
2 EN 3 POR
CRITICAL
LX 8 VFB 6 RSI 5
1% 1/16W MF-LF 2 402
Vout = 1.508V MAX CURRENT = 1.5A f = 1.6MHZ

CRITICAL
65
P1V5S0_FB
<Ra>
R7712
113K
C7715
22UF
BOMOPTIONs:
MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER. MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY. TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE. TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.
4 SKIP
20% 2 6.3V CERM 805
GND 7
THRM_PAD 9
1% 1/16W MF-LF 2 402
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
MCP 0.9V S5 (AUXC) Switcher

7
=PP3V3_S5_P0V9S5
1
CRITICAL
1.8V S0 Switcher
=PP1V8_S0_REG
7 7
C7750
22UF
6.3V 20% CERM 805
CRITICAL 2.2UH-3.25A P0V9S5_SW

1 IHLP1616BZ-SM 2
L7750
=PP0V9_S5_REG
=PP3V3_S0_P1V8S0
1
C7760
10uF
20% 6.3V 2 X5R 603 4
U7760
3
CRITICAL L7760 1 10UH-0.55A-330MOHM VI PCAA031B-SM

2
CRITICAL
Vout = 1.8V MAX CURRENT = 0.3A F = 1MHZ

65
1 VIN
U7750
ISL8009B DFN
IN OUT
C7751
47PF
1 1
R7751
25.5K
1
=P0V9S5_EN P0V9S5_PGOOD
2 EN
3 POR
CRITICAL
LX 8 VFB 6 RSI 5
5% 50V CERM 2 402
1% 1/16W MF-LF 2 402
Vout = 0.902V MAX CURRENT = 1.5A f = 1.6MHZ

CRITICAL
C7762
10uF
65
P0V9S5_FB
<Ra>
R7752
200K
C7755
22UF
A
65
TPS62202
IN
=P1V8S0_EN
FB EN
SOT23-5
SW 5 GND
2
P1V8S0_SW
20% 6.3V 2 X5R 603
4 SKIP
20% 6.3V 2 CERM 805
GND 7
THRM_PAD 9
1% 1/16W MF-LF 2 402
SYNC_MASTER=T27_MLB
PAGE TITLE
<Rb>
Misc Power Supplies

DRAWING NUMBER SIZE
Vout = 0.8V * (1 + Ra / Rb)

R
Apple Inc.
051-8563
REVISION
A.13.0
BRANCH PAGE
K6 NOTES : C7710 AND C7750 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNCED FROM T27
77 OF 109
SHEET
64 OF 80
S5 Rail Enables & PGOOD

65 7
Power Control Signals

State Run (S0) SMC_PM_G2_ENABLE 1 1 1 0 PM_SLP_S4_L 1 1 0 0 PM_SLP_S3_L 1 0 0 0
65 40 39 18 6
ISL6259 Frequency Select

=PP3V42_G3H_CHGR 58 7 VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH
=PP3V42_G3H_PWRCTL
C7840 1
0.1uF
20% 10V CERM 2 402
R78611
10K
5% 1/16W MF-LF 402 2
CRITICAL
Sleep (S3) Soft-Off (S5) Battery Off (G3Hot) Internal pull-ups 100K +/- 20% P3V3S5_EN_L
MAKE_BASE=TRUE
VDD
U7840
SLG4AP012
TDFN 2 IN_A
(IPD)
VFRQ:SLPS4
59
OUT IN
=P5V3V3_REG_EN SMC_PM_G2_EN
MAKE_BASE=TRUE
R7864
PM_SLP_S4_L
1
VFRQ:SLPS4&VFRQ:SLPS3
CHGR_VFRQ
D 3
OUT
58
Q7860
SSM3K15FV
SOD-VESM-HF
39 6
OUT_A* 4
(OD,IPU)
=P3V3S5_EN_L =P0V9S5_EN
1
VFRQ:LOW
1
OUT OUT
59
79 7 6
PP3V3_S5 Threshold: ?? DLY > 10 ms S5PGOOD_DLY

1
6 IN_B 2:1 + 1.3V 7 DLY_1C DLY
OUT_A 3
(OD,IPU)
P0V9S5_EN
MAKE_BASE=TRUE
64
5% 1/16W MF-LF 402
R7860
10K
C7801
VFRQ:SLPS3
0.033UF
69 65 39 18 6
OUT_B 8
(OD,IPU)
10% 16V 2 X5R 402
R7863
PM_SLP_S3_L
1
S 2
5% 1/16W MF-LF 2 402
CHGR_VFRQ_GATE
C7841
220PF
GND 5
THRM PAD 9
5% 1/16W MF-LF 402
5% 25V 2 CERM 402
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
64
IN
P0V9S5_PGOOD
RSMRST_PWRGD
MAKE_BASE=TRUE
OUT
39
PM_WLAN_EN_L
OUT
29
S0 Rail PGOOD Circuitry

PP5V_S0 7 6 S0PGOOD_ISL
7
Pull-up is with power FET.
Q7890
D 6
=PP3V3_S0_PWRCTL
S3 Rail Enables
65 7
SSM6N15FEAPE
SOT563
R7870
10K
S 1
R78201
10K
=PP3V42_G3H_PWRCTL
2 G
29 18
R78132
IN
AP_PWR_EN
AC_OR_S0_L
1% 1/16W MF-LF 402 2
S0 Rail PGOOD (ISL Version)

PP3V3_S0_VMON
59
5% 1/16W MF-LF 402 2 IN IN IN IN IN
P5V3V3_PGOOD P1V5S0_PGOOD MCPCORES0_PGOOD CPUVTTS0_PGOOD MCPPLLLDO_PGOOD NO STUFF
68K
5% 1/16W MF-LF 402 1
Q7890
SSM6N15FEAPE
SOT563
D 3
6 D
Q7891
SSM6N15FEAPE
SOT563
S0PGOOD_ISL
64
R78711
20.0K
1% 1/16W MF-LF 402 2
S0PGOOD_ISL
C7870
0.1uF
P5VS3_EN_L
MAKE_BASE=TRUE
=P5VS3_EN_L
OUT
59
NO STUFF
5 G
40 39 18
Q7891
SSM6N15FEAPE
SOT563
D 3
C7813
0.068UF
IN
S 4
1 S
G 2
20% 10V CERM 2 402
VDD
CRITICAL S0PGOOD_ISL
62
VDDA
63
U7870
3 V2MON 5 V3MON 6 V4MON
SMC_ADAPTER_EN
79 65 7 6 79 65 7 6
10% 2 10V CERM 402
5 G
65 40 39 18 6
S 4
69 65 39 18 6
IN
PM_SLP_S3_L
65 7 6
PP3V3_S0 PP1V5_S0 PP1V05_S0 Worst-Case Thresholds: VDD: 2.9140V V2MON: 3.000V V3MON: 0.610V V4MON: 0.610V
ISL88042IRTJJZ TDFN (IPU)

MR*
1 8
NC
R7872
1
RST*
S0PGOOD_RST_L
10
ALL_SYS_PWRGD
MAKE_BASE=TRUE
OUT
24 39
IN
PM_SLP_S4_L
GND
THRM_PAD
R7812
1
353S2718
5% 1/16W MF-LF 402
P3V3S3_EN
MAKE_BASE=TRUE
=P3V3S3_EN
OUT
66
5% 1/16W MF-LF 402
NO STUFF
1
C7812
0.47UF
18
10% 6.3V 2 CERM-X5R 402
ENET Rail Enables

IN
PM_SLP_RMGT_L
MAKE_BASE=TRUE
7
=P3V3ENET_EN =P0V9ENET_EN
OUT OUT
66 66
S0 Rail PGOOD (BJT Version)

7
R7811
5.1K 2 1
5% 1/16W MF-LF 402
=PP3V3_ENET_PWRCTL
79 65 7 6
=PP3V3_S5_VMON S0PGOOD_BJT
DDRREG_EN
MAKE_BASE=TRUE
1
=DDRREG_EN =USB_PWR_EN
PP3V3_S0 S0PGOOD_BJT
1
OUT OUT
60
R78501
15K
5% 1/16W MF-LF 402 2
R78261
150K
R78101
100K
37
C7810
0.47UF
R7821
15.0K
5% 1/16W MF-LF 402 2
10% 6.3V 2 CERM-X5R 402
P1V2ENET_EN
MAKE_BASE=TRUE
1% 1/16W MF-LF 2 402 OUT

64
1% 1/16W MF-LF 402 2
S0PGOOD_BJT
R7828
S0PGOOD_BJT_L
6 4
S0PGOOD_BJT
R7823
1
S0PGOOD_BJT
10
R78511
15K
5% 1/16W MF-LF 402 2
=P1V2ENET_EN
VMON_3V3_DIV
1K
VMON_Q2_BASE
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
Q1 5 Q2 8 7 Q3
S0PGOOD_BJT
R7824
S0 Rail Enables
R7859
65 39 18 6 69
79 65 7 6
PP1V5_S0
1K
NC
CRITICAL S0PGOOD_BJT
VMON_Q3_BASE
NC
Q7820
ASMCC0179
DFN2015H4-8
5% 1/16W MF-LF 402
2 1 Q4
IN
PM_SLP_S3_L
100
1 2
PM_SLP_S3_R_L
MAKE_BASE=TRUE
=P5VS0_EN =PBUSVSENS_EN
S0PGOOD_BJT
OUT OUT
66
5% 1/16W MF-LF 402
R7825
65 7 6
R7881
33K
22K
5% 1/16W MF-LF 1 402
15K
5% 1/16W MF-LF 1 402
10K
5% 1/16W MF-LF 1 402
5.1K
5% 1/16W MF-LF 1 402
S0PGOOD_BJT
1
R78791
100K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 1 402
R7822
7.15K
5% 1/16W MF-LF 402
R7880
R7882
R7883
R7884
43
PP1V05_S0
1K
VMON_Q4_BASE Worst-Case Thresholds: Q2: 0.XXXV Q3: 0.640V Q4: 0.660V 3.3V w/Divider: 2.345V
353S2809 VMON_EMITTER S0PGOOD_BJT
P3V3S0_EN
MAKE_BASE=TRUE
=P3V3S0_EN =P1V8S0_EN =P1V5S0_EN =MCPCORES0_EN =CPUVTTS0_EN
OUT OUT OUT OUT OUT
66
P1V8S0_EN
MAKE_BASE=TRUE
1% 1/16W MF-LF 2 402
R78271
100
5% 1/16W MF-LF 402 2
64
P1V5S0_EN
MAKE_BASE=TRUE
64
MCPCORES0_EN
MAKE_BASE=TRUE
62
A
1
CPUVTTS0_EN
MAKE_BASE=TRUE
63
SYNC_MASTER=T27_MLB
PAGE TITLE
C7881
0.47UF
C7880
0.47UF
C7882
0.47UF
C7883
0.47UF
C7884
0.47UF
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
Power Sequencing
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE
VTT Rail Enable

20 18
VTT rail must ramp up in about the same time as MEMVDD rail (Q2300). =DDRVTT_EN
OUT
60

IN
MCP_MEM_VDD_EN
MAKE_BASE=TRUE
78 OF 109
SHEET
K6 HAS A PULL UP ON DDRREG_PGOOD. REMOVED ALIAS TO TP SIGNAL
65 OF 80
6
CRITICAL
3.3V S3 FET
7
Q7910
FDC638P_G
SM
3.3V ENET Switch

=PP3V3_S3_FET
6 5 2 1
7 7
=PP3V3_S5_P3V3ENETFET
A2 B2
TPS22924
CSP VIN VOUT A1 B1
U7980
=PP3V3_ENET_FET
=PP3V3_S5_P3V3S3FET
4
Q7910
MOSFET Type FDC638P
65
CRITICAL
IN
U7980
Part TPS22924C Load Switch 18 mOhm Typ 50 mOhm Max 2 A 0.4 A (EDP) Type R(on) I(max) Loading
R79121
10K
C7911
0.033UF
3
=P3V3ENET_EN
C2 ON GND C1
5% 1/16W MF-LF 402 2
P-Channel 65 mOhm @2.5V 2.0 A @85C 0.606 A (EDP)
R7910
P3V3S3_EN_L
1
10% 16V 2 X5R 402
C7910
0.01UF
1 2 10% 16V CERM 402
Rds(on) ID(max) Loading
C7980 1
1UF
10% 6.3V CERM 2 402
47K
P3V3S3_SS
Q7903
SSM3K15FV
SOD-VESM-HF
D 3
5% 1/16W MF-LF 402
1
65
S 2
IN
=P3V3S3_EN
0.9V ENET FET

7
=PP0V9_ENET_P0V9ENETFET
3.3V S0 FET
7
CRITICAL
C7990
0.1UF =PP3V3_S0_FET
7 7
1 3
Q7930
FDC606P_G
1 2 5 6 SOT-6
=PP3V3_S5_P0V9ENETFET
R7990
100K 2 1
5% 1/16W MF-LF 402 1
20% 10V CERM 2 402
D
1
CRITICAL
Q7990
G S
=PP3V3_S5_P3V3S0FET
S
4
P0V9ENET_SS
SI2312BDS
SOT23 2
Q7930
MOSFET FDC606P P-Channel 35 mOhm @2.5V 2.7 A @85C 1.895 A (EDP)
R79321
100K
R7992
69.8K
Q7991
SSM6N15FEAPE
SOT563
D 6
=PP0V9_ENET_FET
C7931
5% 1/16W MF-LF 402 2
R7930
P3V3S0_EN_L
1
10% 2 16V X5R 402
0.033UF
Type
C7930
0.01UF
1 2 10% 16V CERM 402
Rds(on) ID(max) Loading
1% 1/16W MF-LF 402 2
47K
R7991
P0V9ENET_EN_L
1
P3V3S0_SS
10K
S 1
C7991
0.01UF
Q7990
1
MOSFET Type Rds(on) ID(max) Loading
SI2312BDS N-Channel 37 mOhm @2.5V 3.25 A @85C 0.140 A (EDP)
Q7905
SSM3K15FV
SOD-VESM-HF
D 3
5% 1/16W MF-LF 402
Q7991
SSM6N15FEAPE
SOT563
D 3
1% 1/16W MF-LF 402
10% 16V CERM 2 402
P0V9ENET_EN_L_RC
1
65
S 2
65
5 IN
S 4
IN
=P3V3S0_EN
=P0V9ENET_EN
5V S0 FET
CRITICAL
Q7940
TPCP8102
23V1K-SM
7
=PP5V_S3_P5VS0FET
=PP5V_S0_FET
5 6 7 8
1 2 3
Q7940
Part Type Rds(on) Loading TPCP8102 P-Channel 14 mOhm @4.5V 1.675 A (EDP)
R79421
47K
C7941 1
0.033UF
10% 16V 2 X5R 402
5% 1/16W MF-LF 402 2
R7940
P5VS0_EN_L
1
C7940
0.01UF P5VS0_SS
1 2 10% 16V CERM 402
47K
Q7945
SSM3K15FV
SOD-VESM-HF
D 3
5% 1/16W MF-LF 402
1
65
S 2
IN
=P5VS0_EN
SYNC_MASTER=T27_MLB
PAGE TITLE
Power FETs
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

79 OF 109
SHEET
66 OF 80
LCD
16
CONNECTOR
LVDS CONNECTOR:518S0650
LCD_IG_PWR_EN
1
R9014
1K
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
CRITICAL
5% 1/16W MF-LF 2 402
J9000
20474-030E-11
F-RT-SM 31
CRITICAL
C9015
0.001UF
C9010
0.001UF
10% 50V X7R 402
32
2
U9000
FPF1009
1 ON
7
MFET-2X2-8IN
L9004
FERR-120-OHM-1.5A PP3V3_LCDVDD_SW
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM
1
1 0402-LF 2 CRITICAL
10% 50V X7R 402
1 2
=PP3V3_S5_LCD
2 VIN_1 3 VIN_2
VOUT_1 4 VOUT_2 5 THRM PAD 7
PP3V3_LCDVDD_SW_F
VOLTAGE=3.3V
70 6
3 4 5 6 7
L9008
1 0402-LF
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM
120-OHM-0.3A-EMI
2
6
BKL_VSYNC
C
2
C9009
0.1UF
10% 16V X5R 402
GND 6
C9011
0.1UF
C9012
10UF
7
PP3V3_S0_LCD_F
LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2>
VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

74 8 6
10% 16V 2 X5R 402
20% 6.3V 2 X5R 603
8 9 10
=PP3V3_S0_LCD
1 1
(LVDS DDC POWER)
74 8 6
R9008
100K
5% 1/16W MF-LF 402 2
R9009
100K
5% 1/16W MF-LF 402
74 8 6 74 8 6
11 12 13
74 8 6 74 8 6
14 15 16
2
8 6 8 6
LVDS_DDC_CLK LVDS_DDC_DATA
CRITICAL
L9080
90-OHM-200MA AMC2012-SM
SYM_VER-1
79 6 79 6
LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P
70 6
17 18 19
LVDS I/F
74 8
LVDS_IG_A_CLK_N
PPVOUT_SW_LCDBKLT
NC
20 21 22
C9020
74 8
LVDS_IG_A_CLK_P
0.001UF
10% 50V X7R 402
2
NC
23 24 25 26 27
LED BKLT I/F
70 6 70 70 70 6 70 6 70 6
LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6
28 29
NC
30
33 34
SYNC_MASTER=K24_MLB
PAGE TITLE
LVDS CONNECTOR
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

90 OF 109
SHEET
67 OF 80
D
C9300
DP_IG_AUX_CH_P
74 8
D
0.1UF
1 10% 16V X5R 402 2
DP_AUX_CH_C_P
8
S 4
D 3
DP_EXT_DDC_CLK
SIGNAL_MODEL=DP_AUXCH_FET OMIT
SIGNAL_MODEL=DP_AUXCH_FET
G G 2
OMIT
Q9300
SSM6N16FE
SOT563
C9303
10% 50V CERM 402
0.0033UF
Q9300
SOT563
376S0857
SSM6N16FE
C9301
DP_IG_AUX_CH_N
74 8
0.1UF
1
10% 16V X5R 402
DP_AUX_CH_C_N
8
S 4
D 3
DP_EXT_DDC_DATA
SIGNAL_MODEL=DP_AUXCH_FET
G G 2
SIGNAL_MODEL=DP_AUXCH_FET OMIT
5
OMIT
Q9302
SSM6N16FE
SOT563
376S0857
Q9302
SSM6N16FE
SOT563
DP_CA_DET
IN
B
XSTR,FT,N-CH,DUAL,SOT-563
B
REFERENCE DES Q9300,Q9302 CRITICAL CRITICAL BOM OPTION
SYNC_MASTER=K69_MLB
PAGE TITLE
DISPLAYPORT SUPPORT
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

93 OF 109
SHEET
68 OF 80
Port Power Switch

DP_ESD DP_ESD CRITICAL
D
7
CRITICAL
CRITICAL
D
IO NC
4 7
D9410
D9410
RCLAMP0524P
SLP2510P8
U9480
TPS2051B SOT23
L9400
FERR-120-OHM-3A
RCLAMP0524P
SLP2510P8
2
=PP3V3_S5_DP_PORT_PWR
IN
5 4
IN
EN
OUT OC* GND

2
1 3
PP3V3_S0_DPILIM TP_DPPWR_OC_L
1
PP3V3_S0_DPPWR
2 9
65 39 18 6
PM_SLP_S3_L
0603
C9400
0.01UF
20% 16V
IO NC GND
IO NC
1 10
5 6
IO NC GND
3
CERM 402
CRITICAL
1
CRITICAL
1
C9480
22UF
20% 6.3V X5R-CERM-1 603
C9481
0.1UF
20% 10V CERM 402
C9487
100UF
20% 6.3V POLY-TANT CASE-B2-SM
C9485
0.1UF
20% 10V CERM 402
C9486
10UF
20% 6.3V X5R 603
R9420
100K
5% 1/16W MF-LF 402
HDMI_CEC
2 1
CRITICAL
J9400
DSPLYPRT-M97-1
F-RT-THSM
C
FL9403
12-OHM-100MA TCM1210-4SM 4
79 8
SYM_VER-2
2
R9425
1M
5% 1/16W MF-LF 402
DP_EXT_ML_F_P<0>
BOT ROW
TH PINS
2 4 6
FL9400
12-OHM-100MA TCM1210-4SM 1
SYM_VER-2
TOP ROW
SM PINS
1 3 5
79
DP_EXT_ML_F_P<0> DP_EXT_ML_F_N<0>
79
4
79
C
DP_EXT_ML_C_P<0> DP_EXT_ML_C_N<0> DP_EXT_ML_C_P<1> DP_EXT_ML_C_N<1> DP_EXT_ML_C_P<2> DP_EXT_ML_C_N<2>
C9410
0.1uF
1 2 10%
DP_EXT_ML_P<0>
16V X5R 402
IN
8 79
1 8
79
IN
DP_EXT_ML_P<3> DP_EXT_ML_N<3>
BI BI
69 7 7
C9414
0.1uF
2 10%
79
DP_EXT_ML_C_P<3>
16V X5R 402
79 8
IN
C9415
0.1uF
2 10%
79
DP_EXT_ML_C_N<3>
16V X5R 402
79
10 12 14 16 18 20
HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND AUX_CHP AUX_CHN DP_PWR GND ML_LANE2P ML_LANE2N RETURN
FL9401
12-OHM-100MA TCM1210-4SM 1
SYM_VER-2
3 79
C9411
0.1uF
2 10%
DP_EXT_ML_N<0>
16V X5R 402
IN
8 79
4
79
7 9 11 13 1 15 17 19
79 79 79 79
C9412
0.1uF
2 10%
DP_EXT_ML_P<1>
16V X5R 402
IN
8 79
2 3
FL9402
12-OHM-100MA TCM1210-4SM
SYM_VER-2
79
C9413
0.1uF
2 10%
DP_EXT_ML_N<1>
16V X5R 402
IN
8 79
4
79
79 8 79 8
DP_EXT_AUX_CH_C_P DP_EXT_AUX_CH_C_N =PP3V3_S0_DPCONN
2 3
C9416
0.1uF
2 10%
DP_EXT_ML_P<2>
16V X5R 402
IN
8 79
79
C9417
0.1uF
2 10%
DP_EXT_ML_N<2>
16V X5R 402
IN
8 79
=PP5VR3V3_S0_DPCADET
R9443
100K
5% 1/16W MF-LF 402 2 1
DP_ESD CRITICAL
SHIELD PINS
22 21
R9442
100K
5% 1/16W MF-LF 402
1 1
D9411
RCLAMP0524P
SLP2510P8
514-0637
R9421
100K
5% 2 1/16W MF-LF 402
OUT
DP_EXT_CA_DET
6
2
2
IO NC GND
IO NC
1 10
DP_ESD CRITICAL DP_ESD CRITICAL
Q9440
2N7002DW-X-G
SOT-363
D9411
RCLAMP0524P
SLP2510P8
S
1
DP_CA_DET_Q_L
3
D9400
RCLAMP0504F D G
SC70-6-1 5 6
B
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
Q9440
2N7002DW-X-G
SOT-363
S
4
DP_CA_DET_Q
DP to DVI/HDMI
IO NC GND
IO NC
4 7
R9422
1M
5% 1/16W MF-LF 402
Cable Adapter (CA) has 100k pull-up to DP_PWR.
3 4 3
69 7
=PP3V3_S0_DPCONN
R9445
10K
5% 1/16W MF-LF 402 2 1
R9444
10K
5% 1/16W MF-LF 402
OUT
DP_EXT_HPD
6
Q9441
2N7002DW-X-G
SOT-363
S
1
DP_HPD_Q_L
3
Q9441
2N7002DW-X-G
SOT-363
S
4
DP_HPD_Q
R9423
100K
5% 1/16W MF-LF 402 2 1
SYNC_MASTER=K24_MLB
PAGE TITLE
DP Source must pull down HPD input with
DisplayPort Connector
DRAWING NUMBER SIZE
greater than or equal to 100K (DPv1.1a).

R
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*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER. *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE. *LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
D
7 8
=PP5V_S0_BKL
R9701
1
D
CRITICAL 33UH-1.8A-110MOHM
1 1217AS-2SM 2
=PPBUS_SW_BKL CRITICAL
PLACE_NEAR=L9701.1:3mm PLACE_NEAR=L9701.1:3mm 1
5% 1/16W MF-LF 402
BOOST_VOL:HI CRITICAL
L9701
D9701 SOD-123
PPBUS_SW_LCDBKLT_PWR_SW
1 2
PPVOUT_SW_LCDBKLT
PLACE_NEAR=U9701.21:3mm
C9712 1
10UF
10% 25V 2 X5R 805
C9713
0.1UF
NO STUFF
1
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE
RB160M-60G
OMIT
1
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V 1
6 67
C9796
220PF
C9797
10UF
C9799
10UF
OMIT
10% 2 25V X5R 402
R9703
0
R9702
0
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 402 2
10% 50V 2 X7R-CERM 402
10% 2 50V X5R 1210
10% 2 50V X5R 1210
PPVIN_SW_BKL_R
7
PP5V_S0_BKL_VLDO
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V PLACE_NEAR=U9701.22:5mm 1
=PP3V3_S0_BKL_VDDIO
C9711 1
0.1UF
10% 16V 2 X5R 402
C9710 1
10% 25V 2 X5R 603-1
C9714
0.01UF
1UF
10% 2 16V CERM 402
NO STUFF
22
C
NO STUFF
1UF
10% 6.3V X5R 402
23
C9741
VDDIO
C
24
VLDO
VIN
C9740
10UF
1 2 20% 6.3V X5R 603
NO STUFF
R9740
1
U9701
NC
6 GD 5 FSET 20 FILTER 3 ISET 10 SCLK 11 SDA 2 PWM 7 FAULT
BKL_FLTR_R
R9741
1
1% 1/16W MF-LF 402
LP8545SQX
47.0K2
LLP
SW FB OUT1 OUT2 OUT3 OUT4 OUT5 OUT6
BKLT:PROD
21 12 13 6 14 6 16 17 18 19
BKL_FSET BKL_FLTR BKL_ISET BKL_SCL BKL_SDA BKL_PWM
R9753
42
10K
R9717
BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 BKL_ISEN4 BKL_ISEN5 BKL_ISEN6 BKL_VSYNC_R NO STUFF
1 1
LED_RETURN_1
IN
=I2C_BKL_1_SCL
R9757
42
BI
=I2C_BKL_1_SDA
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
OUT
6 67
5% 1/16W MF-LF 402
BKLT:PROD
R9718
1
5% 1/16W MF-LF 402
LED_RETURN_2
R9731
1
TP_BKL_FAULT BKL_EN
2
OUT
67
71 8
301K 2
1% 1/16W MF-LF 402
4 EN
5% 1/16W MF-LF 402
9 GND_S
IN
LCD_BKLT_PWM
15 GND_L
33
100K
C9723
0.1UF
1 GND_SW
R9704
5% 1/16W MF-LF 402 1
R9715
NO STUFF
10% 2 25V X5R 402
OMIT CRITICAL
VSYNC
BKLT:PROD
R9755
10K
R9754
0
R9719
1
LED_RETURN_3
5% 2 50V CERM 402
33PF
25
C9704
1% 1/16W MF-LF 1 402
THRM PAD
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
OUT
67
5% 1/16W MF-LF 402
R97161
90.9K 1% Fpwm=9.62kHz 1/16W MF-LF see spec for others 402 2
R9714
16.2K 1% 1/16W I_LED=23.2mA
BKL_VSYNC
BKLT:PROD
IN
6 67
R9720
1
LED_RETURN_4
MF-LF 2 402
XW9710 SM
1 2
OUT
6 67
GND_BKL_SGND
5% 1/16W MF-LF 402
BKLT:PROD
R9721
1
I_LED=610*1.23/Riset (EEPROM should set EN_I_RES=1)
LED_RETURN_5
OUT
6 67
5% 1/16W MF-LF 402
BKLT:PROD
R9722
1
LED_RETURN_6
OUT
6 67
5% 1/16W MF-LF 402
FOR LP8543: STUFF R9741 NO STUFF R9740, C9740, C9741, R9754
PART NUMBER 103S0198 103S0198 371S0580
QTY 3 3 1 2
DESCRIPTION
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM SCHOTTKY BARRIER DIODE RB160M-40 CAP, 50V, 1210, X5R, 10UF+/-10%
REFERENCE DES
R9717,R9718,R9719 R9720,R9721,R9722
CRITICAL
BOM OPTION BKLT:ENG BKLT:ENG BOOST_VOL:LOW
10.2 ohm resistors for current measurement on LED strings.

SYNC_MASTER=K69_MLB
PAGE TITLE
D9701 C9797,C9799
138S0673
CRITICAL
LCD Backlight Driver

DRAWING NUMBER SIZE
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D
F9800
7
CRITICAL Q9806
FDC638APZ_SBMS001
SSOT6-HF 6
D
5
8 70
=PPBUS_S0_LCDBKLT
1
2AMP-32V
2
PPBUS_S0_LCDBKLT_FUSED
1
PPBUS S0 LCDBkLT FET

MOSFET FDC638APZ P-TYPE 43 mOhm @4.5V 0.65 A (EDP)
0402-HF
R9808
301K
1% 1/16W MF-LF 402
C9802
0.1UF
10% 16V X5R 402
CHANNEL RDS(ON) LOADING
LCDBKLT_EN_DIV
1
R9809
147K
1% 1/16W MF-LF 402
LCDBKLT_EN_L
Q9807
SSM6N15FEAPE
SOT563
IN
LCD_BKLT_EN
LCDBKLT_DISABLE
C
D
6
Q9807
SSM6N15FEAPE
SOT563
24
IN
BKLT_PLT_RST_L
SYNC_MASTER=T27_MLB
PAGE TITLE
LCD Backlight Support

DRAWING NUMBER SIZE
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8
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH
7
MINIMUM NECK WIDTH MAXIMUM NECK LENGTH
6
TABLE_PHYSICAL_RULE_HEAD
5
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
4
CPU / FSB Net Properties
ELECTRICAL_CONSTRAINT_SET FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0 FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1 FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2 FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3 FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_ADDR_GROUP1 FSB_ADSTB1 FSB_1X FSB_BREQ0_L FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_CPURST_L FSB_1X FSB_1X CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP CPU_IERR_L PM_DPRSLPVR NET_TYPE PHYSICAL SPACING FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CPU_50S CPU_50S CPU_50S MCP_50S MCP_50S MCP_50S MCP_50S CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_AGTL CPU_AGTL MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_ADDR FSB_ADDR FSB_ADSTB FSB_ADDR FSB_ADSTB FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB
FSB (Front-Side Bus) Constraints

DIFFPAIR PRIMARY GAP
FSB_50S FSB_DSTB_50S
* *
=50_OHM_SE
=50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE_HEAD
=STANDARD =1:1_DIFFPAIR
=STANDARD
=50_OHM_SE
=1:1_DIFFPAIR
FSB 4X Signal Groups
FSB_D_L<15..0> FSB_DINV_L<0> FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_D_L<31..16> FSB_DINV_L<1> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_D_L<47..32> FSB_DINV_L<2> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_D_L<63..48> FSB_DINV_L<3> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_A_L<16..3> FSB_REQ_L<4..0> FSB_ADSTB_L<0> FSB_A_L<35..17> FSB_ADSTB_L<1> FSB_ADS_L FSB_BREQ0_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<2..0> FSB_TRDY_L CPU_A20M_L CPU_BSEL<2..0> CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L PM_DPRSLPVR IMVP_DPRSLPVR MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND CPU_GTLREF CPU_COMP<3> CPU_COMP<2> CPU_COMP<1> CPU_COMP<0> XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L<4..0> XDP_BPM_L<5> XDP_CPURST_L CPU_VID<6..0> IMVP6_VID<6..0> CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N
6 9 13 6 9 13 6 9 13 6 9 13
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET
LAYER
WEIGHT
FSB_DATA FSB_DSTB
* * * * *
=2x_DIELECTRIC =3x_DIELECTRIC =STANDARD =2x_DIELECTRIC =STANDARD
?
FSB_DATA FSB_DSTB
TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM
=4x_DIELECTRIC =5x_DIELECTRIC =3x_DIELECTRIC =4x_DIELECTRIC =3x_DIELECTRIC
?
6 9 13 6 9 13 6 9 13 6 9 13
? ?
?
FSB_ADDR FSB_ADSTB FSB_1X
FSB_ADDR FSB_ADSTB
?
? ?
?
6 9 13 6 9 13 6 9 13 6 9 13
FSB_1X
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended. FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe. DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s. FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps. Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB 1X signals shown in signal table on right. Intel Design Guide recommends FSB signals be routed only on internal layers. NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
6 9 13 6 9 13 6 9 13 6 9 13
FSB 2X Signals
6 9 13 6 9 13 6 9 13
6 9 13 6 9 13
6 9 13 9 13 9 13 9 13 9 13 9 13 9 13 6 9 13 6 9 13 6 9 13 9 12 13 9 13 9 13
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CPU_50S
* *
=50_OHM_SE
=27P4_OHM_SE
=50_OHM_SE =27P4_OHM_SE
=STANDARD 7 MIL
=STANDARD
FSB 1X Signals
CPU_27P4S
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
9 13 8 9 9 13 9 13 9 13 9 13 9 13 9 13 40 61 9 12 13 9 13 9 13 9 13 40 9 13 9 13 9 13 61 9 13
CPU_AGTL CPU_8MIL CPU_COMP CPU_GTLREF CPU_ITP CPU_VCCSENSE
* * * * * *
=STANDARD 8 MIL 25 MIL 25 MIL =2:1_SPACING 25 MIL
?
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
?
?
SR DG recommends at least 25 mils, >50 mils preferred

? ?
Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints

9 13 9 13 12 13 12 13 13 13
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_FSB_COMP
8 MIL
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4
13 61 61
FSB Clock Constraints

(See above)
MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =100_OHM_DIFF
MINIMUM LINE WIDTH
CLK_FSB_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5
13 13 13 13
9 28 9 9 9 9
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CLK_FSB
=3x_DIELECTRIC
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
9 12 9 12 9 12 9 12 9 12 9 12 9 12 12
(FSB_CPURST_L)
10 61
CPU_VCCSENSE CPU_VCCSENSE
10 61 10 61
(CPU_VCCSENSE) (CPU_VCCSENSE)
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU/FSB Constraints
DRAWING NUMBER SIZE
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8
Memory Bus Constraints
7
6
5
DIFFPAIR NECK GAP
4
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET MEM_A_CLK MEM_A_CLK MEM_A_CKE MEM_A_CNTL MEM_A_CNTL MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 NET_TYPE PHYSICAL SPACING MEM_70D MEM_70D MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MCP_MEM_COMP MCP_MEM_COMP MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MCP_MEM_COMP MCP_MEM_COMP
MEM_40S MEM_70D
* *
=40_OHM_SE
=70_OHM_DIFF
=40_OHM_SE =70_OHM_DIFF
=STANDARD =70_OHM_DIFF
=STANDARD
=70_OHM_DIFF
MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0> MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0> MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0> MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0> MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7> MCP_MEM_COMP_VDD MCP_MEM_COMP_GND
14 25 14 25
14 20 25 14 25 14 25
SPACING_RULE_SET
LAYER
WEIGHT
MEM_CLK2MEM MEM_CTRL2CTRL
* * * * * * * * *
=4:1_SPACING =2:1_SPACING =2.5:1_SPACING =1.5:1_SPACING =3:1_SPACING =1.5:1_SPACING =3:1_SPACING =3:1_SPACING 25 MIL
?
NV DG says 3x inner, 4x outer NV DG says 2x inner, 4x outer

? ?
14 25 14 25 14 25 14 25 14 25
MEM_CTRL2MEM MEM_CMD2CMD MEM_CMD2MEM MEM_DATA2DATA MEM_DATA2MEM MEM_DQS2MEM MEM_2OTHER

? ?

14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27
? ?

? ?
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK MEM_CLK MEM_CLK MEM_CLK MEM_CLK
MEM_CLK MEM_CTRL MEM_CMD MEM_DATA MEM_DQS
* * * * *
MEM_CLK2MEM
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
* * * * *
MEM_CMD2MEM
MEM_CLK2MEM
MEM_CMD2MEM
MEM_CLK2MEM
MEM_CMD2CMD
MEM_CLK2MEM
MEM_CMD2MEM
MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_B_CLK MEM_B_CLK MEM_B_CKE MEM_B_CNTL MEM_B_CNTL MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MCP_MEM_COMP MCP_MEM_COMP
14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_CMD2MEM
14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
* * * * *
MEM_CTRL2MEM
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
* * * * *
MEM_DATA2MEM
MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL
MEM_CTRL2CTRL
MEM_DATA2MEM
MEM_CTRL2MEM
MEM_DATA2MEM
MEM_CTRL2MEM
MEM_DATA2DATA
MEM_CTRL2MEM
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS
* * * * *
MEM_DQS2MEM
* * * * *
* * * * *
MEM_2OTHER
MEM_DQS2MEM
MEM_2OTHER
MEM_DQS2MEM
MEM_2OTHER
14 26 14 26
MEM_DQS2MEM
MEM_2OTHER
14 20 26 14 26 14 26
MEM_DQS2MEM
MEM_2OTHER
DDR3:
Need to support MEM_*-style wildcards!
DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. CMD/CTRL signals should be matched within 150 ps. All memory signals maximum length is 1.030 ps. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
14 26 14 26 14 26 14 26 14 26
14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27
B MCP MEM COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_MEM_COMP
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27
SPACING_RULE_SET
LAYER
WEIGHT
MCP_MEM_COMP
=2x_DIELECTRIC
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2
14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27 14 27
SYNC_MASTER=T27_MLB
PAGE TITLE
Memory Constraints
DRAWING NUMBER SIZE
14 14
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27
101 OF 109
SHEET
73 OF 80
8
PCI-Express
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =90_OHM_DIFF =100_OHM_DIFF MINIMUM LINE WIDTH
7
6
5
DIFFPAIR NECK GAP
4
MCP89 Net Properties
ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP CRT CRT CRT CRT_SYNC CRT_SYNC MCP_DAC_COMP MCP_DAC_COMP DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
PCIE_90D CLK_PCIE_100D
* *
=90_OHM_DIFF =100_OHM_DIFF
=90_OHM_DIFF
=100_OHM_DIFF
PEG_R2D
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PEG_D2R
PCIE CLK_PCIE
* * *
=3X_DIELECTRIC 20 MIL 8 MIL
?
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
PEG_R2D_P<15..0> PEG_R2D_N<15..0> PEG_R2D_C_P<15..0> PEG_R2D_C_N<15..0> PEG_D2R_P<15..0> PEG_D2R_N<15..0> PEG_D2R_C_P<15..0> PEG_D2R_C_N<15..0> PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N MCP_PEX0_TERMP CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC MCP_TV_DAC_RSET MCP_TV_DAC_VREF TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P<5..0> TMDS_IG_TXD_N<5..0> DP_IG_ML_P<3..0> DP_IG_ML_N<3..0> DP_IG_AUX_CH_P DP_IG_AUX_CH_N MCP_TMDS0_RSET MCP_TMDS0_VPROBE
8 8 8 68 8 68 6 29 6 29 15 29 15 29 6 15 29 6 15 29
MCP_PEX_COMP
?
PCIE_AP_R2D
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3
NEED PCIe Gen1/Gen2 notes!

Analog Video Signal Constraints
PCIE_AP_D2R
31 31 15 31 15 31 15 31 15 31 31 31
PCIE_ENET_R2D PCIE_ENET_D2R
MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
CRT_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
33 33 15 33 15 33 15 33 15 33 33 33
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CRT CRT_2CRT CRT_2CLK CRT_2SWITCHER CRT_SYNC
* * * * * *
20 MIL 15 MIL 50 MIL 250 MIL =4x_DIELECTRIC =2x_DIELECTRIC
?
CRT
CRT
CRT_2CRT
PCIE_FW_R2D PCIE_FW_D2R
?
?
?
?
MCP_PE0_REFCLK MCP_PE1_REFCLK MCP_PE2_REFCLK MCP_PE3_REFCLK MCP_PEX_CLK_COMP CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC MCP_DAC_RSET MCP_DAC_VREF TMDS_IG_TXC TMDS_IG_TXC TMDS_IG_TXD TMDS_IG_TXD DP_EXT_ML DP_EXT_ML DP_EXT_AUX_CH DP_EXT_AUX_CH MCP_TMDS0_RSET MCP_TMDS0_VPROBE LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3 MCP_IFPAB_RSET MCP_IFPAB_VPROBE SATA_HDD_R2D
8 15 8 15 15 29 15 29 15 31 15 31 15 33 15 33 15
MCP_DAC_COMP
CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor. - 50-ohm from first to second termination resistor. - 75-ohm from output of three-pole filter to connector (if possible). R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.
Digital Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =90_OHM_DIFF =100_OHM_DIFF Y
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

DP_90D LVDS_100D MCP_DV_COMP
* * *
=90_OHM_DIFF =100_OHM_DIFF 20 MIL

=90_OHM_DIFF =100_OHM_DIFF 20 MIL
=90_OHM_DIFF =100_OHM_DIFF =STANDARD
=90_OHM_DIFF =100_OHM_DIFF =STANDARD
=90_OHM_DIFF
CRT_50S CRT_50S CRT_50S CRT_50S CRT_50S
8 8 8 8 8 8 8
=100_OHM_DIFF
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT LVDS
* *
=3x_DIELECTRIC =3x_DIELECTRIC
?
DISPLAYPORT LVDS
TOP,BOTTOM TOP,BOTTOM
=4x_DIELECTRIC =4x_DIELECTRIC
?
DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D MCP_DV_COMP
LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils. NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps. DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max trace length: LVDS 10 inches, DP 8.5 inches. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2
16 23 16 23
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =90_OHM_DIFF
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SATA_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
SATA SATA_TERMP
* *
=3x_DIELECTRIC 8 MIL
?
SATA
TOP,BOTTOM
=4x_DIELECTRIC
SATA intra-pair matching should be 1 ps. Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6
LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D MCP_DV_COMP
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3> MCP_IFPAB_RSET MCP_IFPAB_VPROBE
8 67 8 67 6 8 67 6 8 67
16 23 16 23
SATA_HDD_D2R
SATA_ODD_R2D
A
SATA_ODD_D2R MCP_SATA_TERMP
SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D
SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_TERMP
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N MCP_SATA_TERMP
17 36 17 36 6 36 6 36 17 36 17 36 6 36 6 36 17 36 17 36 6 36 6 36 17 36 17 36 36 36
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Constraints 1
DRAWING NUMBER SIZE
Apple Inc.
17 R
051-8563
REVISION
A.13.0
BRANCH PAGE

102 OF 109
SHEET
74 OF 80
8
LPC Bus Constraints
7
6
5
DIFFPAIR NECK GAP
4
MCP89 Net Properties
ELECTRICAL_CONSTRAINT_SET LPC_AD LPC_FRAME_L LPC_RESET_L MCP_LPC_CLK0 NET_TYPE PHYSICAL SPACING LPC_55S LPC_55S LPC_55S CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D MCP_USB_RBIAS SMB_55S SMB_55S SMB_55S SMB_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S SMB SMB SMB SMB HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA MCP_HDA_COMP CLK_SLOW_55S CLK_SLOW_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S CLK_SLOW CLK_SLOW SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI LPC LPC LPC CLK_LPC CLK_LPC CLK_LPC USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB
LPC_55S CLK_LPC_55S
* *
=STANDARD =STANDARD
=STANDARD
=STANDARD
LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_T57_P USB_T57_N USB_EXTC_P USB_EXTC_N USB_SDCARD_P USB_SDCARD_N USB_WM_P USB_WM_N MCP_USB_RBIAS_GND SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_PULLDN_COMP PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L SPI_ALT_CLK SPI_ALT_MOSI SPI_ALT_MISO SPI_ALT_CS_L
18 39 41 18 39 41 18 24
SPACING_RULE_SET
LAYER
WEIGHT
18 24 24 39 24 41
LPC CLK_LPC
* *
=1.5x_DIELECTRIC =2x_DIELECTRIC
?
USB_EXTA
17 37 17 37 37 79 37 79 8 17 8 17 8 17 8 17 17 29 17 29 17 29 17 29 17 47 17 47 17 38 17 38 17 37 17 37 6 38 6 38 8 17 8 17 17 30 17 30 8 17 8 17
USB 2.0 Interface Constraints

USB_MINI
MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MCP_USB_RBIAS USB_90D
* *
=STANDARD
=90_OHM_DIFF
8 MIL =90_OHM_DIFF
8 MIL =90_OHM_DIFF
=STANDARD
USB_EXTD USB_CAMERA USB_BT USB_TPAD USB_IR USB_EXTB
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
USB
=2x_DIELECTRIC
USB
TOP,BOTTOM
=4x_DIELECTRIC
SMBus Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

USB_T57 USB_EXTC
SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
USB_SDCARD USB_WM
SMB
=2x_DIELECTRIC
C HD Audio Interface Constraints

PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
MCP_USB_RBIAS
17
DIFFPAIR NECK GAP

HDA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA (SMBUS_SMC_MGMT_SCL) (SMBUS_SMC_MGMT_SDA) HDA_BIT_CLK HDA_SYNC
12 18 42 12 18 42 18 42 18 42
SPACING_RULE_SET
LAYER
WEIGHT
18 51 18 18 51 18 18 18 51 18 51
HDA MCP_HDA_COMP
* *
=2x_DIELECTRIC 8 MIL
?
?
HDA_RST_L
SIO Signal Constraints

HDA_SDIN0 HDA_SDOUT
PHYSICAL_RULE_SET
LAYER
18 51 18
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_HDA_PULLDN_COMP MCP_SUS_CLK
18
18 24 24 39
SPACING_RULE_SET
LAYER
WEIGHT
CLK_SLOW
=1.5x_DIELECTRIC
SPI_CLK SPI_MOSI SPI_MISO SPI_CS0
18 41 6 41 18 41 6 41 6 18 41 18 41 6 41
SPI Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
41 50 41 50 41 50 41 50
SPACING_RULE_SET
LAYER
WEIGHT
SPI
=1.5x_DIELECTRIC
41 41 41 41
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Constraints 2
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

103 OF 109
SHEET
75 OF 80
8
7
6
5
DIFFPAIR NECK GAP
4
RGMII Net Properties
ELECTRICAL_CONSTRAINT_SET MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 NET_TYPE PHYSICAL SPACING MCP_MII_COMP MCP_MII_COMP ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S MCP_BUF0_CLK MCP_BUF0_CLK ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII
MCP RGMII (Ethernet) Constraints

MCP_MII_COMP ENET_MII_55S
* *
=STANDARD =55_OHM_SE
7.5 MIL =55_OHM_SE

7.5 MIL =55_OHM_SE
=STANDARD =55_OHM_SE
=STANDARD =STANDARD
=STANDARD
=STANDARD
MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R<3..0> ENET_RXD<0> ENET_RXD<3..1> ENET_RX_CTRL ENET_CLK125M_TXCLK ENET_TXD<0> ENET_TXD<3..1> ENET_TX_CTRL ENET_RESET_L
17 17
SPACING_RULE_SET
LAYER
WEIGHT
MCP_BUF0_CLK ENET_MII
* *
=3:1_SPACING 12 MIL
?
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_RXCLK

8 17
D
8 17 8 17 8 17 8 17
88E1116R (Ethernet PHY) Constraints

PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =100_OHM_DIFF MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ENET_MDI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_RXD_STRAP ENET_RXD_STRAP ENET_RXD ENET_TXCLK ENET_TXD ENET_TXD ENET_TXD
SPACING_RULE_SET
LAYER
WEIGHT
ENET_MDI
25 MIL
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
24 31
SD Card Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

Ethernet Net Properties

ELECTRICAL_CONSTRAINT_SET ENET_MDI NET_TYPE PHYSICAL SPACING ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI
SD_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
ENET_MDI_P<3..0> ENET_MDI_N<3..0>
31 32 31 32
SD_INTERFACE
=3X_DIELECTRIC
SD Card Net Properties

ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE
SD_DATA
SD_D<4..0> SDCONN_DATA<4..0> BCM57765_CR_DATA<4> SD_D<7..5> SDCONN_DATA<7..5> BCM57765_CR_DATA<7..5> SD_CLK SD_CLK_R SDCONN_CLK SD_CMD SDCONN_CMD BCM57765_CR_CMD
30 30 31 31
SD_DATA_R
30 30 31 31
SD_CLK
30 30 30 31
SD_CMD
30 30 31 31
NOTE: SD_D<7..5> are different to support BCM5764M/BCM57765 co-layout.
SYNC_MASTER=T27_MLB
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

104 OF 109
SHEET
76 OF 80
8
FireWire Interface Constraints
PHYSICAL_RULE_SET
FW_100D
7
LAYER
*
6
5
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
4
FireWire Net Properties
NET_TYPE PHYSICAL FW_100D FW_100D FW_100D FW_100D FW_100D FW_100D FW_100D FW_100D SPACING FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP

=100_OHM_DIFF
MINIMUM LINE WIDTH

=100_OHM_DIFF
MINIMUM NECK WIDTH

=100_OHM_DIFF
MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF
=100_OHM_DIFF
FW_P0_TPA FW_P0_TPA
SPACING_RULE_SET
FW_TP
LAYER
*
=3:1_SPACING
WEIGHT
FW_P0_TPB FW_P0_TPB FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB
FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N
33 35 33 35 33 35 33 35 33 35 33 35 33 35 33 35
D
Port 2 Not Used
SYNC_MASTER=T27_MLB
PAGE TITLE
FireWire Constraints
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

CANNOT SYNC THIS PAGE FROM T27, FW CONSTRAINTS CHANGED TO 100OHM DIFF
105 OF 109
SHEET
77 OF 80
8
PHYSICAL_RULE_SET
1TO1_DIFFPAIR
7
LAYER
*
6
5
DIFFPAIR NECK GAP
4
SMC SMBus Net Properties
NET_TYPE PHYSICAL SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SPACING SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

=STANDARD
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

0.1 MM
0.1 MM
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
6 42 6 42 42 42 42 42 6 42 6 42 42 42
SMBus Charger Net Properties

NET_TYPE ELECTRICAL_CONSTRAINT_SET CHGR_CSI PHYSICAL 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR SPACING
CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N
58 58 58 58
58 58 44 58 44 58
SYNC_MASTER=T27_MLB
PAGE TITLE
SMC Constraints
DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

106 OF 109
SHEET
78 OF 80
8
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR MINIMUM LINE WIDTH
7
6
5
Misc Net Properties
ELECTRICAL_CONSTRAINT_SET (PCIE_AP) NET_TYPE PHYSICAL SPACING CLK_PCIE_100D CLK_PCIE_100D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D ENET_MDI_100D ENET_MDI_100D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D CLK_PCIE CLK_PCIE USB USB USB USB USB USB USB USB USB USB USB USB ENETCONN ENETCONN SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA
DIFFPAIR NECK GAP
3
2
Power Net Properties
NET_TYPE SPACING PHYSICAL THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S THERM THERM THERM THERM THERM THERM THERM THERM SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE MEM_POWER SB_POWER SB_POWER SB_POWER GND
SENSE_1TO1_55S THERM_1TO1_55S DIFFPAIR
* * *
=55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_LT1_P USB_LT1_N USB_TPAD_R_P USB_TPAD_R_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_CONN_P USB_BT_CONN_N USB_LT2_P USB_LT2_N ENETCONN_P<3..0> ENETCONN_N<3..0> SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_RDRV_IN_P SATA_HDD_D2R_RDRV_IN_N SATA_HDD_R2D_RDRV_IN_P SATA_HDD_R2D_RDRV_IN_N SATA_HDD_D2R_RDRV_OUT_P SATA_HDD_D2R_RDRV_OUT_N SATA_HDD_R2D_RDRV_OUT_P SATA_HDD_R2D_RDRV_OUT_N SATA_HDD_D2R_NORDRV_P SATA_HDD_D2R_NORDRV_N SATA_HDD_R2D_NORDRV_P SATA_HDD_R2D_NORDRV_N
6 29 6 29
CPUTHMSNS_D2 CPU_THERMD
=1:1_DIFFPAIR
SPACING_RULE_SET
LAYER
WEIGHT
SENSE THERM AUDIO
* * *
=2:1_SPACING =2:1_SPACING =2:1_SPACING
?
?
(USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_TPAD) (USB_TPAD) (USB_CAMERA) (USB_CAMERA)
37 75 37 75 37 37 47 47
MCPTHMSNS_D2 MCP_THMDIODE SENSE_DIFFPAIR
6 29 6 29 6 29 6 29 37 37
SENSE_DIFFPAIR
SPACING_RULE_SET
LAYER
WEIGHT
32 32
ENETCONN
25 MILS
?
SENSE_DIFFPAIR
36 36 6 36 6 36
SPACING_RULE_SET
LAYER
WEIGHT
GND MEM_POWER
* *
=STANDARD =STANDARD
?
SENSE_DIFFPAIR
?
36 36 36 36
SPACING_RULE_SET
LAYER
WEIGHT
SENSE_DIFFPAIR
GND_P2MM PWR_P2MM
* *
0.20 MM 0.20 MM
1000
1000
36 36 36 36
SENSE_DIFFPAIR SENSE_DIFFPAIR
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK MEM_CMD
GND GND GND GND GND
* * * * *
GND_P2MM
MEM_CLK MEM_CMD MEM_CTRL MEM_DATA MEM_DQS
MEM_POWER MEM_POWER MEM_POWER MEM_POWER MEM_POWER
* * * * *
PWR_P2MM
36 36 36 36 36 36 36 36
CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P MCP_THMDIODE_N ISNS_1V5_S3_P ISNS_1V5_S3_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_AIRPORT_R_P ISNS_AIRPORT_R_N ISNS_HDD_P ISNS_HDD_N ISNS_HDD_R_P ISNS_HDD_R_N ISNS_LCDBKLT_P ISNS_LCDBKLT_N ISNS_LCDBKLT_R_P ISNS_LCDBKLT_R_N ISNS_ODD_P ISNS_ODD_N ISNS_ODD_R_P ISNS_ODD_R_N ISNS_CPUVTT_P ISNS_CPUVTT_N MCPCORES0_VSEN_P MCPCORES0_VSEN_N PP1V5R1V35_S3 PP3V3_S5 PP3V3_S0 PP1V5_S0 GND
45 45 9 45 9 45
18 45 18 45
44 44 21 62 21 62
GND_P2MM
PWR_P2MM
I277
6 7
MEM_CTRL MEM_DATA MEM_DQS
GND_P2MM
PWR_P2MM
6 7 65 6 7 65 6 7 65
GND_P2MM
PWR_P2MM
GND_P2MM
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
Graphics Net Properties

ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D (DP_EXT_ML) DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
CLK_PCIE PCIE SATA USB CLK_PCIE SATA USB
GND GND GND GND SB_POWER SB_POWER SB_POWER
* * * * * * *
GND_P2MM
CLK_FSB CPU_COMP CPU_GTLREF CPU_VCCSENSE
GND GND GND GND
* * * *
GND_P2MM
Audio Net Properties

ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR
8 69 8 69 69 69 69 69 8 69 8 69
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
PWR_P2MM
PWR_P2MM
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
LVDS
GND
GND_P2MM
ENET_MDI
GND
GND_P2MM
LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_A_DATA_P<2..0> LVDS_CONN_A_DATA_N<2..0> LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LVDS_CONN_B_DATA_P<2..0> LVDS_CONN_B_DATA_N<2..0> DP_EXT_ML_P<3..0> DP_EXT_ML_N<3..0> DP_EXT_ML_C_P<3..0> DP_EXT_ML_C_N<3..0> DP_EXT_ML_F_P<3..0> DP_EXT_ML_F_N<3..0> DP_EXT_AUX_CH_C_P DP_EXT_AUX_CH_C_N DP_AUX_CH_SW_P DP_AUX_CH_SW_N
6 67 6 67
AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO
AUD_SPKRAMP_LIN_P AUD_SPKRAMP_LIN_N AUD_SPKRAMP_SUBIN_P AUD_SPKRAMP_SUBIN_N AUD_SPKRAMP_RIN_P AUD_SPKRAMP_RIN_N SSM2315L_P SSM2315L_N SSM2315S_P SSM2315S_N SSM2315R_P SSM2315R_N SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N BI_MIC_P BI_MIC_N HS_MIC_P HS_MIC_N
SPK_OUT SPK_OUT SPK_OUT
B
(DP_EXT_AUX_CH)
DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR
MCP Fanout Constraint Relaxations

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MEM_40S
OVERRIDE
*
OVERRIDE OVERRIDE OVERRIDE
0.09 MM
OVERRIDE
5.8 MM
MCP_DV_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_MEM_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_MII_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_USB_RBIAS
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_DV_COMP
OVERRIDE
*
0.25 MM
OVERRIDE
250 MIL
SYNC_MASTER=T27_MLB
PAGE TITLE
K6/K69 Specific Constraints

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

108 OF 109
SHEET
79 OF 80
8
BOARD LAYERS
7
BOARD AREAS NO_TYPE,BGA
6
TABLE_BOARD_INFO
5
BOARD UNITS (MIL or MM) MM ALLEGRO VERSION 15.2
4
3
2
AREA_TYPE SPACING_RULE_SET
1
TABLE_PHYSICAL_ASSIGNMENT_HEAD
K6/K69 Board-Specific Physical & Spacing Constraints

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
DEFAULT STANDARD BGA_P1MM BGA_P2MM BGA_P3MM
* * * * *
0.1 MM =DEFAULT 0.1 MM 0.2 MM 0.3 MM
?
* MEM_CLK
* * * * * * FSB_DSTB
BGA BGA BGA BGA BGA BGA BGA
BGA_P1MM
MEM_40S
BGA
STANDARD
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

? ?
BGA_P2MM
DEFAULT STANDARD
* *
Y Y
=50_OHM_SE =DEFAULT
0.080 MM =DEFAULT
12.7 MM 12.7 MM
0 MM =DEFAULT
0 MM
CLK_FSB CLK_LPC
BGA_P2MM
=DEFAULT
? ?
BGA_P2MM
CLK_PCIE CLK_SLOW
BGA_P2MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

BGA_P2MM
55_OHM_SE 55_OHM_SE
TOP,BOTTOM *
Y Y
0.090 MM 0.076 MM
0.090 MM
SPACING_RULE_SET
LAYER
WEIGHT
FSB_DSTB
BGA_P3MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
1.5:1_SPACING 2:1_SPACING
* * * * *
0.15 MM 0.2 MM 0.25 MM 0.3 MM 0.4 MM
?
?
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

2.5:1_SPACING 3:1_SPACING
?
50_OHM_SE 50_OHM_SE
TOP,BOTTOM *
Y Y
0.115 MM 0.076 MM
0.115 MM
?
0.076 MM
=STANDARD
=STANDARD
=STANDARD
4:1_SPACING
?
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SPACING_RULE_SET
LAYER
WEIGHT
40_OHM_SE 40_OHM_SE
TOP,BOTTOM *
Y Y
0.165 MM 0.126 MM
0.100 MM
1.5X_DIELECTRIC TOP,BOTTOM =STANDARD
0.105 MM 0.140 MM 0.210 MM 0.280 MM 0.350 MM 0.095 MM 0.126 MM 0.189 MM 0.252 MM 0.315 MM
?
0.100 MM
=STANDARD
=STANDARD
2X_DIELECTRIC 3X_DIELECTRIC
TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM * * * * *
?
?
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

4X_DIELECTRIC 5X_DIELECTRIC
?
27P4_OHM_SE 27P4_OHM_SE
TOP,BOTTOM *
Y Y
0.310 MM 0.222 MM
0.310 MM
?
0.222 MM
=STANDARD
=STANDARD
=STANDARD
1.5X_DIELECTRIC 2X_DIELECTRIC
?
?
PHYSICAL_RULE_SET
LAYER
3X_DIELECTRIC 4X_DIELECTRIC 5X_DIELECTRIC
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

?
70_OHM_DIFF
*
ISL3,ISL4,ISL9,ISL10
N Y Y
=STANDARD 0.151 MM 0.185 MM
=STANDARD =STANDARD
=STANDARD
?
70_OHM_DIFF 70_OHM_DIFF
0.090 MM
TOP,BOTTOM
0.200 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

90_OHM_DIFF 90_OHM_DIFF 90_OHM_DIFF
*
N Y Y
=STANDARD
=STANDARD
0.234 MM
TOP,BOTTOM
0.220 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

*
N Y Y
=STANDARD
=STANDARD
0.244 MM
TOP,BOTTOM
0.230 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

*
N Y Y
=STANDARD
=STANDARD
0.330 MM
TOP,BOTTOM
0.330 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
SYNC_MASTER=T27_MLB
PAGE TITLE
K6/K69 PCB Rule Definitions

DRAWING NUMBER SIZE
Apple Inc.
R
051-8563
REVISION
A.13.0
BRANCH PAGE

109 OF 109
SHEET
80 OF 80

Schem, MLB - Ldo, K6: Schematic / PCB #'S

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What are board areas and layers?

What are board areas and layers?

What are the spacing and physical rules?

What are the spacing and physical rules?

8

System Block Diagram

Power Block Diagram

CPU Power & Ground

eXtended Debug Port (mini-XDP)

MCP CPU Interface

MCP Memory Interface

MCP PCIe Interfaces

MCP SATA, USB & Ethernet

MCP HDA, LPC & MISC

MCP Power & Ground

MCP89 Memory Rail Gating

MCP89 GFX Core Rail Gating

MCP Standard Decoupling

MCP Graphics Support

DDR3 SO-DIMM Connector A

DDR3 SO-DIMM Connector B

DDR3 BYTE/BIT SWAPS-K6

FSB/DDR3 Vref Margining

RIGHT CLUTCH CONNECTOR

SecureDigital Card Reader

Ethernet PHY (Caesar II/IV)

FireWire LLC/PHY (FW643E)

FireWire Port & PHY Power

Sudden Motion Sensor (SMS)

AUDIO: LINE INPUT FILTER

AUDIO: HEADPHONE FILTER

AUDI0: SPEAKER AMP

AUDIO: JACK TRANSLATORS

DC-In & Battery Connectors

PBus Supply & Battery Charger

1.5V/1.35V LVDDR3 Supply

IMVP6 CPU VCore Regulator

MCP VCore Regulator

CPU VTT(1.05V) SUPPLY

Misc Power Supplies

LCD Backlight Driver

LCD Backlight Support

K6/K69 Specific Constraints

K6/K69 PCB Rule Definitions

External USB Connectors

Internal USB Support

LPC+SPI Debug Connector

NOTICE OF PROPRIETARY PROPERTY:

LAST_MODIFIED=Thu Mar 18 17:53:39 2010

64-Bit 1067/1333 MHz

SPI Boot ROM

FAN CONN PG AND CONTROL 46

Fan Ser Prt

Blue Ray dec

DISPLAY PORT CONN

USB PCI-E MAC

U6633, U6623, U6613

System Block Diagram