California Eastern Laboratories

AN1022

APPLICATION NOTE

Designing Low Noise Amplifiers for PCS Application

ABSTRACT This application note will review the process by which microwave amplifier designers choose their designs based on performance requirements, real estate constraint and prices. Traditionally, for small signal amplifiers, there has been three distinct and generally incompatible basic designs that have met most design goals: the high gain, low return loss amplifier, the low noise amplifier and the high output power amplifier. With the emergence of new technologies, in particular digital communications, the need for composite amplifiers that meet specific design goals has increased. This article will demonstrate how the different basic design types can be accomplished using a low cost NEC HJ-FET in a plastic package (Part I), and how improved performance can be achieved for a low noise PCS amplifier by using series feedback techniques (Part 2). Finally, (Part 3) will introduce some device modelization techniques used in creating non linear models and will verify these models with the above mentioned circuits. While the designs proposed may not yield the optimum design solutions for all PCS applications, it does introduce a few important RF and microwave techniques that can be applied to other digital applications.

DEVICE CHOICE AND CHARACTERISTIC The device chosen for all designs is the NE34018, a low noise, low cost Gallium Arsenide Hetero-Junction Field Effect Transistor (HJ-FET) housed in a miniature (SOT-343) plastic surface mount package. This device was selected because it offers an excellent compromise between cost and the high performance associated with High Electron Mobility Transistors: Low Noise figure (0.6 dB) and high gain (16 dB typical) at 2 GHz under low bias conditions (2V, 5 mA), a prime concern for products in the mobile communication industry. Both Noise and S-Parameters for the NE 34018 are available in Table 1. With a 0.6 m by 400 m geometry, the device is large enough to provide a reasonably high output power (output IP3 of 23 dBm typical at 2 V, 10 mA) with noise parameters optimized for the 1 to 3 GHz band (0.6 dB typical at 2 GHz). Additionally, the geometry, larger than other HJ-FETs makes it easier to design at the PCS and MMDS frequency bands both for impedance matching and stability. Other devices available to designers such as standard MESFETs (Metal Semiconductor Field Effect Transistors) were discarded because they provide a typical noise figure of 1.0 dB at 2 GHz. This leaves little margin for matching network losses and device variations when compared to typical PCS amplifier design goals. Other devices, such as PHEMTs (Pseudomorphic High Electron Mobility Transistor) have the required low noise (0.3 dB at 3 GHz), but their small geometry (0.15 m by 180 m) does not provide the necessary output power. Additionally, most PHEMTs are prone to instability problems at low frequencies.

DESIGN CONSIDERATION In this article, the design is for a 58 MHz bandwidth amplifier at a central frequency FC=1960 MHz. The bandwidth represents less than 3% of FC and consideration will only be given to narrow band amplifier reactively matched designs (defined as less than 10% of FC). There are three basic transistor amplifiers designs available to engineers: maximum gain amplifiers, low noise amplifiers and high output power amplification. In each distinct mode of operation, the FET (or Bipolar transistor) is presented with different loads and source impedance transferred from 50 Ohms. Each design goal will require a different design approach and matching networks.

GAIN MATCH THEORY In the design of amplifiers for maximum gain, the purpose is to transform the input and output loads: !S and !L to the matched counterparts of the device: !SM and !LM. This optimal source and load impedance will allow the maximum power transfer through the 2 port network (the amplifier) and will maximize the gain: The device is simultaneously

AN1022
NE34018 S-PARAMETERS VDS = 3 V, IDS = 20 mA CS, IDSS = 71 mA Frequency (GHZ) 0.50 0.75 0.90 0.95 1.00 1.25 2.00 2.50 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 S11 MAG 0.969 0.937 0.915 0.905 0.898 0.852 0.697 0.591 0.493 0.368 0.349 0.362 0.356 0.336 0.385 0.495 S11 ANG -18.7 -27.5 -32.7 -34.4 -36.1 -44.4 -68.4 -84.9 -102.7 -141.9 -173.2 170.2 154.4 123.7 87.0 62.6 S21 MAG 8.662 8.396 8.209 8.159 8.096 7.770 6.775 6.144 5.553 4.526 3.790 3.332 3.024 2.782 2.523 2.245 S21 ANG 160.8 152.0 147.0 145.3 143.6 135.7 113.9 100.9 88.9 68.0 51.2 36.7 22.0 5.7 -11.6 -29.4 S12 MAG 0.016 0.024 0.028 0.029 0.031 0.037 0.056 0.066 0.075 0.091 0.107 0.127 0.148 0.171 0.189 0.200 S12 ANG 81.1 77.0 74.8 74.1 73.3 70.1 61.4 56.5 52.1 44.9 39.9 35.6 28.8 20.3 9.8 -1.8 S22 MAG 0.667 0.652 0.641 0.636 0.632 0.611 0.539 0.496 0.458 0.399 0.343 0.284 0.230 0.199 0.208 0.234 S22 ANG -7.3 -10.9 -12.9 -13.6 -14.3 -17.5 -26.4 -32.0 -37.1 -44.7 -48.1 -50.8 -61.8 -89.6 -127.5 -172.5

NOISE PARAMETERS Frequency (GHz) 1.00 1.50 1.90 2.00 3.00 NF Min (dB) 0.41 0.48 0.59 0.60 0.66 Gamm Opt MAG 0.610 0.560 0.490 0.490 0.450 Gamm Opt MAG 59.7 71.0 88.0 89.0 128.0 r(n) 0.13 0.14 0.12 0.11 0.04

At this point, an important assumption can be made to simplify the calculations. The network is assumed to be unilateral (a perfect isolation between the output and the input: S12 = 0). The value of such an assumption can be assessed by the unilateral figure of merit [3]:

U=

S11 S22 S21 S12 (1 S11 )(1 S22 )

2 2

(2)

Table 1: NE34018 Noise and S-Parameters

This formula defines the boundaries of the error introduced by the simplified calculation between the transducer power gain G and the unilateral transducer gain Gu : (3) If the error is deemed small enough to justify the unilateral assumption, then the unilateral transducer power gain is defined as:
Circuit Load

1 <G< 1 2 2 (1+U ) Gu (1 U )

SM NE34018 Input Matching Network

LM

Source

Output Matching Network

Gu = S21

(1 ISM I )(1 ILM I ) 2 2 1 SM S11 1 LM S22

(4)

Figure 1: Circuit matching. conjugatively matched (Figure 1). From general microwave two port network theory [1], [2], the maximum gain is defined as:

(1 ISM I )(1 ILM I ) G =IS21I 2 I(1 SM S11)(1 LM S22) SM LM S21S12I

2 2 2

In this case, we can easily see that the gain only depends on the S-Parameters of the device and the matching to the input and to the output. The loads !S and !L presented to the active device allow for different designs and optimize the performance of the amplifier. Complex number theory can be utilized to demonstrate that Gu will be maximized if !S = S*11 and !L = S*22 (a well-known simplified matching principle) in which case the obtained maximum gain from the device is:

Gu,Max = S21

1 2 (1 IS11 I )(1 IS22I )

2

(5)

(1)

AN1022
Goals (1932-1990) 16 Min. 2 dB Max. 6 dBm Min. -18 Min. -18 Min. 3 V, 20 mA Max. 250*250 Less than $1 Simulation (1932-1990) 17 Min. 1.5 dB Max. 6 dBm Min. -20 Min. -20 Min. 3 V, 20 mA Max. N/A N/A Test (1932-1990) 16.5 Min. 1.5 dB Max. 6 dBm Min. -19 Min. -20 Min. 3 V, 20 mA Max. 250*250 Less than $1

Frequency Range Gain Noise Figure Input IP3 Input Return Loss Output Return Loss Bias condition Real Estate Price in 100 K Quantities

(MHz) (dB) (dB) (dBm) (dB) (dB) (dBc/Hz) (Mils*Mils) (US$)

Table 2: Maximum Gain Design Performance: Goals, simulation and tests.

This formula shows that the maximum unilateral gain of an amplifier is determined solely by the S-Parameters of the device chosen, regardless of the source or load impedance. In reality (as can be seen by the attached S-Parameters), the isolation of this device is not perfect and consequently S12 " 0 . The condition under which both input and output ports can be matched simultaneously to achieve a maximum gain is much more complicated. The input match depends on the load impedance and vice versa. The resulting calculations are beyond the scope of this article, however, the results are of importance in the design of microwave amplifiers. The maximum gain is found to be achieved when the device is simultaneously conjugatively matched with the source and load coefficients referenced earlier: !SM and !LM. Since the unilateral assumption is no longer valid, these two reflection coefficients involve elaborated complex number calculations routinely processed by linear simulators. These two loads also need to have an amplitude less than 1 to ensure both stability and the matching of a source (or load) that has the real part of its impedance positive. The equivalent and necessary condition to this equation is:

Maximum Stable Gain (MSG) defined as:

1

MSG =

S21 S12

(9)

STABILITY MATCH One area of interest to all designers is the stability of the circuit, especially when using Hetero-Junction FETs with very high gain levels at lower frequency. These types of FETs display a natural propensity to oscillations. The circuit is defined as unconditionally stable when it cannot oscillate under any source or load impedance. The input reflection coefficient must be less than one for all loads. This ensures a positive input resistance from the device, and a similar condition applies to the output resistance in regard to the input loads. These conditions are satisfied with the equations:

S11 +

S12 S21L < 1 for any Source loads 1 L S22

K=

1 IS11I IS22I +II >1 2IS12S21I

(6)

and

L < 1 S S S22 + 12 21 S < 1 for S < 1 1 S S11

1 |S11 | 2 |S22| 2 +|| 2 2 S12 S21

(10)

(11)

Where

= S11 S22 S12S 21

(7)

They translate back in the K factor and the B1 factor:

When the device is simultaneously conjugatively matched, the maximum transducer gain is obtained with the following formula:

K=
And either:

>1

(12)

S Gmax= 21 (K K 2 1) S12

(8) or

= S11 S22 S12 S21 <1 B1 = 1+ S11 2 S22 2 2 >0

(13) (14)

This is the Maximum Available Gain (MAG) provided by device manufacturers and is only valid when K>1. If additionally, |#|<1, the device is unconditionally stable and Gmax will be achieved. When K<1, the transistor is potentially unstable and Gmax does not exist. However, we can see that as K$1 and K>1, Gmax converge towards a value called the

In the circuit design shown in the following sections, care was taken to carry an unconditionally stable circuit by adding a shunt resistance to ground on the output (See the output resistor R1 of schematic of Figure 2). This stabilizing network represents an acceptable compromise between out-

AN1022
put power, gain levels and stability. With such a narrow band design, it is always important to verify the stability issue over a broad frequency range (from 100 MHz to 10 GHz, in this case). MAXIMUM GAIN DESIGN Using these matching techniques on the NE34018 in the band of interest, the circuit was modeled using Libra as a linear simulator (Figure 2) with bias conditions of 3V, 20 mA. The lumped elements were all modeled using lossy elements with a finite Q factor. The topology chosen was a high pass filter on both input and output so that the designer would have better control over the impedance presented out of band at lower frequencies. At these frequencies, these filters present a mismatch with a controlled phase quantity that is chosen to avoid oscillation, they also improve stability by reducing the amount of gain generated by the device and buffer the device from the systems out of band impedances. Finaly, this type of configuration also provides DC isolation on the input and output, further reducing the need for extra components. The simulated gain and input/output return loss performance are presented in Figure 3. The input load presented to the device, S11 of the device and the noise circles are shown in Figure 4. This match yields an excellent return loss (better than 20 dB) with a noise figure of 1.5 dB because the optimal impedance !Opt was not presented. The circuit fabricated as seen in Figure 5 with only five matching elements (DC supply not included) and real estate that could have been limited to 0.250 by 0.250. The actual performance is summarized in Figure 6 at 3 V, 20 mA, and Figure 7 at 3V, 30 mA. Although power was neither simulated nor designed for, the power performance and IP3 were measured and are presented in Figures 8 to 11. Table 2 summarizes the design goals, simulated performance and actual laboratory results. Note that the simulated and actual performance of the circuit match well. However, lumped element matching values utilized to correlate these did not track exactly. This is because the simulation of the DC bias network beyond the RF Ground (C4 and C5 on the assembly drawing) was omitted, and most of the lumped capacitor have a low self-resonance, consequently they no longer act as pure capacitance. For example, a 12 pF capacitor had a self resonance around 1.5 GHz and had a definite inductive behavior beyond self-resonance. Minor tuning had to be performed to define the final circuit match. Once the optimal tuning was achieved, it was also shown that the design performance had little sensitivity to biasing. With an increased bias current, all parameters but noise figure improved. Finally, as expected, the resulting Noise Figure was not low enough for a first stage Low Noise Amplifier, despite the very low minimum noise figure inherent to the device. However, the next section will prove that an excellent performance can be achieved with the proper match.
1 (The MAG or MSG values are provided by California Eastern

LOW NOISE MATCH A low noise amplifier (LNA) design minimizes the noise figure of its active device by presenting an optimal source reflection coefficient !S(Opt)while the output circuit is designed for flat gain and overall stability to the circuit. It is a particular case of the Gain Match theory described earlier in that the input load is fixed and defined by the active devices noise parameters (specifically !S(Opt), and the designer has to adjust accordingly the output match to achieve both gain criteria and stability. With an arbitrary source load, !S, the device yields a noise figure, NF, given by:

NF = NFmin+

(15) Where rn=RN/50 is the equivalent noise resistance usually provided with the noise parameters by device manufacturers. From (15), it is clear that NF = NFmin when !S = !S(Opt) Noise figure can also be expressed as:

4rn I S (Opt) I 2 1+ [1 S 2 ] S(Opt)

2

NF=NF min+

RN S

[ (G - G
S

S (Opt)

) + (BA-BS(Opt) )

(16) Consequently, the noise expression can be simplified to: NF = NFmin + #NF (17) Where the term #NF is a measure of the additional noise generated by a source mismatched, !S, compared to the optimal source !S(Opt). Equation (16) shows that noise figure contours with constant value NFi can be defined as circles centered on: (18) C NF = S(Opt)

1+Ni

2 Ni -NFmin - 1+S(Opt) = S S(Opt)2 Where Ni = 4rn 1- S

(19)

This formula represents the amount of mismatch from the optimal load for a given value of NFi. The associated radius can then be calculated as follows: (20) In practical application, if NFi=NFmin, then CNF = !S(Opt), the radius of the circle is rNF=0 and the device is matched to its minimum noise figure. On the other hand, as seen previously in Part 2, because the device is not matched to the optimal load, a mismatch loss will result, decreasing the circuit gain by a few dB to the associated gain. In a cascaded design, careful consideration should be given to achieve a compromise between noise and gain performance since the noise figure of subsequent amplifier stages will affect the overall performance of the system but will be reduced by a higher gain in the first stage.

rNF =

1 2 2 1+Ni Ni +Ni (1- S(Opt) )

Labs in the Design Parameter Library for all NEC devices.)

AN1022
CAPQ C1 C = Cin Q = 200 F = 100 MOD = prop_to_sqrt_f CAPQ C2 C = Cout Q = 200 F = 100 MOD = prop_to_sqrt_f

S2P SNP2 FILE = n34018h

ML IN TL 2 W = 50 L = 600 MSUB = MSUB_1

PORT ML IN IND P1 TL 1 L1 port = 1 W = 50 L = Lin L = 600 MSUB = MSUB_1

ML IN TL 3 W = 50 L = 100 MSUB = MSUB_1 ML IN TL 9 W = 25 L = 75 MSUB = MSUB_1 CAPP C3 C = 120 TAND = 5.00e-03 Q = 200 FQ = 20 FR = 25

ML IN TL 4 W = 50 L = 100 MSUB = MSUB_1

IND L2 L = Lout ML IN TL 10 W = 25 L = 75 MSUB = MSUB_1 CAPP C4 C = 120 TAND = 5.00e-03 Q = 200 FQ = 20 FR = 25

RES R1 R = Rout

PORT P2 port = 2

IND L3 L = 0.10

VAR _VAR Cin = 1.20 unconst Rout = 100 unconst Lin = 2.20 unconst Cout = 3.50 unconst Lout = 3.30 unconst

Figure 2: Maximum Gain Amplifier. Cimulation circuit 1.

Max_Gain_tb SIJ1 Max_Gain_Amp S [ 1,1 ] dB

Var Eqn

Max_Gain_tb SIJ3 Max_Gain_Amp S [ 2,2 ] dB

Max_Gain_tb SIJ2 Max_Gain_Amp S [ 2,1 ] dB

5.0 0.0 M1 -5.0 M2

19.0
0.5

1.0 2.0 M1 0.2 5.0

18.0

17.0

-10.0 -15.0

16.0 15.0

0.0 0.0

0.2

0.5

1.0

2.0

5.0

0.0

-20.0 M4 -25.0 -30.0 M3 1.0 M1 M2 M3 M4 Frequency 0.5 GHz / DIV Frequency = 1.93000000 Frequency = 1.99000000 Frequency = 1.93000000 Frequency = 1.99000000 3.0

14.0

-j0.2 M2 -0.5 -1.0

Frequency 1.0 to 3.0
Device testing tb S1J1 NE34018 S[11] Max Gain tb S1J3 Input Match S[22] 1 fq device tb NCIRC1 NE34018 NCIRC +0.00dB 1 fq device tb NCIRC1 NE34018 NCIRC +0.10 dB 1 fq device tb NCIRC1 NE34018 NCIRC +0.25 dB

-5.0

13.0 12.0

-2.0

value = 17.4271848 value = 17.0672716 value = -27.2875339 value = -23.2566723

1 fq device tb NCIRC1 NE34018 NCIRC +0.50 dB

M1 : Input Matching network load to the device at 2 GHz M2 : S11 parameter of the OUT at 2 GHz

Figure 3. Max Gain amplifier simulation results.

Figure 4: S-parameter, matching network and noise circles.

AN1022

18 Package - EVAL

J1 C2 L1 C5 C6 C7 U1 C1 L2 R1 C4

J2

C8

100407
C9

P1 GND Vg VD

EVALUATION BOARD PARTS LIST, HIGH GAIN MATCH

QTY 1 1 1 1 1 1 1 2 2 2 1 3 2 1 PART OR IDENTIFYING NO. SD-100407 TF-100413 LL 1608-FHIN8S LL 1608-FH3N3S MCR03J271 MCH185A1R5CK MCH185A2R2CK MCH185A121JK MCH185C102KK 881-6116 NE34018 2340-6111 TG 2052-1215-00 FD-100407 L2 L1 R1 C2 C1 C4, C5 C6, C7 C8, C9 U1 P1 J1, J2 PCB NOMENCLATURE OR DESCRIPTION MATERIAL/SPECIFICATION Schematic Diagram NE34018-EVAL NE34018-EVAL Test Fixture Block 1.8 nH Inductor TOKO 1.2 nH Inductor TOKO 0603 270 OHM RES ROHM 0603 1.8pF CAP ROHM 0603 2.2pF CAP ROHM 0603 120pF CAP ROHM 0603 1000pF CAP ROHM 4.7 F CAP AVX IC NEC, HJ-FET Pin Header 3M OSM JACK OMNI SPECTRA 18 Package-EVAL Fabrication Drawing ITEM NO. 14 13 12 11 10 9 8 7 6 5 4 3 2 1

EVALUATION BOARD PARTS LIST, LOW NOISE FIGURE MATCH

QTY 1 1 1 1 1 1 1 2 2 2 1 3 2 1 PART OR IDENTIFYING NO. SD-100407 TF-100413 LL 1608-FHIN8S LL 1608-FH3N3S MCR03J271 MCH185A1R5CK MCH185A2R2CK MCH185A121JK MCH185C102KK 881-6116 NE34018 2340-6111 TG 2052-1215-00 FD-100407 L2 L1 R1 C2 C1 C4, C5 C6, C7 C8, C9 U1 P1 J1, J2 PCB NOMENCLATURE OR DESCRIPTION MATERIAL/SPECIFICATION Schematic Diagram NE34018-EVAL NE34018-EVAL Test Fixture Block 1.8 nH Inductor TOKO 3.3 nH Inductor TOKO 0603 270 OHM RES ROHM 0603 1.5pF CAP ROHM 0603 2.2pF CAP ROHM 0603 120pF CAP ROHM 0603 1000pF CAP ROHM 4.7 F CAP AVX IC NEC, HJ-FET Pin Header 3M OSM JACK OMNI SPECTRA 18 Package-EVAL Fabrication Drawing ITEM NO. 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Figure 5: NE34018 Evaluation Board.

AN1022
S21 (dB) 19 18 17 16 15 14 13 12 11 10 START 1 GHz S22 1 1 2 2 0 1
34018_pwr_tb Pout 34018_eval_bd_sch PF dBm 40.0 Frequency, GHz 2.0 20.0 Output Power 34018_ip3_tb P2F1_F2 34018_eval_bd_sch PF dBm 34018_ip3_tb P3F2_2FtW 34018_eval_bd_sch PF dBm

1. 1.93 GHz S11 : -27.53 dB S21 : 17.075 dB S22 : -25.036 dB 2. 1.99 GHz S11 : -19.78 dB S21 : 16.485 dB S22 : -24.655 dB Bias Conditions 3 V, 20 mA

Output Power and Harmonics (dBm)

0.0 -20.0

3rd Harmonic 5th Harmonic

S11, S22 -5 (dB) -10 S11 -15 S22 -20 -25 STOP 3 GHz

-40.0

-60.0

-80.0 -100.0 -25.0

-20

-15 -10 Input Power (dBm)

-5

0.0

Figure 6: Maximum Gain Amplifier test results, 3 V, 20 mA.

20 19 18 17 16 S21 15
(dB)

14 13 12 11

10

Figure 7:

;y y ;y ;y ;y ; ;;;;;; yyyyyy ;y y ;y ;y ;y ; yyyyyy ;;;;;; ;y y ;y ;y ;y ; yyyyyy ;;;;;; ;y y ;y ;y ;y ; yyyyyy ;;;;;; ;y y ;y ;y ;y ;

1 2

Figure 9: 2 GHz Evaluation Board, IP3 versus Pin sweep simulation.

20 G1 dB 15
Output Power (dBm) and Gain (dB)

1. 1.93 GHz S11: -48.658 S21: 17.257 dB S22: -30.427 dB

G3 dB P1 dB P3 dB

2. 1.99 GHz S11: -20.849 S21: 16.731 dB S22: -25.007 dB

10

Bias Conditions 3 V, 30 mA

S11, S22
(dB)

-5

-10 -15 -20 -25

S11 S22

-5

S21

-10 -25 -20 -15 -10 -5 Input Power, PIN (dBm) Pout @ 1 dB : Gain @ 1 dB : Pout @ 3 dB : Gain @ 3 dB : 12.485 15.426 13.228 13.412 0 5

START 1.000 000 000 GHz

STOP 3.000 000 000 GHz

Maximum Gain Amplifier test results, 3 V 0 mA.

Frequency : 2.00 GHz Vd : -0.000 V Id : 0.000 mA Bias # : 1 Source impedance : 50 % Load impedance : 50 %

Power Out Gain

34018_pwr_tb Pout 34018_eval_bd_sch PF dBm 20.0

34018_pwr_tb Pout 34018_eval_bd_sch PF dBm

Figure 10: 2 GHz evaluation board, Pout versus Pin sweep test results.
40 20 G1 dB P1 dB 10 0 -10

M1
15.0

Output Power, POUT (dBm) and Harmonics

M2 M3

20

0 -20

Output Power (dBm)

10.0

-30 -40

5.0

-40 -60

-50 -60 -70 -80 -90

0.0

-5.0 Frequency, GHz 2.0 -10.0 -25.0 Eval Board VDS = 3 V ID = 20 mA -20 -15 -10 Input Power (dBm) M1 Power = -25.0 dBm M2 Power = -3.10 dBm M3 P0wer = -3.10 dBm Value = 17.08 dB Value = 16.06 dB Value = 13 dBm -5 0 5.0

-80

-100

-25

-20

-15 -10 Input Power, PIN (dBm) Pout @ P1dB : 12.508 Gain @ P1dB : 15.542 Pout @ .01 dB : 13.744 Gain @ .01 dB : 13.98

-5

-100

Frequency : Vd : Id : Bias # :

2.00 GHz 3.0 V 20 mA 1

Figure 8: NE34018 evaluation board, Pin-Pout simulation.

Linear Gain Third Harmonic Output TOI Fifth Harmonic Noise Floor

Figure 11:

2 GHz Evaluation Board, IP3 versus Pin sweep test results.

Average (dBm) IM3 Average (dBm) IM5 Noise (dBm) Hi IM5

-20

AN1022
The same configuration as the optimum gain design was adopted for the low noise design (a high pass structure), and the simulation results using Libra are summarized in Tables 3 and 4 and presented in Figures 12, 13 and 14. As shown in Table 4, the noise figure performance drastically improves to 0.7 dB, the input return loss decreased to about -5 dB, and the gain by about 2 dB. Once again, these simulated results track very closely with actual laboratory testing, as seen in Figure 15. The noise figure consistently measured between 0.7 and 0.8 dB at 3V, 20 mA. Figure 5 also provides the final assembly drawing of the low noise amplifier design.

Frequency Range Gain Noise Figure Input Return Loss Output Return Loss Bias condition Real Estate Price in 100 K Quantities

(MHz) (dB) (dB) (dB) (dB) (dBc/Hz) (Mils*Mils) (US$)

Goals (1932-1990) 15 Min. 0.8 dB Max. N/A -15 Min. 3 V, 20 mA Max. 250*250 Less than $1

Simulation (1932-1990) 15 Min. 0.75 dB Max. -5 -17 Min. 3 V, 20 mA Max. N/A N/A

Test (1932-1990) 15.5 Min. 0.8 dB Max. -5 -16 Min. 3 V, 20 mA Max. 250*250 Less than $1

Table 3: Low Noise Design Performance: Goals, simulation and tests.

Max Gain_tb SI1J PCS Amplifier Frequency (GHz) 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 S[2,1] dB 12.0467 13.0367 13.8214 14.4192 14.8695 15.1816 15.3737 15.4657 15.4693 15.3946 15.2593 15.0835 14.8711 14.6317 14.3731 14.1018 13.8339 13.5609 13.2850 13.0082 12.7328

Max Gain_tb NF1 PCS Amplifier NF dB 1.2887 1.0898 0.9497 0.8507 0.7812 0.7337 0.6972 0.6845 0.6899 0.7088 0.7211 0.7331 0.7508 0.7725 0.7967 0.8222 0.8476 0.8717 0.8935 0.9118 0.9252

Max Gain_tb NFMIN1 PCS Amplifier NFMIN dB 0.7284 0.6543 0.6100 0.5869 0.5784 0.5798 0.6026 0.6310 0.6625 0.6958 0.7051 0.7177 0.7307 0.7439 0.7570 0.7700 0.7823 0.7941 0.8055 0.8164 0.8267

Max Gain_tb K1 PCS Amplifier K 1.0858 1.0832 1.0997 1.1328 1.1700 1.2131 1.2545 1.2893 1.3211 1.3563 1.3878 1.4253 1.4595 1.4906 1.5190 1.5444 1.5643 1.5818 1.6013 1.6229 1.6472

Table 4: NE34018 Low Noise Amplifier, optimized for Noise Figure.

AN1022
CAPQ C1 C = Cin Q = 200 F = 100 MOD = prop_to_sqrt_f CAPQ C2 C = Cout Q = 200 F = 100 MOD = prop_to_sqrt_f ML IN TL 2 W = 50 L = 462 MSUB = MSUB_1

S2P SNP2 FILE = n34018h

PORT ML IN IND P1 TL 1 L1 port = 1 W = 50 L = Lin L = 462 MSUB = MSUB_1

ML IN TL 3 W = 50 L = 152 MSUB = MSUB_1 ML IN TL 9 W = 25 L = 75 MSUB = MSUB_1 CAPP C3 C = 120 TAND = 5.00e-03 Q = 200 FQ = 20 FR = 25

ML IN TL 4 W = 152 L = 100 MSUB = MSUB_1

IND L2 L = Lout ML IN TL 10 W = 25 L = 75 MSUB = MSUB_1 CAPP C4 C = 120 TAND = 5.00e-03 Q = 200 FQ = 20 FR = 25

RES R1 R = Rout

PORT P2 port = 2

IND L3 L = 0.10

VAR _VAR Cin = 1.40 unconst Rout = 340.18 unconst Lin = 2.70 unconst Cout = 2.80 unconst Lout = 1.20 unconst

Figure 12: Low Noise Amplifier simulation circuit.

Var Eqn
2.00 1.75 1.50 1.25 1.00

Max Gain tb NF1 PCS Amplifier NF db

Max Gain tb SIJ2 PCS Amplifier S[2.1] db 20.0 M2M4 17.5 15.0
S11, S22 dB

Max Gain tb SIJ1 PCS Amplifier S[1.1] db 0.0

Max Gain tb SIJ3 PCS Amplifier S[2.2] db

Max Gain tb SIJ2 PCS Amplifier S[2.1] db 16.0 S21 dB

M3 -5.0 M1 15.0

Noise Figure (dB)

10.0 M1M3 7.5 5.0 2.5 0.0 1.0 1.5 2.0 Frequency (GHz) 2.5 3.0

Gain (dB)

12.5

-10.0

14.0

0.75 0.50 0.25 0.00

-15.0 M2 -20.0 1.0 3.0

13.0

12.0

M1 Frequency = 2.00000000 Value = -5.94497417 M2 Frequency = 2.00000000 Value = -17.4975031 M3 Frequency = 2.00000000 Value = 15.2592710

M1 M2 M3 M4

Frequency = 1.90000000 Frequency = 1.90000000 Frequency = 2.00000000 Frequency = 2.00000000

Value = 0.70883140 Value = 15.3945659 Value = 0.72105206 Value = 15.2592710

Figure 13: Noise Figure and gain simulation.

Figure 14: Input, output return loss and gain simulation.

AN1022
20 19 18 17 16 S21 (dB) 15 14 13 12 11

10

Figure 15: Evaluation board lab results.

;;;;;; yyyyyy y ;y ;y ;y ;y ; yyyyyy ;;;;;; y ;y ;y ;y ;y ; yyyyyy ;;;;;; y ;y ;y ;y ;y ; yyyyyy ;;;;;; y ;y ;y ;y ;y ; y ;y ;y ;y ;y ;

2 1

1. 1.93 GHz S11: -5.134 dB S21: 16.981 dB S22: -18.64 dB

22 20
Output Power (dBm) and Gain (dB)

G1 dB G3 dB E3 dB

50 45 40 P3 dB 35 30 25
Power Added Efficiency (%)
Average (dBm) IM3 Average (dBm) IM5

2. 1.99 GHz S11: -5.275 dB S21: 16.326 dB S22: -18.172 dB Bias Condition 3 V, 20 mA

18 16 14 12 10 8 6 4 2 0 -20 -15 -10 E1 dB

P1 dB

S21

-5

S11 (dB)

S11 -10 S22 -15 -20 -25

20 15 10 5 0 -5 0 5 Input Power, PIN (dBm)

START 1.000 000 000 GHz

STOP 3.000 000 000 GHz

Frequency : Vd : Id : Bias # :

2.00 GHz 3.252 V 20.061 mA 1

Pout @ 1 dB : Gain @ 1 dB : Eff @ 1 dB : Pout @ 3 dB : Gain @ 3 dB : Eff @ 3 dB :

14.875 20.865 34.625 16.08 18.825 42.057

Power Out Efficiency Gain

22 20
Output Power (dBm) and Gain (dB)

G1 dB E1 dB

E3 dB

50 45

Figure 17: Power matched device, Pout versus Pin sweep.

Power Added Efficiency (%)

18 16 14 12 10 8 6 4 2 0 -20 -15

G3 dB

40 35

P3 dB P1 dB

30 25 20 15 10 5 0

40 20
TOI Pavg - low (dBm) POUT (dBm)

20 0 -20 -40 -60 -80 -100

0 X -20 X -40 X -60 X -80 X X X

-10

-5

5
-100

Input Power, PIN (dBm) Frequency : Vd : Id : Bias # : 2.00 GHz 3.252 V 20.016 mA 1 Pout @ 1 dB : Gain @ 1 dB : Eff @ 1 dB : Pout @ 3 dB : Gain @ 3 dB : Eff @ 3 dB : 13.617 19.401 39.96 14.361 17.355 46.359 Power Out Efficiency Gain

-25

-20

-15

-10 PIN (dBm)

-5

Output Power (dBm) X Third Harmonic (dBm) Fifth Harmonic (dBm) Output IP3 (dBm)

Frequency: 2 GHz Bias: 3 V, 20 mA P1dB: 14.875 dBm P1dB Gain: 20.864

Figure 16: 2 GHz Small Signal matched device, Pout versus Pin sweep.

Figure 18. NE34018, 2 GHz, IP3 power matched performance.

AN1022
HIGH POWER MATCH Under normal circumstances, few low noise amplifier designers are concerned with the power performance of their amplifiers. However, the recent expansion of digital modulation schemes (such as QPSK or CDMA) has demanded new requirements such as a specified high linearity performance (or high output power). Since this paper focuses only on LNAs, the power amplifier design will not be addressed. However, the inter-modulation performance and some of the power concepts behind the Third Order Intercept Point (IP3) will be reviewed. In a small signal amplifier, the power levels are low enough that distortion is negligible, and the small signal model or S-Parameters can accurately characterize the device over a wide dynamic range. When the power levels increases to where the device nears saturation, distortion becomes a problem. The transistors parameters will vary appreciably over the signals cycle with the input power level. Consequently, the small signal model is no longer valid. The device no longer amplifies linearly, and harmonic components start to be significant. The power performance of the circuit in class A is calculated because the device remains turned on throughout the signals cycle under the quiescent bias point. As for the high gain and the low noise amplifier, the circuit matching will drive the overall performance of the amplifier. In this situation, the output match will have the most effect on the devices output power and once again the design will be a particular case of gain match theory. The output is fixed to an optimum load for output power while the input is designed for gain and stability criteria. If the device is biased at VCC and presented with an RF load, RL (also known as the load line), then the AC current generates a collector output voltage, Vout, with its DC component being VCC. The inherent size of the device will limit the maximum current that can be delivered (usually slightly above IDSS) and the breakdown voltages (influenced by the fabrication process of the device) will limit the voltage swing. Assuming the signal to be a sine wave, the output power delivered to the load will be: output capacitance of the device. There are several ways to identify such desired loads. DC characteristics and the output parasitics of the device can be used with Steven Cripps method [6] of defining the optimal match on the Smith chart. Another method is to use RF tuners to experimentally define the output impedance that will yield the best results. Figures 16 and 17 show such an experiment. In Figure 16, diode tuners are used to present the conjugate match to the device and record the corresponding P1dB and Psat (defined in this case as the 3 dB compression point) at 3V, 20 mA. Figure 17 exhibits the same device tuned with an optimal power load and the same conjugate source match. In this case, the 1 dB compression point improves by 1.3 dB and the saturated power by 1.7 dB. The load was changed from:

Conjugate = 0.54 < 24.4 to Z Opt = 0.45 < 72.4

Figure 18 exhibits the inter-modulation components of the device when presented with ZOpt. When the optimal output impedance is known, the designer can create his output matching network in the same way !Opt, S*11 or S*22 were reached and achieve optimal output power. It is important to notice that in order to avoid reducing output power performance, the stabilizing network will have to be in the input or relatively lossless.

CONCLUSION This paper describes three different design topologies available to engineers. These designs address amplifiers with a special focus on the PCS band for mobile communication applications. Illustrative examples have been developed and are available as evaluation boards from California Eastern Laboratories. These boards can be used to evaluate the performance of NEC devices. These specific designs address the high gain, low return loss amplifier and the low noise amplifier and use a limited number of matching elements and real estate. Combined with a low part cost, these approaches reduce the overall cost of such an amplifier to a minimum. From a design standpoint, simulators are useful and powerful tools, however, they can be difficult to use and time consuming when a number of variables need to be optimized. This paper reviews some of the analytical techniques that engineers use before simulating and optimizing their designs. When completed, accurate translation of the simulation must be imported into a layout and a test circuit, and this often leads to another round of tuning and optimization. However, this last round is usually minimal, and eventually, laboratory results match the simulation very closely. Part Two of this paper will describe how other techniques, such as series feedback, can be applied to offer an optimal compromise between low noise, excellent input return loss and acceptable IP3 performance for PCS applications.

P Out =

VOut < VCC 2RL 2R L

(20)

This represents the maximum output power that can be delivered by the device under the quiescent bias point (VCC, ICC) related by: ICC= VCC/RL. To optimize the power performance under a given bias point, the designer will have to define the appropriate RF load (both real and imaginary) for the circuit. The real part will be the load line, and the imaginary part must tune out the

AN1022 REFERENCES
[1] Tri T. Ha, Solid State Microwave Amplifier Design, John Wiley and Sons. Chapter 2. [2] R.E. Collins, Foundation of Microwave En gineering, McGraw-Hill. Chapter 5. [3] G. Gonzalez, Microwave Transistor Ampli fiers, Prentice Hall, 1984 [4] S. Satyanarayana, Designing of a Low-Noise Amplifier using HEMTs, RF Design, March 1994. [5] G. Capponi and P. Livreri, HEMT Tradeoffs Minimize LNA Design Time, Microwave and RF, November 1993 [6] S.C. Cripps, A theory for the prediction of GaAs FET load-pull contours, IEEE MTT-S Digest, 1983, pages 221-223.

California Eastern Laboratories

Exclusive Agents for NEC RF, Microwave and Optoelectronic semiconductor products in the U.S. and Canada 4590 Patrick Henry Drive, Santa Clara, CA 95054-1817 Telephone 408-988-3500 FAX 408-988-0279 Telex 34/6393 Internet: http:/WWW.CEL.COM Information and data presented here is subject to change without notice. California Eastern Laboratories assumes no responsibility for the use of any circuits described herein and makes no representations or warranties, expressed or implied, that such circuits are free from patent infingement.
California Eastern Laboratories 01/28/2003