Ordering number : ENA0429

CMOS IC

LC75835W
Overview

1/3, 1/4-Duty General-Purpose LCD Display Driver

The LC75835W is a 1/3, 1/4 duty general-purpose LCD display driver that can be used for displaying segments for mobile devices and other such products under the control of a microcontroller. In addition to being able to directly drive up to 136 LCD segments, the LC75835W can also control up to 16 general-purpose output ports. It incorporates an oscillation circuit that reduces the external resistors and capacitors used for oscillation.

Features
Either 1/4 or 1/3 duty can be selected with the serial control data. 1/4 duty drive: Up to 136 segments can be driven 1/3 duty drive: Up to 105 segments can be driven Either 1/3 or 1/2 bias can be selected with the serial control data. On, off, or blinking for each segment can be set with the serial control data. Serial data control of display switching in 40-bit units. (As a general rule, the display can be switched in 12 segment-units.) Serial data control of current on/off to the LCD drive bias voltage generation divider resistors. Serial data control of the power-saving mode based backup function and the all segments forced off function. Serial data control of switching between the segment output port and general-purpose output port functions. Buzzer control signals (1 channel) can be output from the general-purpose output port. Serial data control of the frame frequency of the common and segment output waveforms. Serial data control of the segment blinking frequency. Serial data control of switching between the internal oscillator operating mode and external clock operating mode. Serial data input supports CCB* format communication with the system controller. Independent VLCD for the LCD driver block (VLCD can be set to any voltage in the range 2.7 to 5.5 volts without regard to the logic block power supply VDD). The INH pin allows the display to be forced to the off state. Incorporation of an oscillator circuit

CCB is a trademark of SANYO Electric Co., Ltd. CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.

D1306HKIM 20060919-S00005 No.A0429-1/35

LC75835W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter Maximum supply voltage Symbol VDD max VLCD max Input voltage VIN1 VIN2 Output voltage Output current VOUT IOUT1 IOUT2 IOUT3 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD VLCD CE, CL, DI, INH, OSCI VLCD1, VLCD2 S1 to S35, COM1 to COM4, P1 to P16 S1 to S35 COM1 to COM4 P1 to P16 *1 Ta = 75C Conditions Ratings -0.3 to +4.5 -0.3 to +6.5 -0.3 to +4.5 -0.3 to VLCD+0.3 -0.3 to VLCD+0.3 300 3 5 100 -30 to +75 -55 to +125 mW C C V A mA V Unit V

Note: *1 The sum of output current through P1 to P16 must be 40mA or less. Allowable Operating Ranges at Ta = -30 to +75C, VSS = 0V
Parameter Supply voltage Symbol VDD VLCD Input voltage VLCD1 VLCD2 Input high-level voltage VIH1 VIH2 Input low-level voltage VIL1 VIL2 External clock operating frequency External clock duty cycle Data setup time Data hold time CE wait time CE setup time CE hold time High-level clock pulse width Low-level clock pulse width Rise time Fall time INH switching time fCK DCK tds tdh tcp tcs tch tH tL tr tf tc VDD VLCD VLCD1 VLCD2 CE, CL, DI, INH OSCI CE, CL, DI, INH OSCI OSCI external clock operating mode [Figure 4] OSCI external clock operating mode [Figure 4] CL, DI CL, DI CE, CL CE, CL CE, CL CL CL CE, CL, DI CE, CL, DI INH, CE [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 2][Figure 3] [Figure 5][Figure 6] 10 0.7VDD 0.7VDD 0 0 15 30 160 160 160 160 160 160 160 160 160 32.8 50 Conditions min 2.7 2.7 2/3VLCD 1/3VLCD Ratings typ max 3.6 5.5 VLCD VLCD 3.6 3.6 0.2VDD 0.2VDD 65 70 kHz % ns ns ns ns ns ns ns ns ns s V V V V Unit

No.A0429-2/35

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Electrical Characteristics for the Allowable Operating Ranges
Parameter Hysteresis Input high-level current Symbol VH IIH1 IIH2 Input low-level current IIL1 IIL2 Output high-level voltage VOH1 VOH2 VOH3 Output low-level voltage VOL1 VOL2 VOL3 Output middle-level voltage *2 VMID2 VMID3 VMID4 VMID5 LCD drive bias voltage VLCD1 VMID1 Pin CE, CL, DI, INH CE, CL, DI, INH OSCI CE, CL, DI, INH OSCI S1 to S35 COM1 to COM4 P1 to P16 S1 to S35 COM1 to COM4 P1 to P16 COM1 to COM4 S1 to S35 S1 to S35 COM1 to COM4 COM1 to COM4 VLCD1 1/3 bias II = 0A Current supply to bias voltage generation divider resistors Outputs open VLCD2 VLCD2 1/3 bias II = 0A Current supply to bias voltage generation divider resistors Outputs open VLCD12 VLCD1, VLCD2 1/2 bias II = 0A Current supply to bias voltage generation divider resistors Outputs open Oscillator frequency Current drain fosc IDD1 IDD2 IDD3 Internal oscillator circuit VDD VDD VDD Power-saving mode VDD = 3.3V normal mode External clock operating mode *3 VDD = 3.3V normal mode External clock operating mode *3 Serial data transfer *4 IDD4 IDD5 VDD VDD VDD = 3.3V normal mode Internal oscillator operating mode VDD = 3.3V normal mode Internal oscillator operating mode Serial data transfer *4 ILCD1 ILCD2 ILCD3 ILCD4 VLCD VLCD VLCD VLCD Power-saving mode VLCD = 5.0V output open Normal mode, 1/2 bias VLCD = 5.0V output open Normal mode, 1/3 bias VLCD = 5.0V output open Normal mode, current to bias voltage generation divider resistors shut off 85 55 1 170 110 135 270 A 50 100 5 Internal oscillator operating mode 236 295 354 1 10 kHz 1/2VLCD -0.03VLCD 1/2VLCD 1/2VLCD +0.03VLCD 1/3VLCD -0.03VLCD 1/3VLCD 1/3VLCD +0.03VLCD V 2/3VLCD -0.03VLCD 2/3VLCD 2/3VLCD +0.03VLCD 1/3 bias IO = 100A 1/3 bias IO = 20A 1/3 bias IO = 20A 1/3 bias IO = 100A VI = 3.6V VI = 3.6V VI = 0V VI = 0V IO = -20A IO = -100A IO = -1mA IO = 20A IO = 100A IO = 1mA 1/2 bias IO = 100A 1/2VLCD -0.9 2/3VLCD -0.9 1/3VLCD -0.9 2/3VLCD -0.9 1/3VLCD -0.9 -1.0 -1.0 VLCD-0.9 VLCD-0.9 VLCD-0.9 0.9 0.9 0.9 1/2VLCD +0.9 2/3VLCD +0.9 1/3VLCD +0.9 2/3VLCD +0.9 1/3VLCD +0.9 V V V Conditions min Ratings typ 0.1VDD 1.0 1.0 A max V A Unit

90

180

10

20

Note: *2 Excluding the bias voltage generation divider resistors (RLCD = 30k typ.) built in the VLCD1 and VLCD2. (See Figure 1.) Note: *3 External clock operating mode (fCK = 32.8kHz, VIH2 = VDD, VIL2 = 0V, rise/fall time = 20ns) Note: *4 Serial data transfer (data transfer frequency 2MHz, VIH1 = VDD, VIL1 = 0V, rise/fall time = 20ns)

No.A0429-3/35

LC75835W
VLCD Except these resistors. RLCD RLCD RLCD To the common and segment drivers

VSS VLCD1 RLCD = 30k (40%)

VLCD2

Figure 1 1. When CL is stopped at the low level

CE VIH1

VIL1

tH CL
VIH1 50% VIL1

tL

tr DI
VIH1 VIL1

tf

tcp

tcs

tch

tds

tdh

Figure 2 2. When CL is stopped at the high level

CE

VIH1

VIL1

tL CL tf DI tds

tH
VIH1 50% VIL1

tr
VIH1 VIL1

tcp

tcs

tch

tdh

Figure 3 3. OSCI pin clock timing in external clock operating mode

tCKH OSCI
VIH2 50% VIL2

tCKL

fCK =

1 tCKH+ tCKL

[kHz]

tCKH 100[%] DCK = tCKH+ tCKL

Figure 4

No.A0429-4/35

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Package Dimensions
unit : mm (typ) 3163B
9.0 7.0 36 37 25 24

48 1 0.5 (0.75) 12 0.18

13

7.0 9.0

0.15

1.7max

0.1

(1.5)

SANYO : SQFP48(7X7)

Pin Assignment

COM4/S35

COM3

S34

0.5

S33

S32

S31

S30

S29

S28

S27

S26

COM2 COM1 VDD VLCD VLCD1 VLCD2 VSS OSCI INH CE CL DI

36 37

25 24

S25

S24 S23 S22 S21 S20 S19 S18 S17 S16/P16 S15/P15 S14/P14

LC75835W

48 1

13 12

S13/P13

P1/S1

P2/S2

P3/S3

P4/S4

P5/S5

P6/S6

P7/S7

P8/S8

P9/S9

P11/S11

P10/S10

P12/S12

Top view

No.A0429-5/35

LC75835W
Block Diagram
COM4/S35 S16/P16

COM1

COM2

COM3

S2/P2

COMMON DRIVER INH

SEGMENT DRIVER & LATCH

OSCI VDD

CLOCK GENERATOR

CONTROL REGISTER

SHIFT REGISTER VLCD CCB INTERFACE

VSS VLCD1 VLCD2

DI

CL

CE

S1/P1

S17

S34

No.A0429-6/35

LC75835W
Pin Functions
Handling Symbol S1/P1 to S16/P16 S17 to S34 COM1 to COM3 COM4/S35 OSCI Pin No. 1 to 16 17 to 34 38 to 36 35 44 Function Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S16/P16 pins can be used as general-purpose output ports when so set up by the control data. Common driver output pins. The frame frequency is fo [Hz]. COM4/S35 can be used as segment output in 1/3 duty mode. External clock input pin. A 15 to 65kHz clock must be supplied to this pin in external clock operating mode. This pin must be connected to ground in internal oscillator operating mode. CE CL DI INH 46 47 48 45 Serial data transfer inputs. Must be connected to the controller. CE: Chip enable CL: Synchronization clock DI: Transfer data Display off control input INH = low (VSS) ...Display forced off S1/P1 to S16/P16 = low (VSS) (These pins are forcibly set to the general-purpose output port and held at the VSS level.) S17 to S34 = low (VSS) COM1 to COM3 = low (VSS) COM4/S35 = low (VSS) Shuts off current to the LCD drive bias voltage generation divider resistors. Stop the internal oscillation circuit. INH = high (VDD)...Display on However, serial data transfer is possible when the display is forced off. VLCD1 VLCD2 VDD VLCD VSS 41 Used to apply the LCD drive 2/3 bias voltage externally. Connect this pin to VLCD2 when using a 1/2-bias drive scheme. 42 Used to apply the LCD drive 1/3 bias voltage externally. Connect this pin to VLCD1 when using a 1/2-bias drive scheme. 39 40 43 Power supply pin for the logic circuit block. A power voltage of 2.7V to 3.6V must be applied to this pin. Power supply pin for the LCD driver block. A power voltage of 2.7V to 5.5 V must be applied to this pin. Power supply pin. Must be connected to ground. I OPEN I OPEN L I GND H I I I GND I GND O OPEN Active I/O O when unused OPEN

No.A0429-7/35

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Serial Data Transfer Formats
(1) 1/4 duty 1. When CL is stopped at the low level When the display data is transferred
CE CL DI
0 1 1 0 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215 D216 0 0 0 0 1 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

No.A0429-8/35

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CE CL DI
0 1 1 0 0 0 1 0 D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0 0 0 0 1 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 24 bit Fixed data 4 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 16 bit Fixed data 12 bit DD 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 16 bit Fixed data 12 bit DD 4 bit

When the control data is transferred

CE CL DI
0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16 Control data 48 bit

PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 Fixed data 4 bit DD 4 bit

Note: DD is the direction data. CCB address ....... "46H" D1 to D272 ......... Display data PC1 to PC16......... General-purpose output port state setting data PS1 to PS16 ......... Segment output port/general-purpose output port switching control data PZ0 to PZ4 ......... Buzzer control signal output selection data PZF ...................... Buzzer control signal frequency setting control data DR ...................... 1/3-bias drive or 1/2-bias drive switching control data DT ...................... 1/4-duty drive or 1/3-duty drive switching control data OC ...................... Internal oscillator operating mode/external clock operating mode switching control data FC0, FC1 ......... Common/segment output waveform frame frequency setting control data BF0, BF1 ......... Segment blinking frequency setting control data SC ...................... Segment on/off control data BC ...................... LCD drive bias voltage generation divider resistor current on/off control data BU ...................... Normal mode/power-saving mode control data

No.A0429-9/35

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2. When CL is stopped at the high level When the display data is transferred
CE CL DI
0 1 1 0 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215 D216 0 0 0 0 1 0 0 1 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

No.A0429-10/35

LC75835W
CE CL DI
0 1 1 0 0 0 1 0 D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0 0 0 0 1 0 1 0 Display data 24 bit Fixed data 4 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 Display data 16 bit Fixed data 12 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

CE CL DI
0 1 1 0 0 0 1 0 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Display data 16 bit Fixed data 12 bit DD 4 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

When the control data is transferred

CE CL DI
0 1 1 0 0 0 1 0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16 Control data 48 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 Fixed data 4 bit DD 4 bit

Note: DD is the direction data. CCB address ....... "46H" D1 to D272 ......... Display data PC1 to PC16......... General-purpose output port state setting data PS1 to PS16 ......... Segment output port/general-purpose output port switching control data PZ0 to PZ4 ......... Buzzer control signal output selection data PZF ...................... Buzzer control signal frequency setting control data DR ...................... 1/3-bias drive or 1/2-bias drive switching control data DT ...................... 1/4-duty drive or 1/3-duty drive switching control data OC ...................... Internal oscillator operating mode/external clock operating mode switching control data FC0, FC1 ......... Common/segment output waveform frame frequency setting control data BF0, BF1 ......... Segment blinking frequency setting control data SC ...................... Segment on/off control data BC ...................... LCD drive bias voltage generation divider resistor current on/off control data BU ...................... Normal mode/power-saving mode control data

No.A0429-11/35

LC75835W
(2) 1/3 duty 1. When CL is stopped at the low level When the display data is transferred
CE CL DI
0 1 1 0 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 0 0 0 0 0 0 0 0 0 0 1 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address Display data Fixed data DD 8 bit 18 bit 4 bit 10 bit

No.A0429-12/35

LC75835W
When the control data is transferred
CE CL DI
0 1 1 0 0 0 1 0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16 B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bit 48 bit

PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 Fixed data DD 4 bit 4 bit

Note: DD is the direction data. CCB address ....... "46H" D1 to D210 ......... Display data PC1 to PC16......... General-purpose output port state setting data PS1 to PS16 ......... Segment output port/general-purpose output port switching control data PZ0 to PZ4 ......... Buzzer control signal output selection data PZF ...................... Buzzer control signal frequency setting control data DR ...................... 1/3-bias drive or 1/2-bias drive switching control data DT ...................... 1/4-duty drive or 1/3-duty drive switching control data OC ...................... Internal oscillator operating mode/external clock operating mode switching control data FC0, FC1 ......... Common/segment output waveform frame frequency setting control data BF0, BF1 ......... Segment blinking frequency setting control data SC ...................... Segment on/off control data BC ...................... LCD drive bias voltage generation divider resistor current on/off control data BU ...................... Normal mode/power-saving mode control data

No.A0429-13/35

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2. When CL is stopped at the high level When the display data is transferred
CE CL DI
0 1 1 0 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data CCB address Display data DD 4 bit 8 bit 24 bit 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data CCB address Display data DD 4 bit 8 bit 24 bit 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data CCB address Display data DD 4 bit 8 bit 24 bit 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data CCB address Display data DD 4 bit 8 bit 24 bit 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data DD CCB address Display data 4 bit 4 bit 8 bit 24 bit

CE CL DI
0 1 1 0 0 0 1 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data CCB address Display data DD 4 bit 8 bit 24 bit 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0 Fixed B0 B1 B2 B3 A0 A1 A2 A3 data CCB address Display data DD 4 bit 8 bit 24 bit 4 bit

CE CL DI
0 1 1 0 0 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 0 0 0 0 0 0 0 0 0 0 1 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 DD CCB address Display data Fixed data 4 bit 8 bit 18 bit 10 bit

No.A0429-14/35

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When the control data is transferred

CE CL DI
0 1 1 0 0 0 1 0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16 Control data 48 bit B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit

PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 Fixed data 4 bit DD 4 bit

Note: DD is the direction data. CCB address ....... "46H" D1 to D210 ......... Display data PC1 to PC16......... General-purpose output port state setting data PS1 to PS16 ......... Segment output port/general-purpose output port switching control data PZ0 to PZ4 ......... Buzzer control signal output selection data PZF ...................... Buzzer control signal frequency setting control data DR ...................... 1/3-bias drive or 1/2-bias drive switching control data DT ...................... 1/4-duty drive or 1/3-duty drive switching control data OC ...................... Internal oscillator operating mode/external clock operating mode switching control data FC0, FC1 ......... Common/segment output waveform frame frequency setting control data BF0, BF1 ......... Segment blinking frequency setting control data SC ...................... Segment on/off control data BC ...................... LCD drive bias voltage generation divider resistor current on/off control data BU ...................... Normal mode/power-saving mode control data

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Serial Data Transfer Example
(1) 1/4 duty When 129 or more segments are used All 544 bits of serial data (including CCB address) must be sent.

8 bit 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3

56 bit PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16

PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 8 bit 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0 0 0 0 1 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215 D216 0 0 0 0 1 0 0 1 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1 D25 D26 D27 D28 D29 D30 D31 D32D33D34D35 D36D37D38D39D40D41D42D43D44D45D46D47D48 0 0 0 0 0 0 1 0 32 bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13D14D15D16D17D18D19D20D21D22D23D24 0 0 0 0 0 0 0 1

D49 D50 D51 D52 D53 D54 D55 D56D57D58D59 D60D61D62D63D64D65D66D67D68D69D70D71D72 0 0 0 0 0 0 1 1

D73 D74 D75 D76 D77 D78 D79 D80D81D82D83 D84D85D86D87D88D89D90D91D92D93D94D95D96 0 0 0 0 0 1 0 0

When fewer than 129 segments are used Depending on the number of segments used, 104 bits, 144 bits, 184 bits, 224 bits, 264 bits, 304 bits, 344 bits, 384 bits, 424 bits, 464 bits or 504 bits (including the CCB address) must be sent as serial data. However, the serial data (control data) shown in the figure below must be sent without fail.
8 bit 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 56 bit PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16

Note: After the above serial data is sent, the contents of the display data can be changed by transferring only the serial data (CCB addresses, display data, fixed data, and direction data) including the display data to be changed in 40-bit units.

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(2) 1/3 duty When 97 or more segments are used All 424 bits of serial data (including CCB addresses) must be sent.

8 bit 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3

56 bit PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16

PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 8 bit 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1 D25 D26 D27 D28 D29 D30 D31 D32D33D34D35 D36D37D38D39D40D41D42D43D44D45D46D47D48 0 0 0 0 0 0 1 0 32 bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13D14D15D16D17D18D19D20D21D22D23D24 0 0 0 0 0 0 0 1

D49 D50 D51 D52 D53 D54 D55 D56D57D58D59 D60D61D62D63D64D65D66D67D68D69D70D71D72 0 0 0 0 0 0 1 1

D73 D74 D75 D76 D77 D78 D79 D80D81D82D83 D84D85D86D87D88D89D90D91D92D93D94D95D96 0 0 0 0 0 1 0 0

When fewer than 97 segments are used Depending on the number of segments used, 104 bits, 144 bits, 184 bits, 224 bits, 264 bits, 304 bits, 344 bits or 384 bits (including the CCB address) must be sent as serial data. However, the serial data (control data) shown in the figure below must be sent without fail.
8 bit 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0 56 bit PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16

Note: After the above serial data is sent, the contents of the display data can be changed by transferring only the serial data (CCB addresses, display data, fixed data, and direction data) including the display data to be changed in 40-bit units.

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Control Data Functions
1. PC1 to PC16: General-purpose output port state setting data This control data is used to set the H and L status of general-purpose output ports P1 to P16.
Output pin Control data P1 PC1 P2 PC2 P3 PC3 P4 PC4 P5 PC5 P6 PC6 P7 PC7 P8 PC8

Output pin Control data

P9 PC9

P10 PC10

P11 PC11

P12 PC12

P13 PC13

P14 PC14

P15 PC15

P16 PC16

Notes: PCn = 1: H (VLCD) is output from output pin Pn (n = 1 to 16). PCn = 0: L (VSS) is output from output pin Pn (n = 1 to 16). If, for instance, output pins S4/P4 and S5/P5 have been selected as the general-purpose output ports at PC4 = 1 and PC5 = 0, H (VLCD) is output from output pin P4 and L (VSS) is output from output pin P5. 2. PS1 to PS16: Segment output port/general-purpose output port switching control data This control data is used to switch between segment output ports and general-purpose output ports for the S1/P1 to S16/P16 output pins.
Output pin Control data S1/P1 PS1 S2/P2 PS2 S3/P3 PS3 S4/P4 PS4 S5/P5 PS5 S6/P6 PS6 S7/P7 PS7 S8/P8 PS8

Output pin Control data

S9/P9 PS9

S10/P10 PS10

S11/P11 PS11

S12/P12 PS12

S13/P13 PS13

S14/P14 PS14

S15/P15 PS15

S16/P16 PS16

Notes: PSn = 1: General-purpose output port Pn is selected for output pin Sn/Pn (n = 1 to 16). PSn = 0: Segment output port Sn is selected for output pin Sn/Pn (n = 1 to 16). If, for instance, PS1 to PS3 = 0, PS4, PS5 = 1 and PS6 to PS16 = 0, general-purpose output ports are selected for output pins S4/P4 and S5/P5 and segment output ports are selected for output pins S1/P1 to S3/P3 and S6/P6 to S16/P16. 3. PZ0 to PZ4: Buzzer control signal output selection data This control data is used to select the general-purpose output ports from which the buzzer control signals (square waves with a 50% duty ratio) are output.
Control data PZ0 1 0 1 0 1 0 1 0 PZ1 0 1 1 0 0 1 1 0 PZ2 0 0 0 1 1 1 1 0 PZ3 0 0 0 0 0 0 0 1 PZ4 0 0 0 0 0 0 0 0 General-purpose output ports from which buzzer control signals are output P1 P2 P3 P4 P5 P6 P7 P8 PZ0 1 0 1 0 1 0 1 0 PZ1 0 1 1 0 0 1 1 0 PZ2 0 0 0 1 1 1 1 0 PZ3 1 1 1 1 1 1 1 0 PZ4 0 0 0 0 0 0 0 1 Control data General-purpose output ports from which buzzer control signals are output P9 P10 P11 P12 P13 P14 P15 P16

Note: Data other than the data listed above must be set if the buzzer control signals are not to be output. For example, set (PZ0, PZ1, PZ2, PZ3, PZ4) = (0, 0, 0, 0, 0). 4. PZF: Buzzer control signal frequency setting control data This control data bit sets the frequency of the buzzer control signals (square waves with a 50% duty ratio).
PZF 0 1 Buzzer control signal frequency fz [Hz] fosc/144, fCK/16 fosc/72, fCK/8

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.)

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5. DR: 1/3 bias drive or 1/2 bias drive switching control data This control data bit selects either 1/3 bias drive or 1/2 bias drive.
DR 0 1 Bias drive scheme 1/3 bias drive 1/2 bias drive

6. DT: 1/4 duty drive or 1/3 duty drive switching control data This control data bit selects either 1/4 duty drive or 1/3 duty drive.
DT 0 1 Duty drive scheme 1/4 duty drive 1/3 duty drive Output pin (COM4/S35) status COM4 (common output) S35 (segment output)

7. OC: Internal oscillator operating mode/external clock operating mode switching control data This control data bit selects either internal oscillator operating mode or external clock operating mode.
OC 0 1 Basic clock operation mode Internal oscillator operating mode External clock operating mode Input pin (OSCI) status Must be connected to GND. The clock signal (15 to 65 [kHz]) must be input from an external source.

8. FC0, FC1: Common/segment output waveform frame frequency setting control data These control data bits set the frame frequency for common and segment output waveforms.
Control data FC0 0 1 0 1 FC1 0 0 1 1 1/4 duty drive fosc/5760, fCK/640 fosc/4608, fCK/512 fosc/3456, fCK/384 fosc/2304, fCK/256 Frame frequency fo [Hz] 1/3 duty drive fosc/5670, fCK/630 fosc/4536, fCK/504 fosc/3402, fCK/378 fosc/2268, fCK/252

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.) 9. BF0, BF1: Segment blinking frequency setting control data Theses control data bits control the segment blinking frequency.
Control data BF0 0 1 0 1 BF1 0 0 1 1 fosc/184320, fCK/20480 fosc/147456, fCK/16384 fosc/110592, fCK/12288 fosc/73728, fCK/8192 Segment blinking frequency fb [Hz]

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.) 10. SC: Segment on/off control data This control data bit controls the on/off state of the segments.
SC 0 1 Display state On Off

Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 11. BC: LCD drive bias voltage generation divider resistor current on/off control data This control data is used to turn on/off the current to the LCD drive bias voltage generation divider resistors.
BC 0 1 LCD drive bias voltage generation divider resister state Turns on current to the divider resistors. Turns off current to the divider resistors.

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12. BU: Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode.
BU 0 Normal mode Power-saving mode In internal oscillator operating mode (OC = 0), the oscillation of the internal oscillation circuit is stopped; in external 1 clock operating mode (OC = 1), the acceptance of the external clock is stopped. The common or segment output pins go to the VSS level. In addition, the current to the LCD drive bias voltage generation divider resistors is turned off. However, the output pins S1/P1 to S16/P16 can be used as general-purpose output ports (the output of a buzzer control signal is impossible.) under the control of control data bits PS1 to PS16. Mode

Display Data and Output Pin Correspondence

1. 1/4 duty
Output pin S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 S9/P9 S10/P10 S11/P11 S12/P12 S13/P13 S14/P14 S15/P15 S16/P16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 D1 D9 D17 D25 D33 D41 D49 D57 D65 D73 D81 D89 D97 D105 D113 D121 D129 D137 D145 D153 D161 D169 D177 D185 D193 D201 D209 D217 D225 D233 D241 D249 D257 D265 COM1 D2 D10 D18 D26 D34 D42 D50 D58 D66 D74 D82 D90 D98 D106 D114 D122 D130 D138 D146 D154 D162 D170 D178 D186 D194 D202 D210 D218 D226 D234 D242 D250 D258 D266 D3 D11 D19 D27 D35 D43 D51 D59 D67 D75 D83 D91 D99 D107 D115 D123 D131 D139 D147 D155 D163 D171 D179 D187 D195 D203 D211 D219 D227 D235 D243 D251 D259 D267 COM2 D4 D12 D20 D28 D36 D44 D52 D60 D68 D76 D84 D92 D100 D108 D116 D124 D132 D140 D148 D156 D164 D172 D180 D188 D196 D204 D212 D220 D228 D236 D244 D252 D260 D268 D5 D13 D21 D29 D37 D45 D53 D61 D69 D77 D85 D93 D101 D109 D117 D125 D133 D141 D149 D157 D165 D173 D181 D189 D197 D205 D213 D221 D229 D237 D245 D253 D261 D269 COM3 D6 D14 D22 D30 D38 D46 D54 D62 D70 D78 D86 D94 D102 D110 D118 D126 D134 D142 D150 D158 D166 D174 D182 D190 D198 D206 D214 D222 D230 D238 D246 D254 D262 D270 D7 D15 D23 D31 D39 D47 D55 D63 D71 D79 D87 D95 D103 D111 D119 D127 D135 D143 D151 D159 D167 D175 D183 D191 D199 D207 D215 D223 D231 D239 D247 D255 D263 D271 COM4 D8 D16 D24 D32 D40 D48 D56 D64 D72 D80 D88 D96 D104 D112 D120 D128 D136 D144 D152 D160 D168 D176 D184 D192 D200 D208 D216 D224 D232 D240 D248 D256 D264 D272

Note: The applies to the case where the S1/P1 to S16/P16 output pins are set to be segment output ports.

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For example, the table below lists the segment output states for the S11 output pin.
Display data D81 0 1 X 1 X 0 0 0 0 0 0 1 0 0 1 D82 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 D83 0 1 X 0 0 1 X 0 0 0 0 1 1 0 0 D84 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 D85 0 1 X 0 0 0 0 1 X 0 0 0 1 1 0 D86 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 D87 0 1 X 0 0 0 0 0 0 1 X 0 0 1 1 D88 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. The LCD segments for COM1, COM2, COM3, and COM4 are blinking. The LCD segment corresponding to COM1 is on. The LCD segments corresponding to COM2, COM3, and COM4 are off. The LCD segment for COM1 is blinking. The LCD segments corresponding to COM2, COM3, and COM4 are off. The LCD segment corresponding to COM2 is on. The LCD segments corresponding to COM1, COM3, and COM4 are off. The LCD segment for COM2 is blinking. The LCD segments corresponding to COM1, COM3, and COM4 are off. The LCD segment corresponding to COM3 is on. The LCD segments corresponding to COM1, COM2, and COM4 are off. The LCD segment for COM3 is blinking. The LCD segments corresponding to COM1, COM2, and COM4 are off. The LCD segment corresponding to COM4 is on. The LCD segments corresponding to COM1, COM2, and COM3 are off. The LCD segment for COM4 is blinking. The LCD segments corresponding to COM1, COM2, and COM3 are off. The LCD segments corresponding to COM1 and COM2 are on. The LCD segments corresponding to COM3 and COM4 are off. The LCD segments corresponding to COM2 and COM3 are on. The LCD segments corresponding to COM1 and COM4 are off. The LCD segments corresponding to COM3 and COM4 are on. The LCD segments corresponding to COM1 and COM2 are off. The LCD segments corresponding to COM1 and COM4 are on. The LCD segments corresponding to COM2 and COM3 are off. The LCD segment corresponding to COM1 is on. 1 0 X 1 0 0 0 0 The LCD segment for COM2 is blinking. The LCD segments corresponding to COM3 and COM4 are off. The LCD segment corresponding to COM2 is on. 0 0 1 0 X 1 0 0 The LCD segment for COM3 is blinking. The LCD segments corresponding to COM1 and COM4 are off. The LCD segment corresponding to COM3 is on. 0 0 0 0 1 0 X 1 The LCD segment for COM4 is blinking. The LCD segments corresponding to COM1 and COM2 are off. The LCD segment corresponding to COM4 is on. X 1 0 0 0 0 1 0 The LCD segment for COM1 is blinking. The LCD segments corresponding to COM2 and COM3 are off. Segment output pin (S11) state

Note: X: dont care

No.A0429-21/35

LC75835W
2. 1/3 duty
Output pin S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 S9/P9 S10/P10 S11/P11 S12/P12 S13/P13 S14/P14 S15/P15 S16/P16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35/COM4 D1 D7 D13 D19 D25 D31 D37 D43 D49 D55 D61 D67 D73 D79 D85 D91 D97 D103 D109 D115 D121 D127 D133 D139 D145 D151 D157 D163 D169 D175 D181 D187 D193 D199 D205 COM1 D2 D8 D14 D20 D26 D32 D38 D44 D50 D56 D62 D68 D74 D80 D86 D92 D98 D104 D110 D116 D122 D128 D134 D140 D146 D152 D158 D164 D170 D176 D182 D188 D194 D200 D206 D3 D9 D15 D21 D27 D33 D39 D45 D51 D57 D63 D69 D75 D81 D87 D93 D99 D105 D111 D117 D123 D129 D135 D141 D147 D153 D159 D165 D171 D177 D183 D189 D195 D201 D207 COM2 D4 D10 D16 D22 D28 D34 D40 D46 D52 D58 D64 D70 D76 D82 D88 D94 D100 D106 D112 D118 D124 D130 D136 D142 D148 D154 D160 D166 D172 D178 D184 D190 D196 D202 D208 D5 D11 D17 D23 D29 D35 D41 D47 D53 D59 D65 D71 D77 D83 D89 D95 D101 D107 D113 D119 D125 D131 D137 D143 D149 D155 D161 D167 D173 D179 D185 D191 D197 D203 D209 COM3 D6 D12 D18 D24 D30 D36 D42 D48 D54 D60 D66 D72 D78 D84 D90 D96 D102 D108 D114 D120 D126 D132 D138 D144 D150 D156 D162 D168 D174 D180 D186 D192 D198 D204 D210

Note: The applies to the case where the S1/P1 to S16/P16 and S35/COM4 output pins are set to be segment output ports.

No.A0429-22/35

LC75835W
For example, the table below lists the segment output states for the S11 output pin.
Display data D61 0 1 X 1 X 0 0 0 0 1 0 1 D62 0 0 1 0 1 0 0 0 0 0 0 0 D63 0 1 X 0 0 1 X 0 0 1 1 0 D64 0 0 1 0 0 0 1 0 0 0 0 0 D65 0 1 X 0 0 0 0 1 X 0 1 1 D66 0 0 1 0 0 0 0 0 1 0 0 0 The LCD segments corresponding to COM1, COM2, and COM3 are off. The LCD segments corresponding to COM1, COM2, and COM3 are on. The LCD segments for COM1, COM2, and COM3 are blinking. The LCD segment corresponding to COM1 is on. The LCD segments corresponding to COM2 and COM3 are off. The LCD segment for COM1 is blinking. The LCD segments corresponding to COM2 and COM3 are off. The LCD segment corresponding to COM2 is on. The LCD segments corresponding to COM1 and COM3 are off. The LCD segment for COM2 is blinking. The LCD segments corresponding to COM1 and COM3 are off. The LCD segment corresponding to COM3 is on. The LCD segments corresponding to COM1 and COM2 are off. The LCD segment for COM3 is blinking. The LCD segments corresponding to COM1 and COM2 are off. The LCD segments corresponding to COM1 and COM2 are on. The LCD segment corresponding to COM3 is off. The LCD segments corresponding to COM2 and COM3 are on. The LCD segment corresponding to COM1 is off. The LCD segments corresponding to COM1 and COM3 are on. The LCD segment corresponding to COM2 is off. The LCD segment corresponding to COM1 is on. 1 0 X 1 0 0 The LCD segment for COM2 is blinking. The LCD segment corresponding to COM3 is off. The LCD segment corresponding to COM2 is on. 0 0 1 0 X 1 The LCD segment for COM3 is blinking. The LCD segment corresponding to COM1 is off. The LCD segment corresponding to COM3 is on. X 1 0 0 1 0 The LCD segment for COM1 is blinking. The LCD segment corresponding to COM2 is off. Segment output pin (S11) state

Note: X: dont care

No.A0429-23/35

LC75835W
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz] VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V

COM1

COM2

COM3

COM4

LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.

LCD driver output when only LCD segments corresponding to COM1 are on.

LCD driver output when only LCD segments corresponding to COM2 are on.

LCD driver output when LCD segments corresponding to COM1 and COM2 are on.

LCD driver output when only LCD segments corresponding to COM3 are on.

LCD driver output when LCD segments corresponding to COM1 and COM3 are on.

LCD driver output when LCD segments corresponding to COM2 and COM3 are on.

LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on.

LCD driver output when only LCD segments corresponding to COM4 are on.

LCD driver output when LCD segments corresponding to COM2 and COM4 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.

Control data FC0 0 1 0 1 FC1 0 0 1 1

Frame frequency fo [Hz] fosc/5760, fCK/640 fosc/4608, fCK/512 fosc/3456, fCK/384 fosc/2304, fCK/256

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.)
No.A0429-24/35

LC75835W
Output Waveforms (1/4-Duty 1/2-Bias Drive Scheme)
fo[Hz] VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V

COM1

COM2

COM3

COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.

Control data FC0 0 1 0 1 FC1 0 0 1 1

Frame frequency fo [Hz] fosc/5760, fCK/640 fosc/4608, fCK/512 fosc/3456, fCK/384 fosc/2304, fCK/256

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.)

No.A0429-25/35

LC75835W
Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]

COM1

COM2

COM3

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are off.

LCD driver output when only LCD segments corresponding to COM1 are on.

LCD driver output when only LCD segments corresponding to COM2 are on.

LCD driver output when LCD segments corresponding to COM1 and COM2 are on.

LCD driver output when only LCD segments corresponding to COM3 are on.

LCD driver output when LCD segments corresponding to COM1 and COM3 are on.

LCD driver output when LCD segments corresponding to COM2 and COM3 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V

Control data FC0 0 1 0 1 FC1 0 0 1 1

Frame frequency fo [Hz] fosc/5670, fCK/630 fosc/4536, fCK/504 fosc/3402, fCK/378 fosc/2268, fCK/252

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.)

No.A0429-26/35

LC75835W
Output Waveforms (1/3-Duty 1/2-Bias Drive Scheme)
fo[Hz] VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V

COM1

COM2

COM3

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are off.

LCD driver output when only LCD segments corresponding to COM1 are on.

LCD driver output when only LCD segments corresponding to COM2 are on.

LCD driver output when LCD segments corresponding to COM1 and COM2 are on.

LCD driver output when only LCD segments corresponding to COM3 are on.

LCD driver output when LCD segments corresponding to COM1 and COM3 are on.

LCD driver output when LCD segments corresponding to COM2 and COM3 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

Control data FC0 0 1 0 1 FC1 0 0 1 1

Frame frequency fo [Hz] fosc/5670, fCK/630 fosc/4536, fCK/504 fosc/3402, fCK/378 fosc/2268, fCK/252

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.)

No.A0429-27/35

LC75835W
The INH pin and Display Control
Since the IC internal data (1/4 duty: the display data D1 to D272 and the control data, 1/3 duty: the display data D1 to D210 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (This sets the S1/P1 to S16/P16, S17 to S34, COM1 to COM3, and COM4/S35 to the VSS level.) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless displays at power on. (See Figures 5 and 6.)

Notes on the Power On/Off Sequences

Applications should observe the following sequences when turning the LC75835W power on and off. (See Figures 5 and 6) At power on: Logic block power supply (VDD) on LCD driver block power supply (VLCD) on At power off: LCD driver block power supply (VLCD) off Logic block power supply (VDD) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. 1. 1/4 duty
t2 t1 VDD VLCD INH tc CE PC1 to PC16,PS1 to PS16, Internal data PZ0 to PZ4,PZF,DR,DT,OC, FC0,FC1,BF0,BF1,SC,BC,BU Internal data (D1 to D24) Display data and control data transfer Undefined

Defined

VIL1

t3

VIL1

Undefined

Undefined

Defined

Undefined

Internal data (D25 to D48)

Undefined

Defined

Undefined

Internal data (D241 to D256)

Undefined

Defined

Undefined

Internal data (D257 to D272)

Undefined

Defined

Undefined

Note: t10 t2>0 t30 (t2>t3) tc10s min Figure 5

No.A0429-28/35

LC75835W
2. 1/3 duty
t1 VDD VLCD INH tc CE PC1 to PC16,PS1 to PS16, Internal data PZ0 to PZ4,PZF,DR,DT,OC, FC0,FC1,BF0,BF1,SC,BC,BU Internal data (D1 to D24) Display data and control data transfer Undefined t2

Defined

VIL1

t3

VIL1

Undefined

Undefined

Defined

Undefined

Internal data (D25 to D48)

Undefined

Defined

Undefined

Internal data (D169 to D192)

Undefined

Defined

Undefined

Internal data (D193 to D210)

Undefined

Defined

Undefined

Note: t10 t2>0 t30 (t2>t3) tc10s min

Figure 6

No.A0429-29/35

LC75835W
Notes on Controller Transfer of Display Data
Since the LC75835W accepts the display data (D1 to D272) divided into 12 separate transfer operations when using 1/4 duty drive scheme and data (D1 to D210) divided into 9 separate transfer operations when using 1/3 duty drive scheme, we recommend that the applications transfer all of the display data within a period of less than 30ms to prevent observable degradation of display quality.

Generation of Buzzer Control Signal

A square wave with a 50% duty ratio is output from the general-purpose output port selected for the output of the buzzer control signal between the start and end of the buzzer control signal output. If, for example, general-purpose output port P1 has been selected as the output of the buzzer control signal (PC1 = 0, PS1 = 1), the waveform shown below will be output.
Tz Tz/2 P1 Beginning of buzzer control signal generation (Send control data PZ0, PZ1, PZ2, PZ3, PZ4 ("1,0,0,0,0"))
Control data PZF 0 1

Tz Tz/2 Tz/2 Tz/2

Tz Tz/2 Tz/2

Tz Tz/2

Tz/2

End of buzzer control signal generation (Send control data PZ0, PZ1, PZ2, PZ3, PZ4 ("0,0,0,0,0"))

Buzzer control signal frequency fz(=1/Tz)[Hz] fosc/144, fCK/16 fosc/72, fCK/8

Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency (32.8 [kHz] typ.)

Oscillation Stabilization Time of the Internal Oscillation Circuit

It must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100s (oscillation stabilization time) after oscillation has started.
Internal oscillation circuit Oscillation stopped Oscillation stabilization time (100 [s] max.) Oscillation operation (under normal conditions)

<Oscillation start> 1. If the INH pin status is switched from L to H when control data OC = 0 and BU = 0 2. If the control data BU is set from 1 to 0 when INH = H and control data OC = 0

No.A0429-30/35

LC75835W
Sample Application Circuit 1
1/4 Duty, 1/3 Bias (When the LCD drive bias voltage is not supplied from an external source)
(P1) (P2) (P16) General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V

VLCD VLCD1 VLCD2 C0.047F C C INH CE CL DI External clock input

P16/S16 S17

From the controller

*5 OSCI

S33 S34

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 0.

Sample Application Circuit 2

1/4 Duty, 1/3 Bias (When the LCD drive bias voltage is supplied from an external source)
(P1) (P2) (P16) General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V R

VLCD VLCD1

100kR1k C0.047F

R VLCD2 C C R INH CE CL DI External clock input

P16/S16 S17

From the controller

*5 OSCI

S33 S34

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 1.

LCD panel (up to 136 segments) No.A0429-31/35

COM1 COM2 COM3 S35/COM4 P1/S1 P2/S2

LCD panel (up to 136 segments)

COM1 COM2 COM3 S35/COM4 P1/S1 P2/S2

LC75835W
Sample Application Circuit 3
1/4 Duty, 1/2 Bias (When the LCD drive bias voltage is not supplied from an external source)
(P1) (P2) (P16) General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V

VLCD VLCD1 VLCD2 C INH CE CL DI External clock input

C0.047F

P16/S16 S17

From the controller

*5 OSCI

S33 S34

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 0.

Sample Application Circuit 4

1/4 Duty, 1/2 Bias (When the LCD drive bias voltage is supplied from an external source)

(P1) (P2) (P16)

General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V R 100kR1k C0.047F

VLCD VLCD1 VLCD2

P16/S16 S17

From the controller

INH CE CL DI External clock input

*5 OSCI

S33 S34

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 1.

LCD panel (up to 136 segments) No.A0429-32/35

COM1 COM2 COM3 S35/COM4 P1/S1 P2/S2

LCD panel (up to 136 segments)

COM1 COM2 COM3 S35/COM4 P1/S1 P2/S2

LC75835W
Sample Application Circuit 5
1/3 Duty, 1/3 Bias (When the LCD drive bias voltage is not supplied from an external source)
(P1) (P2) (P16) General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V

VLCD VLCD1 VLCD2 C0.047F C C INH CE CL DI External clock input P16/S16 S17

From the controller

*5 OSCI

S33 S34 COM4/S35

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 0.

Sample Application Circuit 6

1/3 Duty, 1/3 Bias (When the LCD drive bias voltage is supplied from an external source)

(P1) (P2) (P16)

General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V R

VLCD VLCD1

100kR1k C0.047F

R VLCD2 C C R INH CE CL DI External clock input

P16/S16 S17

From the controller

*5 OSCI

S33 S34 COM4/S35

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 1.

LCD panel (up to 105 segments) No.A0429-33/35

COM1 COM2 COM3 P1/S1 P2/S2

LCD panel (up to 105 segments)

COM1 COM2 COM3 P1/S1 P2/S2

LC75835W
Sample Application Circuit 7
1/3 Duty, 1/2 Bias (When the LCD drive bias voltage is not supplied from an external source)
(P1) (P2) (P16) General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V

VLCD VLCD1 VLCD2 C0.047F C INH CE CL DI External clock input P16/S16 S17

From the controller

*5 OSCI

S33 S34 COM4/S35

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 0.

Sample Application Circuit 8

1/3 Duty, 1/2 Bias (When the LCD drive bias voltage is supplied from an external source)

(P1) (P2) (P16)

General-purpose Output ports Used for functions such as backlight control

+3.3V

VDD VSS

+5V R 100kR1k C0.047F

VLCD VLCD1 VLCD2 P16/S16 S17

From the controller

INH CE CL DI External clock input

*5 OSCI

S33 S34 COM4/S35

*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = 0) has been selected; the clock must be input from an external source when the external clock operating mode (OC = 1) has been selected. *6: Control data BC must be set to 1.

LCD panel (up to 105 segments) No.A0429-34/35

COM1 COM2 COM3 P1/S1 P2/S2

LCD panel (up to 105 segments)

COM1 COM2 COM3 P1/S1 P2/S2

LC75835W

Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 2006. Specifications and information herein are subject to change without notice.

PS No.A0429-35/35