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ATARI'HOMECOMPUTER
SYSTEM

HARDWARE
MANUAL

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from the Corporal;on.

Every effort has been made to ensure that this manual accurately
documents this product of Lhe ATAR] Home Computer Division.
However, due to the ongoing irnprovement and update of the computer
software and haralware, ATARI, INC. cannot guarantee the accuracy
of printed naterial alter the date of publication and disclairns
I i r|\i I i +rr T^r ^h.n^6c
, a- r-r . - J r s , o r o n l s s l o n s .
 TABLE OF CONTENTS

I. I N T R O D U C T I o, N. . . . . .... . .. .I. I

II. D E S C R T P T T0OF NH A R D W A .R. .E ., . . . . . . . . . . . , . , . ..r1.I

. . . . . . . . . .' ,. . . . r rt.
B. POKEY......,. .........rr.23
c. S E R I APLORT........,.............,..,...II.25
D. I N T E R R US
PYTSTEM.....,,..............,,.1r.28
E, CONTRoLLERS,, . ....... .rr.30

III. H A R D W AR
REEC T S T E R
. .S
. ... . .. .. . ,. .. ... .. .....rr1.1

A. P A L . . . . .. . . . ... ... .. ,IIt.l

B. I N T E R R U PCTO N T R O 1 ., . .. . . . . . . . . . . . , . , . . I I I . 1
c. T v L 1 N EC O N T R o L . . . . . , . . . . . . . . , . . . . . . , 1 1 I . 3
D. GMPIIICS CoNTROL. . . . . . . . . . . . . , . . . . . . . . .III. 4
E. P L A Y E RASN DM I S S I L E S. ., . , . . . . , . . . . . . . . . I I 1 . 9
F. A l I D f O... . . . . . .. .. ,.. .IIL 12
G. K E Y B O A RaDn d S P E A K X R . .. . . . . . . . . . . . . . . . I 1 I . 1 5
11. S E R I A LP O R T. . . . . . . , . . . . . . . . . . , . . . . . . , . I r r . 1 7
I. C O N T R O L LPEORR T S , . . . . . . . . . . . . . . . . . . . . . . I I I . t9

rv, pRoeRAM...,...................IV.
s A l t p L ED I S P L A Y I

HAIDIIARERECISTER LISTS. . . . , . . , . . . . v t.
A. A'DRESS ORDER. ........,.....v.1
B. AI,PHABETICALORDER. ;.........,...,v,5

vr, F l c u R E S . . ..,.. , . . . . .. ... ,..vr.t

A. MEMoR MY Ap........,.....................vr. 1
B. N T S Ca n d P A LD I S P L A Y. . . . , , . . . . . . . . . . . . V I . 2
c. SCIIEMATICS.,. ,........vI.3
APPENDIX A: USE OF PLAYER/MISSII,E GRAPHICS
WITH BASIC

APPENDIX B: MlXlNG GRAPIIICS MODES

APPENDIX C: PINOUTS

1t
 I. INTRODUCTION

The ATARI (R) 800rM and ATARI 400rM Personal conputer systems
colrtaln a 6502 nlcroprocessor' 4 I/O chtps, operating systen ROI'I' expandable
R-Alt, and several MsI chlps for sddress decodlng and data bu8 bufferlrg.
Thls nernral ls prloarlly lntended to descrlbe the 4llo chtps tn sufficent
detall to a11ow experlenced plograd&exs to create assembly tanguage Prograrns'
such as vldeo ganes. A11 four Inpul/Ortp\rt chips are controlled by the
rnlcroprocessor by nrltlng dlrectly lnto thell reglsters $hlch are decoded
to exlst ln Elcroprocessol nenory space Just as RAM does. These l/o chtps
can also be interrogated by the nlcroprocessor by leadlng slrdlar reglsters'

!,lany reglsters are wllte only and cannot be read after they are
wrltten. In aone ceses, reading fron the same addless glves the value
contalned ln 4 separate read only reglster. Sone wrlte only reglsters are
gtrobes. No data blts are deeded ln thls case slnce lhe presence of the
address on the bus ls \rhat trtggers the requested actlon. The usual
. conventlon 1s to use the STA (Store Accufillator) hstructlon for such
reglsters. For exanple, STA WSYNC perforrns the ltait for Sync functlon'
STX (Store x) or STY (store Y) vould ltork lust as weL1. In BASIC' a P0KE
could be used (the data could be anythlng). Readlng a reglster ls accoDp-
115hed by using eny of the load instrrcllons (LDA' LDX etc'). Ifl BASIC
a PEEK would be used. When lhe hardltare register naEes are deflned 1n an
equate llst' the proglaxmer can refer to the registers by name ralher than
uslflg the addresses dtreclly.

It ls rea1ly not rreceasary fot the plograffner to kno{ $hlch

\:,- I/O functlons are perfolrned by lthtch of lhe 4 chlps' however lt
does help ln learnlng these functlofls.

Thls nanual should be used ln conluncllon rlth the Operatlng

Systen (oS) Manual, a 6502 prograoning narNal, and the 4343!]!qgl.g9g
Baslc Ref erellce I'I4tuaI.

CHIP T{AME fUNCTION

- ANTIC DMA(Dlrect llenory Access) control

NUl (Non-Maskab1e lnterlupt) control
Vertical and Horlzontal flne scrolllng
I-lght Pen Posltlon reglsters
Vertlcal l1ne counter
WSYNC (ltatl for hortzonlal sync)

CTIA Prlorlty control (display of overlapplag oblects)

Color-Lumlnance control (colors alrd brlghtness asslgned
to all oblects lttcludlng DMA objects fron ANTIC)
?LAYER-MISSIIEobJects (4 players and 4 ldsstles)
cre^h{ r a raoi.rarc
Slze control
l{orlzontal posltlon control
Col11slon detectlon beBteen all objects
S{ltches and lriggers (rnlscellaneous 1/0 functions)
CII1P NAI,IE FI]NCTION

POKEY Keyboard scan and conlrol

Ser1a1 com.lnicatlons port (bidtrectlonal)
Pot scan (digitlzes posltion of 8 tndependelt pots)
Audlo generatlon (4 chanllels)
Tlners
IRQ (na6kable inlerrupt) control fron pertpherals
Randon {runber generator

PIA Controller (Joysllck) lacks read ot write

Peripheral control and lnterrupt lines
IRQ (naskable) lnterrupt control from perirherats

Sectlon II descrtbes rhe hardware in sone deratl, lncludlng the

varlous graphics nodes. Sectlon III lists the hardrrare resisters orle a! a
tlne, describing whar each bit ts used for. It 1s organtzea by functional
groups (lnterruprs, graphlcs, audio, etc.). Section IV contatns a sanple
display plogtafi. Section V conlalns various flgures and block dtagrans of
the system. Sectlons VI and VII 11s! the hard\rare regtsters ln adilress
order and alphabetical order, Sectlon VII includes hex and decfidal
addresses, the OS shadon registers and the page ftrnbers i,,here nore infor_
nation can be found.

r,2
II. DESCRI?TION OF I{ARDWARE

ANTIC AND CTIA

TV Dlsplay: The ANTIC and CTIA chips generate the lelevlsi.on

dtsplay at the rate of 50 frardes per second on the NTSC (US) systein.
The PAL (European) systen ls dlfferent and ts descrtbed in the sectlon
on NTSC vs PAL. Each frame conslsts of 262 horizor.tal TV lines and each
11ne ls nade up of 228 color clocks, as sho\rn 1n figure rt-3, The 5502
Dlcroprocessor runs at 1.79 MHz. Thle rate was chosen so that one
nachine cycle ls equlvalenr ln length to tno color clocks. One clock
ls approxlnately eqral ln width to two TV 1lnes,

In any graphtcs node, the dlsplay is dtvided up lnto soafl sqrares

or rectangles called ptxel8 (plcture elenenle). The highest resolutlon
graphlcs Eode has a plxel slze of I/2 color clock by I Tv llne. A
Bample dlsplay llst la glven 1rl sectlon IV.

The current TV ltne nay be deternined by readlng the vertlcal counter

(VCoIJNT). Ttls reglster glves the llfle count dlvided by 2. 'I}:'ete are 262
l1nes pe! frarne so VCOUNTrufls fron 0 to 130 (0 to 155 on the PAL syste.0).
The 0 potnt occurs near the end of vertical blank (see flgure VI.5),
Verttcal blank (TELANK) 1s the tlne durlng uhlch the electron beaE returns
back to the top of the screen 1n prepaxatlon for lhe flext frane. The
Atarl 800 does not do lnterlaclng, so each frar@ ls ldentical unless
the plogran which ls belng executed changes the dlsplay. verllca1 sync
(vSYNc) occurs durlng the fourth rhrough slxth lines of vertlcdl blank
(VCoUNT = hex 7D through 7I). thls tel1s lhe TV set where each frane
stAits. AJter vsYNc, there are 16 oore 11nes of VBLANK fot a Lotal of 22
ttnes of \'BLANK. The dleplay 1lst Juop and walt lnstructlofl (to be
descrlbed later) causes the dlsplay llst graphlcs to start at lhe end of
VBLANK.

Operatlnq Svsten (0S): The ATARI 400/800 cones wtth a loK Operatlng
Systen (OS) ln ROM. The 0S affects sone of the hardware registers, so
it !d11 be Eentloned fron tltae to tlltre in lhis nanual. Refer lo the OS
nanual for nore deta11s. The 0S descrlpttons in thls na[ua1 apply to the
verslon lhat was belng dlslrlbuted when thls nanual I'as written.

The Os supports nost of the hardnare graphlcs loodes (BASICS, GRAPHICS'

PLoT, and DRAWTOcoEnands). Tte OS always dtsplays 24 background l1nes after
the erd of vertlcal blank. This conventlon 1s used at Atarl to compensate
for televlslon sets \lhlch overacant Most TV's are deslgned so lhat lhe
edges of the plcture are cut off, Thls ts flne for ordlnary broadcasts'
but ulth a conpuler 1t ls essential for all lnpotlan! infornatlon to be
dlsplayed on the screen. It is fairly cor0monfor four to elght colot
ctocks at lhe rtght or left edge of the plcture to overscan. A TV set
that has excesslve overscan rnay have !o readjusted to oblaln a satisfactory
dlaDlav.

II.1
 The 0S uses 192 TV llnes for its display and devotes the remalnlng
24 ltnes to overscanr It uses the standard dlsplay irldth of 160 color
clocks, The hard\rare will allo\r displays of any length, but it ts recon-
nended lhat the standards be followed. The exception night be a border
or other lnfornatlon whlch is nerely decota!1ve and not esse[tla1 to use
of the prograno.

.q,q_lleggjglqE: Since nany of the hard\,rare reglsters are write-only

and cannot be read the 0S has a mnber of "shadow registers'i in RAM.
Every TV frarne durlng vertical blank the OS takes lhe values ln sone of
its shadow registers, and wriles thero ou! to the correspondlng hardware
register. The 0S does attracr color shlfting on all of rhe color registers
ii ATRACT(on 0S reglsrer) is negatlve. This is to prevent da&age Eo rhe
TV screen phosphors h'trlch can occur 1f the brlghtness 1s turned up too hlgh
and the sante hlgh-luninance dlsplay is lef! on for a long tlne. The OS also
reads lhe Joysticks and other conrrollets during vertlcal blank and stores
lhe resulls 1n shadow reglsrers, so rhat user plograns do not have to tnclude
code to unpack the data. Ttere are a few interrupt-related reglsrers $hlch
lhe 0S changes or reads during inlerrupt processing. Prograr0s usually access
the OS shadow registers instead of accessing the hard\tare directly. Ho\rever,
the OS shadoirlng can be disabled by changtng the vertical blank and lnterrup!
veclors (see OS marlual).

l{!:Ig: In addirion to a Vertical Blank Interrupt, which allons rhe

I'Ilctoprocessor to s)'nchronlze to the vertical TV display, this systed also
provides a Walt for Horizontal Sync (WSYNC)cornnand rhat al1ows Ehe
lolcroprocessor to synchronlze ilself to lhe TV horlzontal line rate. Thts
sync takes effect \rhen the processor r.rrites to an I/O location ca11ed
WSYNC,\rhenever it deslres horizontal synchronizat lon. Wriling to thls
address sets a larch which pul1s to zero a pln on the lllctoprocessor
called REAIY. Idhen READYgoes to zeto the Elcroprocessor stops and \raits.
The lalch is autonatlcally reset (returning REAIY true) at the beglnnlng
of the next horizontal blank interval, releasing the nicroprocessor to
resunoe progran execution.

Obiect DMA (Direct Menorv Access): The primary functlon of the Antlc
chip ls to fetch data fron roenoty (independent of the nlcroprocessor) for
display on the TV screen. It does thls lrlth a lechnlqle called "Dlrect
Meoory Access" or Dl4A. It reqrests lhe use of the inenory address and dala
bus by sending a stgnal called HALT to lhe microprocessor, causlng the
processor to becoEe "TRI-STATE" (open circuit) all durlng the next cornputer
cycle. The ANTIC chlp lhen takes over rhe address blrs and reads any data
it r,rishes fron nenory. Another nan€ fo! Lhis rype of DMA 1s "cyc1e stealing".
Once lnitlated, this DMA is conpletely and autonatically conlrolled by lhe
Antlc chip Fithout need for futher microprocessor lnlervention.

There are l\ro types of Dl4A: Playfleld and Player-Missile (see Figure
1I.2). The playfield Dl4A control clrcult on the Antlc chip resernbles a
snall durnb drlcroprocessor. By halting the main nicroprocessor 1t can
fetch its ol'n instructions fron uernory (lhe dtsplay list) addressed by 1ts
program counter(d1splay llst poln!e.). Each instructlon defines the type
(alpha character or nemory nap), and the resolurlon (slze of bits on the
screen), and the Iolation of the data ln menoryL'hich is to be dtsplayed
group or rlnes.
II.2
 Ir ordel to begln thls DI,IA the natn nlcroprocessor lnrsE sEore a
dlsplay l1st of lnstructloos ln nenory, store data to be dlsplayed ln
tdenory, tell the ANTIC where the dlspfay ltst ls (hltlallze the display
1lst potnter) and enable the DMA control flags on the ANTIC (D}.IACTL
register).

In addttlon to the playfteld DlttA descrlbed above, the ANTIC

chlp slDrltaneously colttrols another DMA channel. Thls type of DMA
addressea PLAYER-MISSILE gr:aphics data stored ln neoory and passes the
graphlc8 dala on to the CTIA chip graphlcs reglsters. Thls type of DMA
(1f enabled) occurs antoDatlcally, lnterspersed nith the playfleld DMA
descrlbed prevlously. This ?LAYER-MISSILEDMAhas no dtsplay 1lst or
idstructions, and Is therefore rmlch slEpler than the PLAYFIELD Dl,lA.

III addltlon to the two rypes of dlsplay DMA, the ANTIC chlp also
generates DMA addresses for the refresh of rhe dynanlc nenory RrlM used
1n thls systen. Thla ia also coDpletely autollattc and need be constder-
ed by the programer only lf he ls concerned with real-tlue progrardolng
where an exact count of the conputer cycles 1s lrnportant.

Color-lunlnance I A colot-lumlnance register ls used on the CTIA chlp

for each Player-Mlssile and Playfleld type. Each color-lun reglster is
loaded by the nlcroprocessor \'lth a code representlng the deslred color
end lunlnance of lts correspondlng Player-Misslle or Playfleld type. As
the serlal data pss8es lhrough the CTIA chlp 11 1s 'rtmpressed" \rlrh the
color and hrninance values contalned ilr lhese registers, before being seflt
to the TV dlsplay. In areas of the screen where there are no objects lhe
background color (CoLBK) 1s displayed. The CTIA also does collisron
detectlon (to be descrtbed later;.

?rlorltv: ltren novlng oblects, such as playets and Btsslles,

overlap on the TV screen (with each other or wlth playfleld) a dectslon
ttlst be made as to whlch oblect shons 1n fronr of the othex. Objects
\rhlch appear to pa8s 1n flont of others are satd to have prloriry ower
them. Prlorlty ls asslgned ro aLl objecrs by rhe CTIA chlp befoie the
serlal data fron each object 1s conbtned rrtth the other oblects and sent
to the TV screen.

The prlority of objecls can be conlrolLed by the mtcroprocessor by

I'rltlng lnto the control reglster PRIOR. The functtons of the bits in
thls reglster are glven 1n rhe table 1n the ?RIoR regtsrer descrlption in
sectlon III.

Plavers and }llsslles: The players and nlssiles are snall objecLs
whlch car be moved qutckly in the hortzontal dlrecrlon by changing thelr
poeltlotl reglsters. They are called players and Eissiles because they
$ere orlglnally deslgned to be used ln games for objects such as ahplanes
and bullets. Itowever, there are nany other posstble appllcations for
then. The four player-rulsslle color registers, ln conjunclton l'lth the
four playfield color reglsters and the background color teglster, raake
It posslble !o dlsplay 9 different colors ar the sane ttr0e,

II.3
 obj ec!s = background)

MEMORY},IA?

con!!o11ed by
Displai ltst
lnstructlons

(DI,IACTL)

Playfleld
Dl,lA Erable

MICRO
PROCESSOR

I ' I E M O R Y

Ftgure 1I.2 O B J E C T D I S P I , A Y S O U R C ' S