TDA8950

2 150 W class-D power amplier

Rev. 02 11 June 2009 Product data sheet

1. General description
The TDA8950 is a high-efciency Class D audio power amplier. The typical output power is 2 150 W with a speaker load impedance of 4 . The TDA8950 is available in both HSOP24 and DBS23P power packages. The amplier operates over a wide supply voltage range from 12.5 V to 40 V and features low quiescent current consumption.

2. Features
I Pin compatible with TDA8920B for both HSOP24 and DBS23P packages I Symmetrical operating supply voltage range from 12.5 V to 40 V I Stereo full differential inputs, can be used as stereo Single-Ended (SE) or mono Bridge-Tied Load (BTL) amplier I High output power in typical applications: N SE 2 150 W, RL = 4 (VP = 37 V) N SE 2 170 W, RL = 4 (VP = 39 V) N SE 2 100 W, RL = 6 (VP = 37 V) N BTL 1 300 W, RL = 8 (VP = 37 V) I Low noise I Smooth pop noise-free start-up and switch off I Zero dead time switching I Fixed frequency I Internal or external clock I High efciency I Low quiescent current I Advanced protection strategy: voltage protection and output current limiting I Thermal FoldBack (TFB) I Fixed gain of 30 dB in SE and 36 dB in BTL applications I Fully short-circuit proof across load I BD modulation in BTL conguration

3. Applications
I I I I DVD Mini and micro receiver Home Theater In A Box (HTIAB) system High-power speaker system

NXP Semiconductors

TDA8950
2 150 W class-D power amplier

4. Quick reference data

Table 1. General, VP VP(ovp) Iq(tot) Quick reference data Conditions Operating mode Operating mode; no load; no lter; no RC-snubber network connected Tj = 85 C; LLC = 22 H; CLC = 680 nF (see Figure 10) THD + N = 10 %; RL = 4 ; VP = 39 V THD + N = 0.5 %; RL = 4 ; VP = 37 V THD + N = 10 %; RL = 4 ; VP = 37 V THD + N = 10 %; RL = 6 ; VP = 37 V Mono BTL conguration Po output power Tj = 85 C; LLC = 22 H; CLC = 680 nF (see Figure 10); RL = 8 ; THD + N = 10 %; VP = 37 V
[3] [3] [2]

Symbol Parameter VP[1] = 30 V supply voltage total quiescent current

Min

Typ

Max 40 90 75

Unit V V mA

12.5 35 85 50

overvoltage protection supply voltage Standby, Mute modes; VDD VSS

Stereo SE conguration Po output power

170 100 150 100 300 -

W W W W W

[1] [2] [3]

VP is the supply voltage on pins VDDP1, VDDP2 and VDDA. The circuit is DC adjusted at VP = 12.5 V to 32.5 V. Output power is measured indirectly; based on RDSon measurement; see Section 13.3.

5. Ordering information
Table 2. Ordering information Package Name TDA8950J TDA8950TH DBS23P HSOP24 Description plastic, heatsink small outline package; 24 leads; low stand-off height Version SOT566-3 plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 Type number

TDA8950_2

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TDA8950
2 150 W class-D power amplier

6. Block diagram
VDDA
3 (20)

n.c.
10 (4)

STABI PROT 18 (12) 13 (7)

VDDP2
23 (16)

VDDP1
14 (8) 15 (9)

BOOT1

IN1M IN1P

9 (3) 8 (2) INPUT STAGE PWM MODULATOR SWITCH1 CONTROL AND HANDSHAKE DRIVER HIGH 16 (10) DRIVER LOW VSSP1 OSCILLATOR MODE MANAGER TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION OUT1

n.c. OSC MODE

11 (5) 7 (1) 6 (23)

mute STABI

TDA8950TH (TDA8950J)

VDDP2 22 (15) BOOT2

SGND

2 (19) mute CONTROL SWITCH2 AND HANDSHAKE DRIVER HIGH 21 (14) DRIVER LOW 17 (11) 20 (13) OUT2

IN2P IN2M

5 (22) 4 (21) INPUT STAGE PWM MODULATOR

1 (18)

12 (6)

24 (17)

19 (-)

001aah653

VSSA

n.c.

VSSD

n.c.

VSSP1

VSSP2

Pin numbers in brackets refer to type number TDA8950J.

Fig 1.

Block diagram

TDA8950_2

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TDA8950
2 150 W class-D power amplier

7. Pinning information
7.1 Pinning

OSC IN1P IN1M n.c. n.c. n.c. PROT VDDP1 BOOT1

1 2 3 4 5 6 7 8 9

OUT1 10 VSSP1 11 VSSD 24 VDDP2 23 BOOT2 22 OUT2 21 VSSP2 20 n.c. 19 STABI 18 VSSP1 17 OUT1 16 BOOT1 15 VDDP1 14 PROT 13
001aah654

1 2 3 4 5

VSSA SGND VDDA IN2M IN2P MODE OSC IN1P IN1M

STABI 12 VSSP2 13 OUT2 14 BOOT2 15 VDDP2 16 VSSD 17 VSSA 18 SGND 19 VDDA 20 IN2M 21 IN2P 22 MODE 23

TDA8950J

TDA8950TH

6 7 8 9

10 n.c. 11 n.c. 12 n.c.

001aah655

Fig 2.

Pin conguration TDA8950TH

Fig 3.

Pin conguration TDA8950J

TDA8950_2

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TDA8950
2 150 W class-D power amplier

7.2 Pin description

Table 3. Symbol VSSA SGND VDDA IN2M IN2P MODE OSC IN1P IN1M n.c. n.c. n.c. PROT VDDP1 BOOT1 OUT1 VSSP1 STABI n.c. VSSP2 OUT2 BOOT2 VDDP2 VSSD Pin description Pin TDA8950TH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TDA8950J 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 negative analog supply voltage signal ground positive analog supply voltage channel 2 negative audio input channel 2 positive audio input mode selection input: Standby, Mute or Operating mode oscillator frequency adjustment or tracking input channel 1 positive audio input channel 1 negative audio input not connected not connected not connected decoupling capacitor for protection (OCP) channel 1 positive power supply voltage channel 1 bootstrap capacitor channel 1 PWM output channel 1 negative power supply voltage decoupling of internal stabilizer for logic supply not connected channel 2 negative power supply voltage channel 2 PWM output channel 2 bootstrap capacitor channel 2 positive power supply voltage negative digital supply voltage Description

8. Functional description
8.1 General
The TDA8950 is a two-channel audio power amplier that uses Class D technology. For each channel, the audio input signal is converted into a digital PWM signal using an analog input stage and a PWM modulator; see Figure 1. To drive the output power transistors, the digital PWM signal is fed to a control and handshake block and to highand low-side driver circuits. This level-shifts the low-power digital PWM signal from a logic level to a high-power PWM signal switching between the main supply lines. A 2nd-order low-pass lter converts the PWM signal to an analog audio signal that can be used to drive a loudspeaker.

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TDA8950
2 150 W class-D power amplier

The TDA8950 single-chip Class D amplier contains high-power switches, drivers, timing and handshaking between the power switches, along with some control logic. To ensure maximum system robustness, an advanced protection strategy has been implemented to provide overvoltage, overtemperature and overcurrent protection. Each of the two audio channels contains a PWM modulator, an analog feedback loop and a differential input stage. The TDA8950 also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager. The two independent amplier channels feature high output power, high efciency, low distortion and low quiescent currents, and can be connected in the following congurations:

Stereo Single-Ended (SE) Mono Bridge-Tied Load (BTL)

The amplier system can be switched to one of three operating modes using pin MODE:

Standby mode: featuring very low quiescent current Mute mode: the amplier is operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI converter) input stages

Operating mode: the amplier is fully operational, de-muted and can deliver an output
signal A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure pop noise-free start-up. The bias-current setting of the (VI converter) input stages is related to the voltage on the MODE pin. In Mute mode, the bias-current setting of the VI converters is zero (VI converters are disabled). In Operating mode, the bias current is at a maximum. The time constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated using an RC network connected to pin MODE. An example of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor was omitted, the very short switching time constant could result in audible pop noises being generated at start-up (depending on the DC output offset voltage and loudspeaker used).

+5 V

5.6 k 470

mode control
5.6 k 10 F

mute/ operating

S1

standby/ operating

S2

SGND
010aaa552

Fig 4.

Example of mode selection circuit

TDA8950_2

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TDA8950
2 150 W class-D power amplier

To ensure the coupling capacitors at the inputs (CIN in Figure 10) are fully charged before the outputs start switching, a delay is inserted during the transition from Mute to Operating mode. An overview of the start-up timing is provided in Figure 5. For proper switch-off, the MODE pin should be forced LOW at leaxt 100 ms before the supply lines (VDDA and VSSA) drop below 12.5 V.

audio output
(1)

modulated PWM VMODE 50 % duty cycle operating

> 4.2 V

2.2 V < VMODE < 3 V

mute

0 V (SGND)

standby 100 ms 50 ms

> 350 ms

time

audio output
(1)

modulated PWM VMODE 50 % duty cycle operating

> 4.2 V

2.2 V < VMODE < 3 V

mute

0 V (SGND)

standby 100 ms 50 ms

> 350 ms

time
001aah657

(1) First 14 pulse down. Upper diagram: When switching from Standby to Mute, there is a delay of approximately 100 ms before the output starts switching. The audio signal will become available once VMODE reaches the Operating mode level (see Table 8), but not earlier than 150 ms after switching to Mute. To start-up pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms for the transition between Mute and Operating modes. Lower diagram: When switching directly from Standby to Operating mode, there is a delay of 100 ms before the outputs start switching. The audio signal becomes available after a second delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin MODE be at least 500 ms for the transition between Standby and Operating modes.

Fig 5.

Timing on mode selection input pin MODE

TDA8950_2

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TDA8950
2 150 W class-D power amplier

8.2 Pulse-width modulation frequency

The amplier output signal is a PWM signal with a typical carrier frequency of between 250 kHz and 450 kHz. A 2nd-order LC demodulation lter on the output is used to convert the PWM signal into an analog audio signal. The carrier frequency is determined by an external resistor, ROSC, connected between pins OSC and VSSA. The optimal carrier frequency setting is between 250 kHz and 450 kHz. The carrier frequency is set to 345 kHz by connecting an external 30 k resistor between pins OSC and VSSA. See Table 9 for more details. If two or more Class D ampliers are used in the same audio application, it is recommended that an external clock circuit be used with all devices (see Section 13.4). This will ensure that they operate at the same switching frequency, thus avoiding beat tones (if the switching frequencies are different, audible interference known as beat tones can be generated)

8.3 Protection
The following protection circuits are incorporated into the TDA8950:

Thermal protection:
Thermal FoldBack (TFB) OverTemperature Protection (OTP)

OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protection:

UnderVoltage Protection (UVP) OverVoltage Protection (OVP) UnBalance Protection (UBP) How the device reacts to a fault conditions depends on which protection circuit has been activated.

8.3.1 Thermal protection

The TDA8950 employes an advanced thermal protection strategy. A TFB function gradually reduces the output power within a dened temperature range. If the temperature continues to rise, OTP is activated to shut down the device completely. 8.3.1.1 Thermal FoldBack (TFB) If the junction temperature (Tj) exceeds the thermal foldback activation threshold, the gain is gradually reduced. This reduces the output signal amplitude and the power dissipation, eventually stabilizing the temperature. TFB is specied at the thermal foldback activation temperature Tact(th_fold) where the closed-loop voltage gain is reduced by 6 dB. The TFB range is: Tact(th_fold) 5 C < Tact(th_fold) < Tact(th_prot) The value of Tact(th_fold) for the TDA8950 is approximately 153 C; see Table 8 for more details.
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TDA8950
2 150 W class-D power amplier

8.3.1.2

OverTemperature Protection (OTP) If TFB fails to stabilize the temperature and the junction temperature continues to rise, the amplier will shut down as soon as the temperature reaches the thermal protection activation threshold, Tact(th_prot). The amplier will resume switching approximately 100 ms after the temperature drops below Tact(th_prot). The thermal behavior is illustrated in Figure 6.

Gain (dB)

30 dB

24 dB

0 dB

(Tact(th_fold) 5C)

Tact(th_prot) Tact(th_fold) 2 3

Tj (C)

001aah656

(1) Duty cycle of PWM output modulated according to the audio input signal. (2) Duty cycle of PWM output reduced due to TFB. (3) Amplier is switched off due to OTP.

Fig 6.

Behavior of TFB and OTP

8.3.2 OverCurrent Protection (OCP)

In order to guarantee the robustness of the TDA8950, the maximum output current that can be delivered at the output stages is limited. OCP is built in for each output power switch. OCP is activated when the current in one of the power transistors exceeds the OCP threshold (IORM = 9.2 A) due, for example, to a short-circuit to a supply line or across the load. The TDA8950 amplier distinguishes between low-ohmic short-circuit conditions and other overcurrent conditions such as a dynamic impedance drop at the loudspeaker. The impedance threshold (Zth) depends on the supply voltage. How the amplier reacts to a short circuit depends on the short-circuit impedance:

Short-circuit impedance > Zth: the amplier limits the maximum output current to IORM
but the amplier does not shut down the PWM outputs. Effectively, this results in a clipped output signal across the load (behavior very similar to voltage clipping).

Short-circuit impedance < Zth: the amplier limits the maximum output current to IORM
and at the same time discharges the capacitor on pin PROT. When CPROT is fully discharged, the amplier shuts down completely and an internal timer is started. The value of the protection capacitor (CPROT) connected to pin PROT can be between 10 pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is enabled that will discharge CPROT.
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TDA8950
2 150 W class-D power amplier

When OCP is activated, the power transistors are turned off. They are turned on again during the next switching cycle. If the output current is still greater than the OCP threshold, they will be immediately switched off again. This switching will continue until CPROT is fully discharged. The amplier will then be switched off completely and a restart sequence initiated. After a xed period of 100 ms, the amplier will attempt to switch on again, but will fail if the output current still exceeds the OCP threshold. The amplier will continue trying to switch on every 100 ms. The average power dissipation will be low in this situation because the duty cycle is low. Switching the amplier on and off in this way will generate unwanted audio holes. This can be avoided by increasing the value of CPROT (up to 220 pF) to delay amplier switch-off. CPROT will also prevent the amplier switching off due to transient frequency-dependent impedance drops at the speakers. The amplier will switch on, and remain in Operating mode, once the overcurrent condition has been removed. OCP ensures the TDA8950 amplier is fully protected against short-circuit conditions while avoiding audio holes.
Table 4. Type Current limiting behavior during low output impedance conditions at different values of CPROT VP[1] (V) VI (mV, p-p) f (Hz) CPROT PWM output stops (pF) Short Short (Zth = 0 ) (Zth = 0.5 ) 20 1000 20 1000 1000
[1] [2]

Short (Zth = 1 ) OVP[2] no OVP[2] no no

TDA8950

29.5

500

10 10 15 15 220

yes yes yes yes no

yes yes yes no no

VP is the supply voltage on pins VDDP1, VDDP2 and VDDA. OVP can be triggered by supply pumping; see Section 13.6.

8.3.3 Window Protection (WP)

Window Protection (WP) checks the conditions at the output terminals of the power stage and is activated:

During the start-up sequence, when the TDA8950 is switching from Standby to Mute.
Start-up will be interrupted If a short-circuit is detected between one of the output terminals and pin VDDP1/VDDP2 or VSSP1/VSSP2. The TDA8950 will wait until the short-circuit to the supply lines has been removed before resuming start-up. The short circuit will not generate large currents because the short-circuit check is carried out before the power stages are enabled.

When the amplier is shut down completely because the OCP circuit has detected a
short circuit to one of the supply lines. WP will be activated when the amplier attempts to restart after 100 ms (see Section 8.3.2). The amplier will not start-up again until the short circuit to the supply lines has been removed.

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TDA8950
2 150 W class-D power amplier

8.3.4 Supply voltage protection

If the supply voltage drops below the minimum supply voltage threshold, VP(uvp), the UVP circuit will be activated and the system will shut down. Once the supply voltage rises above VP(uvp) again, the system will restart after a delay of 100 ms. If the supply voltage exceeds the maximum supply voltage threshold, VP(ovp), the OVP circuit will be activated and the power stages will be shut down. When the supply voltage drops below VP(ovp) again, the system will restart after a delay of 100 ms. An additional UnBalance Protection (UBP) circuit compares the positive analog supply voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is triggered if the voltage difference exceeds a factor of two (VDDA > 2 |VSSA| OR |VSSA| > 2 VDDA). When the supply voltage difference drops below the unbalance threshold, VP(ubp), the system restarts after 100 ms. An overview of all protection circuits and their respective effects on the output signal is provided in Table 5.
Table 5. Overview of TDA8950 protection circuits Restart directly N N N[2] Y N N N Restart after 100 ms N Y Y[2] N Y Y Y Pin PROT detection N N Y N N N N

Protection name Complete shutdown TFB[1] OTP OCP WP UVP OVP UBP
[1] [2] [3]

N Y Y[2] N[3] Y Y Y

Amplier gain depends on the junction temperature and heatsink size. The amplier shuts down completely only if the short-circuit impedance is below the impedance threshold (Zth; see Section 8.3.2). In all other cases, current limiting results in a clipped output signal. Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been activated (short-circuit to one of the supply lines).

8.4 Differential audio inputs

The audio inputs are fully differential ensuring a high common mode rejection ratio and maximum exibility in the application.

Stereo operation: to avoid acoustical phase differences, the inputs should be in

antiphase and the speakers should be connected in antiphase. This conguration: minimizes power supply peak current minimizes supply pumping effects, especially at low audio frequencies

Mono BTL operation: the inputs must be connected in anti-parallel. The output of one
channel is inverted and the speaker load is connected between the two outputs of the TDA8950. In practice (because of the OCP threshold) the output power can be boosted to twice the output power that can be achieved with the single-ended conguration. The input conguration for a mono BTL application is illustrated in Figure 7.
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TDA8950
2 150 W class-D power amplier

IN1P IN1M Vin IN2P IN2M

OUT1

SGND

OUT2

power stage
mbl466

Fig 7.

Input conguration for mono BTL application

9. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP[1] IORM Tstg Tamb Tj VMODE VOSC VI VPROT VESD Iq(tot) VPWM(p-p)
[1]

Parameter supply voltage repetitive peak output current storage temperature ambient temperature junction temperature voltage on pin MODE voltage on pin OSC input voltage voltage on pin PROT electrostatic discharge voltage total quiescent current peak-to-peak PWM voltage

Conditions Standby, Mute modes; VDD VSS maximum output current limiting

Min 9.2 55 40 -

Max 90 +150 +85 150 6 SGND + 6 +5 12 +2000 +500 75 120

Unit V A C C C V V V V V V mA V

referenced to SGND referenced to SGND; pin IN1P; IN1M; IN2P and IN2M referenced to voltage on pin VSSD Human Body Model (HBM) Charged Device Model (CDM) Operating mode; no load; no lter; no RC-snubber network connected on pins OUT1 and OUT2

0 0 5 0 2000 500 -

VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.

10. Thermal characteristics

Table 7. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions in free air Typ 40 1.1 Unit K/W K/W

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TDA8950
2 150 W class-D power amplier

11. Static characteristics

Table 8. Static characteristics VP = 35 V; fosc = 345 kHz; Tamb = 25 C; unless otherwise specied. Symbol Supply VP[1] VP(ovp) VP(uvp) VP(ubp) Iq(tot) supply voltage overvoltage protection supply voltage Operating mode Standby, Mute modes; VDD VSS
[3] [2]

Parameter

Conditions

Min 12.5 85 20 -

Typ 30 33 50

Max 40 90 25 75

Unit V V V % mA

undervoltage protection supply voltage VDD VSS unbalance protection supply voltage total quiescent current Operating mode; no load; no lter; no RC-snubber network connected measured at 30 V referenced to SGND Standby mode Mute mode Operating mode
[4] [4][5] [4][5] [4][5]

Istb VMODE

standby current voltage on pin MODE

0 0 2.2 4.2 [4]

480 110 0 9.8

650 6 0.8 3.0 6 150 25 150 30 210 10.3

A V V V V A V mV mV mV mV V

Mode select input; pin MODE

II VI VO(offset)

input current input voltage output offset voltage

VI = 5.5 V DC input SE; Mute mode SE; Operating mode BTL; Mute mode BTL; Operating mode
[6] [6]

Audio inputs; pins IN1M, IN1P, IN2P and IN2M 9.3 Amplier outputs; pins OUT1 and OUT2

Stabilizer output; pin STABI VO(STABI) output voltage on pin STABI Mute and Operating modes; with respect to VSSD

Temperature protection Tact(th_prot) Tact(th_fold) thermal protection activation temperature thermal foldback activation temperature closed loop SE voltage gain reduced with 6 dB
[7]

154 153

C C

[1] [2] [3] [4] [5] [6] [7]

VP is the supply voltage on pins VDDP1, VDDP2 and VDDA. The circuit is DC adjusted at VP = 12.5 V to 42.5 V. Unbalance protection activated when VDDA > 2 |VSSA| OR |VSSA| > 2 VDDA. With respect to SGND (0 V). The transition between Standby and Mute modes has hysteresis, while the slope of the transition between Mute and Operating modes is determined by the time-constant of the RC network on pin MODE; see Figure 8. DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes. The slope caused by any DC output offset is determined by the time-constant of the RC network on pin MODE. At a junction temperature of approximately Tact(th_fold) 5 C, gain reduction commences and at a junction temperature of approximately Tact(th_prot), the amplier switches off.
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TDA8950
2 150 W class-D power amplier

slope is directly related to the time-constant of the RC network on the MODE pin
VO (V) VO(offset)(on) Standby Mute On

VO(offset)(mute)

0.8

2.2

3.0

4.2 5.5 VMODE (V)

coa021

Fig 8.

Behavior of mode selection pin MODE

12. Dynamic characteristics

12.1 Switching characteristics
Table 9. Dynamic characteristics VP[1] = 35 V; Tamb = 25 C; unless otherwise specied. Symbol fosc(typ) fosc VOSC Vtrip ftrack Zi Ci tr(i) Parameter Conditions Min 290 250 Typ 345 Max 365 450 Unit kHz kHz Internal oscillator typical oscillator frequency ROSC = 30.0 k oscillator frequency

External oscillator input or frequency tracking; pin OSC voltage on pin OSC trip voltage tracking frequency input impedance input capacitance input rise time from SGND + 0 V SGND + 5 V
[3] [2]

HIGH-level

SGND + 4.5 500 1 -

SGND + 5 SGND + 2.5 -

SGND + 6 900 15 100

V V kHz M pF ns

[1] [2] [3]

VP is the supply voltage on pins VDDP1, VDDP2 and VDDA. When using an external oscillator, the frequency ftrack (500 kHz minimum, 900 kHz maximum) will result in a PWM frequency fosc (250 kHz minimum, 450 kHz maximum) due to the internal clock divider; see Section 8.2. When tr(i) > 100 ns, the output noise oor will increase.

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TDA8950
2 150 W class-D power amplier

12.2 Stereo SE conguration characteristics

Table 10. Dynamic characteristics VP[1] = 35 V; RL = 4 ; fi = 1 kHz; fosc = 345 kHz; RsL[2] < 0.1 ; Tamb = 25 C; unless otherwise specied. Symbol Po Parameter output power Conditions Tj = 85 C; LLC = 22 H; CLC = 680 nF (see Figure 10) THD + N = 10 %; RL = 4 ; VP = 39 V THD + N = 0.5 %; RL = 4 ; VP = 37 V THD + N = 10 %; RL = 4 ; VP = 37 V THD + N = 10 %; RL = 6 ; VP = 37 V THD Gv(cl) SVRR total harmonic distortion closed-loop voltage gain supply voltage ripple rejection between pins VDDPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz between pins VSSPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz Zi Vn(o) cs |Gv| mute CMRR po input impedance output noise voltage channel separation voltage gain difference mute attenuation common mode rejection ratio output power efciency fi = 1 kHz; Vi = 2 V (RMS) Vi(CM) = 1 V (RMS) SE, RL = 4 SE, RL = 6 BTL, RL = 8 RDSon(hs) RDSon(ls) high-side drain-source on-state resistance low-side drain-source on-state resistance
[10] [9] [5] [5] [5] [5] [5] [5] [5] [5] [3]

Min

Typ

Max Unit

170 [4] [4]

W W W W % % dB dB dB dB dB dB dB dB dB k V V dB dB dB dB % % % m m

100 150 100

Po = 1 W; fi = 1 kHz Po = 1 W; fi = 6 kHz

29 45 -

0.05 0.05 30 90 70 75 120 80 60 80 115 63 160 85 70 75 75 88 90 88 200 190 31 1 -

between one of the input pins and SGND Operating mode; Rs = 0 Mute mode
[6] [7] [8]

[10]

[1] [2] [3] [4] [5] [6] [7]

VP is the supply voltage on pins VDDP1, VDDP2 and VDDA. RsL is the series resistance of the low-pass LC lter inductor used in the application. Output power is measured indirectly; based on RDSon measurement; see Section 13.3. THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall lter; max. limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND. 22 Hz to 20 kHz, using AES17 20 kHz brick wall lter. 22 Hz to 20 kHz, using AES17 20 kHz brick wall lter.
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TDA8950
2 150 W class-D power amplier

[8] [9]

Po = 1 W; fi = 1 kHz. Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.

[10] Leads and bond wires included.

12.3 Mono BTL application characteristics

Table 11. Dynamic characteristics VP[1] = 35 V; RL = 8 ; fi = 1 kHz; fosc = 345 kHz; RsL[2] < 0.1 ; Tamb = 25 C; unless otherwise specied. Symbol Po Parameter output power Conditions Tj = 85 C; LLC = 22 H; CLC = 680 nF (see Figure 10) THD + N = 10 %; RL = 8 ; VP = 39 V THD + N = 0.5 %; RL = 8 ; VP = 37 V THD + N = 10 %; RL = 8 ; VP = 37 V THD Gv(cl) SVRR total harmonic distortion closed-loop voltage gain supply voltage ripple rejection between pin VDDPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz between pin VSSPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz Zi Vn(o) mute CMRR
[1] [2] [3] [4] [5] [6] [7] [8]
[5] [5] [5] [5] [5] [5] [5] [5] [3]

Min

Typ

Max Unit

[4] [4]

340 200 300

W W W % % dB dB dB dB dB dB dB dB dB k V V dB dB

Po = 1 W; fi = 1 kHz Po = 1 W; fi = 6 kHz

45

0.05 0.05 36 80 80 95 120 75 75 90 130 63 190 45 75 75 -

input impedance output noise voltage mute attenuation common mode rejection ratio

measured between one of the input pins and SGND Operating mode; Rs = 0 Mute mode fi = 1 kHz; Vi = 2 V (RMS) Vi(CM) = 1 V (RMS)
[6] [7] [8]

VP is the supply voltage on pins VDDP1, VDDP2 and VDDA. RsL is the series resistance of the low-pass LC lter inductor used in the application. Output power is measured indirectly; based on RDSon measurement; see Section 13.3. THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall lter; max. limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (p-p). 22 Hz to 20 kHz, using an AES17 20 kHz brick wall lter; low noise due to BD modulation. 22 Hz to 20 kHz, using an AES17 20 kHz brick wall lter. Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.

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TDA8950
2 150 W class-D power amplier

13. Application information

13.1 Mono BTL application
When using the power amplier in a mono BTL application, the inputs of the two channels must be connected in parallel and the phase of one of the inputs must be inverted; see Figure 7. In principle, the loudspeaker can be connected between the outputs of the two single-ended demodulation lters.

13.2 Pin MODE

To ensure a pop noise-free start-up, an RC time-constant must be applied to pin MODE. The bias-current setting of the VI converter input is directly related to the voltage on pin MODE. In turn the bias-current setting of the VI converters is directly related to the DC output offset voltage. A slow dV/dt on pin MODE results in a slow dV/dt for the DC output offset voltage, ensuring a pop noise-free transition between Mute and Operating modes. A time-constant of 500 ms is sufcient to guarantee pop noise-free start-up; see Figure 4, Figure 5 and Figure 8 for more information.

13.3 Estimating the output power

13.3.1 Single-Ended (SE)
Maximum output power:
2 RL ---------------------------------------------------- V P ( 1 t w ( min ) 0.5 f osc ) R L + R DSon ( hs ) + R sL = ---------------------------------------------------------------------------------------------------------------------------------------2R L

P o ( 0.5 % )

(1)

Maximum output current is internally limited to 9.2 A: V P ( 1 t w ( min ) 0.5 f osc ) I o ( peak ) = --------------------------------------------------------------------R L + R DSon ( hs ) + R sL Where: (2)

Po(0.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RsL: series impedance of the lter coil VP: single-sided supply voltage or 0.5 (VDD + |VSS|) tw(min): minimum pulse width (typical 150 ns, temperature dependent) fosc: oscillator frequency

Remark: Note that Io(peak) should be less than 9.2 A (Section 8.3.2). Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and the voltage drop across the coil.

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TDA8950
2 150 W class-D power amplier

13.3.2 Bridge-Tied Load (BTL)

Maximum output power:
2 RL ------------------------------------------------------------------ 2V P ( 1 t w ( min ) 0.5 f osc ) R L + R DSon ( hs ) + R DSon ( ls ) = ---------------------------------------------------------------------------------------------------------------------------------------------------------2R L

P o ( 0.5 % )

(3)

Maximum output current internally limited to 9.2 A: 2V P ( 1 t w ( min ) 0.5 f osc ) I o ( peak ) = -----------------------------------------------------------------------------------------R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R sL Where: (4)

Po(0.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RDSon(ls): low-side RDSson of power stage output DMOS (temperature dependent) RsL: series impedance of the lter coil VP: single-sided supply voltage or 0.5 (VDD + |VSS|) tw(min): minimum pulse width (typical 150 ns, temperature dependent) fosc: oscillator frequency

Remark: Note that Io(peak) should be less than 9.2 A; see Section 8.3.2. Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and the voltage drop across the coil.

13.4 External clock

To ensure duty cycle-independent operation, the external clock frequency is divided by two internally. The external clock frequency is therefore twice the internal clock frequency (typically 2 350 kHz = 700 kHz). If several Class D ampliers are used in a single application, it is recommended that all the devices run at the same switching frequency. This can be achieved by connecting the OSC pins together and feeding them from an external oscillator. When using an external oscillator, it is necessary to force pin OSC to a DC level above SGND. This disables the internal oscillator and causes the PWM to switch at half the external clock frequency. The internal oscillator requires an external resistor ROSC, connected between pin OSC and pin VSSA. ROSC must be removed when using an external oscillator. The noise generated by the internal oscillator is supply voltage dependent. An external low-noise oscillator is recommended for low-noise applications running at high supply voltages.

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2 150 W class-D power amplier

13.5 Heatsink requirements

An external heatsink must be connected to the TDA8950. Equation 5 denes the relationship between maximum power dissipation before activation of TFB and total thermal resistance from junction to ambient. T j T amb Rth ( j a ) = ----------------------P (5)

Power dissipation (P) is determined by the efciency of the TDA8950. Efciency measured as a function of output power is given in Figure 20. Power dissipation can be derived as a function of output power as shown in Figure 19.

30 P (W)

mbl469

(1)

20

(2)

10
(3) (4) (5)

0 0 20 40 60 80 100 Tamb (C)

(1) Rth(j-a) = 5 K/W. (2) Rth(j-a) = 10 K/W. (3) Rth(j-a) = 15 K/W. (4) Rth(j-a) = 20 K/W. (5) Rth(j-a) = 35 K/W.

Fig 9.

Derating curves for power dissipation as a function of maximum ambient temperature

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2 150 W class-D power amplier

In the following example, a heatsink calculation is made for an 8 BTL application with a 30 V supply: The audio signal has a crest factor of 10 (the ratio between peak power and average power (20 dB)); this means that the average output power is 110 of the peak power. Thus, the peak RMS output power level is the 0.5 % THD level, i.e. 170 W. The average power is then 110 170 W = 17 W. The dissipated power at an output power of 17 W is approximately 7 W. When the maximum expected ambient temperature is 50 C, the total Rth(j-a) becomes ( 148 50 ) ------------------------- = 14 K/W 7 Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a) Rth(j-c) (thermal resistance from junction to case) = 1.1 K/W Rth(c-h) (thermal resistance from case to heatsink) = 0.5 K/W to 1 K/W (dependent on mounting) So the thermal resistance between heatsink and ambient temperature is: Rth(h-a) (thermal resistance from heatsink to ambient) = 14 (1.1 + 1) = 11.9 K/W The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in Figure 9. A maximum junction temperature Tj = 150 C is taken into account. The maximum allowable power dissipation for a given heatsink size can be derived, or the required heatsink size can be determined, at a required power dissipation level; see Figure 9.

13.6 Pumping effects

In a typical stereo single-ended conguration, the TDA8950 is supplied by a symmetrical supply voltage (e.g. VDD = 30 V and VSS = 30 V). When the amplier is used in an SE conguration, a pumping effect can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is returned to the other supply line (e.g. VSS) and vice versa. When the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source increases and the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on:

Speaker impedance Supply voltage Audio signal frequency Value of supply line decoupling capacitors Source and sink currents of other channels

Pumping effects should be minimized to prevent the malfunctioning of the audio amplier and/or the voltage supply source. Amplier malfunction due to the pumping effect can trigger UVP, OVP or UBP.

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TDA8950
2 150 W class-D power amplier

The most effective way to avoid pumping effects is to connect the TDA8950 in a mono full-bridge conguration. In the case of stereo single-ended applications, it is advised to connect the inputs in anti-phase (see Section 8.4). The power supply can also be adapted; for example, by increasing the values of the supply line decoupling capacitors.

13.7 Application schematic

Notes on the application schematic:

Connect a solid ground plane around the switching amplier to avoid emissions Place 100 nF capacitors as close as possible to the TDA8950 power supply pins Connect the heatsink to the ground plane or to VSSPn using a 100 nF capacitor Use a thermally conductive, electrically non-conductive, Sil-Pad between the TDA8950 heat spreader and the external heatsink

The heat spreader of the TDA8950 is internally connected to VSSD Use differential inputs for the most effective system level audio performance with
unbalanced signal sources. In case of hum due to oating inputs, connect the shielding or source ground to the amplier ground.

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 02 11 June 2009
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NXP Semiconductors

+5 V

RVDDA 10

VDDA VDDP

5.6 k 470

VDDP
CVDDP 470 F CVP 22 F

mode control +5 V SINGLE-ENDED OUTPUT FILTER VALUES LOAD LLC CLC 3 to 6 4 to 8

T2 HFE > 80

GND
CVSSP 470 F

470 k

5.6 k

10 F

470 k

VSSP
RVSSA 10

VSSP VSSA mute/ operating

15 H 22 H

680 nF 470 nF

10 k

T1 HFE > 80

standby/ operating

10 k

SGND VSSA
ROSC 30 k

mode control

VDDP
CVDDP 100 nF

VSSP
CVSSP 100 nF RSN 10

CVP 100 nF

VDDP
CSN 220 pF CSN 220 pF

VDDP1

+ IN1

CIN 470 nF CIN 470 nF

IN1P

4 2

OSC

n.c. n.c. n.c.

23

VSSP1 11

MODE

VSSP 10 OUT1
CBO

LLC RZO 22

IN1M

BOOT1

CLC 15 nF

SGND
CIN 470 nF

19

CZO 100 nF

TDA8950J
15 BOOT2

CBO 15 nF

IN2 +

IN2P

22 14 OUT2

LLC

2 150 W class-D power amplier

CIN 470 nF

IN2M

21 20 VDDA 18 VSSA 12 STABI 7 PROT 17 VSSD 16 VDDP2 13 VSSP2

RSN 10 CVSSP 100 nF

VDDP
CSN 220 pF CSN 220 pF CLC

RZO 22

CZO + 100 nF

CVDDA 220 nF

CVSSA 220 nF CSTAB 470 nF CPROT(1)

CVDDP 100 nF

CVP 100 nF

TDA8950

VSSP

VDDA

VSSA

VSSP

VSSA

VDDP

VSSP

010aaaxxx

22 of 39

(1) The value of CPROT can be in the range 10 pF to 220 pF (see Section 8.3.2)

Fig 10. Typical application diagram

NXP Semiconductors

TDA8950
2 150 W class-D power amplier

13.8 Curves measured in reference design

10 THD (%) 1
010aaa553

(1)

101
(2)

102

(3)

103 102

101

10

102 Po (W)

103

VP = 35 V, fosc = 345 kHz, 2 4 SE conguration. (1) fi = 6 kHz. (2) fi = 1 kHz. (3) fi = 100 Hz.

Fig 11. THD + N as a function of output power, SE conguration with 2 4 load

10 THD (%) 1

010aaa554

101

(1)

(2)

102

(3)

103 102

101

10

102 Po (W)

103

VP = 35 V, fosc = 345 kHz, 2 6 SE conguration. (1) fi = 6 kHz. (2) fi = 1 kHz. (3) fi = 100 Hz.

Fig 12. THD + N as a function of output power, SE conguration with 2 6 load

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2 150 W class-D power amplier

10 THD (%) 1

001aai423

101

(1)

(2)

102

(3)

103 102

101

10

102 PO (W)

103

VP = 35 V, fosc = 345 kHz, 1 8 BTL conguration. (1) fi = 6 kHz. (2) fi = 1 kHz. (3) fi = 100 Hz.

Fig 13. THD + N as a function of output power, BTL conguration with 1 8 load

10 THD (%) 1

001aai424

101

(1)

102

(2)

103 10

102

103

104

fi (Hz)

105

VP = 35 V, fosc = 345 kH, 2 4 SE conguration. (1) Po = 1 W. (2) Po = 10 W.

Fig 14. THD + N as a function of frequency, SE conguration with 2 4 load

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TDA8950
2 150 W class-D power amplier

10 THD (%) 1

001aai701

101

(1)

102

(2)

103 10

102

103

104

fi (Hz)

105

VP = 35 V, fosc = 345 kHz, 2 6 SE conguration. (1) Po = 1 W. (2) Po = 10 W.

Fig 15. THD + N as a function of frequency, SE conguration with 2 6 load

10 THD (%) 1

001aai702

101

102

(1) (2)

103 10

102

103

104

fi (Hz)

105

VP = 35 V, fosc = 345 kHz, 1 8 BTL conguration. (1) Po = 1 W. (2) Po = 10 W.

Fig 16. THD + N as a function of frequency, BTL conguration with 1 8 load

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2 150 W class-D power amplier

0 cs (dB) 20

001aai703

40

60

80

100 10

102

103

104 fi (Hz)

105

VP = 35 V, fosc = 345 kHz, 2 4 SE conguration. 1 W and 10 W respectively.

Fig 17. Channel separation as a function of frequency, SE conguration with 2 4 load

0 cs (dB) 20

001aai704

40

60

80

100 10

102

103

104 fi (Hz)

105

VP = 35 V, fosc = 345 kHz, 2 6 SE conguration. 1 W and 10 W respectively.

Fig 18. Channel separation as a function of frequency, SE conguration with 2 6 load

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2 150 W class-D power amplier

P (W)

40 35 30 25
(1)

001aai705

20
(2)

15
(3)

10 5 0 0 20 40 60 80 100 Po (W) 120

VP = 35 V, fi = 1 kHz; fosc = 345 kHz. (1) 2 4 SE conguration. (2) 2 6 SE conguration. (3) 2 8 SE conguration.

Fig 19. Power dissipation as a function of output power per channel, SE conguration

100 (%) 80
(1) (2)

001aai706

(3)

60

40

20

0 0 20 40 60 80 100 Po (W) 120

VP = 35 V, fi = 1 kHz, fosc = 345 kHz. (1) 2 8 SE conguration. (2) 2 6 SE conguration. (3) 2 4 SE conguration.

Fig 20. Efciency as a function of output power per channel, SE conguration

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TDA8950
2 150 W class-D power amplier

Po (W)

200 180 160 140 120 100

(2) (1)

001aai707

80 60 40 20 0 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 40 Vp (V)

(3) (4)

Innite heat sink used. fi = 1 kHz, fosc = 345 kHz. (1) THD + N = 10 %, 4 . (2) THD + N = 0.5 %, 4 ; THD + N = 10 %, 6 . (3) THD + N = 10 %, 8 ; THD + N = 0.5 %, 6 (4) THD + N = 0.5 %, 8 .

Fig 21. Output power as a function of supply voltage, SE conguration

Po (W)

350 300 250

(1)

001aai708

200
(2)

150
(3)

100 50 0 12.5

(4)

15

17.5

20

22.5

25

27.5

30

32.5

35

37.5 40 Vp (V)

Innite heat sink used. fi = 1 kHz, fosc = 345 kHz. (1) THD + N = 10 %, 8 . (2) THD + N = 0.5 %, 8 . (3) THD + N = 10 %, 16 . (4) THD + N = 0.5 %, 16 .

Fig 22. Output power as a function of supply voltage, BTL conguration

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2 150 W class-D power amplier

45 Gv(cl) (dB) 40
(1)

001aai709

35

30

(2) (3) (4)

25

20 10

102

103

104 fi (Hz)

105

VP = 35 V, fosc = 345 kHz, Vi = 100 mV, Ci = 330 pF, LLC = 15 H, CLC = 680 nF. (1) 1 8 BTL conguration. (2) 2 4 SE conguration. (3) 2 6 SE conguration. (4) 2 8 SE conguration.

Fig 23. Closed-loop voltage gain as a function of frequency

20 SVRR (dB) 40 60
(1)

001aai710

80
(2)

100

120 140 10

(3)

102

103

104 fripple (Hz)

105

Ripple on VDD, short on input pins. VP = 35 V, fosc = 345 kHz, RL = 4 , Vripple = 2 V (p-p). (1) Mute mode. (2) Operating mode. (3) Standby mode.

Fig 24. SVRR as a function of ripple frequency, ripple on VDD

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2 150 W class-D power amplier

20 SVRR (dB) 40 60

001aai711

80 100

(2) (1)

120 140 10

(3)

102

103

104 fripple (Hz)

106

Ripple on VSS, short on input pins. VP = 35 V, fosc = 345 kHz, RL = 4 , Vripple = 2 V (p-p). (1) Mute mode. (2) Operating mode. (3) Standby mode.

Fig 25. SVRR as a function of ripple frequency, ripple on VSS

10 Vo (V) 1 101 102 103 104

(1) (2)

001aai712

105 106 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VMODE (V)

VP = 35 V, fosc = 345 kHz. (1) Mode voltage down. (2) Mode voltage up.

Fig 26. Output voltage as a function of mode voltage

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TDA8950
2 150 W class-D power amplier

50 mute (dB) 60

001aai713

70
(1) (2) (3)

80

90 10

102

103

104 fi (Hz)

105

VP = 35 V, fosc = 325 kHz, Vi = 2 V (RMS). (1) 8 . (2) 6 . (3) 4 .

Fig 27. Mute attenuation as a function of frequency

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2 150 W class-D power amplier

14. Package outline

DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1

non-concave x D Dh

Eh

view B: mounting base side A2

A5 A4

B j

E2 E

E1

L2 L1 L3

L 1 Z e e1 w M 23

Q m

c e2

v M

bp

5 scale

10 mm

DIMENSIONS (mm are the original dimensions) UNIT A 2 mm A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x

Z (1)

12.2 4.6 1.15 1.65 0.75 0.55 30.4 28.0 12 2.54 1.27 5.08 11.8 4.3 0.85 1.35 0.60 0.35 29.9 27.5

6 10.15 6.2 1.85 3.6 9.85 5.8 1.65 2.8

14 10.7 2.4 1.43 2.1 4.3 0.6 0.25 0.03 45 13 9.9 1.6 0.78 1.8

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT411-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION

ISSUE DATE 98-02-20 02-04-24

Fig 28. Package outline SOT411-1 (DBS23P)

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2 150 W class-D power amplier

HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height

SOT566-3

E D x

A X

c y E2 HE v M A

D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 24 Z e bp 13 w M (A3) A 12

5 scale

10 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) bp c D(2) D1 D2 1.1 0.9 E(2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 1 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.7 2.2 8 0

+0.08 0.53 0.32 16.0 13.0 0.04 0.40 0.23 15.8 12.6

0.25 0.25 0.03 0.07

Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT566-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION

ISSUE DATE 03-02-18 03-07-23

Fig 29. Package outline SOT566-3 (HSOP24)

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2 150 W class-D power amplier

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 Surface mount reow soldering description.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for ne pitch SMDs. Reow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

15.2 Wave and reow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature prole. Leaded packages, packages with solder balls, and leadless packages are all reow solderable. Key characteristics in both wave and reow soldering are:

Board specications, including the board nish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

Process issues, such as application of adhesive and ux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave

Solder bath specications, including temperature and impurities

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15.4 Reow soldering

Key characteristics in reow soldering are:

Lead-free versus SnPb soldering; note that a lead-free reow process usually leads to
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window

Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board

Reow temperature prole; this prole includes preheat, reow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classied in accordance with Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220

Package thickness (mm)

Package thickness (mm)

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reow soldering, see Figure 30.

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temperature

maximum peak temperature = MSL limit, damage level

minimum peak temperature = minimum soldering temperature

peak temperature

time
001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature proles for large and small components

For further information on temperature proles, refer to Application Note AN10365 Surface mount reow soldering description.

16. Soldering of through-hole mount packages

16.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.

16.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specied maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

16.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
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16.4 Package related soldering information

Table 14. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[2]
[1] [2]

Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable

For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. For PMFP packages hot bar soldering or manual soldering is suitable.

17. Revision history

Table 15. Revision history Release date 20090611 Data sheet status Product data sheet Change notice Supersedes TDA8950_1 Document ID TDA8950_2 Modications TDA8950_1

Parameter values revised throughout. Revised Figure 4, Figure 10, Figure 11 and Figure 12. Preliminary data sheet -

20080909

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18. Legal information

18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

18.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

19. Contact information

For more information, please visit: http://www.nxp.com For sales ofce addresses, please send an email to: [email protected]

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20. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.1.1 8.3.1.2 8.3.2 8.3.3 8.3.4 8.4 9 10 11 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.3.1 13.3.2 13.4 13.5 13.6 13.7 13.8 14 15 15.1 15.2 15.3 15.4 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pulse-width modulation frequency . . . . . . . . . . 8 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal protection . . . . . . . . . . . . . . . . . . . . . . 8 Thermal FoldBack (TFB) . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . . . . . . . . . 9 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9 Window Protection (WP). . . . . . . . . . . . . . . . . 10 Supply voltage protection . . . . . . . . . . . . . . . . 11 Differential audio inputs . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics. . . . . . . . . . . . . . . . . . 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . 14 Stereo SE conguration characteristics . . . . . 15 Mono BTL application characteristics . . . . . . . 16 Application information. . . . . . . . . . . . . . . . . . 17 Mono BTL application . . . . . . . . . . . . . . . . . . . 17 Pin MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Estimating the output power . . . . . . . . . . . . . . 17 Single-Ended (SE) . . . . . . . . . . . . . . . . . . . . . 17 Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . 18 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 18 Heatsink requirements . . . . . . . . . . . . . . . . . . 19 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 20 Application schematic . . . . . . . . . . . . . . . . . . . 21 Curves measured in reference design . . . . . . 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 Soldering of SMD packages . . . . . . . . . . . . . . 34 Introduction to soldering . . . . . . . . . . . . . . . . . 34 Wave and reow soldering . . . . . . . . . . . . . . . 34 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 34 Reow soldering . . . . . . . . . . . . . . . . . . . . . . . 35 Soldering of through-hole mount packages . 36 16.1 16.2 16.3 16.4 17 18 18.1 18.2 18.3 18.4 19 20 Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering by dipping or by solder wave . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 36 37 37 38 38 38 38 38 38 39

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2009.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 June 2009 Document identifier: TDA8950_2