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Application Note AN4102

A Fairchild Power Switch based SMPS for Color Television Receivers

Introduction
A switched mode power supply (SMPS) typically consists of a power transformer, secondary side rectifier diodes, a switching semiconductor device, a control IC, and peripheral circuits. Besides its basic function of supplying power to the load on the secondary side, an SMPS may have to perform other, special functions, depending on the system. For example, an SMPS for a color television receiver must minimize the effect of switching noise on the screen and reduce power consumption in standby. If the level of integration of the switching circuitry is not high enough, then additional, separate circuits will be required to accommodate all functions; these additional components raise the overall SMPS cost and not uncommonly reduce reliability. The highly integrated Fairchild Power Switch (FPS) combines a high power MOSFET and control IC into one package and, moreover, enhances IC functionality. It includes protective functions, thereby minimizing the number of additional components needed in an SMPS. Fairchild Power Switch (FPS) is widely used in the power circuits of a variety of equipment, such as color TVs, printers, PCs, monitors, and, of course, battery chargers and ac adapters. The KA3S-series Fairchild Power Switch (FPS) series was first introduced for color TVs; the SMPS described in this application note uses a KA5Q-series Fairchild Power Switch (FPS). KA5Q-series Fairchild Power Switch (FPS) incorporates enhanced protection functions and has a much reduced power consumption in standby mode. The most frequently used power circuits in household appliances are the flyback converter and the forward converter, both of which use the pulse width modulation (PWM) control method for fixed frequency switching. However, a general purpose PWM based SMPS cannot be used for a monitor or color TV, because the SMPS's switching noise would seriously affect the display quality. The switching noise would appear in the form of picture noise. To significantly reduce the effect of switching noise on the screen a power supply for a monitor has to be able to synchronize its switching frequency to an external signal, typically the monitor's horizontal sync flyback signal. Such a sync technique cannot be used in color TVs, however, since, unlike monitors, a color TV's horizontal deflection frequency is too low. Instead, an SMPS for a color TV makes use of the so called quasi resonant technique. In this technique a
2002 Fairchild Semiconductor Corporation

capacitor is added between the MOSFET drain and source, which lowers both the rising slope of the voltage Vds between the MOSFET's drain and source and the falling slope of the reverse voltage across the secondary side rectifier diodes when the MOSFET turns off. The shallower slopes reduce the dV/dt switching noise and switching loss, because the MOSFET turns on when Vds is at a minimum or zero. To comply with regulatory trends aimed at reducing standby power consumption, KA5Q-series Fairchild Power Switch (FPS) features a built in burst mode. Burst mode operation make it possible to reduce output voltages in standby to almost half those of the normal on mode. This can reduce standby input power demand to under 3W at 230Vac or, if few peripheral components are added, to possibly even 1.5W. Moreover, as implemented in the KA5Q-series, burst mode operation causes no audible noise and requires almost no additional components. To reduce losses further, KA5Qseries Fairchild Power Switch (FPS) has lower IC start up and operating currents than the KA3S-series, and quasi resonant operation can continue even in burst mode. Also, the KA5Qseries can perform primary side regulation using a built in error amplifier, which replaces the secondary side error amp and eliminates its peripheral circuits. Overall, the KA5Qseries incorporates five protection features to increase SMPS reliability: Pulse by pulse over current protection. Over voltage protection. Over load protection. Thermal protection. Over current latch. This application note contains working design example (Section 8) of an SMPS for use with color TVs or other high power applications. It is a universal input supply adaptable to ac input voltages world wide, and uses the Fairchild Power Switch (FPS)'s burst mode capability to achieve very low standby power consumption: less than 2W at 230Vac. The SMPS features variable frequency, quasi resonant switching; current mode control; built in secondary side regulation; and an array of built in protection features, including pulse by pulse over current protection and shutdown, over voltage protection with auto restart, overload protection with auto restart, and thermal shutdown. Rev. 1.0.2

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APPLICATION NOTE

1. Quasi resonant Operation

When a hard switched SMPS is used for a color TV, the MOSFET generates a very high frequency current spike at turn on, and this spike shows up as noise on the screen. Also, because the MOSFET's output capacitance, Coss is small, a fast MOSFET turn off abruptly increases its drain to source voltage Vds at a high dV/dt. This generates a voltage spike that produces common mode noise on the secondary side, which again results in on screen noise. Figure 1 shows a flyback converter that uses the quasi resonant technique. Lm is the transformer's primary side magnetizing inductance, and D1 is the MOSFET body diode. Neither the inductor nor the diode is a physically separate component. They are integral and implicit to the transformer and MOSFET, respectively, and are shown in Figure 1 for explanatory purposes. Current Id, that flows to the MOSFET increases at a constant rate when the MOSFET is on.
D2 IO

MOSFET off

MOSFET on

Vgs
0

Vds Vin
0

nVo nVo

Ids
0

Ip
Figure 2. Waveforms for the circuit of Figure 1.

ILm + VLm + Vi -

Lm

CO

+ VO -

IDS + Vds

ICR

D1

CR

After all the energy stored in the transformer is delivered to the secondary side, Lm and Cr resonate and Vds starts to decrease. In the ideal case with no losses, the minimum value for Vds would be Vin - Vo. The actual value is slightly higher. At minimum Vds the sensing circuit turns on the MOSFET. (See Section 5 for a description of the sensing method.) Because the MOSFET is turned on when Vds, is minimum and not zero, the potential stored in Cr discharges as soon as the MOSFET turns on, which generates a large current spike. To reduce this spike, the Fairchild Power Switch (FPS)'s control IC is configured to slow the MOSFET's turn-on.The time required for Vds to reach minimum is T R ( T R = LmCr ) , a fixed value independent of the input voltage or output current. Varying the switching frequency regulates the output voltage: the lower the switching frequency, the lower the input voltage and the higher the load current.

Figure 1. Simplified diagram of a flyback converter using the quasi resonant technique.

2. Secondary Side vs. Primary Side Regulation

Secondary side regulation requires an error amplifier and an opto coupler on the secondary side. The amplified error is transferred to the primary side through the opto coupler to control the MOSFET's on time and thereby precisely control the output voltage. The opto coupler also transfers the MCU signal received on the secondary side to the primary side to operate the burst mode. As explained in the following section, the burst mode allows low standby power to be achieved. Therefore, should it be necessary to guarantee a minimum standby power, an error amp and opto coupler would be required on the secondary side and the increased cost these components contribute to the design would have to be accepted. Primary side regulation is a method that regulates secondary side voltage indirectly, by controlling the primary side voltage. In the KA5Q-series Fairchild Power Switch (FPS), the error amp in the control IC senses
2002 Fairchild Semiconductor Corporation

The MOSFET turns off when Id reaches the peak value (Ip in Figure 2) set by the control circuit, at which time the energy stored in the transformer in the form of flux charges capacitor Cr connected between the MOSFET's drain and source. This raises Vds. The rising slope of Vds increases as Ip increases and characteristic impedance Zr = (Lm/Cr)1/2 decreases. Cr, which is much larger than the MOSFET's output capacitance Coss, controls dV/dt when the MOSFET turns on and off, reducing it from what it would be otherwise. The charging of Cr continues until the secondary side rectifier diode D2 turns on, after which the transformer delivers current to the output. D2 is on for an interval proportional to Ip, during which Vds = Vin + nVo, (Figure 2). 2

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the IC's Vcc. This is compared internally to a built in reference. Use of this block may allow the secondary side opto coupler and error amplifier to be eliminated. Primary side regulation will be more cost effective than secondary side regulation. However, primary side regulation is not so precise as secondary side regulation, and its response to load variations is slow. Therefore, primary side regulation is advantageous only when considerations of lower cost out weigh the accompanying increase in standby power consumption and reduction in regulation performance.

their respective levels as determined by R24, R26, and R25.

Vcc 24V 12V 11V 0V VO2

3. Burst Mode Operation

The KA5Q-series Fairchild Power Switch (FPS)s burst mode capability allows all output voltages to be reduced to almost half those in normal (On mode) operation. It switches the Fairchild Power Switch (FPS)'s MOSFET by fixing the peak current (IP) flowing to it, exhibits a very low audible noise and makes possible an input power in standby mode of less than 2W at 230 Vac input. No external devices are required.
VO2

45.8%

0V VF/B 0V Ids

Figure 4. Normal (properly designed) burst mode operation, in which Vcc decreases faster than Vo2.

7805
R5 R4 Photo
OPTO coupler COUPLER

5V

MCU -COM

VO1

R26

R25 Picture off

R6

C KA431LZ
(LM431) A

C1 REF R24

Q1

ON/OFF

Figure 3. Reference diagram to demonstrate Fairchild Power Switch burst mode operation.

Figure 3 is a secondary side regulated circuit that demonstrates the Fairchild Power Switch (FPS)'s burst mode operation. Vo2 in the figure is a low value output voltage that also powers the MCU through the linear regulator 7805. Vo1 is the controlled output voltage that powers horizontal deflection and is the highest power output.

VCC, which powers the Fairchild Power Switch (FPS) on the primary side, is regulated to 24V (see the circuit of Section 8, Fairchild Power Switch (FPS) pin 3). The operation of the burst mode controller depends on Vcc. If Vcc drops to 11V before the output voltages reduce to their respective levels as determined by R24, R26, and R25, the burst mode controller turns on; if it rises to 12V, the controller stops switching. The burst mode controller controls the MOSFET switching by restricting its peak current to a fixed value. This prevents the generation of audible noise and also maintains the Fairchild Power Switch (FPS)'s Vfb at 0V (Figure 4). When the picture on signal goes high again, operation returns to the normal mode. The high picture on signal turns on Q1. Vo1, is divided by R24 and R25, and the resulting voltage is compared to the reference voltage in the error amplifier. Vfb increases, which regulates the MOSFET duty and output voltages increase to normal.

3.2 Design comments and a caution

Note that when the MOSFET stops switching (because the picture on signal has gone low), the output voltages decrease, but at different rates. The rates depend on output current and output capacitance. Because the example of the previous section is a real design, Figure 4 shows that Vcc decreases faster than Vo2. Figure 5 however, shows how the burst mode would operate should Vo2 decrease faster than Vcc. Vo2 would decrease to the voltage set by R24, R26, and R25 before Vcc drops to 11V. The error amp would start to regulate, and the Fairchild Power Switch (FPS)'s Vfb, would increase slightly to a value just above 0V, as shown. Because the load is off, load current is low and Vfb is not at 0V, the MOSFET starts to switch 3

3.1 Burst mode operation in standby

Refer to Figure 3. When the picture on signal is low, Q1 turns off and Vo2 is applied directly through R26 and the diode to the LM431s reference pin, thereby increasing the voltage at this point and in turn increasing the current flow to the opto coupler. The voltage Vfb on the Fairchild Power Switch (FPS)'s feedback pin (pin 4) goes to zero (Figure 4; see also the complete circuit shown in Section 8), stopping the Fairchild Power Switch (FPS) MOSFET's switching action. As also shown in Figure 4, Vcc and Vo2 decrease to
2002 Fairchild Semiconductor Corporation

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APPLICATION NOTE

(see Ids, Figure 5), but the output voltage Vo2 remains at 45.8% of its normal mode voltage. When Vcc finally drops to 11V (45.8% of 24V, its normal mode level), the burst mode controller starts and Vcc and Vo2 increase. When Vcc rises to 12V, the MOSFET stops switching and the above operations repeat.
Vcc 24V 12V 11V 0V VO2

determine the output voltage, which is calculated as follows:

R 24 //R 26 R 25 //R 24 - V + --------------------------------------------- ( V 0.7 ) 2.5 = -------------------------------------------1 2 R + R //R R + R //R 25 24 26 26 25 24 R 25 R 24 ( V 2 0.7 2.5 ) R 26 = ---------------------------------------------------------------------2.5 ( R 25 + R 24 ) V 1 R 24

where, V1, and V2 are the normal mode output voltages, Vo1 and Vo2; an V'1 and V'2 are the desired control loop values for Vo1 and Vo2 in standby (45.8% of their normal mode values). This value is set since the Fairchild Power Switch (FPS) regulates its Vcc voltage to 11V in standby mode and Vcc is normally set to 24V in normal mode.

4.1.Transformer turns ratio

45.8%

0V Vfb 0V Ids

If Vo2 drops to V'2, before Vcc drops to 11V in standby mode, the error amp starts to feed back. If V'2 is too low, the MCU could be reset. Therefore, select V'2 such that the linear regulator (7805) can properly maintain the output. This means the turns ratio should be selected such that (11 / Vcc) > (V'2 / V2). In other words, the transformer should be designed so that Vo2 is maintained slightly higher than V'2. This allows the error amp output to saturate low, permitting the primary side Vfb to remain at ground level.

Figure 5. Abnormal burst mode operation in an improper design allowing Vo2 to decrease faster than Vcc.

5. Fairchild Power Switch Sync Pin Circuitry Design

In quasi resonant operation, the voltage level at the Fairchild Power Switch (FPS) Sync pin (pin 5) determines when the MOSFET turns on. This should be when Vds is lowest. Figure 6 shows the reference voltages, Vrh and Vrf for both normal and burst mode operation. They are used to detect the time required for the voltage across the MOSFET to reach its minimum. The MOSFET turns on when the Sync pin voltage becomes lower than Vrf.
Vcc C15

This kind of operation, where Vo2 decreases faster than Vcc extends the switching period and increases the switching loss. To prevent these effects, increase the value of the output rectifier capacitance (see, e.g., the circuit of Section 8 and Table 1, the parts list for that circuit).

4. Feedback Circuit Design

When secondary side regulation is used, the output voltage is determined by comparing the voltage to be controlled, Vo1, to the reference in the error amp. In this example it is 2. 5 V for an LM431. As shown in Figure 3, when the MCU picture on signal goes high, Q1 turns on and the diode in its collector turns off. Thus, R24 and R25 around the error amp are determined as follows : R 24 -V 2.5 = ------------------------R 24 + R 25 1 V 1 2.5 - R 24 R 25 = --------------------2.5 In standby mode, however, with the picture on signal low, Q1 is off and the diode is on. Now R24, R25, and R26 4

R15
Vsync(t)

5 R16 C12

OSC

BURST MODE CONTROLLER NORMAL : Vrh=4.5V 4.6V Vrf= 2.6V 2.5V BURST MODE : Vrh=2.5V 3.6V Vrf= 1.25V 1.3V

Figure 6. Reference voltages for normal and burst mode operation, Vrh and Vrf.
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Figure 7 shows the waveform of Vsync in normal mode. The peak value of Vsync(t), when divided by R15 and R16 must be greater than the threshold voltage of the sync pin. In normal mode the threshold voltage is 4.6 V, and in standby mode it is 3.6V. Vsync(t) is the voltage across C15. It increases to Vc, which is the maximum voltage of Vsync(t) determined by the auxiliary winding voltage and the ratio of R15 and R16, after the MOSFET turns off. When the transformer current drops to zero, it drops exponentially as shown in Figure 7.
OVP LEVEL
Vsync(t)
(normal)

and does not change once the circuit is set.

OVP LEVEL

Vsync(t) (ST-BY) Vrh Vrf Vrh Vrf

TQ2
TQ1

Vc2

SYNC REF

MOSFET Vg GATE

Vrh Vrf TQ1 Vrh Vrf

Vc1

Figure 8. Stand by mode Vsync waveform.

SYNC. REF.

MOSFET Vg GATE

The output voltage in standby drops to 45-50% of its value in normal mode, and so does Vc. Therefore, to guarantee quasi resonant operation in standby mode, tQ must equal tR, regardless of the mode. To achieve this, the reference in the Fairchild Power Switch (FPS)'s Sync pin comparator changes with the mode.

Figure 7. Normal mode waveforms for Vsync(t).

6. Protection
The time tQ that it takes for Vsync(t) to drop from Vc to Vrf , is calculated as follows: V rf$ 1 t Q = 1n # 1 -------! V "
c

6.1 Over voltage protection

Refer to Figure 8. A problem in the feedback loop can be indicated either when switching shuts down or the output voltage is continuing to increase because it is not regulated. In response to increasing output voltage, a KA5Q-series Fairchild Power Switch (FPS) enters latch mode when the sync pin voltage reaches 12V (typ.) The Fairchild Power Switch (FPS) stops, and all output voltages start to drop. When Vcc reaches 9V, the Fairchild Power Switch (FPS) unlatches and restarts and Vcc again increases. Switching restarts when Vcc reaches 15V. This operation is called auto restart. Be careful of the rising slope of Vsync(t). Its time constant is C12x(R15//R16). If the time constant is too short, the waveform can oscillate causing an over voltage protection (OVP) malfunction. If Vc, the peak value of Vsync(t) approaches the OVP level (12V, typ.) and there are problems in the feedback loop. Output voltage overshoot is reduced but care must be taken so that the OVP does not malfunction due to a slight overshoot, etc. in the output voltage. If Vc is set too low, the Fairchild Power Switch (FPS)'s Primary Side Regulation (PSR) block can start before OVP and regulate Vcc. In that case operation continues, but with an abnormally increased output voltage. 5

where = R 16 C 12

R 16 -V V c = ------------------------R 15 + R 16 cc

When tQ1 as calculated from Vc1 and Vrf1 equals tQ2 as calculated from Vc2 and Vrf2, the following relationship can be derived: V rf2 V rf1 ----------- = ----------V C1 V C2 Therefore, tQ1= tQ2 and are independent of t, and tQ will not change so long as the ratio of Vc to Vrf is constant. When the transformer flyback current becomes zero, Vds starts to decrease. The time required for the voltage across the MOSFET to drop to its minimum value is: tR = L m Cr The equation shows that the time required to drop to minimum voltage is a function of the primary inductance, Lm, and capacitance, Cr, across the MOSFET. This means that tR is independent of changes in input and output voltage
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APPLICATION NOTE

6.2 Thermal shutdown

If the ambient temperature is high, or the temperature inside the device becomes too high due to abnormal operation, the junction temperature of the device can become too high. If it exceeds 150C, the Fairchild Power Switch (FPS) enters latch mode and stops.

6.3 Over current latch

A short circuit in a secondary side rectifier diode or on a transformer pin is equivalent to a leakage inductor of several mH connected to the input bulk capacitor. A large current spike can flow through the MOSFET in the Fairchild Power Switch (FPS), and the MOSFET will be destroyed if the current is not turned off within a few hundred nanoseconds. Although ICs with current mode control generally have over current protection, it may not execute properly due to delays in the IC's internal blocks. Hence, besides using pulse by pulse over current protection to turn off the MOSFET, the Fairchild Power Switch (FPS) also uses an over current latch. This allows the Fairchild Power Switch (FPS) to turn off the MOSFET within 200 ns if the current flow is higher than the over current protection level threshold. The Fairchild Power Switch (FPS) also operates in latch mode to reduce stress on the MOSFET that would result from repeated auto restarts. Once the Fairchild Power Switch (FPS) enters latch mode, the input ac power is cut off. The Fairchild Power Switch (FPS) will unlatch and restart only when Vcc drops below 5V.

6.4 Over load protection (OLP)

Refer to Figure 9, next page. The feedback loop causes the voltage Vfb, on the Fairchild Power Switch (FPS) feedback pin to increase when the output current increases. In the case of a persistent overload condition, Vfb continues to increase because 5mA current source in the Fairchild Power Switch (FPS) charges the compensation capacitor attached to the FB pin. If this voltage reaches 7.5V, the MOSFET stops switching. The delay between Vfb reaching the over current protection level and when the MOSFET stops switching is calculated as follows: ( 7.5 3 ) C 13 - [ sec ] t delay = ------------------------------------6 5 10 Auto restart begins after overload protection triggers.

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7. PCB Layout

3 C H B D EF 1 2

Figure 9.

A proper PCB layout not only reduces the set EMI, but also minimizes the noises that can produce device malfunction. Cautionary items when designing the PCB layout of the 5Q-series are as follows: The space between 2 pin in the 5Q-series and the bulk capacitor (DC link capacitor) - (Ground) terminal should be simple and close as possible. A thick pattern should be used. (C2 in the fig9, very important) PCB pattern should be made such that Cr is as close as possible to pin 1,2. If not, pulse like current flow path becomes longer every time the switch turns on, worsening the noise. (A1, B2 in the fig9, very important) The distance between 2 pin in the 5Q-series and the negative terminal of Vcc capacitor should be close as possible. (D2 in the fig9, very important) The distance between 2 pin in 5Q-series and the negative terminal of Vcc capacitor should be close as possible. (E2 in the fig9,important) The distance between 2pin in the 5Q-series and the negative terminal of Vfb capacitor should be close as possible. (F2 in the fig9,important) The feedback loop PCB pattern should be simple and not be placed close to a comparatively high current flow connection or device. The connection between the ground
2002 Fairchild Semiconductor Corporation

of output which is regulated and the ground of secondary error Amp. is simple and close as possible. (H3 in the fig9, very important) when the primary side control is used, the transformer Vcc (pin 3) winding must be made so as to result in the best coupling coefficient between it and the most important winding.

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APPLICATION NOTE

START-UP

PICTUREON

ST-BY

PICTUREON

OVP

PICTUREON

OLP

Vcc
VST-UP VSTOP
AUTORESTART

VF/B
VSd MAX. DUTY

Vout

Vds

Vovp Vsync

Figure 10. Operation Waveform.

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8. KA5Q Fairchild Power Switch Based SMPS for a Color TV

8.1 Secondary Side Regulation.

BD101

R102

T101

D207

BEAD204 7 C210 C211

fuse
C101

LF101

C102

C206

8 D102 D205 BEAD203 5 C208

R103

C207

C209 6

5Q SERIES

R104 D203 BEAD202 4

BEAD101

D105 C206

C214

C215 3

C107 D103 R106 D106 R107 D202 BEAD201

2 C201

C104

R105

C105

C205

C202

1 ZD101 OPT101 C103 C108 C109 C213

R201 R203 OPT101

R206 VR202 VR201 R204 D201 Q202

MCU
R207

C203 Q201 R205 R208

2002 Fairchild Semiconductor Corporation

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APPLICATION NOTE

8.2 Primary Side Regulation

R102

T101

D207

fuse
C101

LF101 BD101 C102 C206

BEAD20 4 C211

C210

8 D205 BEAD20 3

R103

C207

C208 C209 6

5Q SERIES

R104 D203 BEAD20 2

BEAD10 1 C107

D105

C206

C214 C215 3

D103 R106 R107 D202 BEAD20 1 2

C105 C104

R105

C205

C202 C201 1

ZD101 C103 OPT101 C109 C108 C213

R201 OPT101 R205

Micom
Q201 R207 Q202

R208

10

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Table 1. Parts List for KA5Q based SMPS Part # R101 R102 R103 R104 R105 R106 R107 R108 R109 R201 R202 R203 R204 R205 R206 R207 R208 VR201 VR202 Value open NTC 68k 68k 470 600 10 open open 1k short 1k 40k 4.7k 220k 5k 5k 30k 20 k [Diodes] D101 D102 D103 D104 D105 D106 D201 D202 open 1N4004 1N4937 short 1N4937 1N4148 1N4148 D06U20S(100W) D06U20S(150W) D06U20S(200W) ZNR 400V, 1A 600V, 1A 600V, 1A 600 V, 1A 75V, 0.15A 75V, 0.15A 200V, 6A 200V, 6A 200V, 10A TO-220F TO-220F TO-220F Rating [Resister] 1/2W 4.7 1/2W 1/2W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W fuse 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W box box Note Part # C104 C105 C106 C107 C108 C109 C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C212 C213 C214 C215 Value 47F 3.9nF open 2.2nF 560pF 47nF 1000F 1000F 22nF open 470pF 470pF 470pF 1000F 1000F 1000F 1000F 470pF 560pF 100F (100W) 220F (150W) 330F (200W) 330F (270W) 47F (100W) 100F (150W) 220F (200W) 220F (270W) Rating 50V 50V 50V 1000V 2000V 50V 50V 50V 50V 50V 1000V 1000V 1000V 50V 50V 50V 50V 1000V 2000V 200V 200V 200V 200V 200V 200V 200V 200V Note electrolytic film electrolytic film film film electrolytic electrolytic film film film film film electrolytic electrolytic electrolytic electrolytic film film electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic -

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APPLICATION NOTE

Table 1. Parts List for KA5Q based SMPS (continued) Part # D202 D203 Value D06U20S(270W) D10U60S D20U60S(270W) open D06U20S open D06U20S open [Zener] ZD101 4.7V C101 220nF 220F (100W) C102 330F (150W) 470F (200W) 560F (270W) C103 100nF 0.5W 275V 400V 400V 400V 400V 50V box electrolytic electrolytic electrolytic electrolytic film OPT101 T101 CON201 CON202 Q201 Q202 Rating [Diodes] 200V,20A 600V,10A 600V,20A 200V,10A 200V,10A TO-220F TO-220F TO-220F TO-220F TO-220F BEAD101 BEAD201 BEAD202 BEAD203 BEAD204 Note Part # Value ferrite bead ferrite bead 100 H ferrite bead ferrite bead [Others] H11A817A EER3542 EER4042 EER4942 EER5354 PWR CONN. PWR CONN. KA431LZ C945 KA5Q0765RT KA5Q12656RT KA5Q1265RT KA5Q1565RT npn (E.B.C) Fairchild Rating [Beads] 5A Note

12

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9. Example Transformer Design for Color TV SMPS

9.1 Define system specifications:
Output power, Po = 80W (125V,0.56A for B+ and 13V,0.76A) P B OUT = 70W ,P 13V OUT = 10W Input voltage, 85 to 265 V., (universal input), 60Hz Efficiency 80% Core = EER3542 (Ae = 108mm2)

9.2. Calculate minimum dc input voltage, Vinmin:

The table below shows typical values of Vinmin, Lm, Fsmin for various Pin values. The maximum power input is
Po 80W Pin_max = ------------------------------ = ------------ = 100W efficiency 0.8

For 100W Pin_max, there are two option for capacitor value; 220uF or 330uF. Here, select the 220uF. Then, 93V is the minimum dc input voltage.

Pin (W)

Cin [uF] 220

Vin_min [V] 98

Lm [uH] 700 675 650 700 675 650 600 575 550 600 575 550 500 475 450 500 475 450 400 375 350 400 375 350 350 325 300 350 325 300 325 300 275 325 300 275

Fs_min [kHz] 26.1 27.0 27.9 28.0 29.0 30.0 23.6 24.5 25.6 25.9 27.0 28.1 23.3 24.4 25.7 25.0 26.3 27.6 26.6 28.2 30.0 26.6 28.2 30.0 24.7 26.5 28.5 25.7 27.5 29.6 23.4 25.3 27.4 24.5 26.4 28.7

80 330 105

220 100 330

93

102

330 130 470

96

103

330 150 470

93

101

470 180 560

97

101

470 200 560

94

98

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APPLICATION NOTE

Pin (W)

Cin [uF] 560

Vin_min [V] 94

Lm [uH] 275 250 225 275 250 225 250 200 250 200

Fs_min [kHz] 23.3 25.5 28.1 24.5 26.8 24.5 22.0 24.3 23.4 25.9

240 680 560 270 680 99 91 96

However, because of voltage drops from the line filter, bridge diode, and NTC (negative thermal coefficient), set Vinmin to 100V to allow for a design margin and convenient calculation.

gap calculation to give the correct flux density. V in D max L m = -------------------------------2P in f s

2 2 2 2

9.3 Determine turns ratio, n = Np/Ns:

Turns ratio is a factor in determining Dmax, device operating voltage, and device and transformer dissipation. 650V + 2 V ( acmax ) 120 n = ----------------------------------------------------------------------Vo 650 2 265 120 n = --------------------------------------------------------125 = 1.25 where Vo is the output voltage used for B+ (125V) and 120V is the margin voltage. It can be determined by the designer, or the transformer, etc.

93 0.62 L m = -------------------------------------- = 554 H 2 100 30K Estimated gap length (lg) is NP o A e 3 - 10 l g = --------------------Lm
3 63 4 10 108 10 - 10 = -----------------------------------------------------------------------------6 620 10 = 0.868mm 2 7 6 2

Ae is the cross sectional area of the core = 4 10-7

9.4 Calculate maximum duty, Dmax:

Vo D max = --------------------------------V inmin + nV o 1.25 125 - = 0.62 D max = -----------------------------------------93 + 1.25 125

9.6 Calculate minimum primary turns, Npmin:

The primary turns count must be made larger than Npmin to prevent the transformer from saturating below the Fairchild Power Switch (FPS) Ipeak specification. V inmin D max N pmin = -----------------------------------------------( dB ) ( Ae ) ( Fsmin ) 93 0.62 10 - 59T N pmin = ------------------------------------------0.3 108 30K where dB is the absolute amount of flux density variation in the core.
6

9.5 Calculate transformer inductance, Lm:

Fs, is the minimum operating frequency at the condition of maximum load and minimum input voltage. Therefore Fs, should be set around 25-40kHz. Vinmin condition is calculated as above at operating frequency of any load. From the operating frequency, it is possible to estimate the device and transformer dissipation. Using Fs = 30kHz we calculate Lm. Fs should be corrected to 30103 in the equation below. Following this there should be some explanation of the core 14

2002 Fairchild Semiconductor Corporation

APPLICATION NOTE

AN4102

9.7 Calculate the maximum current, Ipeak,.

At full load and at minimum Vin, Ipeak must be lower than the Ipeak specification of the device to be used. V inmin D max I peak = -----------------------------L m f smin 93 0.62 I peak = ----------------------------------- = 3.46A 554 H 30k
I = 2 PB OUT 2 ( N pmin N 125V ) 1 - 1D ------------------------------------------------------------------------------------------------- -----L f min 3 m s = 2 1 70W 2 1.25 - ------ 0.38 -------------------------------------------554 uH 30kHz 3 = 1.291A

B rms

The wire diameter f of B+ is 0.60mm.

9.8 Determine each output turns count:

125V output: N125V = Npmin./ n = 47turns Volts per turn: (125V + 1V) 50 turns = 2.68V / turn 13V output: (13V + 1V) / 2.68V / turn = 5.22 = 5turns Vcc winding: (24V + 1V) / 2.68V/turn = 9.32 = 9turns 5A ;1mm
2

$ 2 = 1.291A ; # --! 2"

2 $ 2 - = 0.258mm # --! 2"

9.9 Determine wire diameter

The copper coil's current capability is Idensity, 5A/mm . The rms current through primary Np is 1.479A in the example. IPEAK = 3.28A

= 0.573mm Calculated as above, the wire diameter f of winding is 1mm. 13V bias

References
1. Transformer and Inductor Design Handbook. 2nd ed. Col. Wm. T. McLyman. Marcel Dekker, Inc., 1988.
D = 0.61

rms

= I

PEAK

1 - D -----3

1 - 0.62 = 3.46A -----3 = 1.577A

2. Flyback converter design using Fairchild Power Switch. Application note AN4105. Fairchild Electronics, 2000. KA3S0680RB, KA3S0680RFB, KA3S0880RB, KA3S0880RFB, KA3S0765R, KA3S0765RF, KA3S0965R, KA3S0965RF, KA3S1265R, KA3S1265RF, KA5Q0765RT, KA5Q12656RT, KA5Q1265RF, KA5Q1565RF, KA5Q0740RT, KA5Q0945RT

The wire diameter f of Np is 0.65mm.

2 $ 2 I d e nsity ;1mm = Irms ; # --! 2" 2 -$ 5A ;1mm = 1.479A ; # --! 2" 2 $ 2 - = 0.295mm # --! 2" 2

0.613mm % 0.65mm The rms current through secondary B+ is 1.246A in the example.

2002 Fairchild Semiconductor Corporation

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AN4102

APPLICATION NOTE

DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support which (a) are intended for surgical implant into the body, or device or system whose failure to perform can be (b) support or sustain life, or (c) whose failure to per-form reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling can be reasonably expected to result in significant injury to the user.

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3/19/04 0.0m 002 2002 Fairchild Semiconductor Corporation