Dm9000e PDF

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 1. General Description
The DM9000 is a fully integrated and cost-effective single chip Fast Ethernet MAC controller with a general processor interface, a 10/100M PHY and 4K Dword SRAM. It is designed with low power and high performance process that support 3.3V with 5V tolerance. The DM9000 also provides a MII interface to connect HPNA device or other transceivers that support MII interface. The DM9000 supports 8-bit, 16-bit and 32bit uP interfaces to internal memory accesses for different processors. The PHY of the DM9000 can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX. It is fully compliant with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9000 to take the maximum advantage of its abilities. The DM9000 also supports IEEE 802.3x full- duplex flow control. This programming of the DM9000 is very simple, so user can port the software drivers to any system easily.
2. Block Diagram
LED
External MII Interface
EEPROM Interface
PHYceiver
100 Base-TX transceiver TX+/10 Base-T Tx/Rx RX+/100 Base-TX PCS MII
MAC
TX Machine
Control &Status Registers
Memory Management
RX Machine
Internal SRAM
Autonegotiation
MII Management Control & MII Register
Final Version: DM9000-DS-F02 June 26, 2002
Processor Interface
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY Table of Contents
1. General Description ..............................................1 2. Block Diagram 1 3. Features ................................................................4 4. Pin Configuration ..................................................5 4.1 Pin Configuration I: with MII Interface.................5 4.2 Pin Configuration II: with 32-Bit Data Bus...........6 5. Pin Description......................................................7 5.1 MII Interface ........................................................7 5.2 Processor Interface.............................................8 5.3 EEPROM Interface. ............................................9 5.4 Clock Interface ....................................................9 5.5 LED Interface ......................................................9 5.6 10/100 PHY/Fiber .............................................10 5.7 Miscellaneous Pins ...........................................10 5.8 Power Pins ........................................................10 6. Vendor Control and Status Register Set.............11 6.1 Network Control Register (00H)........................13 6.2 Network Status Register (01H) .........................13 6.3 TX Control Register (02H) ................................13 6.4 TX Status Register I (03H)................................14 6.5 TX Status Register II (04H)...............................14 6.6 RX Control Register (05H) ................................14 6.7 RX Status Register (06H) .................................15 6.8 Receive Overflow Counter Register (07H) .......15 6.9 Back Pressure Threshold Register (08H) .........15 6.10 Flow Control Threshold Register (09H) ..........16 6.11 RX/TX Flow Control Register (0AH) ...............16 6.12 EEPROM & PHY Control Register (0BH) .......16 6.13 ROM & PHY Address Register (0CH) ............17 6.14 EEPROM & PHY Data Register (0DH, 0EH)..17 6.15 Wake Up Control Register (0FH)....................17 6.16 Physical Address Register (10H~15H) ...........17 6.17 Multicast Address Register (16H~1DH)..........18 6.18 General Purpose Control Register (1EH).18 6.19 General Purpose Register (1FH) ....................18 6.20 TX SRAM Read Pointer Address Register
2
(22H~23H) ..............................................................18 6.21 RX SRAM Write Pointer Address Register (24H~25H) .......................................................19 6.22 Vendor ID Register (28H~29H).......................19 6.23 Product ID Register (2AH~2BH) .....................19 6.24 Chip Revision Register (2CH).........................19 6.25 Special Mode Control Register (2FH).............19 6.26 Memory Data Read Command without Address Increment Register (F0H) ................................19 6.27 Memory Data Read Command with Address Increment Register (F2H) ................................19 6.28 Memory Data Read_ address Register (F4H~F5H) ......................................................19 6.29 Memory Data Write Command without Address Increment Register (F6H) ................................19 6.30 Memory Data Write Command with Address Increment Register (F8H) ................................19 6.31 Memory Data Write_ address Register (FAH~FBH) ......................................................20 6.32 TX Packet Length Register (FCH~FDH) ........20 6.33 Interrupt Status Register (FEH) ......................20 6.34 Interrupt Mask Register (FFH) ........................20 7. EEPROM Format ................................................21 8. MII Register Description......................................22 8.1 Basic Mode Control Register (BMCR) 00 ......23 8.2 Basic Mode Status Register (BMSR) 01........24 8.3 PHY ID Identifier Register #1 (PHYID1) 02 ...25 8.4 PHY Identifier Register #2 (PHYID2) 03........25 8.5 Auto-negotiation Advertisement Register (ANAR) 04 ....................................................26 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) 05 ................................................27 8.7 Auto-negotiation Expansion Register (ANER) 06 .....................................................................27 8.8 DAVICOM Specified Configuration Register (DSCR) 16 .....................................................28 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) 17 ...................................29 8.10 10BASE-T Configuration/Status (10BTCSR) 18 .....................................................................30
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
9. Functional Description ........................................31 9.1 Host Interface....................................................31 9.2 Direct Memory Access Control .........................31 9.3 Packet Transmission.........................................31 9.4 Packet Reception..............................................31 9.5 100Base-TX Operation .....................................32 9.5.1 4B5B Encoder................................................32 9.5.2 Scrambler.......................................................32 9.5.3 Parallel to Serial Converter ............................32 9.5.4 NRZ to NRZI Encoder....................................32 9.5.5 MLT-3 Converter............................................32 9.5.6 MLT-3 Driver ..................................................32 9.5.7 4B5B Code Group..........................................33 9.6 100Base-TX Receiver.......................................34 9.6.1 Signal Detect..................................................34 9.6.2 Adaptive Equalization ....................................34 9.6.3 MLT-3 to NRZI Decoder.................................34 9.6.4 Clock Recovery Module .................................34 9.6.5 NRZI to NRZ ..................................................34 9.6.6 Serial to Parallel.............................................34 9.6.7 Descrambler...................................................34 9.6.8 Code Group Alignment ..................................35 9.6.9 4B5B Decoder................................................35 9.7 10Base-T Operation..........................................35 9.8 Collision Detection ............................................35 9.9 Carrier Sense....................................................35 9.10 Auto-Negotiation .............................................35 9.11 Power Reduced Mode ....................................36 9.11.1 Power Down Mode.......................................36 9.11.2 Reduced Transmit Power Mode ..................36 10. DC and AC Electrical Characteristics ...............37 10.1 Absolute Maximum Rating (25!C) ................37 10.2 Operating Conditions ......................................37 10.3 DC Electrical Characteristics ..........................38 10.4 AC Electrical Characteristics & Timing Waveforms.......................................................39 10.4.1 TP Interface .................................................39 10.4.2 Oscillator/ Crystal Timing.............................39 10.4.3 Processor Register Read Timing.................39 10.4.4 Processor Register Write Timing .................40 10.4.5 External MII Interface Transmit Timing........41 10.4.6 External MII Interface Receive Timing.........41 10.4.7 MII Management Interface Timing ...............42 10.4.8 EEPROM Interface Timing ..........................42 11. Application Notes ..............................................43 11.1 Network Interface Signal Routing ...................43 11.2 10Base-T/100Base-TX Application Figure 11-1 .........................................................................43 11.3 10Base-T/100Base-TX (Power Reduction Application)"Figure 11-2................................44 11.4 Power Decoupling Capacitors Figure 11-3 .....45 11.5 Ground Plane Layout Figure 11-4 ..................46 11.6 Power Plane Partitioning Figure 11-5 .............47 11.7 Magnetics Selection Guide .............................48 11.8 Crystal Selection Guide Figure 11-6...............48 11.9 Application of reverse MII Figure 11-7............49 12. Package Information .........................................50 12.1 LQFP 100L Outline Dimensions .....................50 13. Appendix ...........................................................51 14. Order Information..............................................53 "
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 3. Features
Supports processor interface: byte/word/dword of I/O command to internal memory data operation Integrated 10/100M transceiver Supports MII and reverses MII interface Supports back pressure mode for half-duplex mode flow control IEEE802.3x flow control for full-duplex mode Supports wakeup frame, link status change and magic packet events for remote wake up Integrated 4K dword SRAM
Supports automatically load vendor ID and product ID from EEPROM Supports 4 GPIO pins Optional EEPROM configuration Very low power consumption mode: $ Power reduced mode (cable detection) $ $ Power down mode Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction.
# # #
# # #
# #
# #
Compatible with 3.3V and 5.0V tolerant I/O 100-pin LQFP with CMOS process
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 4. Pin Configuration
4.1 Pin Configuration I: with MII Interface
75 74 73 72 71 70 69 68 67
66 65 64 63 62 61 60 59 58 57 56
DGND NC LINK_O WAKEUP PW_RST# DGND SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 DVDD IO16 CMD SA4 SA5 SA6 SA7 SA8 SA9 DGND INT
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
NC NC DVDD DVDD GPIO3 GPIO2 GPIO1 GPIO0 EECS EECK EEDO EEDI DGND LINKACT# DUP# SPEED# CLK20MO DGND MDC MDIO DVDD TX_EN TXD3 TXD2 TXD1
DM9000
TXD0 TX_CLK TEST5 RX_CLK RX_ER RX_DV COL CRS DGND RXD3 RXD2 RXD1 RXD0 LINK_I DVDD AVDD TXOTXO+ AGND AGND RXIRXI+ AVDD AVDD BGRES
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
IOR# IOW# AEN IOWAIT DVDD SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 RST DGND TEST1 TEST2 TEST3 TEST4 DVDD X2_25M X1_25M DGND SD AGND
25
DM9000
4.2 Pin Configuration II: with 32-Bit Data Bus
DGND NC LINK_O WAKEUP PW_RST# DGND SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 DVDD IO16 CMD SA4 SA5 SA6 SA7 SA8 SA9 DGND INT
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC DVDD DVDD GPIO3 GPIO2 GPIO1 GPIO0 EECS EECK EEDO EEDI DGND LINKACT# DUP# SPEED# CLK20MO DGND IO32 SD16 DVDD NC SD17 SD18 SD19
DM9000
SD20 SD21 TEST5 SD22 SD23 SD24 SD25 SD26 DGND SD27 SD28 SD29 SD30 SD31 DVDD AVDD TXOTXO+ AGND AGND RXIRXI+ AVDD AVDD BGRES
IOR# IOW# AEN IOWAIT DVDD SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 RST DGND TEST1 TEST2 TEST3 TEST4 DVDD X2_25M X1_25M DGND SD AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, LI= reset Latch Input, #= asserted low P= Power,
5.1 MII Interface

Pin No. 37 41,40,39, 38 43 Pin Name LINK_I RXD [3:0] CRS I/O I I I/O External MII device link status External MII Receive Data 4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode External MII Carrier Sense Active high to indicate the pressure of carrier, due to receive or transmit activities in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface. External MII Collision Detect. This pin is output in reverse MII interface. External MII Receive Data Valid External MII Receive Error External MII Receive Clock External MII Transmit Clock. This pin is output in reverse MII interface. External MII Transmit Data 4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps nibble mode TXD [2:0] is also used as the strap pins of IO base address. IO base = (strap pin value of TXD [2:0]) * 10H + 300H External MII Transmit Enable MII Serial Management Data MII Serial Management Data Clock This pin is also used as the strap pin of the polarity of the INT pin When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin is high active Description
44 45 46 47 49 53,52,51, 50
COL RX_DV RX_ER RX_CLK TX_CLK TXD [3:0]
I/O I I I I/O O
54 56 57
TX_ EN MDIO MDC
O I/O O
Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally
5.2 Processor Interface

1 IOR# I Processor Read Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Processor Write Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Address Enable A low active signal used to select the DM9000. Processor Command Ready When a command is issued before last command is completed, the IOWAIT will be pulled low to indicate the current command is waited
7
IOW#
AEN
IOWAIT
DM9000
14 6,7,8,9,10, 11,12,13, 89,88,87, 86,85,84, 83,82 RST I Hardware Reset Command, active high to reset the DM9000
SD0~15
I/O
Processor Data Bus bit 0~15
93,94,95, 96,97,98
SA4~9
92
CMD
91
IO16
100
INT
SD16~31 (in 56,53,52, double word 51,50,49, mode) 47,46,45, 44,43,41, 40,39,38 37 57 IO32 (in double word mode)
I/O
Address Bus 4~9 These pins are used to select the DM9000. When SA9 and SA8 are in high states, and SA7 and AEN are in low states, and SA6~4 are matched with strap pins TXD2~0, the DM9000 is selected. Command Type When high, the access of this command cycle is DATA port When low, the access of this command cycle is ADDRESS port Word Command Indication When the access of internal memory is word or dword width, this pin will be asserted This pin is low active at default Interrupt Request This pin is high active at default, its polarity can be modified by EEPROM setting or strap pin MDC. See the EEPROM content description for detail Processor Data Bus bit 16~31 These pins are used as data bus bits 16~31 when the DM9000 is set to double word mode (the straps pin EEDO is pulled high and WAKEUP is not pull-high)
Double Word Command Indication This pins is used as the double word command indication when the DM9000 is set to double data word mode, and this pin will be asserted when the access of internal memory is double word width This pin is low active at default
Note: The pins of processor interface except SD8,SD9 and IO16 are all have a pulled down resistor about 60k ohm internally
5.3 EEPROM Interface 64 EEDI 65 EEDO
I I/O
Data from EEPROM Data to EEPROM This pin is also used as a strap pin. It combines with strap pin WAKEUP, and it can set the data width of the internal memory access The decoder table is the following, where the logic 1 means the strap pin is pulled high WAKEUP EEDO data width 0 0 16-bit 0 1 32-bit 1 0 8-bit 1 1 reserved
DM9000
66 67 EECK EECS O I/O Clock to EEPROM Chip Select to EEPROM This pin is also used as a strap pin to define the LED modes. When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface 21 X2_25M 22 59 X1_25M CLK20MO
O I O
Crystal 25MHz Out Crystal 25MHz In 20Mhz Clock Output It is used as the clock signal for the external MII devices clock is 20MHz This pin has a pulled down resistor about 60k ohm internally.
5.5 LED Interface 60 SPEED100#
61
DUP#
62
LINK&ACT#
Speed LED Its low output indicates that the internal PHY is operated in 100M/S, or it is floating for the 10M mode of the internal PHY Full-duplex LED In LED mode 1, Its low output indicates that the internal PHY is operated in full-duplex mode, or it is floating for the half-duplex mode of the internal PHY In LED mode 0, Its low output indicates that the internal PHY is operated in 10M mode, or it is floating for the 100M mode of the internal PHY Link LED In LED mode 1, it is the combined LED of link and carrier sense signal of the internal PHY In LED mode 0, it is the LED of the carrier sense signal of the internal PHY only
5.6 10/100 PHY/Fiber 24 SD
25 26 27 28 29 30 31 32 33
BGGND BGRES AVDD AVDD RXI+ RXIAGND AGND TXO+
P I/O P P I I P P O
Fiber-optic Signal Detect PECL signal, which indicates whether or not the fiber-optic receive pair is receiving valid levels Bandgap Ground Bandgap Pin Bandgap and Guard Ring Power RX Power TP RX Input TP RX Input RX Ground TX Ground TP TX Output
9
DM9000
34 35 TXOAVDD O P TP TX Output TX Power
5.7 Miscellaneous 16,17,18, TEST1~TEST4 19 48 68,69,70, 71 TEST5 GPIO0~3
Operation Mode Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application It must be ground. General I/O Ports Registers GPCR and GPR can program these pins The GPIO0 is an output mode, and output data high at default is to power down internal PHY and other external MII device GPIO1~3 defaults are input ports Cable Link Status Output. Active High This pin is also used as a strap pin to define whether the MII interface is a reversed MII interface (pulled high) or a normal MII interface (not pulled high). This pin has a pulled down resistor about 60k ohm internally. Issue a wake up signal when wake up event happens This pin has a pulled down resistor about 60k ohm internally. Power on Reset Active low signal to initiate the DM9000 The DM9000 is ready after 5us when this pin deasserted Not Connect
I I/O
78
LINK_O
79 80
WAKEUP PW_RST#
O I
74,75,77
NC
5.8 Power Pins DVDD 5,20,36, 55,72,90, 73 15,23,42, DGND 58,63,81, 99,76
Digital VDD
Digital GND
10
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6. Vendor Control and Status Register Set
The DM9000 implements several control and status registers, which can be accessed by the host. These CSRs Register NCR NSR TCR TSR I TSR II RCR RSR ROCR BPTR FCTR FCR EPCR EPAR EPDRL EPDRH WCR PAR MAR GPCR GPR TRPAL TRPAH RWPAL RWPAH VID PID CHIPR SMCR MRCMDX MRCMD MRRL MRRH MWCMDX MWCMD MWRL Description Network Control Register Network Status Register TX Control Register TX Status Register I TX Status Register II RX Control Register RX Status Register Receive Overflow Counter Register Back Pressure Threshold Register Flow Control Threshold Register RX Flow Control Register EEPROM & PHY Control Register EEPROM & PHY Address Register EEPROM & PHY Low Byte Data Register EEPROM & PHY High Byte Data Register Wake Up Control Register Physical Address Register Multicast Address Register General Purpose Control Register General Purpose Register TX SRAM Read Pointer Address Low Byte TX SRAM Read Pointer Address High Byte RX SRAM Write Pointer Address Low Byte RX SRAM Write Pointer Address High Byte Vendor ID Product ID CHIP Revision Special Mode Control Register Memory Data Read Command Without Address Increment Register Memory Data Read Command With Address Increment Register Memory Data Read_ address Register Low Byte Memory Data Read_ address Register High Byte Memory Data Write Command Without Address Increment Register Memory Data Write Command With Address Increment Register Memory Data Write_ address Register Low Byte are byte aligned. All CSRs are set to their default values by hardware or software reset unless they are specified Offset 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H-15H 16H-1DH 1EH 1FH 22H 23H 24H 25H 28H-29H 2AH-2BH 2CH 2FH F0H F2H F4H F5H F6H F8H FAH Default value after reset 00H 00H 00H 00H 00H 00H 00H 00H 37H 38H 00H 00H 40H XXH XXH 00H Determined by EEPROM XXH 01H XXH 00H 00H 04H 0CH 0A46H 9000H 00H 00H XXH XXH 00H 00H XXH XXH 00H
11
DM9000
MWRH TXPLL TXPLH ISR IMR Memory Data Write _ address Register High Byte TX Packet Length Low Byte Register TX Packet Length High Byte Register Interrupt Status Register Interrupt Mask Register FBH FCH FDH FEH FFH 00H XXH XXH 00H 00H
Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> Where% <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value <Access Type>: RO = Read only RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write 1 WO = Write only Reserved bits are shaded and should be written with 0. Reserved bits are undefined on read access.
12
DM9000
6.1 Network Control Register (00H) Bit Name Default Description 7 EXT_PHY 0,RW Selects external PHY when set. Selects Internal PHY when clear. This bit will not be affected after software reset 6 WAKEEN 0,RW Wakeup Event Enable When set, it enables the wakeup function. Clearing this bit will also clears all wakeup event status This bit will not be affected after a software reset 5 RESERVED 0,RO Reserved 4 FCOL 0,RW Force Collision Mode, used for testing 3 FDX 0,RW Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode 2:1 LBK 00,RW Loopback Mode Bit 2 1 0 0 Normal 0 1 MAC Internal loopback 1 0 Internal PHY 100M mode digital loopback 1 1 (Reserved) 0 RST 0,RW Software reset and auto clear after 10us 6.2 Network Status Register (01H) Bit Name Default 7 SPEED 0,RO 6 5 4 3 2 1 0 LINKST WAKEST RESERVED TX2END TX1END RXOV RESERVED 0,RO 0,RW/C1 0,RO 0,RW/C1 0,RW/C1 0,RO 0,RO
Description Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no meaning when LINKST=0 Link Status 0:link failed 1:link OK, when Internal PHY is used Wakeup Event Status. Clears by read or write 1 This bit will not be affected after software reset Reserved TX Packet 2 Complete Status. Clears by read or write 1 Transmit completion of packet index 2 TX Packet 1 Complete status. Clears by read or write 1 Transmit completion of packet index 1 RX FIFO Overflow Reserved
6.3 TX Control Register (02H) Bit Name Default 7 RESERVED 0,RO 6 5 4 3 2 1 0 TJDIS EXCECM PAD_DIS2 CRC_DIS2 PAD_DIS1 CRC_DIS1 TXREQ 0,RW 0,RW 0,RW 0,RW 0,RW 0,RW 0,RW
Description Reserved Transmit Jabber Disable When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable Excessive Collision Mode Control : 0:aborts this packet when excessive collision counts more than 15, 1: still tries to transmit this packet PAD Appends Disable for Packet Index 2 CRC Appends Disable for Packet Index 2 PAD Appends Disable for Packet Index 1 CRC Appends Disable for Packet Index 1 TX Request. Auto clears after sending completely
13
DM9000
6.4 TX Status Register I ( 03H ) for packet index I Bit Name Default Description 7 TJTO 0,RO Transmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted 6 LC 0,RO Loss of Carrier It is set to indicate the loss of carrier during the frame transmission. It is not valid in internal loopback mode 5 NC 0,RO No Carrier It is set to indicate that there is no carrier signal during the frame transmission. It is not valid in internal loopback mode 4 LC 0,RO Late Collision It is set when a collision occurs after the collision window of 64 bytes 3 COL 0,RO Collision Packet It is set to indicate that the collision occurs during transmission 2 EC 0,RO Excessive Collision It is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 RESERVED 0,RO Reserved 6.5 TX Status Register II ( 04H ) for packet index I I Bit Name Default Description 7 TJTO 0,RO Transmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted 6 LC 0,RO Loss of Carrier It is set to indicate the loss of carrier during the frame transmission. It is not valid in internal loopback mode 5 NC 0,RO No Carrier It is set to indicate that there is no carrier signal during the frame transmission. It is not valid in internal loopback mode 4 LC 0,RO Late Collision It is set when a collision occurs after the collision window of 64 bytes 3 COL 0,RO Collision packet, collision occurs during transmission 2 EC 0,RO Excessive Collision It is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 RESERVED 0,RO Reserved 6.6 RX Control Register ( 05H ) Bit Name Default 7 RESERVED 0,RO WTDIS 0,RW 6 5 4 3 2 1 0
14
Description Reserved Watchdog Timer Disable When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled Discard Long Packet Packet length is over 1522byte Discard CRC Error Packet Pass All Multicast Pass Runt Packet Promiscuous Mode RX Enable
DIS_LONG DIS_CRC ALL RUNT PRMSC RXEN
0,RW 0,RW 0,RW 0,RW 0,RW 0,RW
DM9000
6.7 RX Status Register ( 06H ) Bit Name Default 7 RF 0,RO 6 5 4 3 2 1 0 MF LCS RWTO PLE AE CE FOE 0,RO 0,RO 0,RO 0,RO 0,RO 0,RO 0,RO Description Runt Frame It is set to indicate that the size of the received frame is smaller than 64 bytes Multicast Frame It is set to indicate that the received frame has a multicast address Late Collision Seen It is set to indicate that a late collision is found during the frame reception Receive Watchdog Time-Out It is set to indicate that it receives more than 2048 bytes Physical Layer Error It is set to indicate that a physical layer error is found during the frame reception Alignment Error It is set to indicate that the received frame ends with a non-byte boundary CRC Error It is set to indicate that the received frame ends with a CRC error FIFO Overflow Error It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H ) Bit Name Default Description 7 RXFU 0,R/C Receive Overflow Counter Overflow This bit is set when the ROC has an overflow condition 6:0 ROC 0,R/C Receive Overflow Counter This is a statistic counter to indicate the received packet count upon FIFO overflow 6.9 Back Pressure Threshold Register (08H) Bit Name Default Description 7:4 BPHW 3H, RW Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern when RX SRAM free space is lower than this threshold value Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes) 3:0 JPT 7H, RW Jam Pattern Time. Default is 200us bit3 bit2 bit1 bit0 time 0 0 0 0 5us 0 0 0 1 10us 0 0 1 0 15us 0 0 1 1 25us 0 1 0 0 50us 0 1 0 1 100us 0 1 1 0 150us 0 1 1 1 200us 1 0 0 0 250us 1 0 0 1 300us 1 0 1 0 350us 1 0 1 1 400us 1 1 0 0 450us 1 1 0 1 500us 1 1 1 0 550us 1 1 1 1 600us
Final Version: DM9000-DS-F02 June 26, 2002 15
DM9000
6.10 Flow Control Threshold Register ( 09H ) Bit Name Default Description 7:4 HWOT 3H, RW RX FIFO High Water Overflow Threshold Send a pause packet with pause_ time=FFFFH when the RX RAM free space is less than this value., If this value is zero, its means no free RX SRAM space. Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes) 3:0 LWOT 8H, RW RX FIFO Low Water Overflow Threshold Send a pause packet with pause_time=0000 when RX SRAM free space is larger than this value. This pause packet is enabled after the high water pause packet is transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM size (1 unit=1K bytes) 6.11 RX/TX Flow Control Register ( 0AH ) Bit Name Default Description 7 TXP0 0,RW TX Pause Packet Auto clears after pause packet transmission completion. Set to TX pause packet with time = 0000h 6 TXPF 0,RW TX Pause packet Auto clears after pause packet transmission completion. Set to TX pause packet with time = FFFFH 5 TXPEN 0,RW Force TX Pause Packet Enable Enables the pause packet for high/low water threshold control 4 BKPA 0,RW Back Pressure Mode This mode is for half duplex mode only. It generates a jam pattern when any packet comes and RX SRAM is over BPHW 3 BKPM 0,RW Back Pressure Mode This mode is for half duplex mode only. It generates a jam pattern when a packets DA matches and RX SRAM is over BPHW 2 RXPS 0,R/C RX Pause Packet Status, latch and read clearly 1 RXPCS 0,RO RX Pause Packet Current Status 0 FLCE 0,RW Flow Control Enable Set to enable the flow control mode (i.e. to disable TX function) 6.12 EEPROM & PHY Control Register ( 0BH ) Bit Name Default Description 7:6 RESERVED 0,RO Reserved 5 REEP 0,RW Reload EEPROM. Driver needs to clear it up after the operation completes 4 WEP 0,RW Write EEPROM Enable 3 EPOS 0,RW EEPROM or PHY Operation Select When reset, select EEPROM; when set, select PHY 2 ERPRR 0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after the operation completes. 1 ERPRW 0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after the operation completes. 0 ERRE 0,RO EEPROM Access Status or PHY Access Status When set, it indicates that the EEPROM or PHY access is in progress
16
DM9000
6.13 EEPROM & PHY Address Register ( 0CH ) Bit Name Default Description 7:6 PHY_ADR 01,RW PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if internal PHY is selected 5:0 EROA 0,RW EEPROM Word Address or PHY Register Address 6.14 EEPROM & PHY Data Register (EE_PHY_L%0DH EE_PHY_H%0EH) Bit Name Default Description 7:0 EE_PHY_L X,RW EEPROM or PHY Low Byte Data This data is made to write low byte of word address defined in Reg. CH to EEPROM or PHY 7:0 EE_PHY_H X,RW EEPROM or PHY High Byte Data This data is made to write high byte of word address defined in Reg. CH to EEPROM or PHY 6.15 Wake Up Control Register ( 0FH ) Bit Name Type Description 7:6 RESERVED 0,RO Reserved 5 LINKEN 0,RW When set, it enables Link Status Change Wake up Event This bit will not be affected after software reset 4 SAMPLEEN 0,RW When set, it enables Sample Frame Wake up Event This bit will not be affected after software reset 3 MAGICEN 0,RW When set, it enables Magic Packet Wake up Event This bit will not be affected after software reset 2 LINKST 0,RO When set, it indicates that Link Change and Link Status Change Event occurred This bit will not be affected after software reset 1 SAMPLEST 0,RO When set, it indicates that the sample frame is received and Sample Frame Event occurred. This bit will not be affected after software reset 0 MAGICST 0,RO When set, indicates the Magic Packet is received and Magic packet Event occurred. This bit will not be affected after a software reset 6.16 Physical Address Register ( 10H~15H ) Bit Name Default 7:0 PAB5 X,RW Physical Address Byte 5 7:0 PAB4 X,RW Physical Address Byte 4 7:0 PAB3 X,RW Physical Address Byte 3 7:0 PAB2 X,RW Physical Address Byte 2 7:0 PAB1 X,RW Physical Address Byte 1 7:0 PAB0 X,RW Physical Address Byte 0
Description (15H) (14H) (13H) (12H) (11H) (10H)
17
DM9000
6.17 Multicast Address Register ( 16H~1DH ) Bit Name Default 7:0 MAB7 X,RW Multicast Address Byte 7 7:0 MAB6 X,RW Multicast Address Byte 6 7:0 MAB5 X,RW Multicast Address Byte 5 7:0 MAB4 X,RW Multicast Address Byte 4 7:0 MAB3 X,RW Multicast Address Byte 3 7:0 MAB2 X,RW Multicast Address Byte 2 7:0 MAB1 X,RW Multicast Address Byte 1 7:0 MAB0 X,RW Multicast Address Byte 0 Description (1DH) (1CH) (1BH) (1AH) (19H) (18H) (17H) (16H)
6.18 General purpose control Register ( 1EH ) Bit Name Default Description 7:4 RESERVED 0,RO Reserved 3:0 GEP_CNTL 0001,RW General Purpose Control Define the input/output direction of General Purpose Register When a bit is set 1, the direction of correspondent bit of General Purpose Register is output. GPIO0 default is output for POWER_DOWN function. Other defaults are input 6.19 General purpose Register ( 1FH ) Bit Name Default Description 7:4 RESERVED 0,RO Reserved 3:1 GEPIO3-1 0,RW General Purpose When the correspondent bit of General Purpose Control Register is 1, the value of the bit is reflected to pin GEPIO3-1 When the correspondent bit of General Purpose Control Register is 0, the value of the bit to be read is reflected from correspondent pins of GEPIO3-1 The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively 0 GEPIO0 1,RW General Purpose When the correspondent bit of General Purpose Control Register is 1, the value of the bit is the output to pin GEPIO0 When the correspondent bit of General Purpose Control Register is 0, the value of the bit to be read is reflected from pin GEPIO0. GEPIO0 default output 1 to POWER_DOWN Internal PHY. Driver needs to clear this POWER_DOWN signal by writing 0 when it wants PHY to be active. This default value can be programmed by EEPROM. Please refer to the EEPROM description 6.20 TX SRAM Read Pointer Address Register (22H~23H) Bit Name Default Description 7:0 TRPAH 00H,RO TX SRAM Read Pointer Address High Byte (23H) 7:0 TRPAL 00H.RO TX SRAM Read Pointer Address Low Byte (22H) 6.21 RX SRAM Write Pointer Address Register (24H~25H) Bit Name Default Description 7:0 RWPAH 0CH,RO RX SRAM Write Pointer Address High Byte (25H) 7:0 RWPAL 04H.RO RX SRAM Write Pointer Address Low Byte (24H)
18
DM9000
6.22 Vendor ID Register (28H~29H) Bit Name Default 7:0 VIDH 0AH,RO 7:0 VIDL 46H.RO Description Vendor ID High Byte (29H) Vendor ID Low Byte (28H)
6.23 Product ID Register (2AH~2BH) Bit Name Default 7:0 PIDH 90H,RO Product ID High Byte (2BH) 7:0 PIDL 00H.RO Product ID Low Byte (2AH) 6.24 Chip Revision Register (2CH) Bit Name Default 7:0 CHIPR 00H,RO
Description
Description CHIP Revision
6.25 Special Mode Control Register ( 2FH ) Bit Name Default 7 SM_EN 0,RW Special Mode Enable 6~3 RESERVED 0,RO Reserved 2 FLC 0,RW Force Late Collision 1 FB1 0,RW Force Longest Back-off time 0 FB0 0,RW Force Shortest Back-off time
Description
6.26 Memory Data Read Command without Address Increment Register (F0H) Bit Name Default Description 7:0 MRCMDX X,RO Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged 6.27 Memory Data Read Command with Address Increment Register (F2H) Bit Name Default Description 7:0 MRCMD X,RO Read data from RX SRAM. After the read of this command, the read pointer is increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit respectively) 6.28 Memory Data Read_address Register (F4H~F5H) Bit Name Default Description 7:0 MDRAH 00H,R/W Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1 7:0 MDRAL 00H,R/W Memory Data Read_ address Low Byte 6.29 Memory Data Write Command without Address Increment Register (F6H) Bit Name Default Description 7:0 MWCMDX X,WO Write data to TX SRAM. After the write of this command, the write pointer is unchanged
19
DM9000
6.30 Memory data write command with address increment Register (F8H) Bit Name Default Description 7:0 MWCMD X,WO Write Data to TX SRAM After the write of this command, the write pointer is increased by 1,2, or 4, depends on the operator mode. (8-bit, 16-bit,32-bit respectively) 6.31 Memory data write_address Register (FAH~FBH) Bit Name Default Description 7:0 MDRAH 00H,R/W Memory Data Write_ address High Byte 7:0 MDRAL 00H,R/W Memory Data Write_ address Low Byte 6.32 TX Packet Length Register (FCH~FDH) Bit Name Default 7:0 TXPLH X,R/W TX Packet Length High byte 7:0 TXPLL X,,R/W TX Packet Length Low byte
Description
6.33 Interrupt Status Register (FEH) Bit Name Default Description 7:6 IOMODE 0, RO Bit 7 Bit 6 0 0 16-bit mode 0 1 32-bit mode 1 0 8-bit mode 1 1 Reserved 5~4 RESERVED 0,RO Reserved 3 ROOS 0,RW/C1 Receive Overflow Counter Overflow Latch 2 ROS 0,RW/C1 Rx Overflow Latch 1 PTS 0,RW/C1 Packet Transmitted Latch 0 PRS 0,RW/C1 Packet Received Latch 6.34 Interrupt Mask Register (FFH) Bit Name Default 7 PAR 0,RW 6~4 3 2 1 0 RESERVED ROOM ROM PTM PRM 0,RO 0,RW 0,RW 0,RW 0,RW
Description Enable the SRAM read/write pointer to automatically return to the start address when pointer addresses are over the SRAM size. Driver needs to set. When driver sets this bit, REG_F5 will set to 0Ch automatically Reserved Enable Receive Overflow Counter Overflow Latch Enable RX Overflow Latch Enable Packet Transmitted Latch Enable Packet Received Latch
20
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 7. EEPROM Format
name MAC address Auto Load Control Word 0 3 offset Description 0~5 6 Byte Ethernet Address 6-7 Bit 1:0=01: Update vendor ID and product ID Bit 3:2=01: Accept setting of WORD6 [8:0] Bit 5:4=01: Accept setting of WORD6 [11:9] Bit 7:6=01: Accept setting of WORD7 [3:0] Bit 9:8=01: Accept setting of WORD7 [6:4] Bit 11:10=01: Accept setting of WORD7 [7] Bit 13:12=01: Accept setting of WORD7 [8] Bit 15:14=01: reserved 8-9 2 byte vendor ID (Default: 0A46H) 10-11 2 byte product ID (Default: 9000H) 12-13 When word 3 bit [3:2]=01, these bits can control the IOR, IOW and INT pins polarity. Bit0: Reserved Bit1: IOR pin is active low when set (default: active low) Bit2: IOW pin is active low when set (default: active low) Bit3: INT pin is active low when set (default: active high) Bit4: INT pin s open-collected (default: force output) Bit5: Reserved Bit6: Reserved Bit7: Reserved Bit8: Reserved When word 3 bit [5:4]=01, the I/O base can be re-configured. Bit11:09: I/O base (default: 300H) 000 : 300H 001 : 310H 010 : 320H 011 : 330H 100 : 340H 101 : 350H 110 : 360H 111 : 370H Bit15:12: reserved Depend on the setting of word 3: Bit0: The WAKEUP pin is active low when set (default: active high) Bit1: The WAKEUP pin is in pulse mode when set (default: level mode) Bit2: magic wakeup event is enabled when set. (default: no)) Bit3: link_change wakeup event is enabled when set (default: no) Bit6:4: reserved Bit7: LED mode 1 (default: 0) Bit8: internal PHY is enabled after power-on (default: no) The GPR bit 0 and the GPIO0 pin are modified from this bit. Bit15:9: reserved
Vendor ID Product ID pin control
4 5 6
Wake-up mode control
14-15
RESERVED RESERVED
8 9
16-17 18-19
21
DM9000
RESERVED RESERVED 10 11 20-21 22-23
8. MII Register Description

AD Name 15 D 00 CONTROL Reset 01 STATUS T4 Cap. 0 1 Next Page LP Next Page 14 Loop back TX FDX Cap. 0 0 FLP Rcv Ack LP Ack 13 12 11 10 Isolate 9 8 7 Coll. Test Pream. Supr. 0 Auto-N Compl. 0 Remote Fault 0 6 5 4 3 Reserved Link Jabber Status Detect 0 0 Version No. Advertised Protocol Selector Field Link Partner Protocol Selector Field Pardet Fault Rsvd Rsvd Force Reserved 100LNK PHY ADDR [4:0] LP Next Pg Able Next Pg Able New Pg Rcv LP AutoN Cap. Remote LoopOut Auto-N Cap. 0 Extd Cap. 0 2 1 0 Speed Auto-N Power Select Enable Down TX HDX 10 FDX 10 HDX Cap. Cap. Cap. 0 0 0 1 1 1 Remote Reserved Fault LP Reserved RF Restart Full Auto-N Duplex Reserved 0 T4 Adv LP T4 1
02 PHYID1 03 PHYID2 04 Auto-Neg. Advertise 05 Link Part. Ability 06 Auto-Neg. Expansion 16 Specified Config. 17 Specified Conf/Stat 18 10T Conf/Stat
0 0 FC Adv LP FC Reserved
1 Model No. TX FDX TX HDX 10 FDX 10 HDX Adv Adv Adv Adv LP LP LP LP TX FDX TX HDX 10 FDX 10 HDX
BP 4B5B 100 FDX Rsvd
BP SCR 100 HDX LP Enable
BP BP_AD Rsvd TX ALIGN POK 10 10 HDX Reserved FDX HBE SQUE JAB 10T Enable Enable Enable Serial
RPDCTR Reset -EN St. Mch
Pream. Sleep Supr. mode Auto-N. Monitor Bit [3:0]
Reserved
Polarity Reverse
Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where% <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched from pin # at reset <Access Type>: RO = Read Only RW = Read/Write <Attribute (s)>: SC = Self Clearing P = Value Permanently Set LL = Latching Low LH = Latching High
22
DM9000
ISA to Ethernet MAC controller with integrated 10/100 PHY
8.1 Basic Mode Control Register (BMCR) - 00 Bit Bit Name Default Description 0.15 Reset 0, RW/SC Reset 1=Software reset 0=Normal operation This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed 0.14 Loopback 0, RW Loopback Loop-back control register 1 = Loop-back enabled 0 = Normal operation In 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the MII receive outputs 0.13 Speed selection 1, RW Speed Select 1 = 100Mbps 0 = 10Mbps Link speed may be selected either by this bit or by auto-negotiation. When auto-negotiation is enabled and bit 12 is set, this bit will return to the auto-negotiation selected media type 1, RW Auto-negotiation Enable 0.12 Auto1 = Auto-negotiation is enabled, bit 8 and 13 will be in autonegotiation negotiation status enable 0.11 Power down 0, RW Power Down While in the power-down state, the PHY should respond to the management transactions. During the transition to power-down state and while in the power-down state, the PHY should not generate spurious signals on the MII 1=Power down 0=Normal operation 0.10 Isolate 0,RW Isolate 1 = Isolates the PHY from the MII with the exception of the serial management. (When this bit is asserted, the PHY does not respond to the TXD [0:3], TX_EN, and TX_ER inputs, and it shall present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[0:3], COL and CRS outputs. When PHY is isolated from the MII it shall respond to the management transactions) 0 = Normal operation 0.9 Restart auto0,RW/SC Restart Auto-negotiation negotiation 1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning a value of 1 until autonegotiation is initiated by the PHY. The operation of the autonegotiation process will not be affected by the management entity that clears this bit 0 = Normal operation
Final Version: DM9000-DS-F01 April 12, 2002
23
DM9000
0.8 Duplex mode 1,RW Duplex Mode 1 = Full duplex operation. Duplex selection is allowed when Autonegotiation is disabled (bit 12 of this register is cleared). With enabled auto-negotiation, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation Collision Test 1 = Collision test is enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN 0 = Normal operation Reserved Write as 0, ignore on read
0.7
Collision test
0,RW
0.6-0.0
RESERVED
0,RO
8.2 Basic Mode Status Register (BMSR) - 01 Bit Bit Name Default Description 1.15 100BASE-T4 0,RO/P 100BASE-T4 Capable 1 = Able to perform in 100BASE-T4 mode 0 = Not able to perform in 100BASE-T4 mode 1.14 100BASE-TX 1,RO/P 100BASE-TX Full Duplex Capable full duplex 1 = Able to perform 100BASE-TX in full duplex mode 0 = Not able to perform 100BASE-TX in full duplex mode 1.13 100BASE-TX 1,RO/P 100BASE-TX Half Duplex Capable half duplex 1 = Able to perform 100BASE-TX in half duplex mode 0 = Not able to perform 100BASE-TX in half duplex mode 1.12 10BASE-T 1,RO/P 10BASE-T Full Duplex Capable full duplex 1 = Able to perform 10BASE-T in full duplex mode 0 = Not able to perform 10BASE-TX in full duplex mode 1.11 10BASE-T 1,RO/P 10BASE-T Half Duplex Capable half duplex 1 = Able to perform 10BASE-T in half duplex mode 0 = Not able to perform 10BASE-T in half duplex mode 1.10-1.7 RESERVED 0,RO Reserved Write as 0, ignore on read 1.6 MF preamble 0,RO MII Frame Preamble Suppression suppression 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed 0,RO Auto-negotiation Complete 1.5 Auto1 = Auto-negotiation process completed negotiation 0 = Auto-negotiation process not completed Complete 1.4 Remote fault 0, Remote Fault 0,RO/LH 1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is specific PHY implementation. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0 = No remote fault condition detected 1,RO/P Auto Configuration Ability 1.3 Auto1 = Able to perform auto-negotiation negotiation 0 = Not able to perform auto-negotiation Ability 1.2 Link status 0,RO/LL Link Status 1 = Valid link is established (for either 10Mbps or 100Mbps
24 Final Version: DM9000-DS-F02 June 26, 2002
DM9000
operation) 0 = Link is not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be, and remain cleared until it is read via the management interface Jabber Detect 1 = Jabber condition detected 0 = No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a PHY reset. This bit works only in 10Mbps mode Extended Capability 1 = Extended register capable 0 = Basic register capable only
1.1
Jabber detect
0, RO/LH
1.0
Extended capability
1,RO/P
8.3 PHY ID Identifier Register #1 (PHYID1) - 02 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E Bit 2.15-2.0 Bit Name OUI_MSB Default <0181H> Description OUI Most Significant Bits Bit 3 to 18 of the OUI (00606E) are mapped to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY Identifier Register #2 (PHYID2) - 03 Bit Bit Name Default Description 3.15-3.10 OUI_LSB <101110>, OUI Least Significant Bits RO/P Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively 3.9-3.4 VNDR_MDL <001100>, Vendor Model Number RO/P Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3.3-3.0 MDL_REV <0000>, Model Revision Number RO/P Four bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3)
25
DM9000
8.5 Auto-negotiation Advertisement Register (ANAR) - 04 This register contains the advertised abilities of this DM9000 device as they will be transmitted to its link partner during Auto-negotiation. Bit 4.15 Bit Name NP Description Next Page Indication 0 = No next page available 1 = Next page available The PHY has no next page, so this bit is permanently set to 0 0,RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The PHY's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit 0, RW Remote Fault 1 = Local device senses a fault condition 0 = No fault detected X, RW Reserved Write as 0, ignore on read 0, RW Flow Control Support 1 = Controller chip supports flow control ability 0 = Controller chip doesnt support flow control ability 0, RO/P 100BASE-T4 Support 1 = 100BASE-T4 is supported by the local device 0 = 100BASE-T4 is not supported The PHY does not support 100BASE-T4 so this bit is permanently set to 0 1, RW 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the local device 0 = 100BASE-TX full duplex is not supported 1, RW 100BASE-TX Support 1 = 100BASE-TX is supported by the local device 0 = 100BASE-TX is not supported 1, RW 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the local device 0 = 10BASE-T full duplex is not supported 1, RW 10BASE-T Support 1 = 10BASE-T is supported by the local device 0 = 10BASE-T is not supported <00001>, RW Protocol Selection Bits These bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD Default 0,RO/P
4.14
ACK
4.13 4.12-4.11 4.10 4.9
RF RESERVED FCS T4
4.8 4.7 4.6 4.5 4.4-4.0
TX_FDX TX_HDX 10_FDX 10_HDX Selector
26
DM9000
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation Bit 5.15 5.14 Bit Name NP ACK Description Next Page Indication 0 = Link partner, no next page available 1 = Link partner, next page available 0, RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The PHY's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit 0, RO Remote Fault 1 = Remote fault indicated by link partner 0 = No remote fault indicated by link partner X, RO Reserved Write as 0, ignore on read 0, RW Flow Control Support 1 = Controller chip supports flow control ability by link partner 0 = Controller chip doesnt support flow control ability by link partner 0, RO 100BASE-T4 Support 1 = 100BASE-T4 is supported by the link partner 0 = 100BASE-T4 is not supported by the link partner 0, RO 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the link partner 0 = 100BASE-TX full duplex is not supported by the link partner 0, RO 100BASE-TX Support 1 = 100BASE-TX half duplex is supported by the link partner 0 = 100BASE-TX half duplex is not supported by the link partner 0, RO 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the link partner 0 = 10BASE-T full duplex is not supported by the link partner 0, RO 10BASE-T Support 1 = 10BASE-T half duplex is supported by the link partner 0 = 10BASE-T half duplex is not supported by the link partner <00000>, RO Protocol Selection Bits Link partners binary encoded protocol selector Default 0, RO
5.13 5.12-5.11 5.10
RF RESERVED FCS
5.9 5.8 5.7 5.6 5.5 5.4-5.0
T4 TX_FDX TX_HDX 10_FDX 10_HDX Selector
8.7 Auto-negotiation Expansion Register (ANER)- 06 6.15-6.5 RESERVED X, RO Reserved Write as 0, ignore on read 6.4 PDF 0, RO/LH Local Device Parallel Detection Fault PDF = 1: A fault detected via parallel detection function. PDF = 0: No fault detected via parallel detection function 6.3 LP_NP_ABLE 0, RO Link Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page available LP_NP_ABLE = 0: Link partner, no next page 6.2 NP_ABLE 0,RO/P Local Device Next Page Able
DM9000
6.1 PAGE_RX 0, RO/LH NP_ABLE = 1: next page available NP_ABLE = 0: no next page New Page Received A new link of code-word page received. This bit will be automatically cleared when the register (register 6) is read by management Link Partner Auto-negotiation Able A 1 in this bit indicates that the link partner supports Autonegotiation
6.0
LP_AN_ABLE
0, RO
8.8 DAVICOM Specified Configuration Register (DSCR) - 16 Bit Bit Name Default Description 16.15 BP_4B5B 0, RW Bypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5ccccccccB and 5B4B operation 16.14 BP_SCR 0, RW Bypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 16.13 BP_ALIGN 0, RW Bypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 0 = Normal operation 16.12 BP_ADPOK 0, RW Bypass ADPOK Force signal detector (SD) active. This register is for debug only, not release to customers. 1=Force SD is OK 0=Normal operation 16.11 RESERVED 0, RO Reserved Write as 0, ignore on read 16.10 TX 1, RO 100BASE-TX 1 = 100BASE-TX operation 0 = Reserved 16.9 RESERVED 0, RO Reserved 16.8 RESERVED 0, RO Reserved Write as 0, ignore on read 16.7 F_LINK_100 0, RW Force Good Link in 100Mbps 0 = Normal 100Mbps operation 1 = Force 100Mbps good link status This bit is useful for diagnostic purposes 16.6 RESERVED 0, RO Reserved Write as 0, ignore on read Reserved 16.5 RESERVED 0, RO Write as 0, ignore on read Reduced Power Down Control Enable 16.4 RPDCTR-EN 1, RW This bit is used to enable automatic reduced power down 0: Disable automatic reduced power down 1: Enable automatic reduced power down Reset State Machine 16.3 SMRST 0, RW When writes 1 to this bit, all state machines of PHY will be reset.
28 Final Version: DM9000-DS-F02 June 26, 2002
DM9000
16.2 MFPSC 0, RW This bit is self-clear after reset is completed MF Preamble Suppression Control MII frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off Sleep Mode Writing a 1 to this bit will cause PHY to enter the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset Remote Loopout Control When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing
16.1
SLEEP
0, RW
16.0
RLOUT
0, RW
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 Bit Bit Name Default Description 17.15 100FDX 1, RO 100M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M full duplex mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.14 100HDX 1, RO 100M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M half duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.13 10FDX 1, RO 10M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.12 10HDX 1, RO 10M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M half duplex mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.11RESERVED 0, RO Reserved 17.9 Write as 0, ignore on read 17.8-17.4 PHYADR[4:0] (PHYADR), PHY Address Bit 4:0 RW The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY 17.3-17.0 ANMB[3:0] 0, RO Auto-negotiation Monitor Bits These bits are for debug only. The auto-negotiation status will be written to these bits
DM9000
B3 b2 b1 b0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 In IDLE State Ability Match Acknowledge Match Acknowledge Match Fail Consistency Match Consistency Match Fail Parallel Detects Signal_ link_ ready Parallel Detects Signal_ link_ ready Fail Auto-negotiation Completed Successfully
8.10 10BASE-T Configuration/Status (10BTCSR) - 18 Bit Bit Name Default Description 18.15 RESERVED 0, RO Reserved Write as 0, ignore on read 18.14 LP_EN 1, RW Link Pulse Enable 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation 18.13 HBE 1,RW Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the PHY is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) 18.12 SQUELCH 1, RW Squelch Enable 1 = normal squelch 0 = low squelch 18.11 JABEN 1, RW Jabber Enable Enables or disables the Jabber function when the PHY is in 10BASE-T full duplex or 10BASE-T transceiver loopback mode 1 = Jabber function enabled 0 = Jabber function disabled 18.10RESERVED 0, RO Reserved 18.1 Write as 0, ignore on read 18.0 POLR 0, RO Polarity reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is set and cleared by 10BASE-T module automatically
30
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 9. Functional Description
9.1 Host Interface The host interface is the ISA BUS compatible mode. There are eight IO bases, which are 300H, 310H, 320H, 330H, 340H, 350H, 360H, and 370H. The IO base is latched from strap pins or loaded from the EEPROM. There are only two addressing ports through the access of the host interface. One port is the INDEX port and the other is the DATA port. The INDEX port is decoded by the pin CMD =0 and the DATA port by the pin CMD =1. The contents of the INDEX port are the register address of the DATA port. Before the access of any register, the address of the register must be saved in the INDEX port. location 0x0C00 if the end of address (i.e. 16K) is reached.
9.3 Packet Transmission There are two packets, sequentially named as index I and index II, can be stored in the TX SRAM at the same time. The TX Control Register (02h) controls the insertion of CRC and pads. Their statuses are recorded at TX Status Register I (03h) and TX Status Register II (04h) respectively. The start address of transmission is 00h and the current packet is index I after software or hardware reset. Firstly write data to the TX SRAM using the DMA port and then write the byte count to byte_ count register at TX Packet Length Register (0fch/0fdh). Set the bit 0 of TX Control Register (02h). The DM9000 starts to transmit the index I packet. Before the transmission of the index I packet ends, the data of the next (index II) packet can be moved to TX SRAM. After the index I packet ends the transmission, write the byte count data of the index II to BYTE_COUNT register and then set the bit 0 of TX Control Register (02h) to transmit the index II packet. The following packets, named index I, II, I, II,, use the same way to be transmitted. 9.4 Packet Reception The RX SRAM is a ring data structure. The start address of RX SRAM is 0C00h after software or hardware reset. Each packet has a 4-byte header followed with the data of the reception packet which CRC field is included. The format of the 4-byte header is 01h, status, BYTE_COUNT low, and BYTE_COUNT high. It is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (the 8-bit, 16bit or 32-bit mode ).
9.2 Direct Memory Access Control The DM9000 provides DMA capability to simplify the access of the internal memory. After the programming of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. The memorys address will be increased with the size that equals to the current operation mode (i.e. the 8-bit, 16-bit or 32bit mode) and the data of the next location will be loaded into internal data buffer automatically. It is noted that the data of the first access (the dummy read/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. The internal memory size is 16K bytes. The first location of 3K bytes is used for the data buffer of the packet transmission. The other 13K bytes are used for the buffer of the receiving packets. So in the write memory operation, when the bit 7 of IMR is set, the memory address increment will wrap to location 0 if the end of address (i.e. 3K) is reached. In a similar way, in the read memory operation, when the bit 7 of IMR is set, the memory address increment will wrap to
31
DM9000
9.5 100Base-TX Operation The block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Converter - NRZI to MLT-3 - MLT-3 Driver 9.5.1 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5bit (5B) code group for transmission, see reference Table 1. This conversion is required for control and packet data to be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code-group pair (01101 00111) indicating the end of frame. After the T/R code-group pair, the 4B5B encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9000 includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not require 4B5B conversion. 9.5.2 Scrambler The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100BaseTX operation. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to the repeated 5B sequences, like the continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 9.5.3 Parallel to Serial Converter The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler, and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI encoder block 9.5.4 NRZ to NRZI Encoder After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard, for 100Base -TX transmission over Category-5 unshielded twisted pair cable. 9.5.5 MLT-3 Converter The MLT-3 conversion is accomplished by converting the data stream output, from the NRZI encoder into two binary data streams, with alternately phased logic one event. 9.5.6 MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformers primary winding, resulting in a minimal current MLT-3 signal. Refer to figure 4 for the block diagram of the MLT-3 converter.
32
DM9000
9.5.7 4B5B Code Group
Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R H V V V V V V V V V V
Meaning Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Idle SFD (1) SFD (2) ESD (1) ESD (2) Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
4B code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined Table 1
5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
33
DM9000
9.6 100Base-TX Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data that is then provided to the MII. The receive section contains the following functional blocks: - Signal Detect - Digital Adaptive Equalization - MLT-3 to Binary Decoder - Clock Recovery Module - NRZI to NRZ Decoder - Serial to Parallel - Descrambler - Code Group Alignment - 4B5B Decoder 9.6.1 Signal Detect The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX standards for both voltage thresholds and timing parameters. 9.6.2 Adaptive Equalization When transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. 9.6.3 MLT-3 to NRZI Decoder The DM9000 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The relationship between NRZI and MLT-3 data is shown in figure 4. 9.6.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125Mhz reference clock. T he extracted and synchronized clock and data are presented to the NRZI to NRZ decoder.
9.6.5 NRZI to NRZ The transmit data stream is required to be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block. 9.6.6 Serial to Parallel
The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter. It converts the data stream to parallel data to be presented to the descrambler.
9.6.7 Descrambler Because of the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, and it descrambles the data streams, and presents the data streams to the Code Group alignment block.
34
DM9000
ISA to Ethernet MAC controller with integrated 10/100 PHY
9.6.8 Code Group Alignment The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a fixed boundary. 9.6.9 4B5B Decoder The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (J/K symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the end-of-frame delimiter (T/R Symbols). The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer. 9.7 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9000 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then the Manchester encoded. When receiving, the bit stream, encoded by the Manchester, is decoded and converted into nibble format to present to the MII interface. 9.8 Collision Detection For half-duplex operation, a collision is detected when the tr a n s m it and r ec ei ve c ha nn el s ar e ac ti v e simultaneously. When a collision is detected, it will be reported by the COL signal on the MII interface. Col lis i on d etec t io n is d is a ble d in F u ll Dup le x operation. 9.9 Carrier Sense Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During full-duplex mode, CRS is asserted only during receive operations. 9.10 Auto-Negotiation The objective of Auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Auto-negotiation does not test the characteristics of the linked segment. The AutoNegotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. Auto-negotiation also provides a parallel detection function for devices that do not support the Autonegotiation feature. During Parallel detection there is no exchange of information of configuration. Instead, the receive signal is examined. If it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. This allows devices not to support Auto-negotiation but support a common mode of operation to establish a link.
Final Version: DM9000-DS-F01 April 12, 2002
35
DM9000
9.11 Power Reduced Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9000 automatically turns off the power and enters the Power Reduced mode, whether its operation mode is Nway or force mode. When enters the Power Reduced mode, the transmit circuit still sends out fast link pules with minimum power consumption. If a valid signal is detected from the media, which might be N-ways fast link pules, 10Base-T normal link pules, or 100Base-TX MLT3 signals, the dev ic e will wak e up and res um e a norm al operation mode. That can be writing Zero to Reg.16.4 of MII register to disable Power Reduced mode. 9.11.1 Power Down Mode The Reg.0.11 of MII register can be set high to enter the Power Down mode, which disables all transmit, receive functions and MII interface functions, except the MDC/MDIO management interface. 9.11.2 Reduced Transmit Power Mode The additional Transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its TX side and using a 8.5K& resistor on BGRES and AGND pins, and the TXO+/TXO- pulled high resistors should be changed from 50 & to 78 & . This configuration could be reduced about 20% transmit power.
36
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 10. DC and AC Electrical Characteristics
10.1 Absolute Maximum Ratings ( 25C ) Symbol Parameter DVDD AVDD Supply Voltage VIN DC Input Voltage (VIN) VOUT DC Output Voltage(VOUT) Tstg Storage Temperature Rang (Tstg) Tc Case Temperature LT Lead Temp. (TL, Soldering, 10 sec.) ESD ESD rating (Rzap=1.5k Czap=100PF) Min. -0.3 -0.5 -0.3 -65 0 --Max. 3.6 5.5 3.6 +150 85 235 3000 Unit V V V C C C V Conditions
EIAJ-4701 Air Flow = 0m/min J-STD-020A Human Body Mode
10.2 Operating Conditions Symbol Parameter DVDD,AVDD Supply Voltage PD 100BASE-TX (Power Dissipation) 10BASE-T TX 10BASE-T idle Auto-negotiation Power Reduced Mode(without cable) Power Down Mode
Min. 3.135 -------------
Max. 3.465 100 85 44 60 20 10
Unit V mA mA mA mA mA mA
Conditions 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Comments Stresses above, which are listed under Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above, which indicated in the operational sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the reliability of the device.
37
DM9000
10.3 DC Electrical Characteristics (VDD = 3.3V) Symbol Inputs VIL VIH IIL IIH Outputs VOL VOH Receiver VICM Parameter Input Low Voltage Input High Voltage Input Low Leakage Current Input High Leakage Current Output Low Voltage Output High Voltage Min. 2.0 -1 2.4 Typ. 0.9 Max. 0.8 1 0.4 Unit V V uA uA V V V Conditions
VIN = 0.0V VIN = 3.3V IOL = 4mA IOH = -4mA 100 Termination Across Peak to Peak Peak to Peak Absolute Value Absolute Value
RX+/RX- Common Mode Input Voltage Transmitter VTD100 100TX+/- Differential Output Voltage VTD10 10TX+/- Differential Output Voltage ITD100 100TX+/- Differential Output Current ITD10 10TX+/- Differential Output Current
1.9 4.4 !19! !44!
2.0 5 !20! !50!
2.1 5.6 !21! !56!
V V mA mA
38
DM9000
10.4 AC Electrical Characteristics & Timing Waveforms 10.4.1 TP Interface Symbol Parameter tTR/F 100TX+/- Differential Rise/Fall Time tTM 100TX+/- Differential Rise/Fall Time Mismatch tTDC 100TX+/- Differential Output Duty Cycle Distortion tT/T 100TX+/- Differential Output Peak-to-Peak Jitter XOST 100TX+/- Differential Voltage Overshoot 10.4.2 Oscillator/Crystal Timing Symbol Parameter tCKC TCKC tPWH TCKC tPWL OSC Pulse Width Low 10.4.3 Processor Register Read Timing
Min. 3.0 0 0 0 0
Typ. -
Max. 5.0 0.5 0.5 1.4 5
Unit ns ns ns ns %
Conditions
Min. 39.998 16 16
Typ. 40 20 20
Max. 40.002 24 24
Unit ns ns ns
Conditions 50ppm
AEN,SA ,CMD IOR
T1
T5
*
SD
T2 T3
* ) ) * T4 )
T6
*
IO16,IO32
Note 1.2
T7
T8
Symbol T1 T2 T3 T4 T5 T6 T7 T8
Parameter System address valid to IOR valid IOR width SD Setup time IOR invalid to SD invalid IOR invalid to system address invalid IOR invalid to next IOR valid 'access DM9000( System address valid to IO16,IO32 valid System address invalid to IO16, IO32 invalid
Min. 5 22
Typ.
Max.
10 4 5 80 5 5
Unit ns ns ns ns ns ns ns ns
39
DM9000
Note% 1. The IO16 is valid when the SD bus width is 16-bit or 32-bit, and the system address is data port (i.e. CMD is high) and the value of address port is memory data register index.'ex. F0H, F2H, F6H or F8H( 2. The IO32 is valid when the SD bus width is 32-bit, the system address is data port (i.e. CMD is high) and the value of address port is memory data register index'ex. F0H, F2H, F6H or F8H(
10.4.4 Processor Register Write Timing
AEN,SA,CMD IOW SD IO16,IO32
T1
)
T2
*
T6
T5
* )
)
T3
++
T4
* ) *
T7
) ) *
T8
Note1.2
Symbol T1 T2 T3 T4 T5 T6 T7 T8
Parameter System Address Valid to IOW Valid IOW Width SD Setup Time SD Hold Time IOW Invalid to System Address Invalid IOW Invalid to Next IOW validaccess DM9000( System Address Valid to IO16, IO32 Valid System Address Invalid to IO16, IO32 Invalid
Min. 5 22 22 5 5 84
Typ.
Max.
5 5
Unit ns ns ns ns ns ns ns ns
Note% 1. The IO16 is valid when the SD bus width is 16-bit or 32-bit and system address is data port (i.e. CMD is high) and the value of address port is memory data register index (ex. F0H, F2H, F6H or F8H(
2. The IO32 is valid when the SD bus width is 32-bit and system address is data port (i.e. CMD is high) and the value of address port is memory data register index (ex. F0H, F2H, F6H or F8H)
40
DM9000
10.4.5 External MII Interface Transmit Timing
T2
*
TXCK TXEN
++
++
)
TXD[3:0]
T1
++
Symbol T1 T2
Parameter TXEN,TXD[3%0] Setup Time TXEN,TXD[3%0] Hold Time
Min.
Typ. 32 8
Max.
Unit ns ns
10.4.6 External MII Interface Receive Timing
RXCK RXER,RXDV ++
)
RXD[3:0]
T1
*
++
T2
Symbol T1 T2
Parameter RXER, RXDV,RXD[3%0] Setup Time RXER, RXDV,RXD[3%0] Hold Time
Min. 5 5
Typ.
Max. Unit ns ns
41
DM9000
10.4.7 MII Management Interface Timing
*
MDC
T1
) )
T2
MDIO (drive by DM9601) MDIO (drive by externcl MII)
* ) *
T3
) ) *
Unit Mhz ns ns ns ns
T5
T4
Symbol T1 T2 T3 T4 T5
Parameter MDC Frequency MDIO by DM9000 Setup Time MDIO by DM9000 Hold Time MDIO by External MII Setup Time MDIO by External MII Hold Time
Min.
Typ. 2 187 313
Max.
40 40
10.4.8 EEPROM Interface Timing
)
EESS EECK EEDO EEDI
T2
) ) T4 * ) * T5
++
T1
T6
*
T7
)
Symbol T1 T2 T3 T4 T5 T6 T7
42
*
Unit Mhz ns ns ns ns ns ns
Parameter EECK Frequency EECS Setup Time EECS Hold Time EEDO Setup Time EEDO Hold Time EEDI Setup Time EEDI Hold Time
Min.
Typ. 0.375 500 2166 480 2200
Max.
80 80
DM9000
43
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11. Application Notes
11.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50 & resistors as close as possible to the DM9000 RXI, and TXO, pins. Traces routed from RXI, and TXO, to the transformer should run in close pairs directly to the transformer. The designer should be careful not to cross the transmit and receive pairs. As always, vias should be avoided as much as possible. The network interface should be void of any signals other than the TXO, and RXI, pairs between the RJ-45 to the transformer and the transformer to the DM9000.. There should be no power or ground planes in the area under the 11.2 10Base-T/100Base-TX Application network side of the transformer to include the area under the RJ-45 connector. (Refer to Figure 4 and 5) Keep chassis ground away from all active signals. The RJ-45 connector and any unused pins should be tied to chassis ground through a resistor divider network and a 2KV bypass capacitor. The Band Gap resistor should be placed as physically close as pins 25 and 26 as possible (refer to Figure 1 and 2). The designer should not run any high-speed signal near the Band Gap resistor placement.
RXI+
29 50 " 1% 30 0.1F
Transformer
1:1 3 6 1 4
AGND
RJ45
RXI-
50 " AGND 1% 3.3V AVDD 0.1F 50" 1% 33 50" 1% 0.1F AGND
DM9000
TX0+
5 1:1 2 7 8
3.3V AVCC
TX0-
34
0.1F
BGRES BGGND
26 AGND 25 6.8K", 1%
75" 1%
75 " 1% 75 " 1%
75 " 1%
0.1F/2KV AGND
Chasis GND
Figure 11-1
44
DM9000
11.3 10Base-T/100Base-TX (Power Reduction Application)
RXI+
29 50 " 1% 30 50 " AGND 1% 3.3V AVDD 0.1F
Transformer
1:1 3 6 1
0.1F
RJ45
RXI-
4
AGND
DM9000
TX+
78" 1% 33 78" 1% 34 AGND
0.1F
5 1.25:1 2 7 8
3.3V AVCC
TX0-
0.1F
BGRES BGGND
26 25 AGND 8.5K", 1%
75" 1%
75 " 1% 75 " 1%
75 " 1% 0.1F/2KV or 0.01F/ 2KV
AGND
Chasis GND
Figure 11-2
45
DM9000
11.4 Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9000 (The best placed distance is < 3mm from pin). The recommended decoupling capacitor is 0.1-F or 0.01-F, as required by the design layout.
90 5
73 72
DM9000
20 55 27 28 35 36
Figure 11-3
46
DM9000
11.5 Ground Plane Layout Davicom Semiconductor recommends a single ground plane approach to minimize EMI. Ground plane partitioning can cause increased EMI emissions that could make the network interface card not comply with specific FCC regulations (part 15). Figure 4 shows a recommended ground layout scheme.
Figure 11-4
47
DM9000
11.6 Power Plane Partitioning The power planes should be approximately illustrated in Figure 5. The ferrite bead used should perform an impedance at least 75& at 100MHz. A suitable bead is the Panasonic surface mound bead, part number EXCCL4532U or equivalent. A 10-F electrolytic bypass capacitors should be connected between VDD and Ground at the device side of each of the ferrite bead.
Figure 11-5
48
DM9000
11.7 Magnetics Selection Guide Refer to Table 2 for transformer requirements. Transformers, meeting these requirements, are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetics before Manufacturer Pulse Engineering Delta YCL Halo using them in an application. The transformers listed in Table 2 are electrical equivalents, but may not be pin-to-pin equivalents.
Nano Pulse Inc. Fil-Mag Bel Fuse Valor Macronics
Part Number PE-68515, H1078, H1012 H1102 LF8200, LF8221x 20PMT04, 20PMT05 TG22-3506ND, TD22-3506G1, TG22S010ND TG22-S012ND NPI 6181-37, NPI 6120-30, NPI 6120-37 NPI 6170-30 PT41715 S558-5999-01 ST6114, ST6118 HS2123, HS2213 Table 2
11.8 Crystal Selection Guide A crystal can be used to generate the 25MHz reference clock instead of a oscillator. The crystal must be a fundamental type, and series-resonant.
Connects to X1_25M and X2_25M, and shunts each crystal lead to ground with a 22pf capacitor (see figure 6).
X2_25M 21 22
X1_25M
Y1 C18 22pf AGND
25M C19 22pf AGND
Figure 11-6 Crystal Circuit Diagram

DM9000
11.9 Application of reverse MII
RXCLK TXCLK RXD0 RXD1 RXD2 RXD3 TXD0 TXD1 TXD2 TXD3 RXDV TXEN CRS COL RXER MDC MDIO TXCLK RXCLK TXD0 TXD1 TXD2 TXD3 RXD0 RXD1 RXD2 RXD3 TXEN RXDV CRS COL RXER TXER MDC MDIO
DM9000
SWITCH HUB
Reverse MII Link Full Mode (Reverse MII

Figure 11-7
Normal MII Normal MII)
Note: When operating DM9000 at Reverse MII mode, pin 87 is pulled high . At this application, the txclk , col and crs pins will be changed from input to output.
50
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 12. Package Information
12.1 LQFP 100L Outline Dimensions
HD
75
Unit: Inches/mm
5.
76
50
.00
26
25
HE
e GD
b c
GD ~ ~
A2
See Detail F Seating Plane
A.
L L.
Detail F
Symbol A A1 A2 b c D E e F GD HD HE L L1 y
Dimensions In Inches 0.063 Max. 0.004 0.002 0.055 0.002 0.009 0.002 0.006 0.002 0.551 0.005 0.551 0.005 0.020 BSC. 0.481 NOM. 0.606 NOM. 0.630 0.006 0.630 0.006 0.024 0.006 0.039 Ref. 0.004 Max. 0 ~ 12
Dimensions In mm 1.60 Max. 0.1 0.05 1.40 0.05 0.22 0.05 0.15 0.05 14.00 0.13 14.00 0.13 0.50 BSC. 12.22 NOM. 15.40 NOM. 16.00 0.15 16.00 0.15 0.60 0.15 1.00 Ref. 0.1 Max. 0 ~ 12
Notes: 1. Dimension D & E do not include resin fins. 2. Dimension GD is for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system.
51
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 13. APPENDIX:
1. Data Sheet Changed Errata List Items 1 2 3 4 5 6 Before Modification 4 BKPM 3 BKPA Data & Ver. 05/02/2001 P01 06/14/2001 P01 06/22/2001 P01 12/05/2001 P02 12/05/2001 P02 12/05/2001 P02 Page Page 1 Page 14 Page 7 Page 11 Page 38 Content DM9000 Data Sheet Start Modify Block Diagram Check TableA-1-A &A-1-B Check TableA-2-A &A-2-B Check TableA-3-A &A-2-B Check TableA-4-A &A-4-B
0,RW 0,RW
Back pressure mode. This mode is for half duplex mode only. Generate a jam pattern when a packets DA match and RX SRAM over BPHW Back pressure mode. This mode is for half duplex mode only. Generate a jam pattern when any packet coming and RX SRAM over BPHW
Table A-1-A
After Modification 4 BKPA 3 BKPM
0,RW 0,RW
Back pressure mode. This mode is for half duplex mode only. Generate a jam pattern when any packet coming and RX SRAM over BPHW Back pressure mode. This mode is for half duplex mode only. Generate a jam pattern when a packets DA match and RX SRAM over BPHW
Table A-1-B
Before Modification 16,17,18, TEST1~TEST4 19
Operation Mode Test1,2,3,4=(1,1,0,0) : the processor interface is ISA compatible Test1,2,3,4=(1,1,0,1) : the processor interface is for general processor
Table A-2-A
After Modification 16,17,18, TEST1~TEST4 19
Operation Mode Test1,2,3,4=(1,1,0,0) in normal application

Table A-2-B
Before Modification Bit Name 2:1 LBK
Default 00,RW
Description Loopback mode Bit 2 1 0 0 normal 0 1 MAC internal loopback 1 0 internal PHY digital loopback 1 1 internal PHY analog loopback
Table A-3-A
52
DM9000
After Modification Bit Name 2:1 LBK Default 00,RW Description Loopback mode Bit 2 1 0 0 normal 0 1 MAC internal loopback 1 0 internal PHY 100M mode digital loopback 1 1 (Reserved)
Table A-3-B
Before Modification Symbol Parameter T3 SD Setup time IOW invalid to next IOW 'access DM9000( T6
TableA-4-A
Min. 5 80
Typ.
Max.
Unit ns ns
After Modification Symbol Parameter T3 SD Setup time IOW invalid to next IOW 'access DM9000( T6
Table A-4-B
Min. 22 84
Typ.
Max.
Unit ns ns
53
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 14. Order Information
Part Number DM9000E Pin Count 100 Package LQFP DAVICOMs terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyers orders shall be based on these terms.
Disclaimer
The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification, and the provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
Company Overview
DAVICOM Semiconductor Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industrys best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements.
Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards.
Contact Windows
For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5798858
Sales & Marketing Office: 2F, No. 5, Industry E. Rd., IX, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5646929 Email: [email protected] Web site: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
54

Dm9000e PDF

Uploaded by

Copyright:

Available Formats

Dm9000e PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Dm9000e PDF

Uploaded by

Copyright:

Available Formats

DM9000

External MII Interface

Control &Status Registers

MII Management Control & MII Register

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

5.1 MII Interface

COL RX_DV RX_ER RX_CLK TX_CLK TXD [3:0]

TX_ EN MDIO MDC

5.2 Processor Interface

Final Version: DM9000-DS-F02 June 26, 2002

Processor Data Bus bit 0~15

5.3 EEPROM Interface 64 EEDI 65 EEDO

5.4 Clock Interface 21 X2_25M 22 59 X1_25M CLK20MO

5.5 LED Interface 60 SPEED100#

5.6 10/100 PHY/Fiber 24 SD

BGGND BGRES AVDD AVDD RXI+ RXIAGND AGND TXO+

Final Version: DM9000-DS-F02 June 26, 2002

5.7 Miscellaneous 16,17,18, TEST1~TEST4 19 48 68,69,70, 71 TEST5 GPIO0~3

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

DIS_LONG DIS_CRC ALL RUNT PRMSC RXEN

0,RW 0,RW 0,RW 0,RW 0,RW 0,RW

Final Version: DM9000-DS-F02 June 26, 2002

Description (15H) (14H) (13H) (12H) (11H) (10H)

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Description CHIP Revision

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Vendor ID Product ID pin control

Wake-up mode control

8. MII Register Description

BP 4B5B 100 FDX Rsvd

BP SCR 100 HDX LP Enable

RPDCTR Reset -EN St. Mch

Pream. Sleep Supr. mode Auto-N. Monitor Bit [3:0]

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F01 April 12, 2002

Final Version: DM9000-DS-F02 June 26, 2002

4.13 4.12-4.11 4.10 4.9

4.8 4.7 4.6 4.5 4.4-4.0

TX_FDX TX_HDX 10_FDX 10_HDX Selector

Final Version: DM9000-DS-F02 June 26, 2002

5.13 5.12-5.11 5.10

5.9 5.8 5.7 5.6 5.5 5.4-5.0

T4 TX_FDX TX_HDX 10_FDX 10_HDX Selector

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F02 June 26, 2002

Final Version: DM9000-DS-F01 April 12, 2002

Final Version: DM9000-DS-F02 June 26, 2002