ASICs...

THE COURSE (1 WEEK)

LOW-LEVEL 9
DESIGN ENTRY

Key concepts: design entry • electronic-design automation (EDA) • schematic • connectivity •

schematic entry • schematic capture • netlist • documentation • hardware description language
(HDL) • logic synthesis • low-level design-entry

9.1 Schematic Entry

Key terms and concepts: graphical design entry • transforms an idea to a computer file • an
“old” method that periodically regains popularity • schematic sheets • frame • border • “spades”
and “shovels” • component or device • low-cost

ANSI (American National Standards Institute) and ISO (International Standards

Organization) schematic sheet sizes
ANSI sheet Size (inches) ISO sheet Size (cm)
A 8.5 × 11 A5 21.0 × 14.8
B 11 × 17 A4 29.7 × 21.0
C 17 × 22 A3 42.0 × 29.7
D 22 × 34 A2 59.4 × 42.0
E 34 × 44 A1 84.0 × 59.4
A0 118.9 × 84.0

1
2 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

(a) (b)

26
19
A
4 26

13 5
10
26
B
"spade" 26
and
"shovel"
NAND exclusive-OR

IEEE-recommended dimensions and their construction for logic-gate symbols

(a) NAND gate
(b) exclusive-OR gate (an OR gate is a subset)

instance attribute:
fanout=2
cell name
dot AND
A carryout
C net fanout=4 net fanin=4
B
and1 INV
net attribute: little big
net name
connection symbol inv1
OR AND
sum
D
and2
or1 GND
instance attribute: cell fanin=2 connector VDD
instance name

Terms used in circuit schematics

ASICs... THE COURSE 9.1 Schematic Entry 3

9.1.1 Hierarchical Design

Key terms and concepts: use of hierarchy to hide complexity • hierarchical design • subsche-
matic • child • parent • flat design • flat netlist

cell: AND
instance: and1
A C
B AC
cell: INV instance: inv1 BD
D cell: HADD
cell: OR cell: AND
instance: or1 instance: and1

(a) multiple instances of (b)

the same cell
cell: HADD parent
cell: HADD
instance: ha1 cell: OR
instance: or1
A AC cell: INV
CO
instance: INV1
B BD
cell: OR
AC instance: OR1

CI BD S cell: AND
children instance: and1
cell: HADD instance: and2
instance: ha2
(c) (d)

Schematic example showing hierarchical design

(a) The schematic of a half-adder, the subschematic of cell HADD
(b) A schematic symbol for the half adder
(c) A schematic that uses the half-adder cell
(d) The hierarchy of cell HADD
4 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

9.1.2 The Cell Library

Key terms: modules (cells, gates, macros, books) • schematic library (vendor-dependent) •
retargeting • porting a design • primitive cells or cells (flip-flops or transistors?) • hard macro
(placement) • soft macro (connection)

9.1.3 Names

Key terms: cell name • cell instance • instance name • icon (picture) • symbol • name spaces •
case sensistivity • hierarchical names

9.1.4 Schematic Icons and Symbols

Key terms: derived icon • derived symbol • subcell • vectored instance • cardinality

schematic instance name

internal node Trigger
cell library
and1
D connector
n1
or1 name Data DQ Flag
primitive EN Q
cells n2 e1 EN
inv1
and2 n3 DLAT cell
external node name
(a) (b) (c)

A cell and its subschematic

(a) A schematic library containing icons for the primitive cells
(b) A subschematic for a cell, DLAT, showing the instance names for the primitive cells
(c) A symbol for cell DLAT
ASICs... THE COURSE 9.1 Schematic Entry 5

internal node vectored name

and1
D1

different inv1 n1 or1 D1 DQ Q1 L[1:4]

Q1 L1
instance EN D[1:4] DQ Q[1:4]
names and2 external
n3 node DLAT EN EN
D2
D2 DQ Q2 DLAT vectored
inv2 L2
Q2 EN instance
(c)
DLAT
D3
D3 DQ Q3
inv3 L3
Q3 EN
bus
DLAT width
D4 4 4
D4 DQ Q4 DQ
inv4 L4
EN Q4 EN EN bus EN
DLAT FourBit

(a) (b) (d)

A 4-bit latch:
(a) drawn as a flat schematic from gate-level primitives
(b) drawn as four instances of the cell symbol DLAT
(c) drawn using a vectored instance of the DLAT cell symbol with cardinality of 4
(d) drawn using a new cell symbol with cell name FourBit
6 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

9.1.5 Nets

Key terms: local nets • external nets • delimiter • Verilog and VHDL naming

9.1.6 Schematic Entry for ASICs and PCBs

Key terms: component • TTL SN74LS00N • Quad 2-input NAND • component parts • reference
designator • R99 • pin number • part assignment

9.1.7 Connections

Key terms: terminals • pins, connectors, or signals • wire segments or nets • bus or buses (not
busses) • bundle or array • breakout • ripper (EDIF) • extractor • swizzle (Compass datapath)

DQ7
C DQ7 DQ6 C
3 3
D[1] 2 D[1] 2 DQ6 DQ3
1 1 DQ5 DQ2
D[2] 0 D[2] 0 DQ4 DQ5
B DQ4 B
bus ripper 8 DQ2
DQ3 DQ0
3 3 DQ3
E[1] 2 A E[1] 2 DQ2 A
DQ2
1 1 DQ1
E[2] 0 E[2] 0 DQ0 DQ1
DQ0
(a) (b)

An example of the use of a bus to simplify a schematic

(a) An address decoder without using a bus
(b) A bus with bus rippers simplifies the schematic and reduces the possibility of making a
mistake in creating and reading the schematic
ASICs... THE COURSE 9.1 Schematic Entry 7

9.1.8 Vectored Instances and Buses

NB1
4 4 16 16
D[1:4] DQ Q[1:4] D[1:16] DQ Q[1:16]

EN EN EN
FourBit SixteenBit

NB2 (b)
4 4
D[5:8] DQ Q[5:8]

EN
FourBit

NB3
4 4 D1 vectored
D[9:12] DQ Q[9:12] bus vectored
instance
4
EN
D[9:12]
FourBit 4 4
DQ Q[1:16]
4
NB4 EN EN
4 4 4 mismatch in
D[13:16] DQ Q[13:16] cardinality
FourBit[1:4]
EN mismatch in
EN
cardinality
FourBit
(a) (c)

A 16-bit latch:
(a) drawn as four instances of cell FourBit
(b) drawn as a cell named SixteenBit
(c) drawn as four multiple instances of cell FourBit

9.1.9 Edit-in-Place

Key terms: edit-in-place • alias • dictionary of names

9.1.10 Attributes

Key terms: name • identifier • label • attribute • property • NFS filenames (28 characters)
8 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

9.1.11 Netlist Screener

Key terms: schematic or netlist screener catches errors at an early stage • handle (to find com-
ponents) • snap to grid • wildcard matching • automatic naming • datapath (multiple instances)
• vectored cell instance • vectored instance • cell cardinality • cardinality • terminal polarity • ter-
minal direction • fanout • fanin • standard load

9.1.12 Schematic-Entry Tools

Key terms: icon edit-in-place • timestamp or datestamp • versions • version number • design
manager or library manager • version history • check-out • undo • rubber banding • global nets
• connectors • off-page connector • multipage connector • fanout • fanin • standard load

9.1.13 Back-Annotation

Key terms: logical design • prelayout simulation• physical design • parasitic capacitance •
interconnect delay • back-annotation • postlayout simulation
ASICs... THE COURSE 9.2 Low-Level Design Languages 9

9.2 Low-Level Design Languages

Key terms and concepts: changes to a schematic are tedious • no standards for schematics
• PLD design entry • a design language is better than schematic entry • a low-level design
language is not as powerful as logic synthesis • legacy code

9.2.1 ABEL

ABEL
Statement Example Comment
Module module MyModule You can have multiple modules.
Title A string is a character series between
title 'Title in a String'
quotes.
Device MYDEV is Device ID for documenta-
MYDEV device '22V10' ; tion.
22V10 is checked by the compiler.
Comment "comments go between double The end of a line signifies the end of a
quotes" comment; there is no need for an end
"end of line is end of quote.
comment
@ALTER- @ALTERNATE "use alternate
operator alternate default
NATE symbols
AND * &
OR + #
NOT / !
XOR :+: $
XNOR :*: !$
Pin declara- Pin 22 is the IO for input on pin 2 for a
tion MYINPUT pin 2; I3, I4 pin 3, 22V10.
4 ;
MYOUTPUT is active-low at the chip
/MYOUTPUT pin 22; IO3,IO4 pin
pin.
21,20 ;
Signal names must start with a letter.
Equations equations Defines combinational logic.
IO4 = HELPER ; HELPER = /I4 ; Two-pass logic
Assignments MYOUTPUT = /MYINPUT ; Equals '=' is unlocked assignment.
10 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

Clocked assignment operator (regis-

IO3 := I4 ;
tered IO)
Signal sets D = [D0, D1, D2, D3] ; A signal set, an ABEL bus
Q = [Q0, Q1, Q2, Q3];
Q := D ; 4-bit-wide register
Suffix MYOUTPUT.RE = CLR ; Register reset
MYOUTPUT.PR = PRE ; Register preset
Addition COUNT = [D0, D1, D2]; Can’t use @ALTERNATE
COUNT := COUNT + 1; if you use '+' to add.
Enable Three-state enable (ENABLE is a key-
ENABLE IO3 = IO2; word).
IO3 = MYINPUT;
IO3 must be a three-state pin.
Constants K = [1, 0, 1] ; K is 5.
Relational Operators:
IO# = D == K5 ; == != < > <=
>=
End end MyModule Last statement in module

Example:

module MUX4
title '4:1 MUX'
MyDevice device 'P16L8' ;
@ALTERNATE
"inputs
A, B, /P1G1, /P1G2 pin 17,18,1,6 "LS153 pins 14,2,1,15
P1C0, P1C1, P1C2, P1C3 pin 2,3,4,5 "LS153 pins 6,5,4,3
P2C0, P2C1, P2C2, P2C3 pin 7,8,9,11 "LS153 pins 10,11,12,13
"outputs
P1Y, P2Y pin 19, 12 "LS153 pins 7,9
equations
P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);
P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);
end MUX4
ASICs... THE COURSE 9.2 Low-Level Design Languages 11

9.2.2 CUPL

Key terms and concepts: CUPL is a PLD design language from Logical Devices • CUPL 4.0
• extension • fitter • Atmel ATV2500B • complex PLD • “buried” features • pin-number tables •
skeleton headers and pin declarations

SEQUENCE BayBridgeTollPlaza {
PRESENT red
IF car NEXT green OUT go; /* conditional synchronous output */
DEFAULT NEXT red; /* default next state */
PRESENT green
NEXT red; } /* unconditional next state */

CUPL statements for state-machine entry

Statement Description
IF NEXT Conditional next state transition
IF NEXT OUT Conditional next state transition with synchronous output
NEXT Unconditional next state transition
NEXT OUT Unconditional next state transition with asynchronous out-
put
OUT Unconditional asynchronous output
IF OUT Conditional asynchronous output
DEFAULT NEXT Default next state transition
DEFAULT OUT Default asynchronous output
DEFAULT NEXT OUT Default next state transition with synchronous output

You may encode state machines as truth tables in CUPL:

FIELD input = [in1..0];

FIELD output = [out3..0];
TABLE input => output {00 => 01; 01 => 02; 10 => 04; 11 => 08; }

CUPL file for a 4-bit counter (for an ATMEL PLD) that illustrates extensions:

Name 4BIT; Device V2500B;

/* inputs */
12 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

pin 1 = CLK; pin 3 = LD_; pin 17 = RST_;

pin [18,19,20,21] = [I0,I1,I2,I3];
/* outputs */
pin [4,5,6,7] = [Q0,Q1,Q2,Q3];
field CNT = [Q3,Q2,Q1,Q0];
/* equations */
Q3.T = (!Q2 & !Q1 & !Q0) & LD_ & RST_ /* count down */
# Q3 & !RST_ /* ReSeT */
# (Q3 $ I3) & !LD_; /* LoaD*/
Q2.T = (!Q1 & !Q0) & LD_ & RST_ # Q2 & !RST_ # (Q2 $ I2) & !LD_;
Q1.T = !Q0 & LD_ & RST_ # Q1 & !RST_ # (Q1 $ I1) & !LD_;
Q0.T = LD_ & RST_ # Q0 & !RST_ # (Q0 $ I0) & !LD_;
CNT.CK = CLK; CNT.OE = 'h'F; CNT.AR = 'h'0; CNT.SP = 'h'0;

CUPL extensions guide the logic fitter, for example:

output.ext = (Boolean expression);
.OE is output enable
.CK marks the clock
.T configures sequential logic as T flip-flops
.OE (wired high) is an output enable
.AR (wired low) is an asynchronous reset
.SP (wired low) is an synchronous preset
ASICs... THE COURSE 9.2 Low-Level Design Languages 13

CUPL 4.0 extensions

Exten- Exten-
Explanation Explanation
sion sion
D L D input to a D register DFB R D register feedback of
combinational output
L L L input to a latch LFB R Latched feedback of
combinational output
J, K L J-K-input to a J-K register TFB R T register feedback of
combinational output
S, R L S-R input to an S-R register INT R Internal feedback
T L T input to a T register IO R Pin feedback of registered
output
DQ R D output of an input D IOD/T R D/T register on pin feedback
register path selection
LQ R Q output of an input latch IOL R Latch on pin feedback path
selection
AP, AR L Asynchronous preset/reset IOAP, L Asynchronous preset/reset
IOAR of register on feedback path
SP, SR L Synchronous preset/reset IOSP, L Synchronous preset/reset of
IOSR register on feedback path
CK L Product clock term (async.) IOCK L Clock for pin feedback
register
OE L Product-term output enable APMUX, L Asynchronous preset/reset
ARMUX multiplexor selection
CA L Complement array CKMUX L Clock multiplexor selector
PR L Programmable preload LEMUX L Latch enable multiplexor
selector
CE L CE input of a D-CE register OEMUX L Output enable multiplexor
selector
LE L Product-term latch enable IMUX L Input multiplexor selector of
two pins
OBS L Programmable observability TEC L Technology-dependent fuse
of buried nodes selection
BYP L Programmable register T1 L T1 input of 2-T register
bypass
14 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

ABEL and CUPL pin declarations for an ATMEL ATV2500B

ABEL CUPL
device_id device 'P2500B';
"device_id used for JEDEC
filename device V2500B;
I1,I2,I3,I17,I18 pin 1,2,3,17,18; pin [1,2,3,17,18] =
O4,O5 pin 4,5 istype [I1,I2,I3,I17,I18];
'reg_d,buffer'; pin [7,6,5,4] = [O7,O6,O5,O4];
O6,O7 pin 6,7 istype 'com'; pinnode [41,65,44] =
O4Q2,O7Q2 node 41,44 istype [O4Q2,O4Q1,O7Q2];
'reg_d'; pinnode [43,68] = [O6Q2,O7Q1];
O6F2 node 43 istype 'com';
O7Q1 node 220 istype 'reg_d';
ASICs... THE COURSE 9.2 Low-Level Design Languages 15

9.2.3 PALASM

Key terms and concepts: PALASM is a PLD design language from AMD/MMI • PALASM 2 •
ordering of the pin numbers is important • DEVICE • often need manufacturer’s data sheet

PALASM 2
Statement Example Comment
Chip CHIP abc 22V10 Specific PAL type
CHIP xyz USER Free-form equation entry
Pinlist CLK /LD D0 D1 D2 D3 D4 GND Part of CHIP statement; PAL pins in
NC Q4 Q3 Q2 Q1 Q0 /RST VCC numerical order starting with pin 1
String STRING string_name 'text' Before EQUATIONS statement
Equations EQUATIONS After CHIP statement
A = /B Logical negation
A = B * C Logical AND
A = B + C Logical OR
A = B :+: C Logical exclusive-OR
A = B :*: C Logical exclusive-NOR
Polarity inversion /A = /(B + C) Same as A = B + C
Assignment A = B + C Combinational assignment
A := B + C Registered assignment
Comment A = B + C ; comment Comment
Functional equa- name.TRST Output enable control
tion
name.CLKF Register clock control
name.RSTF Register reset control
name.SETF Register set control

Example:

TITLE video ; shift register

CHIP video PAL20X8
CK /LD D0 D1 D2 D3 D4 D5 D6 D7 CURS GND NC REV Q7 Q6 Q5 Q4 Q3 Q2 Q1
Q0 /RST VCC
STRING Load 'LD*/REV*/CURS*RST' ; load data
STRING LoadInv 'LD*REV*/CURS*RST' ; load inverted of data
16 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

STRING Shift '/LD*/CURS*/RST' ; shift data from MSB to LSB

EQUATIONS
/Q0 := /D0*Load+D0*LoadInv:+:/Q1*Shift+RST
/Q1 := /D1*Load+D1*LoadInv:+:/Q2*Shift+RST
/Q2 := /D2*Load+D2*LoadInv:+:/Q3*Shift+RST
/Q3 := /D3*Load+D3*LoadInv:+:/Q4*Shift+RST
/Q4 := /D4*Load+D4*LoadInv:+:/Q5*Shift+RST
/Q5 := /D5*Load+D5*LoadInv:+:/Q6*Shift+RST
/Q6 := /D6*Load+D6*LoadInv:+:/Q7*Shift+RST
/Q7 := /D7*Load+D7*LoadInv:+:Shift+RST;
ASICs... THE COURSE 9.3 PLA Tools 17

9.3 PLA Tools

Key terms and concepts: developed at UC Berkeley • eqntott input format • espresso
logic-minimization program • widely used tools in the 1980s • important stepping stones to
modern logic synthesis software

A PLA tools example

Input (6 minterms): F1 = A|B|!C; F2 = !B&C; F3 = A&B|C;
A B C F1 F2 F3 eqntott output espresso output
0 0 0 1 0 0 .i 3
0 0 1 0 1 1 .i 3 .o 3
.o 3 .p 6
0 1 0 1 0 0 .p 6 1-- 100
0 1 1 1 0 1 --0 100 11- 001
1 0 0 1 0 0 --1 001 --0 100
-01 010 -01 011
1 0 1 1 1 1
-1- 100 -11 101
1 1 0 1 0 1 1-- 100 .e
11- 001
1 1 1 1 0 1 .e

Output (5 minterms): F1 = A|!C|(B&C); F2 = !B&C; F3 = A&B|(!B&C)|(B&C);

18 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

The format of the input and output files used by the PLA design tool espresso
Expression Explanation
# comment # must be first character on a line
[d] Decimal number
[s] Character string
.i [d] Number of input variables
.o [d] Number of output variables
.p [d] Number of product terms
.ilb [s1] [s2]... Names of the binary-valued variables must be after .i and .o
[sn]
.ob [s1] [s2]... Names of the output functions must be after .i and .o
[sn]
.type f Following table describes the ON set; DC set is empty
.type fd Following table describes the ON set and DC set
.type fr Following table describes the ON set and OFF set
.type fdr Following table describes the ON set, OFF set, and DC set.
.e Optional, marks the end of the PLA description.

The format of the plane part of the input and output files for espresso
Plane Character Explanation
I 1 The input literal appears in the product term
I 0 The input literal appears complemented in the product term
I - The input literal does not appear in the product term
O 1 or 4 This product term appears in the ON set
O 0 This product term appears in the OFF set
O 2 or - This product term appears in the don’t care set
O 3 or ~ No meaning for the value of this function
ASICs... THE COURSE 9.4 EDIF 19

9.4 EDIF
Key terms: electronic design interchange format (EDIF) • EDIF version 2 0 0 • EDIF 3 0 0 han-
dles buses, bus rippers, and buses across schematic pages • EDIF 4 0 0 includes new exten-
sions for PCB and multichip module (MCM) data • Library of Parameterized Modules (LPM) •
Electronic Industries Association (EIA) • ANSI/EIA Standard 548-1988

9.4.1 EDIF Syntax

Key terms: EDIF looks like Lisp or Postscript • a “write-only” language • (keywordName
{form}) • keywords • forms • “define before use” • identifiers • &clock, Clock, and clock
are the same • (e 14 -1) is 1.4 • scale factor • technology section •
numberDefinition • scale • "A quote is % 34 %"is a string with an embedded
double-quote character

EDIF file
library
library
technology
cell
The hierarchical nature of an EDIF file cell
view
view
interface
contents
20 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

9.4.2 An EDIF Netlist Example

EDIF file for the halfgate netlist

(edif halfgate_p (viewType NETLIST) (viewRef

(edifVersion 2 0 0) (interface COMPASS_mde_view
(edifLevel 0) (port I (cellRef INV
(keywordMap (direction (libraryRef
(keywordLevel 0)) INPUT)) xc4000d))))
(status (port O (net myInput
(written (direction (joined
(timeStamp 1996 7 OUTPUT)) (portRef
10 22 (designator myInput)
5 10) "@@Label"))))) (portRef I
(program "COMPASS (library working (instanceRef
Design Automation -- (edifLevel 0) B1_i1))))
EDIF Interface" (technology (net myOutput
(version "v9r1.2 (numberDefinition ) (joined
last updated 26-Mar- (simulationInfo (portRef
96")) (logicValue H) myOutput)
(author (logicValue L))) (portRef O
"mikes"))) (cell (instanceRef
(library xc4000d (rename HALFGATE_P B1_i1))))
(edifLevel 0) "halfgate_p") (net VDD
(technology (cellType GENERIC) (joined ))
(numberDefinition (view (net VSS
) COMPASS_nls_view (joined ))))))
(simulationInfo (viewType NETLIST) (design HALFGATE_P
(logicValue H) (interface (cellRef HALFGATE_P
(logicValue (port myInput (libraryRef
L))) (direction working))))
(cell INPUT))
(rename INV (port myOutput
"inv") (direction
(cellType OUTPUT))
GENERIC) (designator
(view "@@Label"))
COMPASS_mde_view (contents
(instance B1_i1
ASICs... THE COURSE 9.4 EDIF 21

9.4.3 An EDIF Schematic Icon

(0, 0)
cell

Pin_2 INV Pin_1

Value
instance

(76, -32)

An EDIF view of an inverter icon

The coordinates shown are in EDIF units. The crosses that show the text location origins
and the dotted bounding box do not print as part of the icon.
22 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

9.4.4 An EDIF Example

EDIF file for a standard-cell schematic icon

(edif pvsc370d (cellType GENERIC) (figure icon_FG

(edifVersion 2 0 0) (view Icon_view (path
(edifLevel 0) (viewType SCHEMATIC) (pointList
(keywordMap (interface (pt 0 20)
(keywordLevel 0)) (port A2 (pt 10 20)))
(status (direction INPUT)) (path
(written (port A1 (pointList
(timeStamp 1993 2 9 22 (direction INPUT)) (pt 0 0)
38 36) (port Z (pt 10 0)))
(program "COMPASS" (direction OUTPUT)) (path
(version "v8")) (property label
(author "mikes"))) (string "")) (pointList
(library pvsc370d (symbol (pt 10 -5)
(edifLevel 0) (portImplementation (pt 10 25)))
(technology (name A2 (path
(numberDefinition ) (display (pointList
(figureGroup connector_FG
(pt 10 -5)
connector_FG (origin
(pt 30 -5)))
(color 100 100 100) (pt -5 1))))
(path
(textHeight 30) (connectLocation
(pointList
(visible (figure
connector_FG (pt 10 25)
(true )))
(dot (pt 30 25)))
(figureGroup icon_FG
(pt 0 0))))) (path
(color 100 100 100)
(portImplementation (pointList
(textHeight 30)
(name A1 (pt 45 10)
(visible
(display (pt 60 10)))
(true )))
connector_FG (openShape
(figureGroup
instance_FG (origin (curve
(color 100 100 100) (pt -5 21)))) (arc
(textHeight 30) (connectLocation (pt 30 -5)
(visible (figure (pt 45 10)
(true ))) connector_FG (pt 30 25)))))
(figureGroup net_FG (dot (boundingBox
(color 100 100 100) (pt 0 20))))) (rectangle
(textHeight 30) (portImplementation (pt -15 -28)
(visible (name Z (pt 134 27)))
(true ))) (display (keywordDisplay
connector_FG instance
(figureGroup bus_FG
(origin (display icon_FG
(color 100 100 100)
(pt 60 15)))) (origin
(textHeight 30)
(connectLocation (pt 20 29))))
(visible
(figure (propertyDisplay
(true )) connector_FG label
(pathWidth 4))) (dot (display icon_FG
(cell an02d1 (pt 60 10))))) (origin
ASICs... THE COURSE 9.5 CFI Design Representation 23

Compass and corresponding Cadence figureGroup names

Compass name Cadence name Compass name Cadence name
connector_FG pin net_FG wire
icon_FG device bus_FG not used
instance_FG instance

autoroute
[@instanceName] I0 I1 [@instanceName]
a1 1x z a1 1x z a1 1x z a1 1x z
a2 a2 a2 a2
[@cellname] an02d1 an02d1 [@cellname]
bounding box
(a) (b) (c)

The bounding box problem

(a) The original bounding box for the an02d1 icon
(b) Problems in Cadence Composer due to overlapping bounding boxes
(c) A “shrink-wrapped” bounding box created using Cadence SKILL

9.5 CFI Design Representation

Key terms: CAD Framework Initiative (CFI) • design representation (DR) • information model
(IM) • CFI started as an attempt to standardize schematic entry • CFI ended up as an attempt
to close the stable door after the horse had bolted

9.5.1 CFI Connectivity Model

Key terms: EXPRESS language • EXPRESS-G • schema • Base Connectivity Model (BCM) •
five-box model • an elegant method to represent complex notions
24 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

days in day shopping grocery

January number list item
L[1:31] S[0:?]

(a) (b)

person

man wife 1 woman

husband 1

child
father 1 mother 1

children S[0:?] children S[0:?]

(c)

Examples of EXPRESS-G
(a) Each day in January has a number from 1 to 31
(b) A shopping list may contain a list of items
(c) An EXPRESS-G model for a family:
“Men, women, and children are people.”
“A man can have one woman as a wife, but does not have to.”
“A wife can have one man as a husband, but does not have to.”
“A man or a woman can have several children.”
“A child has one father and one mother.”
ASICs... THE COURSE 9.5 CFI Design Representation 25

Library

contains
S[0:?]

presents S[0:?]
Cell Port
contains
S[0:?]

has contains Net connects

S[0:?] has
describer describer
connects
S[0:?]
Cell Inst presents S[0:?] Port Inst

The original “five-box” model of electrical connectivity. (There are actually six boxes or types in
this figure; the Library type was added later.)
“A library contains cells.”
“Cells have ports, contain nets, and can contain other cells.”
“Cell instances are copies of a cell and have port instances.”
“A port instance is a copy of the port in the library cell.”
“You connect to a port using a net.”
“Nets connect port instances together.”
26 SECTION 9 LOW-LEVEL DESIGN ENTRY ASICS... THE COURSE

SCHEMA family_model;
ENTITY person
ABSTRACT SUPERTYPE OF (ONEOF (man, woman, child));
name: STRING;
date of birth: STRING;
END_ENTITY;

ENTITY man
SUBTYPE OF (person);
wife: SET[0:1] OF woman;
children: SET[0:?] OF child;
END_ENTITY;

ENTITY woman
SUBTYPE OF (person);
husband: SET[0:1] OF man;
children: SET[0:?] OF child;
END_ENTITY;

ENTITY child
SUBTYPE OF (person);
father: man;
mother: woman;
END_ENTITY;
END_SCHEMA;
ASICs... THE COURSE 9.6 Summary 27

9.6 Summary
Key concepts:
Schematic entry using a cell library
Cells and cell instances, nets and ports
Bus naming, vectored instances in datapath
Hierarchy
Editing cells
PLD languages: ABEL, PALASM, and CUPL
Logic minimization
The functions of EDIF
CFI representation of design information