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    A Noval Approach of FFT

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    Sijo Mathew
    The document discusses the design and implementation of low power and area efficient adder and Vedic multiplier for FFT. It proposes a carry select adder using a binary to excess-1 converter to reduce area and power compared to regular adders. It also proposes a Vedic multiplier based on the Urdhva Tiryagbhyam algorithm of ancient Indian mathematics to improve speed and reduce area of multipliers. The proposed adder and multiplier designs are evaluated in terms of delay, area and power consumption.

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    A Noval Approach of FFT

    Uploaded by

    Sijo Mathew
    47 views3 pages
    The document discusses the design and implementation of low power and area efficient adder and Vedic multiplier for FFT. It proposes a carry select adder using a binary to excess-1 converter to reduce area and power compared to regular adders. It also proposes a Vedic multiplier based on the Urdhva Tiryagbhyam algorithm of ancient Indian mathematics to improve speed and reduce area of multipliers. The proposed adder and multiplier designs are evaluated in terms of delay, area and power consumption.

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    a method to implement fft

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    The document discusses the design and implementation of low power and area efficient adder and Vedic multiplier for FFT. It proposes a carry select adder using a binary to excess-1 converter to reduce area and power compared to regular adders. It also proposes a Vedic multiplier based on the Urdhva Tiryagbhyam algorithm of ancient Indian mathematics to improve speed and reduce area of multipliers. The proposed adder and multiplier designs are evaluated in terms of delay, area and power consumption.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    47 views3 pages

    A Noval Approach of FFT

    Uploaded by

    Sijo Mathew
    The document discusses the design and implementation of low power and area efficient adder and Vedic multiplier for FFT. It proposes a carry select adder using a binary to excess-1 converter to reduce area and power compared to regular adders. It also proposes a Vedic multiplier based on the Urdhva Tiryagbhyam algorithm of ancient Indian mathematics to improve speed and reduce area of multipliers. The proposed adder and multiplier designs are evaluated in terms of delay, area and power consumption.

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    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    DESIGN AND IMPLEMENTATION OF LOW POWER AND AREA EFFICIENT ADDER AND VEDIC MULTIPLIER FOR FFT

    ABSTRACT
    The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes Resulted in the integration of a number of processor cores into one chip. This load is reduced by supplementing the main processor with Co-Processor. The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in application and the speed of FFT depends greatly on the multiplier and adder. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. It is used for design a multiplier. Carry select adder (CSLA) is the fastest adder used to perform an arithmetic functions. The proposed design has reduced area and power as compared with the regular Adders and Multipliers. This work evaluates the performance of the proposed designs in terms of delay, area, power. Keywords FFT, CSLA,Vedic multiplier, low power, area efficient.

    INTRODUCTION
    The increase in the popularity of portable systems as well as the rapid growth of the power density in integrated circuits have made power dissipation one of the important design objectives, second thing area & performance. So here the carry select adder and Vedic multiplier are modified for reducing the above factors. The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation and machine inspection. The choice of FFT sizes is decided by different operation standards. It is desirable to make the FFT size changeable according to the operation environment. Achieving a successful design means the system should be able to support different operating modes required by diverse applications with low power consumption requirement.Based on the idea of sharing two adders used in the Carry Select Adder (CSA), a new design of a low-power high performance adder is presented. The new adder is faster than a Ripple Carry Adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA. In a typical processor, Multiplication is one of the basic arithmetic operations

    and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multipliers. In computers, a typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations, particularly multiplication operations. In this paper, comparative study of different multipliers is done for low power requirement and high speed. The paper gives information of Urdhva Tiryakbhyam algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers. Vedic Mathematics also suggests more formulae for multiplication i.e. Nikhilam Sutra which can increase the speed of multiplier by reducing the number of iterations.The paper gives information of Urdhva Tiryakbhyam algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers. Vedic Mathematics also suggests more formulae for multiplication i.e. Nikhilam Sutra which can increase the speed of multiplier by reducing the number of iterations. Increasingly huge data sets and the need for low power in adders tend to increase. The traditional serial adders are no longer suitable for large adders because of its huge area and high power. All systems tends to trade off between speed and power. The computation time taken by the array multiplier is comparatively less. because the partial products are calculated independently in parallel. The delay associated with the array multiplier is the time taken by the signals to propagate through the gates that form the multiplication array. Large booth arrays are required for high speed multiplication and exponential operations which in turn require large partial sum and partial carry registers. In this paper the carry select adder designed only 128-bit and Vedic multiplier designed 32 bit.

    I. CARRY SELECT ADDER


    Design of area- and power-efficient highspeed data path logic systems are one of the most substantial areas of research in vlsi system design. in digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. the sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. the csla is used in many computational systems to alleviate the problem of

    carry propagation delay by independently generating multiple carries and then select a carry to generate the sum . however, the csla is not area efficient because it uses multiple pairs of ripple carry adders (rca) to generate partial sum and carry by considering carry input cin=0 and cin=1 then the final sum and carry are elected by the multiplexers (mux).the basic idea of this work is to use binary to excess-1 converter(bec) instead of rca with in the regular csla to achieve lower area and power consumption . the main advantage of this bec logic comes from the lesser number of logic gates than the n-bitfull adder (fa) structure.

    II. MULTIPLIER USING VEDIC


    MATHEMATICS Complex multiplication is of immense importance in digital signal processing (dsp) and image processing (ip).to implement the hardware module of discrete fourier transformation (dft), discrete cosine transformation(dct), discrete sine transformation (dst) and modem broadband communications; large numbers of complex multipliers are required. complex number multiplication is performed using four real number multiplications and two additions/ subtractions. in real number processing, carry needs to be propagated from the least significant bit (lsb) to the most significant bit (msb) when binary partial products are added. Figure1 4-BIT BEC X0 = ~B0 ;X1 = B0^B1 ; X2 = B2^ (B0 & B1); X3 = B3^(B0 & B1 & B2)

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