Vi INSTITUTE OF TECHNOLOGY (A UNIT OF Vi MICROSYSTEMS PVT.

LTD) SIRUNKUNDRAM DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL ELECTRONICS LAB MANUAL Prepared by T.Jaibalaganesh Assistant professor, ECE Vi Institute of Technology

Vi INSTITUTE OF TECHNOLOGY SIRUNGUNDRAM LABORATORY OBSERVATION SUBJECT CODE : SUBJECT NAME : NAME : REG. NO. : BRANCH : YEAR :

INDEX Exp. No. DATE EXPERIMENT NAME ASSIGN/SELF STUDY MARK OBSERV.MARK STAFF INITIAL 1

10

11

INTRODUCTION There are 3 hours allocated to a laboratory session in Digital Electronics. It i s a necessary part of the course at which attendance is compulsory. Here are some guidelines to help you perform the experiments and to submit the r eports: 1. Read all instructions carefully and carry them all out. 2. Ask a demonstrator if you are unsure of anything. 3. Record actual results (comment on them if they are unexpected!) 4. Write up full and suitable conclusions for each experiment. 5. If you have any doubt about the safety of any procedure, contact the demonstr ator beforehand. 6. INTRODUCTION ABOUT DIGITAL IC TRAINER KIT Digital IC Trainer (VBET - 21) is an assembly of instruments required in analog and digital electronic experiments. This is equivalent to a complete laboratory set-up excep t an oscilloscope. This trainer will enable the users to understand and test the IC.s and help the engin eer to test the circuits developed. The diagram of VBET 21 is displayed below: It contains the following sections, 1. Solder less bread board: Used for testing 14/16 pin digital IC.s of 54 and 74 series. It is also used fo r testing digital circuits.

2. Clock generator: The clock signal is generated and the frequency is externally variable. The fre quency is chosen to provide perceptible indication on the counter. 3. Pulse generator: The clock signal is generated and the frequency is externally variable by using slide switch. 4. Manual clock: The clock signal is generated manually by using push button. 5. Logic input: Logic level of high or low input is made through slide switches. The LED.s are provided to show the logic level of high or low output. 6. Logic output: The LED of the section is used to show the output. 7. Seven segment display: It displays the BCD count from (0-9) by giving the output. THE BREADBOARD The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a node. Tha t is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily for power supply connections, but are also used for any node requiring a large number of c onnections. Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts is a node. You will build your circuits on the terminal strips by inserting the leads of ci rcuit components into the contact receptacles and making connections with 22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power supply connections to separate bus strips. breadboard1 breadboardconnections

Fig. The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated c ircuits) used during the experiments. Incorrect connection of power to the ICs could result in them exploding or becoming very hot - with the possible serious injury occurring to the people wor king on the experiment! Ensure that the power supply polarity and all components and connect ions are correct before switching on power. BUILDING THE CIRCUIT Throughout these experiments we will use TTL chips to build circuits. The steps for wiring a circuit should be completed in the order described below: 1. Turn the power (Trainer Kit) off before you build anything! 2. Make sure the power is off before you build anything! 3. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus strips on your breadboard. 4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction with pin 1 at the upper-left corner. (Pin 1 is often identified by a d ot or a notch next to it on the chip package) 5. Connect +5V and GND pins of each chip to the power and ground bus strips on t he breadboard. 6. Select a connection on your schematic and place a piece of hook-up wire betwe en corresponding pins of the chips on your breadboard. It is better to make the sho rt connections before the longer ones. Mark each connection on your schematic as yo u go, so as not to try to make the same connection again at a later stage. 7. Get one of your group members to check the connections, before you turn the p ower on. 8. If an error is made and is not spotted before you turn the power on. Turn the power off immediately before you begin to rewire the circuit. 9. At the end of the laboratory session, collect you hook-up wires, chips and al l equipment and return them to the demonstrator.

10. Tidy the area that you were working in and leave it in the same condition as it was before you started.

COMMON CAUSES OF PROBLEMS 1. Not connecting the ground and/or power pins for all chips. 2. Not turning on the power supply before checking the operation of the circuit.

3. Leaving out wires. 4. Plugging wires into the wrong holes. 5. Driving a single gate input with the outputs of two or more gates 6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, comp onents at the start of the experiment and return them to their proper place after you have finished the experiment. Please inform the demonstrator or technician if you locate faulty equipment. If you damage a c hip, inform a demonstrator, don't put it back in the box of chips for somebody else to use.

DIGITAL INTEGRATED CIRCUITS (ICs) The digital integrated circuits are a collection of large number of resistors, diodes and transistors fabricated on a single piece of silicon called a substrate. This substrate with integrated components on it usually referred as a chip . The most common type of package is a dual-in-line pack age (DIP) is shown below. It is so called as it contains two parallel rows of pins. The pins are nu mbered in a counterclockwise fashion when viewed from the top. LOGIC GATES INTRODUCTION NOT GATE TRANSISTOR LEVEL DIAGRAM:

1 2 3 4 5 6 7 (b) (a) Fig. (a) Dual-in-line package; (b) top view of chip. Small dot Notch 14 13 12 11 10 9 8

PRACTICAL INVERTER CIRCUIT FLIP-FLOP IN AN ACTION D-LATCH IN AN ACTION

FLIP-FLOP USED IN ENCODER CIRCUIT

EX.NO. DATE : STUDY OF LOGIC GATES

AIM To study about logic gates and verify their truth tables APPARATUS REQUIRED 1. AND GATE IC 7408 2. OR GATE IC 7432 3. NOT GATE IC 7404 4. NAND GATE 2 I/P IC 7400 5. NOR GATE IC 7402 6. X-OR GATE IC 7486 7. NAND GATE 3 I/P IC 7410 8. IC TRAINER KIT - 1 THEORY Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NO R and XOR are known as universal gates. Basic gates form these gates. AND GATE The AND gate performs a logical multiplication commonly known as AND function. T he output is high when both the inputs are high. The output is low level when any o ne of the inputs is low. OR GATE The OR gate performs a logical addition commonly known as OR function. The outpu t is high when any one of the inputs is high. The output is low level when both the i nputs are low. NOT GATE The NOT gate is called an inverter. The output is high when the input is low. Th e output is low when the input is high. NAND GATE The NAND gate is a contraction of AND-NOT. The output is high when both inputs a re low and any one of the input is low .The output is low level when both inputs ar e high. NOR GATE The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output is low when one or both inputs are high. X-OR GATE The output is high when any one of the inputs is high. The output is low when bo th the inputs are low and both the inputs are high. PROCEDURE (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.

AND GATE NOT GATE OR GATE X-OR GATE 2-INPUT NAND GATE 2-INPUT OR GATE 3-INPUT AND GATE C:\Documents and Settings\user\Desktop\7486.jpg C:\Documents and Settings\user\Desktop\TTL-IC-7400-NAND-gate-dual-input.jpg C:\Documents and Settings\user\Desktop\7402-pin-connection-diagram.jpg C:\Documents and Settings\user\Desktop\7415.jpg

3-INPUT NOR GATE 3-INPUT NAND GATE RESULT C:\Documents and Settings\user\Desktop\7427_pinout.jpg C:\Documents and Settings\user\Desktop\7410diagram.gif

EX.NO: DATE: DESIGN AND IMPLEMENTATION OF ADDER AND SUBTRACTOR USING LOGIC GATES AIM To design and implement Adders and Subtractors using logic gates APPARATUS REQUIRED S.No. Name of the Apparatus Range Quantity 1 Digital Trainer kit

1 2 OR gate IC 7432 1 3 AND gate IC 7408 1 4 Ex-OR gate IC 7486 1 5 NOT gate IC 7404 1

5 Connecting wires

some

ADDER THEORY A combinational circuit that performs the addition of two binary digits is calle d a half adder. This circuit needs two binary inputs and two binary outputs. The input va riables designate the augends and the addend bits; the output variables produce the sum and carry. The simplified Boolean functions for the two outputs can be obtained directly from the truth ta ble. The simplified sums of products expressions are: Sum S = A B + AB Carry C = AB Where A & B are input variables. A full adder is a combinational circuit that forms the arithmetic sum of three i nput bits. It consists of three inputs and two outputs. The input variables designate the auge nds, addend and carry from the previous lower significant position. The output variables designa ted by sum and carry. The simplified Boolean expressions for the outputs are: Sum S = AnBnCn-1 + AnBnCn-1 +AnBnCn-1 + AnBnCn-1 Carry C = AnBnCn-1 + AnBnCn-1 + AnBn Where A & B are inputs and C is the carry from the previous lower stage.

HALF ADDER Block schematic A S =A B B C = AB Truth Table

Half Adder A B CARRY SUM 0 0 1 1

0 1 0 1 0 0 0 1 0 1 1 0

HALF ADDER VERILOG CODE FOR HALF ADDER module half adder (sum, carry,a,b); input a,b; output sum, carry; xor (sum, a,b); and(carry,a,b); end module

VHDL CODE FOR HALF ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL entity half adder is Port (a, b: in bit; sum, carry: out bit); end half adder; architecture behavioral of half adder is begin process(a,b) begin sum<= a xor b; carry<= a and b; end process; end Behavioral; FULL ADDER BLOCK SCHEMATIC

An

Full Adder Sn = (An Bn) Cn-1 Bn Cn-1 Cn = Cn-1 (An Bn) +AnBn TRUTH TABLE A B C CARRY SUM 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1

K-Map for SUM: SUM = A.B.C + A.BC. + ABC. + ABC K-Map for CARRY CARRY = AB + BC + AC LOGIC DIAGRAM VERILOG CODE FOR FULL ADDER module fulladder(s,cout, a,b,cin); input a,b,cin; output s,cout; wire p,q,r; xor(s,a,b,cin); and(p,a,b); and(q, b,cin); and(r,a,cin); or(cout,p,q,r); endmodule

VHDL CODE FOR FULL ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fa is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end fa; architecture Behavioral of fa is begin process(a,b,c) begin sum <= (a xor b)xor c; carry <= (a and b)or ((a xor b)and c); end process; end Behavioral; SUBTRACTOR THEORY: A combinational circuit that performs the subtraction of two binary digits is ca lled a half subtractor. This circuit needs two binary inputs and two binary outputs. The inp ut variables designate the minuend and the subtrahend bits; the output variables produce the difference and borrow. The simplified Boolean functions for the two outputs can be obtained dir ectly from the truth table. The simplified sums of products expressions are: Difference = AB + AB Borrow = AB Where A & B are input variables. A full subtractor is a combinational circuit that forms the arithmetic sum of th ree input bits. It consists of three inputs and two outputs. The input variables designate the s ubtrahend, minuend and borrow from the previous lower significant position. The output variables de signated by difference and borrow. The simplified Boolean expressions for the outputs are:

Difference Dn = AnBnCn-1 + AnBnCn-1 +AnBnCn-1 + AnBnCn-1

Borrow Cn = Cn-1 (An Bn) + An Bn Where A & B are inputs and C is the carry from the previous lower stage.

HALF SUBTRACTOR Block schematic

TRUTH TABLE A B BORROW DIFFERENCE 0 0 1 1

0 1 0 1 0 1 0 0 0 1 1 0

HALF SUBTRACTOR VERILOG CODE FOR HALF SUBTRACTOR: module halfsubtractor (diff, borrow, a,b); input a,b; output diff,borrow; xor(diff,a,b); not(a1,a) and(borrow,a1,b); endmodule

VHDL CODE FOR HALF SUBTRACTOR: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hs is Port ( a : in STD_LOGIC; b : in STD_LOGIC; diff : out STD_LOGIC; borrow : out STD_LOGIC); end hs; architecture Behavioral of hs is begin process(a,b) begin diff <= a xor b; borrow <= a and (not b); end process; end Behavioral; FULL SUBTRACTOR Block schematic:

An

Full subtractor Dn = (An Bn) Cn-1 Bn Cn-1 Cn = Cn-1 (An Bn) + AnBn TRUTH TABLE: A B C BORROW DIFFERENCE 0 0 0 0 1 1 1

0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 0 0 1

K-Map for Difference: K-Map for Borrow: LOGIC DIAGRAM FULL SUBTRACTOR VERILOG CODE FOR FULL SUBTRACTOR: module fullsubtractor(diff,bout, a,b,cin); input a,b,cin; output diff,bout; wire p,q,r; xor(s,a,b,cin); not (a1,a) and(p,a1,b); and(q,b,cin); and(r,a,cin); or(cout,p,q,r); endmodule VHDL CODE FOR FULL SUBTRACTOR: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fs is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC;

diff : out STD_LOGIC; borrow : out STD_LOGIC); end fs; architecture Behavioral of fs is begin process(a,b,c) begin diff <=(a xor b)xor c; borrow <= ((not(a xor b)) and c) or ((not a)and b ); end process; end Behavioral; PROCEDURE: 1. Verify the gates. 2. Make the connections as per the circuit diagram. 3. Switch on VCC and apply various combinations of input according truth table. 4. Verify the output. VIVA QUESTIONS: 1. 2. 3. 4. 5. What What What What What is do is is is half adder? you mean by carry propagation delay? the difference between serial adder and parallel adder? Full adder? a combinational circuit?

VIVA QUESTIONS: 1. 2. 3. 4. 5. What is Half Subtractor? What do you mean by carry propagation delay? What is BCD adder? What is Full Subtractor? Write the design procedure for combinational circuit?

RESULT ASSIGNMENT 1. Draw a full adder circuit using two half adders.

EX.NO. DATE: DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING LOGIC GATES BCD TO EXCESS 3 AND EXCESS 3 TO BCD CODE CONVERSION AIM: To convert the given BCD numbers to Excess - 3 codes and vice versa APPARATUS REQUIRED: S.No. Name of the apparatus Range Quantity 1 Digital Trainer kit

1 2 OR gate IC 7432 2 3 AND gate IC 7408 2 4 3-Input AND gate IC 7411 1 5 NOT gate IC 7404

1 6 Ex-OR gate IC 7486 1 7 Connecting wires

some

THEORY: BCD code to Excess-3 code conversion: Binary coded decimal code as the name itself conveys it is a code in which a dec imal is represented by binary numbers. Whereas Excess-3 code is one in which a decimal v alue (X) is represented by a binary code, which corresponds to another decimal value whose v alue is 3 in excess (X + 3). The mathematical expression, which represents this conversion, i s as follows. _______ E3 = B0B2 + B1B2 + B3 E1 = B0 B1 _ _ _ _ _ E2 = B0B2 + B1B2 + B0B1B2 E0 = B0 Excess3 code of decimal digit x. is obtained by adding 3(0011) to the BCD code of decimal digit x.. Excess3 is a sequential code because each succeeding code is one binary no. g reater than its preceding code.Excess3 is a self complementing code. Example: Excess3 for (5)10 are: Decimal No. B3 B2 B1 B0 (5)10 0 1 0

1 +

(3)10 0 0 1 1 =

(8)10 1 0 0 0 Excess 3 E3 E2 E1 E0

BCD TO EXCESS-3 CODE CONVERTER: Truth Table: Decimal No. BCD Excess 3

B3 B2 B1 B0 E3 E2 E1 E0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0

1 0 0 2 0 0 1 0 0 1 0 1 3 0 0 1 1 0 1 1 0 4 0 1 0 0 0 1 1 1

5 0 1 0 1 1 0 0 0 6 0 1 1 0 1 0 0 1 7 0 1 1 1 1 0 1 0 8 1 0

0 0 1 0 1 1 9 1 0 0 1 1 1 0 0

K-Map for E3:

E3 = B3 + B2 (B0 + B1) K-Map for E2:

K-Map for E1: K-Map for E0: LOGIC DIAGRAM: BCD TO EXCESS-3 CONVERTOR

VHDL CODE FOR BCD-EXCESS3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd2x3 is Port (B3: in STD_LOGIC; B2: in STD_LOGIC; B1: in STD_LOGIC; B0: in STD_LOGIC; E3: out STD_LOGIC; E2: out STD_LOGIC; E1: out STD_LOGIC; E0: out STD_LOGIC ;) end bcd2x3; architecture Behavioral of bcd2x3 is begin E3 <= B3 or (B2 and (B1 or B0)); E2 <= B2 xor (B1 or B0); E1 <= B1 xnor B0; E0 <= not b0; end Behavioral; EXCESS3-BCD CONVERTER TRUTH TABLE: Excess 3 Input

BCD Output E3 E2 E1 E0 B3 B2 B1 B0 0 0 0 0 0 1 1 1 1 1

0 1 1 1 1

0 0 0 0 1

1 0 0 1 1 0 0 1 1 0

1 0 1 0 1 0 1 0 1 0

0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1

K-Map for B3:

A = X1 X2 + X3 X4 X1 K-Map for B2: K-Map for B1: K-Map for B0:

LOGIC DIAGRAM: EXCESS-3 TO BCD CONVERTER VHDL CODE FOR BCD-EXCESS3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity x32bcd is Port (X3: in STD_LOGIC; X2: in STD_LOGIC; X1: in STD_LOGIC; X0: in STD_LOGIC; A: out STD_LOGIC; B: out STD_LOGIC; C: out STD_LOGIC; D: out STD_LOGIC ;) end x32bcd; architecture Behavioral of x32bcd is begin E3 <= B3 or (B2 and (B1 or B0)); E2 <= B2 xor (B1 or B0); E1 <= B1 xnor B0; E0 <= not b0; end Behavioral; PROCEDURE: 1. Convert BCD to EXCESS-3 code and EXCESS-3 code to BCD by the procedure given above. 2. Perform the K-Map Simplification 3. Draw the logic diagram for the K-Map simplified output. 4. Use various Logic GATES and breadboard to implement the circuit.

VIVA QUESTIONS: 1. What are code converters?

2. Distinguish between Boolean addition and Binary addition:

3. What is decoder?

4. What is encoder?

5. What is Priority Encoder?

RESULT: SELF STUDY 1. Write a VERILOG code for BCD-EXCESS3 and vice-versa.

EX.NO: DATE: BINARY TO GRAY AND GRAY TO BINARYCODE CONVERSION AIM: To convert given binary numbers to gray codes and vice versa APPARATUS REQUIRED: S.No. Name of the apparatus Range Quantity 1 Digital Trainer kit

1 2 Ex-OR gate IC 7486 1 3 Connecting wires

some

THEORY: BINARY TO GRAY CODE CONVERSION: Binary code is representing a decimal number with the help of 8421 code, where t he numbers show to us the weights of their respective positions.Only a single bit c hange from one code word to the next in sequence.And Gray code can be attained from the binary code as illustrated in the following example. Consider a binary number 1101 for which the corresponding Gray code is going to be found out. B3 B2 B1 B0 BINARY 1 1 0 1 + + +

GRAY 1 0 1 1 1 G3 G2 G1 G0 As can be clearly seen, Gray code generation follows some simple steps. The Most Significant Bit (MSB) of the binary code is retained as the MSB of the Gray code too. The next bit of the Gray code can be attained by adding the MSB and the adjacent bit of the b inary code. The consequent bits of the Gray code can be attained in the same fashion. If this co nversion is given a little more thought, one striking feature that one would find is that except for the MSB the consequent bits in the Gray code will be 1 if and only if the corresponding bit and the previous code of the Binary code are not the same. Using the observation we can write the following expressions: G3 = B3 G2 = B3 B2 G1 = B2 B1 G0 = B1 B0

Truth Table Binary Gray B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

BINARY TO GRAY CODE CONVERTOR: K-Map for G3: G3=B3 K-Map for G2:

K-Map for G1: K-Map for G0: Binary to gray code converter: Circuit Diagram:

VHDL CODE FOR BINARY-GRAY CODE CONVERTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cc is Port ( b3 : in STD_LOGIC; b2 : in STD_LOGIC; b1 : in STD_LOGIC; b0 : in STD_LOGIC; g3 : out STD_LOGIC; g2 : out STD_LOGIC; g1 : out STD_LOGIC; g0 : out STD_LOGIC); end cc; architecture Behavioral of cc is begin g3 <= b3; g2 <= b2 xor b3; g1 <= b1 xor b2; g0 <= b0 xor b1; end Behavioral; Gray to Binary code conversion: A Gray code can also be converted into a binary code in almost a similar manner but with some deviations. With the help of an example this conversion is explained below. Consider a Gray code 1111 for which a binary is going to be found out. G3 G2 G1 G0 GRAY 1 1 1 1 1

+ + + BINARY 1 1 0 1 B3 B2 B1 B0 By looking at the illustration it is very easy to understand that MSB of both th e codes are the same whereas the consecutive bits of the binary is attained by adding the co rresponding bit of the Gray code with the sum of the more significant bits. The expressions for the individual bits of the binary code in terms of the bits of the Gray code. B3 = G3 B2 = G3 G2 B1 = G3 G2 G1 B0 = G3 G2 G1 G0

Truth Table: Gray to Binary G3 G2 G1 G0 B3 B2 B1 B0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0

0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1

1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

K-Map for B3: B3 = G3 K-Map for B2:

K-Map for B1: K-Map for B0: LOGIC DIAGRAM: GRAY CODE TO BINARY CONVERTOR

VHDL CODE FOR GRAY-BINARY CONVERTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gtb is Port ( g3 : in STD_LOGIC; g2 : in STD_LOGIC; g1 : in STD_LOGIC; g0 : in STD_LOGIC; b3 : out STD_LOGIC; b2 : out STD_LOGIC; b1 : out STD_LOGIC; b0 : out STD_LOGIC); end gtb; architecture Behavioral of gtb is begin b3 <= g3; b2 <= g2 xor g3; b1 <= g1 xor (g2 xor g3); b0 <= g0 xor (g1 xor (g2 xor g3)); end Behavioral; PROCEDURE: 1. The circuit connections are made as shown in fig. 2. Pin (14) is connected to +Vcc and Pin (7) to ground. 3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are gi ven at respective pins and outputs G0, G1, G2, and G3 are taken for all the 16 combinations of the input. 4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are gi ven at respective pins and outputs B0, B1, B2, and B3 are taken for all the 16 combinations of inputs. 5. The values of the outputs are tabulated. RESULT: ASSIGNMENT 1. Design a code converter that converts a decimal digit from 8,4,2,1 to BCD. 2. Design a code converter that converts a code from 5211 to 4211 3. Design a code converter that converts a code from 8421 to 2421

SELF STUDY 1. Write a VERILOG code for Binary to Gray and vice-versa.

FUNCTIONAL DIAGRAM OF IC 7483 Operand1 Operand2 PIN DIAGRAM OF IC 7483 B3 B2 B1 B0 A3 A2 A1 A0

4 bit IC 7483 C4 C0 O/P

EX.NO.3 DATE: 3. DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER / SUBTRACTOR AND BCD ADDER USING IC7483 AIM To study the 4 bit binary adder/subtractor and BCD adder using IC7483. APPARATUS REQUIRED S.No. Name of the apparatus Range Quantity 1 Digital Trainer kit

1 2 OR gate IC 7432 1 3 AND gate IC 7408 1 4 Binary Adder / Subtractor IC 7483 2 5 Connecting wires

some

THEORY The full adder/sub tractors are capable of adding/subtracting only two single di git binary numbers along with a carry input. But in practice we need to add/subtract binary numbers, which are much longer than just one bit. To add/subtract two n-bit binary numbers we n eed to use the nbit parallel subtractor/adder. Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input bi nary numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is t he input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the powe r supply and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001 and the B inputs and the input carry to five toggle switches. The five outputs are appli ed to indicator lamps. Perform the addition of a few binary numbers and check that the output su m and output carry give the proper values. Show that when the input carry is equal to 1, it a dds 1 to the output sum. Binary subtractor The subtraction of two binary numbers can be done by taking the 2.s complement o f the subtrahend and adding it to the minuend. The 2.s complement can be obtained by t aking the 1.s complement and adding. To perform A-B, we complement the four bits of B, add the m to the four bits of A, and add 1 through the input carry. The four XOR gates complement the bits of B when the mode select M=1(because) and leave the bits of B unchanged when M=0(because ) .Thus, when the mode select M is equal to 1, the input carry C0 is equal 1 and the sum output is A plus the 2.s complement of B. when M is equal to 0, the input ca rry is equal to 0 and the sum generates A+B. xx0

4-BIT BINARY ADDER: 4-BIT BINARY SUBTRACTOR:

LOGIC DIAGRAM OF 4-BIT BINARY ADDER/SUBTRACTOR

TRUTH TABLE

Input Data A Input Data B Addition Subtraction A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1 1 0

0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1

1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 0 1 1 0 1

1 1 0 1 1 0 1

BCD ADDER 4-BIT BCD ADDER Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. A BCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum. LOGIC DIAGRAM

PROCEDURE 1. Connections are given as per the circuit diagram. 2. Set mode M =0 such that the circuit will operate in addition mode. 3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry . 4. Repeat the same step in step 3 by keeping M=1 such that circuit will operate in subtraction mode.

RESULT ASSIGNMENT 1. Design a 4-bit binary adder using basic gates

EX.NO. DATE: DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE COMPARATOR USING LOGIC GATES AIM To design and construct a 2 bit magnitude comparator using logic gates. APPARATUS REQUIRED S.No Name of the apparatus Range Quantity 1 Digital Trainer kit

1 2 NOR gate IC 7402 2 3 AND gate IC 7408 2 4 NOT gate IC 7404 1 5 Ex-OR gate IC 7486 1 6

Connecting wires

some

THEORY MAGNITUDE COMPARATOR A magnitude comparator is a combinational circuit that compares two number A and B and determines relative magnitudes. The outcome of the comparison is specified by th ree binary variables which indicate whether (A>B), (A=B), (A<B). The circuit for comparing two n-bit numbers has 22n entries in the truth table and this is even difficult with n=3 a s it requires 64 entries in truth table. The MSB of A and B is compared and the bit position is c hecked where (A>B) or (A=B) or (A<B). If (A>B) or (A<B) that is the final output. But if (A=B ) then next significant bit is compared. 4.1 2-BIT MAGNITUDE COMPARATOR . For a 2 bit comparator, each input word is 2 bit long . The output of 2 bit magnitude comparator is (A=B)=(A1. B1)(A0. B0) (A=B) = A<B = A>B = 1010010101010101BBAABBAABBAABBAA 01011001BBABABAA 11001010BABAABBA

Block diagram: TRUTH TABLE OUTPUT INPUT A>B A=B A<B A0 A1 B2 B1 2 bit Magnitude Comparator Inputs Outputs A1 A0 B1 B0 A<B A=B A>B 0 0 0 0 0 1

0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0

1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0

1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0

0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0

K MAP

CIRCUIT DIAGRAM:

VHDL CODE FOR 2-BIT MAGNITUDE COMPARATOR LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity comparator is port ( a1 : in std_logic; a0 : in std_logic; b1 : in std_logic; b0 : in std_logic; alessb : out std_logic; agreaterb : out std_logic; aequalb : out std_logic); end comparator; architecture behavioral of comparator is begin aequalb <= (not(a1 xor b1)) and (not(a0 xor b0)); alessb <= (((not a0) and b0) and ((not a1) or b1)) or ((not a1) and b1); agreaterb <= ((a0 and (not b0)) and (a1 or (not b1))) or (a1 and (not b1)); end behavioral; PIN DIAGRAM OF IC7485

CONNECTION DIAGRAM OF 4-BIT MAGNITUDE COMPARATOR CONNECTION DIAGRAM OF 8-BIT COMPARATOR USING TWO 4-BIT COMPARATOR

FUNCTION TABLE TRUTH TABLE PROCEDURE 1. Connections are given as per in the circuit diagram. 2. Inputs are given through the logic switches. 3. Outputs are noted and verified with truth table.

RESULT SELF STUDY 1. Write a VERILOG code for 2-bit magnitude comparator.

EX.NO. DATE: DESIGN AND IMPLEMENTATION OF 16-BIT ODD / EVEN PARITY GENERATOR & CHECKER AIM To design and construct an odd/even parity checker/generator using logic gates. APPARATUS REQUIRED S.No. Name of the apparatus Range Quantity 1 Digital Trainer kit

1 2 Parity Generator / Checker IC 74180 2 3 NOT gate IC 7404 1 4 Connecting wires

some

THEORY A parity bit is used for detecting errors during transmission of binary informat ion. A parity bit is an extra bit included with a binary message to make the number is either

even or odd. The message including the parity bit is transmitted and then checked at the receiver ends for errors. An error is detected if the checked parity bit doesn.t correspond to the one transm itted. The circuit that generates the parity bit in the transmitter is called a parity generator. and the circuit that checks the parity in the receiver is called a parity checker.. In even parity, the added parity bit will make the total number is even amount. In odd parity, the added parity bit will make the total number is odd amount. The parit y checker circuit checks for possible errors in the transmission. If the information is passed in even parity, then the bits required must have an even number of 1.s. An error occur during transmissio n, if the received bits have an odd number of 1.s indicating that one bit has changed in value duri ng transmission. 3- BIT EVEN PARITY GENERATOR

TRUTH TABLE 3 bit message Parity bit x y z p 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0

1 0 1 1 0 0 1 1 1 1

4-BIT EVEN PARITY CHECKER

C TRUTH TABLE

Four Bits Received Parity Error Check x y z P C 0 0

0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1

1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0

PIN DIAGRAM OF IC74180 Where, I0-I7 data inputs OI odd input EI even input . O Odd parity output . E Even parity output FUNCTION TABLE INPUTS

OUTPUTS Number of High Data Inputs (I0 I7) PE PO SE SO EVEN 1 0 1 0 ODD 1 0 0 1 EVEN 0 1 0 1

ODD 0 1 1 0 X 1 1 0 0 X 0 0 1 1

TRUTH TABLE INPUTS OUTPUTS NO. OF 1 S EVEN ODD . EVEN . ODD EVEN ODD EVEN ODD X X H H L L H L L L H H H L H L L H L H L H H L L H

5.3 CONNECTION DIAGRAM OF 16-BIT PARITY GENERATOR/CHECKER FUNCTION TABLE

INPUTS OUTPUTS NO. OF 1 S EI OI . E . O EVEN 0 1 0 1 1 0 1 0 ODD 0 1 1 0 1 0 0 1 X 1 1 0 0 0 0 1 1

LOGIC DIAGRAM 16 BIT ODD/EVEN PARITY CHECKER TRUTH TABLE I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 11 Active SE SO 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 I0

LOGIC DIAGRAM 16 BIT ODD/EVEN PARITY GENERATORS TRUTH TABLE I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0

Active SE SO 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

PROCEDURE 1. Connections are given as per in the circuit diagram. 2. Inputs are given through the logic switches. 3. Outputs are noted and verified with truth table.

RESULT SELF-STUDY 1. Implementation of 4-bit Odd Parity Generator circuit. 2. Implementation of 4-bit Odd Parity Checker circuit. 3. Write a VERILOG & VHDL code for 3-bit even parity generator & 4-bit even pari ty checker VIVA QUESTIONS 1. What is a Hamming code?

2. How many parity bits are required to form Hamming code if message bits are 6?

3. Generate the even parity Hamming codes for following binary data 1101 and 100 01?

4. A seven bit Hamming code is received as 1111101. What is the correct code?

EX.NO DATE: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER USING LOGIC GATES AIM To design and implement multiplexer and demultiplexer using logic gates APPARATUS REQUIRED S.No. Name of the apparatus Range Quantity 1 Digital Trainer kit

2 OR gate IC7432 1 3 AND gate IC7411 1 4 NOT gate IC7404 1 5 Connecting wires

THEORY MULTIPLEXER Multiplexer means transmitting a large number of information units over a smalle r number of channels or lines. A digital multiplexer is a combinational circuit that sele cts binary information from one of many input lines and directs it to a single output line. The selecti on of a particular input line is controlled by a set of selection lines. Normally there are 2n inpu t line and n selection lines whose bit combination determine which input is selected. DEMULTIPLEXER The function of Demultiplexer is in contrast to multiplexer function. It takes i nformation from one line and distributes it to a given number of output lines. For this rea son, the demultiplexer is also known as a data distributor. Decoder can also be used as d emultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND ga tes. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line.

4-1 MULTIPLEXER SYMBOL LOGIC DIAGRAM

FUNCTION TABLE S0 S1 D0 D1 D2 D3 O/P 0 0 1 X X X 1 0 0 0 X X X 0 0 1 X 1 X X 1

0 1 X 0 X X 0 1 0 X X 1 X 1 1 0 X X 0 X 0 1 1 X X X 1 1 1 1

X X X 0 0

VERILOG CODE FOR 4-1 MULTIPLEXER module mux(f,d0,d1,d2,d3,s0,s1); input d0,d1,d2,d3,s0,s1; output f; wire ns1,ns0,p,q,r,s; not (ns1,s1); not(ns0,s0); and(p,ns0,ns1,i0); and(q,s0,ns1,i1); and(r,ns0, s1,i2); and(s,s0, s1,i3); or(f,p,q,r,s); endmodule

VHDL CODE FOR 4-1 MULTIPLEXER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( d3 : in STD_LOGIC; d2 : in STD_LOGIC; d1 : in STD_LOGIC; d0 : in STD_LOGIC; s1 : in STD_LOGIC; s0 : in STD_LOGIC; mout : out STD_LOGIC); end mux; architecture Behavioral of mux is begin mout <= (((d0 and (not s1) and (not s0)) or (d1 and (not s0) and s1)) or ((d2 and s0 and (not s1)) or (d3 and s0 and s1))); end Behavioral; BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXERS FUNCTION TABLE S1 S0 INPUT 0 0 X . D0 = X S1. S0. 0 1 X . D1 = X S1. S0 1 0 X . D2 = X S1 S0. 1 1 X . D3 = X S1 S0

Y = X S1. S0. + X S1. S0 + X S1 S0. + X S1 S0

VERILOG CODE FOR 1-4 DE-MULTIPLEXER module demux(do,d1,d2,d3, a,b,s); input a,b,s; output d0,d1,d2,d3; wire a1,b1; not (a1,a); not(b1,b); and(d0,b1,a1,s); and(d1,b,a1,s); and(d2,b1,a,s); and(d3,b,a,s); endmodule PIN DIAGRAM FOR IC 74150

CONNECTION DIAGRAM OF 16-1 MULTIPLEXER USING IC74150 FUNCTION TABLE

2-4 DEMULTIPLEXERS E B A D0 D1 D2 D3 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0

1 1 1 0 0 0 1

LOGIC DIAGRAM PIN DIAGRAM FOR IC 74154 1242174113E741141374042611346215B51233A56D0D1D2D3

CONNECTION DIAGRAM OF 4-16 DEMULTIPLEXER USING IC74154

PROCEDURE 1. Connections are given as per in the circuit diagram. 2. Inputs are given through the logic switches. 3. Outputs are noted and verified with truth table

RESULT VIVA QUESTIONS: 1. What are the applications of multiplexer?

2. What is the difference between multiplexer & demultiplexer?

3. In 2n: 1 multiplexer how many selection lines are used?

4. Draw a 2 to 1 multiplexer circuit

5. Draw a 1 to 2 demultiplexer circuit.

6. What is the difference between a decoder and a demultiplexer? ASSIGNMENT 1. Implementation of 8-1 multiplexer using two 4-1 mux & a 2-1 mux. 2. Write a VHDL code for 1-4 & 2-4 demux.

MINIPROJECT 1. LED CHASER USING 4-BIT SYNCHRONOUS COUNTER & 3-8 DEMULTIPLEXER

EX.NO: DATE: DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER AIM To design and implement encoder and decoder using logic gates and study of IC 74 45 and IC 74147. APPARATUS REQUIRED S.No. COMPONENT SPECIFICATION QTY. 1. 3 I/P NAND GATE IC 7410 2 2. OR GATE IC 7432 3 3. NOT GATE IC 7404 1 2. IC TRAINER KIT 1 3. PATCH CORDS -

27

THEORY ENCODER An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n input lines and n output lines. In encoder the output lines generates the bin ary code corresponding to the input value. In octal to binary encoder it has eight inputs , one for each octal digit and three output that generate the corresponding binary code. In encoder i t is assumed that only one input has a value of one at any given time otherwise the circuit is mea ningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero outputs c an also be generated when D0 = 1. DECODER A decoder is a multiple input multiple output logic circuit which converts coded input into coded output where input and output codes are different. The input code generall y has fewer bits than the output code. Each input code word produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible outputs. 2n outp ut values are from 0 through out 2n 1.

1-4 DECODER LOGIC DIAGRAM 2-4 DECODERS LOGIC DIAGRAM

TRUTH TABLE INPUT OUTPUT E A B D0 D1 D2 D3 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0

1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0

VHDL CODE FOR DECODER library ieee ; use ieee.std_logic_1164.all ; entity dec2to4 IS port ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0); en : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; end dec2to4 ; architecture Behavior OF dec2to4 is signal enw : STD_LOGIC_VECTOR(2 DOWNTO 0); begin enw <= en & w; with enw select y <= 1000. when 100., 0100. when 101., 0010. when 110., 0001. when 111., 0000. when others ; end Behavior ;

BCD TO DECIMAL DECODER PIN DIAGRAM FOR IC 7445 CONNECTION DIAGRAM OF BCD-DECIMAL DECODER USING IC7445

FUNCTION TABLE: INPUTS OUTPUTS A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 0 0 0 0 0 1 1 1 1 1 1 1

1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1

0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1

1 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1

1 1 1 1 1 1 1 0

8 to 3 ENCODER LOGIC DIAGRAM

TRUTH TABLE INPUT OUTPUT Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0

1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1

PIN DIAGRAM FOR IC 74147 10 LINE TO 4 LINE PRIORITY ENCODER CONNECTION DIAGRAM OF IC74147

FUNCTION TABLE INPUTS OUTPUTS I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0 H H H H H H H H H H H H H X

X X X X X X X L L H H L X X X X X X X L H L H H H X X X X X

X L H H H L L L X X X X X L H H H H L L H X X X X L H H H H

H L H L X X X L H H H H H H L H H X X L H H H H H H H H L L

X L H H H H H H H H H L H L H H H H H H H H H H H L

PROCEDURE (i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.

RESULT

MINI PROJECT 1. SIMPLE DIGITAL SECURITY SYSTEM http://www.electronicsforu.com/electronicsforu/circuitarchives/my_documents/my_ pictures/64A_march_4_efy.png The digital security system circuit

http://www.electronicsforu.com/electronicsforu/circuitarchives/my_documents/my_ pictures/B45_march_2_-efy.png

The proposed wiring diagram of loops

EX.NO. DATE: CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER AIM To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter. APPARATUS REQUIRED S.No. COMPONENT SPECIFICATION QTY. 1. JK FLIP FLOP IC 7476 2 2. NAND GATE IC 7400 1 3. IC TRAINER KIT 1 4. PATCH CORDS 30

THEORY A counter is a register capable of counting number of clock pulse arriving at it s clock input. Counter represents the number of clock pulses arrived. A specified sequence of s

tates appears as counter output. This is the main difference between a register and a counter. Th ere are two types of counter, synchronous and asynchronous. In synchronous common clock is given to a ll flip flop and in asynchronous first flip flop is clocked by external pulse and then each succe ssive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is t riggered by output of first stage. Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous operation. 4-bit ripple counter which follows a sequence of 16 states can be converted into Mod10(decade counter) and Mod-12 counter using simple feed back loop. Decade counte r follows a sequence of ten states and returns to 0 after the count of 9. Mod-12 counter fol lows a sequence of 12 states and returns to 0 after the count of 11.

PIN DIAGRAM FOR IC 7476 LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER

TRUTH TABLE CLK QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0

1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1 10 0 1

0 1 11 1 1 0 1 12 0 0 1 1 13 1 0 1 1 14 0 1 1 1 15 1 1 1 1

VERILOG CODE FOR 4-BIT RIPPLE COUNTER module counter( clk, count ); input clk;

output[3:0] count; reg[3:0] count; wire clk; initial count = 4'b0; always @( negedge clk ) count[0] <= ~count[0]; always @( negedge count[0] ) count[1] <= ~count[1]; always @( negedge count[1] ) count[2] <= ~count[2]; always @( negedge count[2] ) count[3] <= ~count[3]; endmodule

VHDL CODE FOR 4-BIT RIPPLE COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture Behavioral of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end Behavioral; LOGIC DIAGRAM FOR MOD-10 RIPPLE COUNTER

TRUTH TABLE CLK QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0

1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1 10 0 0

0 0

VERILOG CODE FOR MOD-10 COUNTER Module counter4b (clk, rst, led); output [3:0] led; input clk, rst; reg [28:0] cntr = 0; reg [3:0] led; always @ (posedge clk) begin if (rst==1.b1) begin cntr<=0; led<=cntr[20:17]; end else begin cntr<=cntr + 1; led<=cntr[20:17]; end if (cntr==4.b1010) begin cntr<=0; led<=cntr[20:17]; end end end module

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER TRUTH TABLE CLK QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0

1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1 10 0 1

0 1 11 1 1 0 1 12 0 0 0 0

VERILOG CODE FOR MOD-12 COUNTER Module counter4b (clk, rst, led); Output [3:0] led; Input clk, rst; reg [28:0] cntr = 0; reg [3:0] led; always@(posedge clk) begin if(rst==1.b1) begin cntr<=0; led<=cntr[20:17]; end else begin cntr<=cntr + 1; led<=cntr[20:17]; end if(cntr == 4.b1100) begin cntr<=4.b0000; led<=cntr[20:17]; end end end module PROCEDURE (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.

RESULT

SELF STUDY 1. Write a VHDL code for MOD-10 and M0D-12 ripple counter.

MINI PROJECT 1. FREQUENCY DIVIDER

EX.NO. DATE: DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER AIM To design and implement 3 bit synchronous up/down counter. APPARATUS REQUIRED S.No. COMPONENT SPECIFICATION QTY. 1. JK FLIP FLOP IC 7476 2 2. 3 I/P AND GATE IC 7411 1 3. OR GATE IC 7432 1 4. XOR GATE IC 7486 1 5. NOT GATE IC 7404 1

6. IC TRAINER KIT 1 7. PATCH CORDS 35

THEORY A counter is a register capable of counting number of clock pulse arriving at it s clock input. Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of progressing in increasing order or decreasing order through a certain sequenc e. An up/down counter is also called bidirectional counter. Usually up/down operation of the c ounter is controlled by up/down signal. When this signal is high counter goes through up sequence and when up/down signal is low counter follows reverse sequence. STATE TABLE PRESENT STATE NEXT STATE FLIP-FLOP INPUTS Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1

J0 K0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 1 0 0 X 1 X X 1 0 1 0 0

1 1 0 X X 0 1 X 0 1 1 1 0 0 1 X X 1 X 1 1 0 0 1 0 1 X 0 0 X

1 X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 1 1 1 X 0 X 0 1 X 1 1 1 0

0 0 X 1 X 1 X 1

3-BIT SYNCHRONOUS UP COUNTERS TABULATION Clock Q2 Q1 Q0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1

6 1 1 0 7 1 1 1

STATE TABLE PRESENT STATE NEXT STATE FLIP-FLOP INPUTS Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 1 1 1 1

1 0 X 0 X X X 1 1 1 0 1 0 1 X 0 X X 1 X 1 0 1 1 0 0 X 0 0 0

X 1 1 0 0 0 1 1 X 1 1 1 1 X 0 1 1 0 1 0 0 X 0 0 X 1 0 1 0 0

0 1 0 X 1 1 1 X 0 0 1 0 0 0 0 X X X X 1 0 0 0 1 1 1 1 X X X

1 X

VERILOG CODE FOR 3-BIT SYNCHRONOUS UP COUNTER module synccounter(clk,reset,out); input clk,reset; output [2:0] out; reg [2:0] out; always @(posedge clk) begin if (reset == 1'b1) out <= 3'b000; else out <= out+1'b1; end endmodule VHDL CODE FOR 3-BIT SYNCHRONOUS UP COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity 3bc is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; sel : in STD_LOGIC; q : out STD_LOGIC); end 3bc; architecture Behavioral of 3bc is begin process(clk,reset) begin if reset = '1' then q <= "000"; else if rising_edge(clk) and reset ='0' and sel = '0' then q <= q+1; if rising_edge(clk) and reset = '0' and sel = '1' then q <= q+2; end if; end if; end process; end Behavioral;

3-BIT SYNCHRONOUS DOWN COUNTERS TABULATION Clock Q2 Q1 Q0 0 1 1 1 1 1 1 0 2 1 0 1 3 1 0 0 4 0 1 1 5 0 1 0

6 0 0 1 7 0 0 0

VERILOG CODE FOR 3-BIT SYNCHRONOUS DOWN COUNTER module synccounter(clk,reset,out); input clk,reset; output [2:0] out; reg [2:0] out; always @(posedge clk) begin if (reset == 1'b1) out <= 3'b111; else out <= out-1'b1; end endmodule

VHDL CODE FOR 3-BIT SYNCHRONOUS DOWN COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity 3bc is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; sel : in STD_LOGIC; q : out STD _LOGIC); end 3bc; architecture Behavioral of 3bc is begin process(clk,reset) begin if reset = '1' then q <= "111"; else if rising_edge(clk) and reset ='0' and sel = '0' then q <= q-1; if rising_edge(clk) and reset = '0' and sel = '1' then q <= q-2; end if; end if; end process; end Behavioral; 3-BIT SYNCHRONOUS UP/DOWN COUNTERS TRUTH TABLE Input Up/Down Present State QA QB QC Next State QA+1 Q B+1 QC+1 A JA KA B JB KB C JC KC 0 0 0 0 1 1 1 1 X 1 X 1 X 0 1 1 1

1 1 0 X 0 X 0 X 1 0 1 1 0 1 0 1 X 0 X 1 1 X 0 1 0 1 1 0 0 X 0 0 X X 1 0 1 0 0 0 1 1 X 1 1 X 1 X 0 0 1 1 0 1 0 0 X X 0 X 1 0 0 1 0

0 0 1 0 X X 1 1 X 0 0 0 1 0 0 0 0 X 0 X X 1 1 0 0 0 0 0 1 0 X 0 X 1 X 1 0 0 1 0 1 0 0 X 1 X X 1 1 0 1 0 0 1 1 0 X X 0 1 X 1 0 1 1

1 0 0 1 X X 1 X 1 1 1 0 0 1 0 1 X 0 0 X 1 X 1 1 0 1 1 1 0 X 0 1 X X 1 1 1 1 0 1 1 1 X 0 X 0 1 X 1 1 1 1 0 0 0 X 1 X 1 X 1

K MAP LOGIC DIAGRAM

CHARACTERISTICS TABLE Q Qt+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

VHDL CODE FOR 4-BIT UPDOWN COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity up_dn_beh4 isPort ( clk,rst : in STD_LOGIC;u_d : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end up_dn_beh4; architecture Behavioral of up_dn_beh4 is signal cnt: std_logic_vector (2 downto 0); signal en : std_logic; beginq <= cnt; P1:process(clk) beginif(clk ' event and clk = '1') thenif (rst = '1') then cnt <

= "000"; elsif (u_d = '1' and en = '1') then cnt <= cnt + 1; elsif (en = '0') then cnt <= cnt - 1; end if; end if; end process P1; P2: process(cnt) begin if (cnt = "000") then en <= '1'; elsif (cnt = "111") then en <= '0'; end if; end process P2;end Behavioral;

VERILOG CODE FOR 4-BIT UPDOWN COUNTER module up_down_counter (count, D_in, load, count_up, cntr_on, clk, reset); output [2:0] count; input load, count_up, cntr_on, clk, reset; input [2:0] D_in; reg [2:0] count; always @ (posedge reset or posedge clk) if (reset==1'b1) count=3'b0; else if (load==1'b1) count=D_in; if (cntr_on==1) begin if (count_up==1'b1) count=count + 1; else count=count - 1; end endmodule PROCEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.

RESULT:

SELF STUDY 1. SYNCHRONOUS DECADE COUNTER:

2. GRAY CODE COUNTER

MINIPROJECT 1. LED WALKER USING RING COUNTER:

2. LED FLASHER USING 5-STAGE JHONSON COUNTER( IC 4017)

EX.NO. DATE: IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT REGISTERS AIM To implement the 4 bit shift register using flip flops and to study the operatio ns in the following modes. (i) serial in serial out (ii) Serial in parallel out (iii) Parallel in parallel out.

APPARATUS REQUIRED S.No. Name of the apparatus Range Quantity 1 Digital Trainer kit

1 2 D Flip Flop IC 7474 2 3 Connecting wires

some

THEORY SHIFT REGISTER A register is a device capable of storing a bit. The data can be serial or paral lel. The register can convert a data from serial to parallel and vice versa shifting then digits t o left and right is the

important aspect for arithmetic operations, A register capable of shifting its binary information either to the right or to the left is called a shift register. An N bit shift register consists of N flip-flops and the gates t hat control the shift operation. A shift register can be used in four different configurations dependi ng upon the way in which the data are entered into and taken out of it. These four configurations a re: . . . . Serial-input, Serial-output Parallel-input, Serial-output Serial-input, parallel-output Parallel-output, parallel-output

The serial input is a single line going to the input of the leftmost flip-flop o f the register. The serial output is a single line from the output of the rightmost flip-flop of the register, so that the bits stored in the register can come out through this line one at a time. The parallel output consists of N lines, one for each of the flip-flops in the r egister, so the information stored in the register can be inspected through these lines all at o nce. PROCEDURE 1. The flip-flop is connected using connecting wires as shown in the circuit. 2. The flip flop are then reset to zero internally with the help of reset to set inputs. 3. The bits are shifted in by giving suitable clock input. 4. Thus the truth table is then verified.

PIN DIAGRAM OF IC7474 SERIAL IN SERIAL OUT TRUTH TABLE Clock Serial in Serial out 1 1 0 2 0 0 3 0 0 4 1 1 5 X 0 6 X 0 7 X 1

VERILOG CODE FOR SISO SHIFT REGISTER module siso(so,clk,rst,si); input clk, rst, si; output so; reg so; reg [23:0] temp; always @ posedge(clk) then begin if rst=.1. then begin temp[20:17]<=4.b0000; end else begin temp[20:17]<=temp[19:17] & si; end end end so<= temp[20] endmodule VHDL CODE FOR SISO SHIFT REGISTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is port(clk : in std_logic; rst : in std_logic; si : in std_logic; s o : out std_logic); end siso; architecture behavioral of siso is signal temp : std_logic_vector(3 downto 0); begin process(clk,rst); begin if rising_edge(clk) then if rst=.1. then temp<= (others=>.0.); else temp <=temp(2 downto 0) & si; end if; end if; end process; so<= temp(3); end behavioral;

SERIAL IN PARALLEL OUT TRUTH TABLE CLK DATA OUTPUT QA QB QC QD 1 1 1 0 0 0 2 0 0 1 0 0 3 0 0 0 1 1 4 1

1 0 0 1

VERILOG CODE FOR SIPO module shiftreg(clk,rst,si,po); input clk; input rst; input si; output [3:0] po; wire [3:0] po; reg [3:0] _reg_; initial begin : process_2 _reg_=4.b0000; end assign po = _reg_; always @(posedge clk) begin : process_1 if (clk === 1.b1) begin if (rst === 1.b0)

begin _reg_<=4.b0000; end else begin _reg_<= {_reg_[2:0], si }; end end end end module VHDL CODE FOR SIPO library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is port(clk : in std_logic; rst : in std_logic; si : in std_logic; p o : out std_logic_vector(3 downto 0)); end sipo; architecture behavioral of sipo is signal temp : std_logic_vector(3 downto 0); signal sig : std_logic_vector(29 downto 0); begin po<=temp(3 downto 0); process(clk,rst); begin if rising_edge(clk) then if rst=.1. then temp <= (others=>.0.); else sig<=sig+1; case sig(20 downto 19) is when 00 => temp(0) <= temp(1); when 01 => temp(1) <= temp(2); when 10 => temp(2) <= temp(3); when 11 => temp(3) <= si; when others => null; end case; end if; end if; end process; end behavioral;

PARALLEL IN SERIAL OUT MANUAL MODE PARALLEL IN SERIAL OUT PARALLEL IN SERIAL OUT USING NAND GATE

TRUTH TABLE: CLK Q3 Q2 Q1 Q0 O/P 0 1 0 0 1 1 1 0 0 0 0 0 2 0 0 0 0 0 3 0 0 0

0 1

VERILOG CODE FOR PISO module piso(clk, rst, pi, so); input clk, rst; input [3:0]pi; output so; reg so; reg [29:0]temp; reg [29:0] sig; always @ (posedge clk) begin if(rst==1.b0; end else begin temp[20:17]<=pi[3:0]; sig<=sig+1; case (sig[20:19]) 2.b00: begin so<=temp[17]; end 2.b01: begin so<=temp[18]; end 2.b10: begin so<=temp[19]; end 2.b11: begin so<=temp[20]; end default endcase end end endmodule

VHDL CODE FOR PISO library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is port(clk : in std_logic; rst : in std_logic; pi : in std_logic_ve ctor(3 downto 0); so : out std_logic); end piso; architecture behavioral of piso is signal temp : std_logic_vector(3 downto 0); signal sig : std_logic_vector(29 downto 0); begin process(clk,rst) begin if rising_edge(clk) then if rst = 1. then temp <= (others=>.0.); else temp(3 downto 0) <= pi(3 downto 0); end if; sig<=sig+1; case sig(25 downto 22) is when 0000 => so <= temp(0); when 0100 => so <= temp(1); when 1000 => so <= temp(2); when 1100 => so <= temp(3); when others => null; end case; end if; end process; end behavioral;

PARALLEL IN PARALLEL OUT TRUTH TABLE CLK DATA INPUT OUTPUT DA DB DC DD QA QB QC QD 1 1 0 0 1 1 0 0 1 2 1 0 1 0 1 0 1

VERILOG CODE FOR PIPO module pipo(po, clk, rst, pi); input clk; input rst; input pi[3:0]; output po[3:0]; reg[3:0]po; reg[29:0]temp; always@ posedge(clk) begin if rst==1b.0 begin temp[20:17]<=4b.0000; end else begin temp[20:17]<=pi[3:0]; end end end po[3:0]<=temp[20:17]; endmodule

VHDL CODE FOR PIPO library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pipo is port(clk : in std_logic; rst : in std_logic; pi : in std_logic_ve ctor(3 downto 0); po : out std_logic_vector(3 downto 0)); end pipo; architecture behavioral of pipo is signal temp : std_logic_vector(29 downto 0); begin process(clk,rst); begin if rising_edge(clk) then if rst=.1. then temp(20 downto 17) <= (others => 0.); else temp(20 downto 17) <= pi(3 downto 0); end if; end if; end process; po <= temp(20 downto 17); end behavioral; RESULT VIVA QUESTIONS 1. What is race around condition? How it is avoided?

2. Derive the characteristic equation of a D flip flop?

3. Derive the characteristic equation of a T flip flop?

4. Distinguish between combinational and sequential logic circuits:

5. Derive the characteristic equation of a SR flip flop?

6. Derive the characteristic equation of a JK flip flop?

7. What is meant by the term edge triggered?

8. What is the difference between synchronous and asynchronous logic circuits?

9. Draw the state diagram of a JK flip flop:

10. How will you convert a JK flip into a D flip flop?