IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

3, MARCH 2012 1295

A Low Cost Flyback CCM Inverter for AC
Module Application
Yanlin Li, Student Member, IEEE, and Ramesh Oruganti, Senior Member, IEEE
AbstractThe unfolding-type yback inverter operating in dis-
continuous conduction mode (DCM) is popular as a low-cost solu-
tion for a photovoltaic (PV) ac module application. This paper aims
to improve the efciency by using a scheme based on continuous
conduction mode (CCM) for this application. Design issues, both
for the power scheme and the control scheme, are identied and
trade-offs investigated. An open-loop control of the secondary cur-
rent, based on feedback control of the primary current, is proposed
in order to bypass the difculties posed by the moving right half
plane zero in the duty cycle to secondary current transfer function.
The results presented show an improvement of 8% in California
efciency compared to the benchmark DCM scheme for a 200-W
PV module application. The output power quality at rated power
level is capable of meeting IEC61727 requirements. The stability of
the yback inverter in CCM has been veried at selected working
conditions.
Index TermsCurrent control, distributed power generation,
inverters, power quality, power system stability, solar energy.
I. INTRODUCTION
N
OWADAYS, distributed power generation in residential
areas, using solar panels, is well accepted and also sup-
ported by recent developments in building integrated photo-
voltaic (BIPV) systems as well as microgrid systems. However,
when PV panels are connected in series to feed a string inverter
with a global maximum power point tracker (MPPT), a consid-
erable power loss due to modular mismatches caused by both
varying panel orientations and shading would occur [1].
A major approach to solve this issue has been to package
the PV panel with a module-integrated inverter, called an ac
module [2], which directly serves the grid. Though requiring a
large number of dcac conversion stages, the approach allows
for easy plug and play system expansion. Also, only ac cable
wiring is needed, which simplies the installation.
The acceptability of an ac module depends on its efciency,
cost effectiveness, and reliability. Three major trends are noted
Manuscript received January 16, 2011; revised May 27, 2011; accepted July
17, 2011. Date of current version February 7, 2012. This paper, composed of
the work with further analysis and experimental results, was presented in part in
conference papers AFlyback-CCMInverter Scheme for Photovoltaic ACMod-
ule Application, at Australasian Universities Power Engineering Conference
(AUPEC 2008, pp. 16) and A Low-Cost High Efciency Inverter for Pho-
tovoltaic AC Module Application, at the 35th IEEE Photovoltaic Specialists
Conference (PVSC35, 2010, pp. 28532858). Recommended for publication by
Associate Editor R.-L. Lin.
The authors are with the Power Electronics Laboratory, Department of Elec-
trical and Computer Engineering, National University of Singapore, Singapore
117576, Singapore (e-mail: [email protected]; [email protected]).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPEL.2011.2164941
in the study of inverter topologies for this application. The rst
is the use of a transformerless inverter [3][8] that is motivated
by the benets of reduction in size and cost and also by pos-
sible efciency improvement [3]. However, the limited voltage
boosting capability of such an inverter unit prevents the use of
this technology in universal grid voltage range (85265 V ac)
applications.
Another trend is focused on an isolated cascaded scheme that
includes one or more dc voltage boosting stage and a conven-
tional full bridge PWM inverter [9], [10]. This type of inverter
has by far the highest reported efciencies compared to other
isolated inverters. Also, the electrolytic capacitor for power de-
coupling can be replaced by a higher voltage lm capacitor with
longer lifetime. However, the penalty paid for this approach is
more component count and hence higher cost.
Considerations of reducing the cost have led to a third ap-
proach based on an unfolding type inverter. Here, the voltage
boosting, isolation, and output current shaping are all performed
by a dcdc converter that is then followed by a low-frequency
unfolding stage. A yback inverter with center-tapped sec-
ondary windings is often adopted leading to a simple overall
system [11]. However, in this scheme, the yback is operated
in the discontinuous conduction mode (DCM) resulting in high
current stress and lower efciencies. This is particularly true
in low voltage and high-current applications such as the ac
module under consideration. Aware of this limitation of the y-
back DCM scheme at larger power levels, Ji et al. [12] and
Kyritsis et al. [13] have studied the yback inverter operating in
a dual switching mode between DCM and boundary conduction
mode (BCM).
When operated in continuous conduction mode (CCM), a
yback converter has lower peak currents and hence higher ef-
ciencies. This has been exploited before in both dc/dc power
conversion and ac/dc power factor (PF) correction applications.
However, the control to output current transfer function in a y-
back CCM converter has a right half plane (RHP) zero, which
causes difculty in controlling the output current of the con-
verter effectively. This may have prevented the use of the y-
back CCM converter in dc/ac inverter applications. Therefore,
in our approach, we investigate the feasibility of a yback in-
verter operating (mainly) in CCM mode as a grid-connected ac
module inverter, with a view to demonstrating that a signicant
efciency improvement can be realized without adding to the
complexity of both the power and control circuits.
In the industry, efciency gures weighted over a range of
operating conditions (California efciency [14] or European ef-
ciency [1]) are used to characterize the inverter performance.
Additional techniques are usually used to improve this gure
0885-8993/$26.00 2011 IEEE
1296 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Fig. 1. Circuit topology of yback inverter.
over what can be obtained with a straightforward power con-
verter topology. Our approach is not targeted at these weighted
efciency (California or European) improvement technologies,
but at the efciency improvement due to change in the basic
operating mode of the yback inverter itself. In order to provide
a fair comparison, the designs of the power topology for both
the proposed CCMapproach and the DCM-only approach (used
as a benchmark) are presented and compared in Section II. The
control challenges faced in this application and ways of resolv-
ing them are discussed in Section III. An open-loop control of
the secondary side current, based on the feedback control of the
primary side current, is proposed in order to bypass the dif-
culties posed by the moving RHP zero in the transfer function.
The control modeling and design are covered in Section IV. The
experimental results are presented in Section V. The pros and
cons of the proposed scheme, including the well-known life-
time issue related to large electrolytic capacitor, are discussed
in Section VI.
II. FLYBACK CCM INVERTERSTEADY-STATE ANALYSIS
The topology is the same as that used in a yback ac module
operating in DCM [11] and consists of an input capacitorC
pv
, a
yback dc/dc converter with two secondary windings together
with a waveformunfolding arrangement, and an LCoutput lter
(see Fig. 1). The secondary side switches S1 and S2 are turned
ON and OFF, respectively, during the positive and negative
half cycles to generate the ac output. In each half cycle, the
inverter works as a dc to dc yback converter with the average
output current (i
sec1
or i
sec2
) shaped as a half sinusoid at the line
frequency. Though the inverter is designed to operate in CCM
under full load conditions, it is inevitable that it would enter the
DCM region around the zero crossing instants of the line cycle
or at low solar irradiation levels.
A. Quasi-Steady-State Analysis
As the operating condition of the inverter changes slowly
during an ac period compared to a switching period, the inverter
can be assumed to operate in quasi-steady state around each
instant of an ac cycle. It is also assumed that capacitor C
pv
is
large so that the input voltage V
pv
is nearly constant in an ac
cycle.
Unlike in DCM operation, the transformer core will not be
fully demagnetized in CCM operation in each switching cycle.
This causes the transformer core to serve as an energy buffer,
adding to the order of the system. However, our earlier investi-
gations [15] have shown that the effect of this incomplete core
demagnetization on the inputoutput energy balance in each
switching cycle is very small and can be neglected. Assum-
ing lossless operation, the power balance equations under both
DCM and CCM conditions can be written as
V
pv
I
pv
= V
rms
I
rms
(1)
I
pri
V
pv
= I
g
V
g
= 2V
rms
I
rms
sin
2
(t) (2)
where V
pv
,I
pv
= the dc values of the PV module voltage and
current, V
rms
, I
rms
= the RMS values of the grid voltage and
current, I
pri
= the quasi-steady-state value of the primary side
current averaged over a switching cycle, I
g
,V
g
= the quasi-
steady values of the grid current and voltage assumed to be
constant in one switching cycle, and = the angular frequency
of the ac supply.
Equation (1) is based on the power balance over an ac cycle,
while (2) is based on the power balance in each switching cycle.
The mismatch between the dc output power of the PVmodule as
in (1) and the pulsating input power of yback inverter indicated
by (2) is handled by the input capacitor C
pv
, as shown in Fig. 1.
Based on converter operating waveforms, the primary side
average current I
pri
can be shown to be
I
pri
=
D
2
DCM
V
pv
2L
m
f
s
. (3)
Here, D
DCM
is the duty cycle in DCMoperation and f
s
is the
switching frequency. Also, L
m
is the primary side magnetizing
inductance of the transformer. By substituting (1) and (3) into
(2), the duty ratio of the inverter in DCM is obtained [16]
D
DCM
= 2

I
pv
L
m
f
V
pv
|sin(t)| = D
amp
|sin(t)| . (4)
Equation (4) shows that in DCM, the duty cycle varies accord-
ing to the (rectied) grid voltage, while its amplitude (D
amp
)
is determined by the ratio of V
pv
byI
pv
. In this case, a simple
open-loop scheme without current feedback can be adopted. By
varying D
amp
, the ratio of V
pv
over I
pv
can be varied in or-
der to seek and operate the system at maximum power point
(MPP) [11].
When operated in CCM, by assuming quasi-steady-state oper-
ation and using inductor voltseconds balance over a switching
period, the duty ratioD
CCM
can be obtained
D
CCM
=
|V
g
|
(nV
pv
+|V
g
|)
. (5)
Here, the duty cycle does not directly determine the current
and hence power level. Therefore, a closed-loop current control
is necessary in this case.
The peak duty cycle values (denoted by the symbol) in an
ac period occur at the ac peak instants in both cases and can be
written as

D
DCM
= D
amp
= 2

I
pv
L
m
f
s
V
pv
(6)

D
CCM
=

2V
rms
(nV
pv
+

2V
rms
)
. (7)
LI AND ORUGANTI: A LOW COST FLYBACK CCM INVERTER FOR AC MODULE APPLICATION 1297
Fig. 2. Design aid diagramof yback inverter for V
rms
= 230 V. (The numbers
on the lines indicate the peak duty ratios.)
TABLE I
WORST-CASE CURRENT AND VOLTAGE STRESSES
The design condition for the peak duty cycle to occur at the
DCM/CCM boundary operation can be derived by equating (6)
and (7)
I
pv
L
mc
f
s
=
V
pv
4
_
nV
pv
/
_
2V
rms
_
+ 1

2
. (8)
Here, L
mc
is the critical inductance above which the operation
is in the CCM mode.
Equations (6)(8) relate the peak control variable

D, the PV
module specications V
pv
, I
pv
, and the design parameters of the
inverter, viz., n, L
m
, and f
s
, under both DCM and CCM condi-
tions. A design aid diagram is shown in Fig. 2 for an assumed
grid voltage of 230 V
rms
and for two assumed values of the turns
ratio n ( = 10 and 4). For the assumed V
rms
and n values, every
point on the graph in Fig. 2 represents a possible inverter design.
For example, n =10, I
pv
L
m
f
s
= 3, and V
pv
= 22 V represents
a CCM design with

D = 0.6. The curves marked as boundary
represent the boundary between CCM design and DCM-only
design for the two n values assumed. The choice of

D inu-
ences the component current stresses, as will be discussed in the
following sections.
B. Component Stresses
The worst-case current and voltage stresses in the inverter
circuit can be obtained (see Table I) froma basic circuit analysis.
For a DCM-only design, as shown in (9), the peak primary
current depends on the input powerI
pv
V
pv
, f
s
, and L
m
values
and not on n. A larger L
m
, but less than L
mc
, would reduce
the primary side current. For a CCM design, the peak current
stress is related to both n and L
m
values (10). The primary side
peak current has the same value as the peak value of the net
transformer magnetizing current (primary side and secondary
side combined) reected on to the primary. In (10), the rst
term is the average value of the net magnetizing current, while
the second term is half of the peak-to-peak ripple in the net
magnetizing current. A larger n value would lead to a higher
average net magnetizing current (rst term) while at the same
time reducing the current ripple (second term). As the average
magnetizing current is larger than the current ripple in CCM
operation, in general, a smaller n value is preferable to reduce
the primary side current stress.
Smaller turns ratio would also require a larger peak duty
ratio (7). As a result, the diode voltage stress is reduced as well
(13) so that a diode with a smaller forward voltage drop can
be chosen. However, the secondary side current stress increases
(11). The MOSFET voltage stress also increases (12) requiring
a MOSFET with larger on resistance (for the same die size).
Thus, the trade-off between the current and voltage stresses of
devices on both sides of the transformer determines n. Since
in grid-connected ac module application, the input current and
output voltage are large, the primary side current stress and
output side voltage stress are more crucial. Therefore, a small n
is generally preferred.
C. Suggested Design Steps
Step 1: Identify PV panel specications. The voltage V
pv
and
current I
pv
values given by the manufacturer cor-
respond to MPP and vary with solar irradiance and
temperature. For design purposes, a constant V
pv
is
used, while the variation of power is considered to be
due to current change.
Step 2: Choose a switching frequency f
s
considering the
trade-off between the switching losses and the trans-
former size.
Step 3: Choose an initial transformer turns ratio n. This can
be tuned later.
Step 4: Obtain the peak duty ratio

D and L
mc
using (7) and
(8).
Step 5: Calculate voltage stresses of the primary and sec-
ondary side devices using (12)(14).
Step 6: Choose L
m
(>L
mc
) based on acceptable primary
current stress using (10). A larger L
m
reduces the
primary current stress, while increasing transformer
size.
Step 7: Calculate the secondary current stress using (10) and
(11).
Step 8: Return to steps 37 until the voltage and current
stresses are acceptable.
If the primary current stress or the secondary diode voltage
stress is too large, n can be reduced. If the secondary side
current stress or the primary side voltage stress is too large, then
n can be increased.
In our paper, a yback inverter was designed for CCM
operation for a power level of 200 W for the Kyocera
solar module KC200GT. Another yback inverter was de-
signed for DCM-only operation as a benchmark for the same
1298 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
TABLE II
DESIGN OF FLYBACK INVERTERS FOR OPERATION IN CCM AND DCM.
(SPECIFICATIONS V
pv
= 27 V, P
pv
= 0200 W, AND V
rms
= 230 V)
specications. Table II gives the design parameters of both in-
verters as well as the respective current and voltage stresses
at rated power. Magnetics ferrite cores (R material with the
lowest loss at 100

C) are selected as indicated in Table II. The

resonant frequency of the output lter is 7 kHz that ensures
adequate ltering of the switching frequency ripple component.
In Table II, as expected, the current stresses both on the primary
and the secondary sides are lower in the CCM design.
III. OUTPUT CURRENT SHAPING AND CONTROL CHALLENGES
The two basic control requirements are: MPPT capability re-
quired by the PVapplication and output current shaping required
by the grid connection. In a single-stage inverter, a dual-loop
conguration is usually adopted, wherein a fast inner control
loop tracks the line frequency waveform and a slow outer loop
ensures operation at MPP. In order to prevent distorting the out-
put ac current, the MPPT tracking speed is purposely designed
to be slower than the line frequency. The performance of the
implemented MPPT scheme in the outer loop does not, in gen-
eral, depend on the inverter and the control scheme adopted.
Therefore, it is not discussed in this paper. The challenges of
the inverter control for the proposed yback CCM scheme lie
in the output current shaping and these are addressed in detail
in this paper.
The rst challenge is due to the wide-ranging operating con-
ditions of the inverter. Although designed to operate in CCM
at rated power level, the inverter, in reality, would operate in
a combined CCM/DCM mode, slipping into DCM operation
around the zero-crossing instants of the ac cycle. Moreover,
the large variation in the PV panel power would make the
Fig. 3. Proposed indirect control of yback CCMinverter. (a) Block schematic
diagram (G
c
(s) includes the current sensing scale factor k
i
, controller, and
PWM gain 1/V
m
). (b) Detailed schematic diagram.
combined DCM/CCM operation even more complex. For in-
stance, complete operation in DCM region alone can take place
at low irradiation/power levels.
Another difculty arises in CCM operation due to the non-
minimum phase nature of the yback inverter, which shows up
as an RHP zero in the linearized small-signal control to output
current transfer function. This would greatly limit the achiev-
able system bandwidth (BW). As indicated earlier, the system
operating point varies widely; this would result in large changes
in the RHP zero location. A controller designed to accommo-
date the worst-case (minimum) RHP zero, which occurs at the
peak of ac voltage under maximum load, was found to result
in unacceptably low BW (even lower than 100 Hz) when the
operation changes to DCM at low instantaneous ac voltages.
Thus, the widely varying RHP zero in CCM operation results
in poor tracking performance in the DCM operating zone, and
hence, unacceptable output power quality.
In our approach [see Fig. 3(a) and (b)], this problemis avoided
by sensing and controlling the primary switch current directly
rather than the output current. In Fig. 3(b), the primary current
reference signals (v
iref
) magnitude is determined by an external
MPPT scheme and its shape is determined by the sensed instan-
taneous grid voltage by assuming inputoutput power balance
based on (2) in each switching cycle. As a result, the output
current is controlled in an open-loop manner. The effect of the
RHP zero is felt, in this case, only in the uncontrolled dynamics
relating the output current to the input current.
We had applied earlier one-cycle control (OCC), which is a
fast and large-signal nonlinear control method, for the control of
the primary current in this application [15]. However, the scheme
was found to suffer from bifurcation problems at low-power
levels. In this paper, a simple average current mode (ACM)
control [see Fig. 3(b)] has been adopted for the primary current
control loop.
IV. CONTROL STABILITY AND DESIGN
Although the PV yback inverter is a time-varying nonlinear
system, it is simplied as a time-invariant linear system by
treating it to be in quasi-steady state around each instant of the
LI AND ORUGANTI: A LOW COST FLYBACK CCM INVERTER FOR AC MODULE APPLICATION 1299
ac cycle. This is justied due to the relatively slower variation of
the ac waveform in comparison to the switching frequency [17].
Due to the variations in output power and instantaneous grid
voltage, a set of transfer functions is needed to model all possible
operating conditions. The controller design must ensure that the
current tracking performance is good and the closed-loop system
is stable under all the different conditions.
A. Small-Signal Modeling of Flyback Inverter
The inverter operation is assumed to be ideal and lossless for
now in the modeling. This will be reconsidered in Section V
while reviewing the experimental results. For a given power
levelP
pv
, the boundary grid voltage V
gb
at which DCM/CCM
transition occurs can be obtained by equating (4) and (5)
V
gb
= V
pv
_
V
rms

1
2P
pv
f
s
L
m
n
_
. (15)
When |V
g
| < V
gb
, the inverter works in DCMand the control-
to-primary current transfer function can be shown to be
G
id DCM
=
|V
g
|
V
rms

2P
pv
L
m
f
s
. (16)
The transfer function is a simple gain that tends toward zero
as the instantaneous grid voltage V
g
goes toward zero.
When |V
g
| > V
gb
, the operation is in CCM and the control-
to-primary current transfer function can be shown to be
G
id CCM
=
|V
g
|
nsL
m
_
1
s
s
z
_
(17)
where
s
z
=
V
2
rms
V
pv
P
pv
nL
m
(|V
g
| + nV
pv
)
. (18)
This transfer function has a pole at origin followed by a
varying left half plane (LHP) zero.
Fig. 4(a) explores the low-frequency gain (gain at 2f
ac
=
100 Hz) and LHP zero variations over half ac cycle at four
different power levels. It is observed that the gain at 100 Hz in
CCM mode is only related to grid voltage, while the LHP zero
varies with both power and grid voltage. Compared to the DCM
case, yback converter in CCM operation has much larger gains
at 100 Hz at the cost of a smaller phase at lower frequencies.
Due to these differences, the design of a single controller to
accommodate both operating modes requires a careful trade-off
between tracking performance in DCM operation and stability
in CCM operation.
In order to simplify the controller design process, a few crit-
ical plant operating conditions are chosen as reference condi-
tions. In CCM operation, at the transition between DCM and
CCM modes, the smallest 100-Hz gain and the largest LHP
zero [see Fig. 4(a)] occur together. When the power level re-
duces, both the gain at 100 Hz and the LHP zero reduce at
the CCM/DCM transition instant, introducing a series of such
worst-case operating points. Of these cases, the ones under the
maximum and minimum power levels are used as the plant ref-
erences [curves A and B in Fig. 4(b)]. All the other boundary
Fig. 4. Variation of plant transfer function with grid voltage and power level.
(a) Variation of low-frequency gain (at 2f
ac
= 100 Hz) and LHP zero with
power level over ac half period (1) 100%, (2) 75%, (3) 50%, and (4) 25%
(DCM-only with no LHP zero) of rated power P
r
(200 W). (b) Plant references
(A: worst case in CCM at P
c
; B: worst case in CCM at P
r
; C: DCM at
P
r
and V
g
= 10 V).
operating cases at other power levels are within the range de-
ned by these two curves. The minimum power level for CCM
operation is given by
P
c
=
1
2L
m
f
s

1
_
n/V
rms
+

2
_
V
pv
_
2
. (19)
In DCM case, the performance [here, gain as given by (16)]
becomes poorer as the grid voltage V
g
reduces and also as the
power level P
pv
decreases. There is, in fact, no way to com-
pensate for this fully. In our design, operation at full power
with a small grid voltage of 10 V is considered as a reference
case, as shown in curve C of Fig. 4(b). Though the tracking
performance will be poorer at lower voltages and lower power,
the main aim is to keep the resulting overall current distortion
within acceptable limits at rated power.
B. Design of Controller
A type II compensator given by (20) is chosen for the design
G
C
=
k
s

s + z
s + p
. (20)
This controller (curves G
C1
and G
C2
in Fig. 5) is es-
sentially a PI controller together with a single-pole lter for the
averaging of the current waveform. The integrator increases the
1300 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Fig. 5. Illustration of controller design (k/s, G
C 1
, and G
C 2
with different
pole values) and their open-loop Bode plots (G
1
and G
2
for plant reference
B).
low-frequency gain and the system BW in DCM (curve C
in Fig. 4). However, as indicated by curves A and B in
Fig. 4, a pole already exists at origin for the yback in CCM
mode. Together with the controllers integrator, this creates a
total phase change of 180

in the open-loop response at low

frequencies. Therefore, in order to provide an adequate phase
margin at crossover frequency in CCM, the zero is needed in the
compensator, followed by a pole for ltering the high-frequency
switching components.
C. Design Procedure
The controller is rst designed to ensure the stability in CCM;
its performance in DCMis then veried. Also, in Fig. 5, the poles
p
1
and p
2
have been located so as to make the design ideas
visually clearer; they do not correspond to the actual designed
controller.
1) Choice of k: A high k value (see Fig. 5) is desired to en-
sure a high gain at twice the line frequency (2f
ac
) and wide BW,
especially in DCM operation. However, to prevent bifurcation,
the compensator output v
comp
in Fig. 3(b) needs to intersect the
ramp signal v
ramp
once every switching cycle. To ensure this
for the primary current control of yback converter, the upslope
of v
comp
( =k V
m
I
pri
) must be smaller than the upslope of
v
ramp
( = V
m
/T
s
) [18]. Therefore, this limit can be expressed
as
k <
f
s
I
pri
. (21)
Equation (21) provides an upper limit for k depending on the
maximum value of I
pri
, which occurs at the peak grid voltage
and full power. A margin should be provided in the value of k to
account for parameter variations. A second upper limit on k is
imposed so as to keep the largest loop BW to be less thanf
s
/2,
as required by sampling theory. In practice, the largest BW is
made even less (say, less thanf
s
/4)
2) Choice of k: With the choice of k value, the curve k/s
is xed. The zero is then placed at the worst-case crossover
frequency of the loop response, assuming a controller of k/s
only, so as to achieve a 45

phase margin.
TABLE III
PERFORMANCE OF THE DESIGNED SYSTEM AT SEVERAL KEY
OPERATION CONDITIONS
3) Choice of p: Fig. 5 shows two controllers (G
C1
and
G
C2
) with the same zero (z
1
= z
2
) but different pole values
(p
1
< p
2
); it also shows the corresponding open-loop Bode plots
(G1 and G2) based on plant B (see Fig. 4). First, it may
be noted that the maximum gain at 2f
ac
is limited by the curve
k/s. A larger pole p
2
reduces the controller gain at 2f
ac
(see
curve G
C2
) and the loop BW (see curve G
2
). Although
a large pole value causes a larger phase bump (G
2
versus
G
1
), this does not necessarily lead to a larger phase margin
(PM
1
> PM
2
). Also, the pole should be sufciently small (say,
less than f
s
/5) in order to lter out the switching components.
On the other hand, if the pole is too close to the zero, it will
deteriorate the phase boost provided by the zero. In our design,
the pole p is at 16 kHz, which is sufciently low to lter the
switching components, while at the same time, ensure a phase
margin of 29

at the boundary conduction condition under the

rated power (see Table III).
The designed controller for the yback CCM inverter is
G
C
=
5000
s

s + 5 10
4
s + 10
5
. (22)
The controller in (22) can be implemented by the com-
pensation circuit in Fig. 3(b), where k
i
= 0.47, V
m
= 3 V,
R
i
= 3.9 k, R
f
= 2.2 k, and C
f z
= C
f p
= 8.6 nF.
The performance of the controller in (22) has been analyti-
cally veried at a few quasi-steady-state operating points (see
Table III). Here, P
r
is the rated power and P
c
is the critical
power given by (19). Voltage V
gb
refers to the grid voltage at the
CCM/DCM boundary operation. The largest loop BW, which
occurs at rated power and maximum grid voltage, is below f
s
/4
as discussed before. The phase margins show the system to be
stable in all the cases considered. The BW and the 2f
ac
gain are
both generally high in CCM and DCM at higher voltages. Even
at a low grid voltage of 10 V in DCM operation, the system has
a reasonable BW and 2f
ac
gain.
V. IMPLEMENTATION AND EXPERIMENTAL RESULTS
Two experimental inverters, one based on the proposed
scheme and the other on the benchmark yback DCM inverter
scheme [11], have been built for a Kyoceras 200-W PV module
(KC200GT). Based on (4), the duty cycle of the yback DCM
inverter is directly controlled to follow the rectied grid voltage
that results in the output current tracking the sinusoidal grid
waveform automatically in an open-loop manner. The circuit
parameters (see Fig. 1) and the operating conditions are listed
LI AND ORUGANTI: A LOW COST FLYBACK CCM INVERTER FOR AC MODULE APPLICATION 1301
Fig. 6. PV side and grid side waveforms with V
pv
= 27 V and P
pv
= 200 W.
(a) DCM scheme. (b) Proposed CCMACM scheme.
in Table II. Both schemes were tested at a xed input voltage of
27 V and under different input power levels according to [14].
In order to sense the current accurately, a current transformer
(CT)-based technique proposed in [19] was adopted and modi-
ed for the ac application. Here, the primary side current wave-
shape is reconstructed on the CT secondary side by restoring
the dc component (and any line-frequency-related component)
removed by the CT operation.
A. Steady-State Operation
Fig. 6 shows the input and output waveforms of the proposed
yback CCM scheme and also the benchmark scheme at rated
power. As expected, the peak primary current stress in the CCM
scheme (25 A) is around half of that in the DCMscheme (48 A),
which agrees with the calculated values in Table II.
In Fig. 6, distortion of current waveforms (i
g
) in both DCM-
only and CCM schemes may be noted around the zero-crossing
intervals. This is partly caused by a dead time (a) when the
ac current goes through zero and the secondary side operation
switches from S1 to S2 and vice versa. Another reason is due to
the inability of the pulsewidth modulation (PWM) IC (SG3524
here) to reach very low duty cycle values. Besides, in CCM,
because of the tracking delay of the controller as well as the
incomplete demagnetization of the yback transformer, the sec-
ondary side current in Fig. 6(b) does not fall to zero during
switching between S1 and S2, which makes the output current
experience a sudden change, thereby causing oscillation (b) at
the output lter resonant frequency.
Additionally, when the operation switches between DCMand
CCM, the tracking capability of the controller changes, which
is reected as a distortion (c) in the output current waveform i
g
.
Fig. 7. Efciency versus normalized power (referred to rated power of
200 W) for the DCM and CCM scheme.
Fig. 8. Open-loop Bode plots verication at P
r
(200 W) and V
gb
(112 V);
R
w
= 0.25 in Theo-2.
At rated power, the total harmonic distortion (THD) is 4.1%
for the DCM scheme and 4.4% for the CCM scheme, while the
PF is 0.995 and 0.991, respectively. Both the schemes satisfy
the requirements of IEC61727 [20] in this regard.
Fig. 7 shows the marked improvement in the efciency
achieved with the proposed CCM scheme over the benchmark
DCM scheme. The weighted efciencies for the solar powered
inverter, i.e., European efciency and California efciency [14],
were found to be 86.3% and 87.4%, respectively for the CCM
scheme and 79.4% and 79.4% for the DCM scheme. Thus,
the proposed CCM approach results in signicantly higher ef-
ciencies while still maintaining output current distortion within
limits.
B. Stability and Tracking Performance
The low-current THD (<5% as required) veries that the
scheme has satisfactory tracking performance. The current
waveform in Fig. 8 also visually shows that the tracking perfor-
mance is reasonable and the system is stable in all the quasi-
steady-state operating points.
It must be noted that the stability of the yback inverter in
DCM is not an issue when the system is already stable in CCM,
as the open-loop phase margin in DCM of 90

is larger than that

of the CCM case (refer to Figs. 4(b) and 5). The stability test of
the inverter under CCM operation was carried out by measuring
the open-loop gain under several dc to dc operating conditions
(input voltage, output voltage, and current). These conditions
were set to correspond to different quasi-steady-state conditions
at different power levels. However, the Bode plots of the inverter
corresponding to instantaneous power transfer above the rated
1302 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
power, e.g., V
g
> 2V
rms
at P
r
, could not be measured due to the
higher power burden involved.
One of these test results is shown in Fig. 8, which compares
the theoretical and experimental open-loop Bode plots of the
system in CCM operation near the boundary conduction condi-
tion at rated power.
In Fig. 8, the theoretical modeling given by (17)(18) (Theo-
1) and the experimental results show important differences. The
pole at origin has shifted, instead, to a low frequency, which
is attributed to the presence of the primary winding resistance
R
w
of the yback transformer. Also, the inuence of the output
lter causes a notch around the resonant frequency of 7 kHz.
The modied theoretical model (Theo-2) after inclusion of these
effects can be shown to be
1
G
id2 CCM
=
s
3
L
f
C
f
L
m
I
Lm
+ s
2
L
f
C
f
k
a
+ sI
Lm
_
L
f
(1 D)/n
2
+ L
m
_
+k
a
s
3
L
f
C
f
L
m
+ s
2
L
f
C
f
R
w
+ s
_
L
f
(1 D)
2
/n
2
+ L
m
_
+R
w
(23)
where k
a
= V
g
/n + R
w
I
Lm
and I
Lm
= I
pri
+ nI
g
is the y-
back transformer magnetizing current at a certain quasi-steady
state. The value of R
w
was measured to be 0.25 .
The plot of Theo-2 agrees better with the experimental
results. As the lter resonant frequency is very close to the
crossover frequency, multiple gain crossovers occur both in
Theo-2 and the test curve. The experimental BW of the loop
gain (the rst crossover) is 6050 Hz, close to the estimated
6650 Hz BW, while the smaller of the two phase margins is 47

(during the rst crossover), which is higher than the estimated

value of 38.3

using Theo-2.
In addition, the frequency response tests have also been car-
ried out at selected power levels over the set of worst-case
conditions dened in Fig. 4(b) (between P
c
and P
r
). Here also,
the experimental results conrm the theoretical modeling and
stability of the system.
VI. DISCUSSION OF THE PROPOSED SCHEME
Asignicant efciency improvement (8%) has been achieved
with the yback CCM approach. The resulting weighted ef-
ciency of 87.4%, though less than some industry values, still
forms a good basis for further efciency improvement. For ex-
ample, by adopting nondissipative snubber circuit, interleaving
[21], or soft switching techniques [21][23], we can expect sig-
nicant improvements in efciency at rated power level. Like-
wise, by adopting burst mode operation [24] or pulse frequency
modulation at light load, higher efciency can be achieved at
low-power levels. Through such modications, it will be possi-
ble to obtain higher overall efciencies (California efciency or
European efciency).
The higher efciency of the proposed scheme has been
achieved at the cost of higher distortion in the current waveform.
However, the current THD value is still below 5% as required
1
The authors will be happy to provide the derivation upon request to an
interested reader.
by the standards [20]. It has also been demonstrated that the
designed system is stable at varying operation conditions.
A major concern in single-stage inverters is the requirement
of a large-value input electrolytic capacitor that generally has a
short lifetime [1] due to the high operating temperature of the ac
module behind the PV module exposed to the sun. The problem
exists in both the popular DCM scheme and the proposed CCM
scheme.
By proper thermal design, it is possible to extend the lifetime
of the capacitor signicantly. For example, in [25], four 2200-
mF electrolytic capacitors with a rated lifetime of 8000 h at 105

C are used in parallel. According to [25], by ensuring the core

capacitor temperature to be below 65

C in the inverter design,
a capacitor lifetime of 30 years can be realized.
Alternatively, a power decoupling circuit [26][28], such as
the active lter in [28], can be added to lessen the impact due to
the large electrolytic capacitor. The addition of the power decou-
pling circuit can be expected to reduce the efciency somewhat.
VII. CONCLUSION
This paper has proposed and demonstrated that the yback
CCM scheme can be a viable solution for medium-power ac
module application. Design issues, both for the power scheme
and the control scheme, have been identied and trade-offs in-
vestigated. The results presented showan improvement of 8%in
California efciency compared to the benchmark DCM scheme
for a 200-W PV module application. The output power quality
at rated power level is satisfactory and is capable of meeting
IEC61727 [20] requirements. The stability of the yback in-
verter in CCM has been veried at selected working conditions.
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10.
Yanlin Li (S08) received the B.E. degree from the
University of Electronic Science and Technology of
China (UESTC), Chengdu, China, in 2005. She is cur-
rently working toward the Ph.D. degree at the Power
Electronics Laboratory, Department of Electrical and
Computer Engineering, National University of Sin-
gapore, Singapore, Singapore.
Her current research interests include the model-
ing, analysis and control of power converter, applica-
tion of renewable energy, such as photovoltaic-grid-
connected inverter, etc.
Ramesh Oruganti (S83M85SM01) received
the B.Tech. and M.Tech. degrees fromIndian Institute
of Technology, Madras, India, and the Ph.D. degree
from Virginia Tech, Blacksburg, in 1987.
He worked for several years in India in the area of
power conversion. After being a faculty member for
more than two decades, he is currently an Adjunct
Associate Professor in the Department of Electrical
and Computer Engineering, National University of
Singapore, Singapore. He is also a freelance consul-
tant in energy systems research area. He has authored
several papers in power electronics. He holds a patent on dc-dc converters. His
current research interests include several major areas of power electronics, in-
cluding, more recently, renewable energy applications of power electronics.
Dr. Oruganti was the recipient of two prize paper awards.