Topic09 The Timer Subsystem On The Freescale MC9S12X

Topic Video 09
Timers: Father Time in a uP...
Friday, 5 November 2010
Timer
The timer section of the 9S12X is based around a 16 bit free running counter driven by the system clock. The timer system provides the following basic functions:
A Timer overow

Can be used to generate interrupts at predetermined intervals.
Up to 8 Output Compare Functions

Can be used to generate a variety of output waveforms by comparing the free running counter to programmable registers.
Up to 8 Input Compare Functions
Can be used to latch the value in the free running counter on the edges of an input signal.
A single 16 bit pulse accumulator Pulse Width Modulator
Timer Overow
One of the great features of the timer subsystem is the timer overow. The timer is a free running 16 bit counter called TCNT, it increments from $0000 to $FFFF, then overows back to $0000 and continues once more. Each time TCNT resets back to $0000, the timer can trigger a Timer Overow Interrupt (TOI). The period of the TOI can be altered by changing the rate at which the counter TCNT increments. The counter increments on each rising edge of the clock source, so changing the frequency of the clock source, through prescaling would therefore change the period between TOIs.
Timer Overow
A 2bit Example
TCNT Free Running Counter 00
Timer Overow
A 2bit Example
Timer Overow
A 2bit Example
Timer Overow
A 2bit Example
Timer Overow
A 2bit Example
TOI
Controlling the TOI
Programming the Timer Overow is done using the following registers of the Enhanced Capture Timer.
TCNTH TSCR1 TCNTL TSCR2 TFLG2
Controlling the TOI

TSCR1
TEN TSWAI TSFRZ TFFCA PRNT 0 0 0
TEN (Timer Enable)

This bit enables the Timer Subsystem 0 means subsystem is OFF 1 means subsystem is ON
TSWAI(Timer module stops while in WAIT mode)

This bit controls the behavior of the system during WAIT. 0 means subsystem is running unaffected during a WAIT. 1 means subsystem is disabled during WAIT.
Controlling the TOI

TSCR1
TSFRZ (Timer and modulus counter stop while in Freeze mode)

This bit controls the behavior of the system during FREEZE. 0 means subsystem is running unaffected during a FREEZE. 1 means subsystem is disabled during FREEZE.
TFFCA (Timer Fast Flag Clear all).

0 means that the TOF ag must be manually cleared. 1 means that any read or write to a Output/Input compare register automatically resets the TOF ag.
Controlling the TOI

TSCR1
PRNT(Precision Timer)
This bit controls the behavior of the Timer. 0 means legacy timer is enabled. 1 means precision timer is enabled.
Controlling the TOI

TSCR2
TOI 0 0 0 TCRE PR2 PR1 PR0
TOI (Timer Overow Interrupt Enable)

0 means Timer overow interrupt is disabled. 1 means Timer overow interrupt is enabled.
TCRE (Timer Counter Reset Enable).

0 means that TCNT runs normally and overows at $FFFF. 1 means that TCNT is reset when its contents equals that of TC7.
Controlling the TOI

TSCR2
TOI 0 0 0 TCRE PR2 PR1 PR0
PR2-PR0 (Timer Prescaler Select)

When PRNT is cleared, these bits select the main Timer Prescaler.
Prescale factor = 2PR[2:0]
Controlling the TOI

TFLG2
TOF 0 0 0 0 0 0 0
TOF (Timer Overow Flag)

Writing 1 to TOF resets the timer overow ag. Failure to reset this ag in the ISR will result in a continuos ring of the TOI interrupt.
Using the TOI

Since the TOI is a part of the timer subsystem, it makes sense that the timer must be enabled for it to work. The Timer Overow System is enabled by setting the msb (0x80) of the TSCR1. The remaining bits in this register are related to IOC and are not required by the TOI. The TOI is enabled by ensuring that TOI in TSCR2 is set and that TCRE is cleared. A value for PR2-PR0 needs to be chosen in order to produce the desired interrupt period. Lastly, interrupts need to be enabled (assuming an ISR has been written that resets TOF in TFLAG2).
Using the TOI

Finding a value for PR2-PR0
The value for PR is simply a prescaler on the Bus Clock (fbus) to produce the Timer Clock (ftimer). ftimer = fbus / (2PR) The Timer Clock is then used to pulse TCNT which increments on each rising clock edge. It will take 65536 clock pulses to cause TCNT to overow. So the TOI period (TOIperiod) would be TOIperiod = (2PR*65536)/fbus
Timer Overow System

BUS CLOCK TSCR1 TSCR2
TSCR2
Timer Overow System
Example

We would like to create a program to toggle the output on pin 1 of PORTA every 131ms. Firstly, we will need to calculate the value of PR.
TOIperiod = (2PR*65536)/fbus PR = log2 ( (TOIperiod*fbus)/65536 )
Assuming an 8MHz bus clock, the value for PR is

PR = log2 ( (TOIperiod*fbus)/65536 ) PR = log2 ( (0.131*8000000)/65536 ) PR = 4
Example
mainloop: MOVB #$F7,IVBR MOVB #$01,DDRA MOVB #$01,PORTA JSR Spin InitTOI: InitTOI BRA Spin MOVB #$80,TSCR1 MOVB #$84,TSCR2 CLI RTS TOI_ISR: MOVB #$80,TFLG2 ; Reset TOF Flag LDAA EORA STAA RTI PORTA #$01 PORTA ; Turn on Timer Subsystem, Fast Flag Clearing is OFF. ; Turn on TOI, TCRE is OFF and prescaler set at 4. ; Turn ON interrupts.
Example
ORG $FFDE DC.W TOI_ISR
; Set up Interrupt Vector Table ; TOI Vector
Pulse Width Modulation

Pulse width modulation is the process of encoding numbers into the width of digital pulses. With the use of a free running counter both the width and period of a digital pulse can be set using programmable registers. Pulse width modulation is an efcient means of controlling electric motors. It allows the speed of the motor to be varied without losing valuable torque.

The 9S12X has 8 PWM channels. Each PWM channel has a duty register and a period register associated with it.
DUTY PERIOD
The duty register denes the value at which the PWM channel will change its state. The period register denes the value at which the counter and channel must reset.

A 3bit Example
DUTY PERIOD
Free Running Counter 000

A 3bit Example
DUTY PERIOD

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011 011
101
Free Running Counter

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101 101
Free Running Counter

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101

A 3bit Example
DUTY PERIOD
011
101
On-Chip PWM Subsystem
The PWM Subsystem on the MC9S12XDP512 contains

Eight independent PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Programmable PWM enable/disable for each channel Software selection of PWM duty pulse polarity for each channel
On-Chip PWM Subsystem
Controlling the PWM
Interaction with the PWM subsystem is done via the following register set.
PWME PWMSCLA PWMPOL PWMSCLB PWMCLK PWMCNTx PWMPRCLK PWMDTYx PWMCAE PWMPERx PWMCTL
Controlling the PWM
PWME (PWM Enable Register)

PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
PWMEx (Pulse Width Modulation Enable)

0 means the PWM channel is disabled. 1 means the PWM channel is enabled.
Controlling the PWM
PWMPOL (PWM Polarity Register)

PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
PPOLx (Pulse Polarity)

0 means the PWM channel output starts low. 1 means the PWM channel output starts high.
Controlling the PWM

PWMCLK (PWM CLock Select Register)
PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
PCLKx (Pulse Clock Source Select)

For PCLK7, PCLK6, PCLK3, PCLK2 0 means ClockB is the clock source. 1 means ClockSB is the clock source. For PCLK5, PCLK4, PCLK1, PCLK0 0 means ClockA is the clock source. 1 means ClockSA is the clock source.
Controlling the PWM

PWMPRCLK (PWM Prescale Clock Select Register)
0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0
PCKBx (ClockB prescaler)

These three bits are used to prescale ClockB.
PCKAx (ClockA prescaler)

These three bits are used to prescale ClockA.
Controlling the PWM

PWMSCLA (PWM Scale A Register)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Prescaler for Clock SA fClockSA = Clock A / ( 2 * PWMSCLA) Note a value of $00 in PWMSCLA means 256.
Controlling the PWM

PWMSCLB (PWM Scale B Register)
Prescaler for Clock SB fClockSB = Clock B / ( 2 * PWMSCLB) Note a value of $00 in PWMSCLB means 256.
PWM Clocks
Controlling the PWM

PWMCAE (PWM Center Align Enable Register)
CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
CAEx (Center Aligned Output Mode)

0 means channel works in left-aligned mode. 1 means channel works in center-aligned mode.
Controlling the PWM

PWMCTL (PWM Control Register)
CON67 CON45 CON23 CON01 PSWAI PFREZ 0 0
CONxy (Concatenate Channels)

0 means the channels work as two seperate independent 8 bit channels. 1 means both channels work as a single 16 bit PWM channel, channel x provides the output channel y is unused.
PSWAI (PWM Stops in WAIT mode)

0 means PWM functions normally in WAIT mode. 1 means STOP the input clock to the PWM when in WAIT mode.
Controlling the PWM

PWMCTL (PWM Control Register)
CON67 CON45 CON23 CON01 PSWAI PFREZ 0 0
PFREZ (PWM Stops Counters in Freeze Mode)

0 allows PWM to continue normally in FREEZE mode. 1 means STOP the input clock to the PWM when in FREEZE mode.
Controlling the PWM

PWMCNTx (PWM Channel Counter Registers)
Each Channel has its own counter associated with it. These counters can be read at any time but can not be written to.
Controlling the PWM

PWMPERx (PWM Channel Period Registers)
Each Channel has its own period register associated with it. These registers can be written to at any time, but it is always a good idea to turn off the channel before modifying it.
Controlling the PWM

PWMDTYx (PWM Channel Duty Registers)
Each Channel has its own duty register associated with it. These registers can be written to at any time, but it is always a good idea to turn off the channel before modifying it.
Using the PWM
When using the PWM system there are a few questions that you need to ask about your application.

Does the application require 8 or 16 bit PWM? What clock frequency does your application require? Does the waveform need to be center-aligned? Does the output waveform need to start at 0 or 1?
Example
We have an application that requires a 10Hz waveform with a 50% duty cycle (PWMPER = 2 * PWMDTY) on PWM0.
The PWMPER in combination with clock prescalers will enable us to create a 10 Hz waveform. Assuming we used ClockA as our clock source and also assuming our bus clock was 8MHz, we could only prescale Clock A down to 62.5kHz (8MHz/ 128). Therefore we shall require the use of clock SA.
Example
The problem can be reduced mathematically to

10Hz = fbus /( 2PCKA2:0 * 2 * PWMSCLA * PWMPER0)
If we choose PCKA2:0 to be 7 and PWMSCLA to be 132 then PWMPER0 must be PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 ) PWMPER0 = 23.67 (24) PWMDTY0 = 12 (for 50%)
Example
The problem can be reduced mathematically ClockA to

Example

Example
ClockSA The problem can be reduced mathematically Prescaler to 10Hz = fbus /( 2PCKA2:0 * 2 * PWMSCLA * PWMPER0)
Example

Example
The problem can be reduced mathematically ClockSA to

Example

Example
mainloop: Spin InitPWM: JSR InitPWM BRA Spin MOVB #$00,PWME MOVB #$00,PWMPOL MOVB #$01,PWMCLK MOVB #$00,PWMCAE MOVB #$00,PWMCTL MOVB #24,PWMPER0 MOVB #12,PWMDTY0 MOVB #$01,PWME RTS ; Turn OFF PWM Channels. ; All PWM channels start low. ; Clock SA chosen for PWM0. ; All PWM channels are left-justied. ; All PWM channels are independent. ; Set the period to 24 (10Hz). ; Set the duty cycle to 12 (50%). ; Enable PWM0
MOVB #$07,PWMPRCLK ; Set ClockA prescale to /128.
MOVB #132,PWMSCLA ; Set SA clock prescaler to /132.
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Topic Video 09

Timers: Father Time in a uP...

Friday, 5 November 2010

Up to 8 Output Compare Functions

Up to 8 Input Compare Functions

A single 16 bit pulse accumulator Pulse Width Modulator

Friday, 5 November 2010

Friday, 5 November 2010

TCNT Free Running Counter 00

Friday, 5 November 2010

TCNT Free Running Counter 01

Friday, 5 November 2010

TCNT Free Running Counter 10

Friday, 5 November 2010

TCNT Free Running Counter 11

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TCNT Free Running Counter 00

Friday, 5 November 2010

Controlling the TOI

Friday, 5 November 2010

Controlling the TOI

TEN (Timer Enable)

TSWAI(Timer module stops while in WAIT mode)

Friday, 5 November 2010

Controlling the TOI

TSFRZ (Timer and modulus counter stop while in Freeze mode)

TFFCA (Timer Fast Flag Clear all).

Friday, 5 November 2010

Controlling the TOI

Friday, 5 November 2010

Controlling the TOI

TOI (Timer Overow Interrupt Enable)

TCRE (Timer Counter Reset Enable).

Friday, 5 November 2010

Controlling the TOI

PR2-PR0 (Timer Prescaler Select)

Prescale factor = 2PR[2:0]

Friday, 5 November 2010

Controlling the TOI

TOF (Timer Overow Flag)

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Using the TOI

Friday, 5 November 2010

Using the TOI

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Timer Overow System

Timer Overow System

Friday, 5 November 2010

Assuming an 8MHz bus clock, the value for PR is

Friday, 5 November 2010

Friday, 5 November 2010

ORG $FFDE DC.W TOI_ISR

; Set up Interrupt Vector Table ; TOI Vector

Friday, 5 November 2010

Pulse Width Modulation

Friday, 5 November 2010

Pulse Width Modulation

Friday, 5 November 2010

Pulse Width Modulation