C8251 Programmable Communication Interface: CAST, Inc. April 1999 - A1.3 1

C
Function Description
ST
C8251 Programmable Communication Interface
The C8251 programmable communications interface (USART) megafunction provides data formatting and control to a serial communication channel. The megafunction has select, read/write, interrupt and bus interface logic features that allow data transfers over an 8-bit bi-directional parallel data bus system. With proper formatting and error checking, the megafunction can transmit and receive serial data, supporting both synchronous and asynchronous operation.
Features
Synchronous and asynchronous operation Programmable data word length, parity and stop bits Parity, overrun and framing error checking instructions and counting loop interactions Supports up to 1.750 Mbps transmission rates Divide-by 1,-16,-64 mode False start bit deletion Automatic break detection Internal and external synch character detection Peripheral modem control functions The C8251 was developed in VHDL and synthesizes to approximately 2,300 gates depending on the technology used Functionality based on the Intel 8251A device
Symbol
RESETn CLK TX_CLK DO[7:0] RX_CLK TxD RDn TXE WRn RTSn CSn DTRn C_Dn TxRDY EXTSYNDET RxRDY DIN[7:0] SYN_BREAK CTSn DSRn RxD
CAST, Inc.
April 1999 A1.3
C8251 USART Data Sheet
Block Diagram
TX_CLK CLK C_Dn CSn RDn WRn RESETn
Block3
Chip Select & R/W Control Clock Gen. Parity Gen. Modem Control DTRn RTSn DSRn CTSn
Block4
DIN[7:0] Data Bus Buffers
Trasmit Data Register
Parallel to Serial Trasmit Control
TxD
Block2
TxE TxRDY
Control Register
EXTSYNDET RX_CLK Parity Checker RxD
Receive Control Clock Gen. Serial to Parallel
RxRDY SYN_BREAK Status Register Out Mux DO[7:0]
Block1
Receive Data Register
Figure 1: C8251 USART Block Diagram
Pin Description
Name RESET CLK TX_CLK RX_CLK RDn WRn CSn C_Dn EXTSYNDET DIN[7:0] CTSn DSRn RxD Type In In In In In In In In In In In In In Polarity Low Low Low Low High Low Low Description External reset Master clock Transmit clock Receive clock Read control Write control Chip Select Control/Data Select External synch detect Data Input Bus Clear-to -Send Data Set Ready Receive Data
CAST, Inc.
Pin Description (Continuation)

Name D0[7:0] TxD TxE RTSn DTRn TxRDY RxRDY SYN_BREAK Type Out Out Out Out Out Out Out Out Polarity Low Low Low High High Low Description Data Output Bus Transmit Data Transmitter empty Request-to-Send Data Terminal Ready Transmit ready Receiver ready Sync/Break detect
Applications
Serial data communications applications Modem interface
Functional Description
The C8251 core is partitioned into modules as shown in figure 1 and described below.
Block1
The Receiver Buffer and Control accept serial data, convert it to parallel format, check for parity, framing, overrun, break and send the formatted data to the CPU.
Block2
The Transmitter Buffer and Control logic accept parallel data from the Data Bus Buffer, convert it to serial, inserting required characters or bits depending on communication protocol, and output the formatted serial stream to the TxD output pin.
Block3
The Modem Control Logic consists of a set of inputs and outputs that can be used to interface to almost any modem .
Block4
The CPU interface shares common interface signals with the CPU: Data Bus, Read, Write, Chip selects, Reset and Master CLK.
Core Assumptions
Active-low reset input The 1 stop bit mode is not supported Separate EXTSYNDET and SYN_BREAK signals The bi-directional data bus has been split in two separate data buses: DIN and DO
CAST, Inc.
Verification Methods
The C8251 USART megafunctions functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model which contained the original Intel 8251 chip, and the results compared with the megafunctions simulation outputs.
Device Utilization & Performance

Target Device EPF6010A EPF8820A EPF10K10 EPF10K10A Speed Grade -1 -2 -3 -1 Utilization LCs EABs 533 533 533 533 Performance Fmax 19 MHz 12 MHz 16 MHz 25 MHz Availability Now Now Now Now
Deliverables
Encrypted Licenses Post-synthesis AHDL Assignment & Configuration Symbol file Include file Graphic Design file of test circuit Vectors for testing the functionality of the megafunction VHDL Source Licenses VHDL RTL source code Testbench Example testbench wrapper for post-route simulation Vectors for testbench Simulation script Synthesis script Expected results for testbench
Megafunction Modifications
The C8251 megafunction can be customized to include: 16 bit Internal Baud Rate Generator Remove either synchronous or asynchronous sections in order to reduce area Please contact CAST directly for any required modifications.
CAST, Inc.
24 White Birch Drive Pomona, New York 10907 USA Phone: +1 914-354-4945 Fax: +1 914-354-0325 E-Mail: [email protected] URL: www.cast-inc.com The C8251 megafunction is licensed from Moxsyn S.r.l. CAST, Inc. 4

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C

C8251 Programmable Communication Interface

April 1999 A1.3

C8251 USART Data Sheet

Trasmit Data Register

Parallel to Serial Trasmit Control

EXTSYNDET RX_CLK Parity Checker RxD

Receive Control Clock Gen. Serial to Parallel

RxRDY SYN_BREAK Status Register Out Mux DO[7:0]

Figure 1: C8251 USART Block Diagram

C8251 USART Data Sheet

Pin Description (Continuation)

C8251 USART Data Sheet

Device Utilization & Performance

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