74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
January 2008

Features
ICC reduced by 50% Output source/sink 24mA ACT74 has TTL-compatible inputs
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positivegoing pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and
Q HIGH
Ordering Information
Order Number
74AC74SC 74AC74SJ 74AC74MTC 74AC74PC 74ACT74SC 74ACT74SJ 74ACT74MTC 74ACT74PC
Package Number
M14A M14D MTC14 N14A M14A M14D MTC14 N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard.
1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2
Description
Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
Truth Table
(Each Half)
Inputs SD
L H L H H H
Outputs CP
X X X
CD
H L L H H H
D
X X X H L
Q
H L H H L Q0
Q
L H H L H Q0
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock
www.fairchildsemi.com 2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC IIK Supply Voltage DC Input Diode Current VI = 0.5V VI = VCC + 0.5 VI IOK DC Input Voltage DC Output Diode Current VO = 0.5V VO = VCC + 0.5V VO IO DC Output Voltage
Parameter
Rating
0.5V to +7.0V 20mA +20mA 0.5V to VCC + 0.5V 20mA +20mA 0.5V to VCC + 0.5V 50mA 50mA 65C to +150C 140C
DC Output Source or Sink Current
ICC or IGND DC VCC or Ground Current per Output Pin TSTG Storage Temperature TJ Junction Temperature
Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC Supply Voltage AC ACT VI VO TA V / t V / t Input Voltage Output Voltage Operating Temperature
Parameter
Rating
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC 40C to +85C 125mV/ns 125mV/ns
Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V
DC Electrical Characteristics for AC

Symbol
VIH
Parameter
Minimum HIGH Level Input Voltage
VCC (V)
3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5
TA = +25C Conditions
VOUT = 0.1V or VCC 0.1V VOUT = 0.1V or VCC 0.1V IOUT = 50A
TA = 40C to +85C Guaranteed Limits Units

V 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 75 A mA mA A V V V
Typ.
1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 0.1
VIL
Maximum LOW Level Input Voltage
VOH
Minimum HIGH Level Output Voltage
VIN = VIL or VIH, IOH = 12mA VIN = VIL or VIH, IOH = 24mA VIN = VIL or VIH, IOH = 24mA(1) IOUT = 50A
VOL
Maximum LOW Level Output Voltage
3.0 4.5 5.5 3.0 4.5 5.5
VIN = VIL or VIH, IOL = 12mA VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL = 24mA(1) VI = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND
IIN(3) IOLD IOHD ICC

(3)
Maximum Input Leakage Current Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current
5.5 5.5 5.5 5.5
2.0
20.0
Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
DC Electrical Characteristics for ACT

Symbol
VIH VIL VOH
Parameter
Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage
VCC (V)
4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5
TA = +25C Conditions
VOUT = 0.1V or VCC 0.1V VOUT = 0.1V or VCC 0.1V IOUT = 50A VIN = VIL or VIH, IOH = 24mA VIN = VIL or VIH, IOH = 24mA(4) IOUT = 50A VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL= 24mA(4) VI = VCC, GND VI = VCC 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 2.0 0.6 0.001 0.001 4.86 0.1 0.1 0.36 0.36 0.1
TA = 40C to +85C Guaranteed Limits Units

V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 75 20.0 A mA mA mA A V
Typ.
1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86
VOL
Maximum LOW Level Output Voltage
4.5 5.5 4.5 5.5
IIN ICCT IOLD IOHD ICC
Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(5) Maximum Quiescent Supply Current
5.5 5.5 5.5 5.5 5.5
Notes: 4. All outputs loaded; thresholds on input associated with output under test.
AC Electrical Characteristics for AC

TA = +25C, CL = 50pF Symbol
fMAX tPLH tPHL tPLH tPHL
TA = 40C to +85C, CL = 50pF Min.

95 125
Parameter
Maximum Clock Frequency Propagation Delay, CDn or SDn to Qn or Qn Propagation Delay, CDn or SDn to Qn or Qn Propagation Delay, CPn to Qn or Qn Propagation Delay, CPn to Qn or Qn
VCC (V)(6)
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Min.
100 140 3.5 2.5 4.0 3.0 4.5 3.5 3.5 2.5
Typ.
125 160 8.0 6.0 10.5 8.0 8.0 6.0 8.0 6.0
Max.
Max.
Units
MHz
12.0 9.0 12.0 9.5 13.5 10.0 14.0 10.0
2.5 2.0 3.5 2.5 4.0 3.0 3.5 2.5
13.0 10.0 13.5 10.5 16.0 10.5 14.5 10.5
ns ns ns ns
Note: 5. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V.
AC Operating Requirements for AC

tS tH tW trec
TA = 40C to +85C, CL = 50 pF Units

ns ns ns ns 4.5 3.0 0.5 0.5 7.0 5.0 0 0
Parameter
Set-up Time, HIGH or LOW, Dn to CPn Hold Time, HIGH or LOW, Dn to CPn CPn or CDn or SDn Pulse Width Recovery Time, CDn or SDn to CP
VCC (V)(7)
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Typ.
1.5 1.0 2.0 1.5 3.0 2.5 2.5 2.0
Guaranteed Minimum
4.0 3.0 0.5 0.5 5.5 4.5 0 0
Note: 6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V.
AC Electrical Characteristics for ACT

fMAX tPLH tPHL tPLH tPHL
TA = 40C to +85C, CL = 50pF Min.

125 9.5 2.5 3.0 4.0 3.0 10.5 11.5 13.0. 11.5
Parameter
Maximum Clock Frequency Propagation Delay, CDn or SDn to Qn or Qn Propagation Delay, CDn or SDn to Qn or Qn Propagation Delay, CPn to Qn or Qn Propagation Delay, CPn to Qn or Qn
VCC (V)(8)
5.0 5.0 5.0 5.0 5.0
Min.
145 3.0 3.0 4.0 3.5
Typ.
210 5.5 6.0 7.5 6.0
Max.
Max.
Units
MHz ns ns ns ns
10.0 11.0 10.0
Note: 7. Voltage range 5.0 is 5.0V 0.5V.
AC Operating Requirements for ACT

tS tH tW trec
TA = 40C to +85C, CL = 50pF Units

ns ns ns ns 3.5 1.0 6.0 0
Parameter
Set-up Time, HIGH or LOW, Dn to CPn Hold Time, HIGH or LOW, Dn to CPn CPn or CDn or SDn Pulse Width Recovery Time, CDn or SDn to CP
VCC (V)(9)
5.0 5.0 5.0 5.0
Typ.
1.0 0.5 3.0 2.5
Guaranteed Minimum
3.0 1.0 5.0 0
Note: 8. Voltage range 5.0 is 5.0V 0.5V.
Capacitance
Symbol
CIN CPD
Parameter
Input Capacitance Power Dissipation Capacitance
Conditions
VCC = OPEN VCC = 5.0V
Typ.
4.5 35.0
Units
pF pF
Physical Dimensions
8.75 8.50 7.62
14 8 B A
0.65
5.60 6.00 4.00 3.80
PIN ONE INDICATOR
1.70
1.27
1.27 (0.33)
0.51 0.35
0.25
M
LAND PATTERN RECOMMENDATION

C B A
1.75 MAX 1.50 1.25 0.25 0.10

C 0.10 C
SEE DETAIL A
0.25 0.19
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13
0.50 X 45 0.25 R0.10 R0.10

8 0
0.90 0.50 (1.04)

DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 9
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
0.43 TYP
0.65
1.65
0.45
6.10
12.00 TOP R0.09 min
& BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

19.56 18.80 14 8
6.60 6.09 1
(1.74)
1.77 1.14 5.33 MAX 0.38 MIN
8.12 7.62 0.35 0.20
3.56 3.30
3.81 3.17
0.58 0.35
2.54
8.82
NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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Rev. I32
ACEx Build it Now CorePLUS CROSSVOLT CTL Current Transfer Logic EcoSPARK EZSWITCH *
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Preliminary
First Production
No Identification Needed
Full Production
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