Nlint Rules

nLint
Rule Category
SpringSoft, Inc.
Hsinchu, Taiwan and San Jose, CA www.springsoft.com
nLint Rule Category 1
Printing
Printed on April 3, 2009
Version
This manual supports nLint 2009 series and higher versions.
Copyright
All rights reserved. No part of this manual may be reproduced in any form or by any means without written permission of SpringSoft, Inc.: No. 25, Industry East Road IV Science-Based Industrial Park Hsinchu 300, Taiwan, R.O.C. or 2025 Gateway Place, Suite 400, San Jose, CA 95110 www.springsoft.com Copyright (c) 1996-2009 SpringSoft, Inc.
Trademarks
Debussy, Verdi and nLint are trademarks or registered trademarks of SpringSoft USA, Inc. or SpringSoft, Inc. in the United States and other countries. The product names used in this manual are the trademarks or registered trademarks of their respective owners.
Confidentiality
The information in this document is confidential and is covered by a license agreement between SpringSoft and your organization. Distribution and disclosure are restricted.
Restricted Rights
The information contained in this document is subject to change without notice.
2 nLint Rule Category
About This Book

Overview
This book is designed to allow you to quickly become proficient in nLint checking rules. The book should be read from beginning to end. Sections you are already familiar with can be skipped.
Audience
The audience for this book includes chip designers who require faster and more efficient automated and customizable checking tools. This document assumes that you have a basic knowledge of the platform on which your version of nLint runs: Unix, Linux, or Windows NT; and that you are knowledgeable in Verilog/VHDL and digital logic design.
Conventions Used in This Book

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Related Publications
nLint User Guide and Tutorial Explains how to install nLint and guides you step-by-step through the nLint system. nLint Guide to User-definable Rules and Open KDB Reference Manual Provides guide to user-definable rules (UDR) and Open KDB Reference. nLint Release Notes and Installation Files For current information about the latest software version, see nLint Release Notes shipped with the product and the Installation Files in the distribution directories.
How to Reach SpringSoft, Inc.

Dual Headquarters Taiwan: No. 25, Industry East Road IV Science-Based Industrial Park Hsinchu 300, Taiwan, R.O.C. Phone: 886-3-579-4567 FAX: 886-3-579-9000 US: 2025 Gateway Place, Suite 400 San Jose, CA 95110 U.S.A. Phone: 1-888-NOVAS-38 (1-888-668-2738) or 408-467-7888 FAX: 408-467-7889 E-Mail: [email protected] for license request and sales information. [email protected] for technical support. URL: http://www.springsoft.com
Simulation
22005 Loss of Significant Bit 22006 (Verilog) Significant Bits Extended by X/Z/? 22009 (Verilog) Non-zero Bit(s) Truncated 22011 Combinational Loop 22013 Asynchronous Loop 22014 Synchronous Loop 22016 (Verilog) Apparent Loop 22018 (Verilog) Logic '1' Used to Extend Significant Bits of Constants 22019 (Verilog) Bit Index out of Bus Range 22024 (Verilog) Logic '0' Used to Extend Significant Bits of Constants 22026 (Verilog) Zero Bit(s) Truncated 22079 Constant Conditional Expression 22082 Port Not Connected 22083 Parameter Bit-width Too Long 22085 No Return Value in a Conditional Branch of a Function 22089 (Verilog) Vector Used in a Single-bit Logical Operation 22091 (Verilog) Multi-bit Expression when One Bit Expression Expected 22109 (Verilog) Logical or Bitwise OR Used in Event Control 22112 (Verilog) Zero Loop Count 22113 Infinite Loop 22115 (Verilog) Undefined Repeat Expression 22139 (Verilog) Constant Event Expression 22151 (Verilog) Assignment to an Input Signal 22169 Unassigned Bits in Function's Return Value 22179 Signal in Sensitivity List Changed in the Block 22187 (Verilog) Negative Delay 22195 Signal Assigned to Self 22217 (Verilog) Event Never Triggered 22235 All Bits Shifted Out 22243 (Verilog) Default Not Used as the Last Case Label 22247 (Verilog) Delay in Non-blocking Assignment 22269 Combinational Path between Two Registers is Too Long 22271 Report Snake Path 22279 Port is Deliberately Not Connected 22281 (Verilog) Gate Port is Not Connected 22283 (Verilog) Gate Port is Deliberately Not Connected 23008 (Verilog) Default is Not Found 23011 Incomplete Sensitivity List
23013 Extra Signal in Sensitivity List 23028 (Verilog) Memory is Read and Written at Same Time 23029 Race Condition in Sequential Logic 23030 Race Condition in Combinational Logic 23123 Overlapped Case Labels 23125 (Verilog) Procedural Continuous Assignment Not Synthesizable 23131 (Verilog) Operation on X/Z 27003 Event Control or Delay Statement Not Found in All Branches 27071 (VHDL) Bit or Bit_vector Type Not Recommended 27099 (VHDL) Composite Record Used as Trigger 27101 (VHDL) Function Returning Dynamically Allocated Memory may Lead to Memory Leak 27105 (VHDL) Attribute Leads to Bad Simulation Performance 27109 (VHDL) Non-event Attribute on Sensitive Signal 27111 (VHDL) Should Rising_Edge or Falling_Edge Function 27115 (VHDL) Integer Type Used 27123 Temporary Variable Used in Non-blocking Assignment 27125 Un-initialized Variable Referenced in an Edge-triggered Block 27127 Un-initialized Variable Referenced in Combinational Process 27335 Synopsys Directives 'translate_off'/'translate_on' Used 27337 (Verilog) Synopsys Directives 'full_case' Used 27550 (VHDL) Global Signal without Initial Value 27573 (VHDL) Timeout Clause in Wait Statement Ignored by Synthesis 27661 Asynchronous Reference in Edge-sensitive Logic 27662 (Verilog) Dual Set or Reset Detected 27672 (Verilog) Large Bit Width of Reduction Operand 27673 (Verilog) Signal Written and Read in Same Always Block 27676 (Verilog) Signal Read before Written in Same Always Block 27805 (Verilog) Task in 'always_comb' Block 27821 (Verilog) Incomplete Assignment in 'always_comb' 29807 (Verilog) Fractional Delay Value
Synthesis
22019 (Verilog) Bit Index out of Bus Range 22075 (Verilog) Nested Edge-triggers 22077 (Verilog) Edge-trigger in Task 22083 Parameter Bit-width Too Long 22119 (Verilog) Logic Expression Used in Sensitivity List 22121 (Verilog) Duplicate Signal Found in Sensitivity List 22177 (Verilog) Signal Driven by Both Blocking and Non-blocking Assignments 22193 (Verilog) Recursive Function Call 22194 (Verilog) Function Call Stack Exceeds Maximum Depth 22207 (Verilog) Non-constant Shift Amount 22211 Signal Stuck at Logic 1 22213 Signal Stuck at Logic 0 22218 (Verilog) Ignore Do Not Care Values in Case Expressions 22239 Non-constant Case Label 22247 (Verilog) Delay in Non-blocking Assignment 23001 Bit Select in Sensitivity List 23002 Inferred Storage Not in Library 23003 Inferred Latch 23004 Inferred Mux 23005 Inferred Tri-state 23008 (Verilog) Default is Not Found 23011 Incomplete Sensitivity List 23015 (Verilog) Blocking/Non-blocking Assignment in Edge-triggered Block 23016 (Verilog) Blocking/Non-blocking Assignment in Combinational Block 23017 Case-like If Statement 23021 (Verilog) Gate Instance Found 23025 Non-constant Bit Range 23026 (Verilog) Loop Variable Not the Same in All Parts 23027 Non-constant 'for' Loop Count 23031 Z or X Used in Conditional Expression 23033 (Verilog) Non-constant Divisor 23034 (Verilog) Non-constant Dividend 23035 (Verilog) Loop Variable Changed in 'for' Loop 23037 (Verilog) Blocking and Non-blocking Statements in the Same Always Block 23039 While Statement Not Synthesizable 23042 Bit of a Bus Signal Used as Special Type Signal 23043 Multiple Bits in Special Type Signal 23044 Special Type Port Connected to an Expression 23045 (Verilog) Time Variable Not Synthesizable
23047 Real Variable Not Synthesizable 23049 (Verilog) Realtime Variable Not Synthesizable 23050 (Verilog) Unpacked Union Not Synthesizable 23051 (Verilog) Event Not Synthesizable 23053 (Verilog) UDP Instance Not Synthesizable 23055 (Verilog) Specify Block Not Synthesizable 23057 (Verilog) Initial Block Not Synthesizable 23059 (Verilog) Task Not Synthesizable 23061 (Verilog) UDP Not Synthesizable 23065 (Verilog) Macromodule Not Synthesizable 23069 (Verilog) Function with Integer Return Value 23071 Function Returning Real Not Synthesizable 23073 (Verilog) Net Types Not Synthesizable 23075 (Verilog) Delay Ignored by Synthesis 23077 (Verilog) Defparam Not Synthesizable 23079 (Verilog) Memory Not Synthesizable 23083 (Verilog) Drive Strength Not Synthesizable 23087 (Verilog) Repeat Statement Not Synthesizable 23089 (Verilog) Delay Control Ignored by Synthesis 23091 (Verilog) Event Control in Unsuitable Place is Not Synthesizable 23095 (Verilog) Wait Statement Not Synthesizable 23097 (Verilog) Event Enable Statement Not Synthesizable 23099 (Verilog) Fork Statement Not Synthesizable 23101 (Verilog) Task Call Not Synthesizable 23103 (Verilog) System Task Call Not Synthesizable 23105 (Verilog) Disable Statement Not Synthesizable 23107 (Verilog) Force Statement Not Synthesizable 23109 (Verilog) Release Statement Not Synthesizable 23115 (Verilog) String Constant Not Synthesizable 23117 (Verilog) Real Constant Not Synthesizable 23119 (Verilog) Hierarchical Reference Not Synthesizable 23123 Overlapped Case Labels 23125 (Verilog) Procedural Continuous Assignment Not Synthesizable 23127 (Verilog) Deassign Statement Not Synthesizable 23129 (Verilog) Case Equivalence Operator Not Synthesizable 23133 (Verilog) Redundant Asynchronous Signal 23135 (Verilog) Different Polarity in Condition and Sensitivity List 23137 (Verilog) Both Edge and Non-edge Expressions in the Sensitivity List 24017 (Verilog) Synopsys Template Directive should be Used Before Parameter 27081 (VHDL) 'std_ulogic_vector' Not Recommended
27083 (VHDL) Resolved/Unresolved Type Not Recommended 27107 (VHDL) WAIT Statement Not the First Statement 27122 (Verilog) Variable is Conditionally Assigned in the Block 27123 Temporary Variable Used in Non-blocking Assignment 27126 Unassigned Variable Referenced in an Edge-triggered Block 27128 Variable Not Fully Assigned before Referenced in Combinational Process 27181 (VHDL) Use Signal Instead of Variable in Process 27335 Synopsys Directives 'translate_off'/'translate_on' Used 27337 (Verilog) Synopsys Directives 'full_case' Used 27505 (VHDL) Non-integer Type Generic Not Synthesizable 27507 (VHDL) Declaration Here Not Synthesizable 27509 (VHDL) Passive Entity Statement Ignored by Synthesis 27515 (VHDL) Shared Variable Not Synthesizable 27517 (VHDL) File Object Declaration Ignored by Synthesis 27518 (VHDL) File Operation Not Synthesizable 27519 (VHDL) Alias Ignored by Synthesis 27521 (VHDL) Group Ignored by Synthesis 27522 (VHDL) Group Template Ignored by Synthesis 27523 (VHDL) Pure or Impure for Sub-program Not Synthesizable 27524 Synthesis Ignores Initial Value 27525 (VHDL) User-defined Attribute Except ENUM_ENCODING Ignored 27529 (VHDL) Signature Not Synthesizable 27531 (VHDL) Deferred Constant in Package Declaration Not Synthesizable 27533 (VHDL) Null Range Not Synthesizable 27535 (VHDL) Access Type Declaration Ignored by Synthesis 27536 (VHDL) Object of Ignored Type Not Synthesizable 27537 (VHDL) Incomplete Type Declaration 27539 (VHDL) Multi-dimensional Array Not Synthesizable 27541 (VHDL) Non-integer Type Range Value Not Synthesizable 27543 (VHDL) User-defined Resolution Function Ignored by Synthesis 27545 (VHDL) Signal with REGISTER or BUS Kind Not Synthesizable 27549 (VHDL) Assigning to Global Signal Not Synthesizable 27550 (VHDL) Global Signal without Initial Value 27551 (VHDL) Linkage Mode Not Synthesizable 27553 (VHDL) Type Conversion in Formal Part of Association List Not Synthesizable 27557 (VHDL) Disconnect Ignored by Synthesis 27559 (VHDL) Xnor Operator Not Synthesizable 27561 (VHDL) Shift Operator Not Synthesizable 27563 (VHDL) Non-static Operand in Multiplying or Miscellaneous Operation 27565 (VHDL) Null for Expression Not Synthesizable
27567 (VHDL) Allocator and Deallocator Not Synthesizable 27571 (VHDL) Wait on Sensitivity List Not Synthesizable 27573 (VHDL) Timeout Clause in Wait Statement Ignored by Synthesis 27575 (VHDL) Assertion Statement Ignored by Synthesis 27577 (VHDL) Report Statement Not Synthesizable 27581 (VHDL) Transport Delay in Signal Assignment Ignored by Synthesis 27585 (VHDL) Multiple Waveform Elements Not Synthesizable 27587 (VHDL) Unaffected Clause Not Synthesizable 27589 (VHDL) After Clause Ignored by Synthesis 27595 (VHDL) POSTPONED Not Synthesizable 27597 (VHDL) Guarded Expression Not Synthesizable 27598 (VHDL) Explicit Signal GUARD Not Synthesizable 27599 (VHDL) Guarded Signal Assignment Not Synthesizable 27601 (VHDL) Block Header Not Synthesizable 27605 (VHDL) Binding Specification in Component Instantiation Statement Not Synthesizable 27609 (VHDL) Non-synthesizable Pre-defined Attribute 27610 (VHDL) Expression in Attribute Not Synthesizable 27613 (VHDL) Package TEXTIO Not Synthesizable 27615 (VHDL) Wait Statement in Sub-program Not Synthesizable 27617 (VHDL) Use Clause Not Referencing the Entire Package 27619 (VHDL) Physical Type Declaration Ignored by Synthesis 27621 (VHDL) Floating Type Declaration Ignored by Synthesis 27623 (VHDL) File Type Enumeration Not Synthesizable 27625 (VHDL) Severity Level Enumeration Ignored by Synthesis 27627 (VHDL) File Type Declaration Ignored by Synthesis 27629 (VHDL) File in Port Association Not Synthesizable 27631 (VHDL) VHDL-93 Only Syntax Not Synthesizable 27633 (VHDL) Configuration Specification Ignored by Synthesis 27635 (VHDL) Index Name on Unconstrained Object Not Synthesizable 27639 (VHDL) Explicit Inertial Delay Not Synthesizable 27641 (VHDL) Meta-logic Value in Case Choice 27643 (VHDL) Edge Specification in Concurrent Signal Assignment Not Synthesizable 27645 (VHDL) Same Signal Assigned and Referenced in Waveforms Not Synthesizable 27649 (VHDL) Generate Parameter Specification Not Static 27651 (VHDL) Extended Identifier Not Synthesizable 27653 (VHDL) Clock Signal Type Not BIT or STD_ULOGIC 27655 (VHDL) Else Branch Following Edge Condition Not Synthesizable 27657 (VHDL) Statements Outside of Edge-sensitive If Statement Not Synthesizable 27661 Asynchronous Reference in Edge-sensitive Logic 27662 (Verilog) Dual Set or Reset Detected
27663 (VHDL) Unconstrained Port Not Synthesizable 27664 (Verilog) Large Multiplier Inferred 27666 (Verilog) Complex Repeating Statements is Not Allowed 27667 (Verilog) Condition Signal Assigned to 'x' in Default Branch 27668 (Verilog) Arithmetic/Relational Operations Sharing with Large Operand Not Allowed 27669 (Verilog) Timing Path Limited in Two Sub Blocks 27670 (Verilog) Always Block Contains Multiple Resets 27671 (Verilog) Critical Path in Multiple Blocks 27674 (Verilog) Reduce Selectors with Same Contents 27676 (Verilog) Signal Read before Written in Same Always Block 27801 (Verilog) 'iff' Construct Not Synthesizable 27803 (Verilog) Statement Labels Not Synthesizable 27805 (Verilog) Task in 'always_comb' Block 27813 (Verilog) Constructs in $root Not Synthesizable 27821 (Verilog) Incomplete Assignment in 'always_comb' 27823 (Verilog) Event Control Construct in 'always_comb' 27825 (Verilog) Repeated Common Subexpression Not Allowed in 'for' Loop 27829 (Verilog) Unintended Logic Inferred 28101 (Verilog) Both Set and Reset Found for a Flip-flop/Latch 29112 (Verilog) Use Simple Expression for Asynchronous Set or Reset 29113 (Verilog) If Statement Describing Asynchronous Set/Reset should be the Most Beginning Statement in a Always Block 29115 (Verilog) Clock cannot be Explicitly Read in Always Block 29116 (Verilog) Signal Assigned by Independent Statements in a Sequential Block 29118 (Verilog) Do Not Use Integer Variable in Port Expression 29201 (Verilog) Mismatched Synopsys 'translate_on'/'translate_off' Comments 29211 (Verilog) Procedural Continuous Assignment Used in Task/Function 29212 (Verilog) Procedural Continuous Deassign Used in Task/Function 29810 (Verilog) Non-blocking Statement in Function 29818 (Verilog) 'set_dont_touch' Used 29819 (Verilog) Arithmetic Operations in 'for' Loop 29820 (Verilog) Logical or Relational Operations in 'for' Loop 29821 (Verilog) Instance/Module Name Matches Library Cell Name 29822 (Verilog) Library Cell Instantiated 29823 (Verilog) Flip-flop Initialized in Initial Block
DFT
22001 Signal with Multiple Drivers 22002 Three-state Net Not Properly Driven 22007 Constant Connected to Instance 22008 (Verilog) Expression Connected to an Instance Port 22011 Combinational Loop 22013 Asynchronous Loop 22014 Synchronous Loop 22020 Multiple Tri-state Cause Potential Bus Contention 22053 Gated Clock 22054 Inverted Clock 22055 Buffered Clock 22056 Reset Driven by Combinational Logic 22057 Set Driven by Combinational Logic 22058 Reset is Driven by a Path with Potential Glitch 22059 Set Driven by Sequential Logic 22127 Clock Signal Used as Data Input 22128 Clock Signal Feeds into Macro 22129 Clock Signal Used as Reset 22130 Clock Feeds into Primary Output 22131 Clock Driven by Sequential Logic 22132 Clock Active on Both Edges 22134 (Verilog) Clock Feeds into Floating Gate 22181 Multiple Clock Signals 22203 Reset Signal Used as Data Input 22204 Reset Signal Feeds into Primary Output 22205 Reset Driven by Sequential Logic 22227 Set Signal Used as Data Input 22228 Set Signal Feeds into Primary Output 22229 Clock Signal Used as a Control 22231 Clock Signal Used as Set 22269 Combinational Path between Two Registers is Too Long 22271 Report Snake Path 25001 Signal with No Driver 25003 Signal with No Load 25014 (Verilog) Input Signal Not Driven by Flip-Flop 27381 Scan Enable Driven by Combinational Logic 27383 Scan Enable Driven by Sequential Logic 27385 Scan Enable Signal Used as Data Input 27387 Scan Enable Feeds into Primary Output
ERC
23401 (Verilog) Floating Net 23405 (Verilog) Input Floating 23407 (Verilog) Partial Input Floating 23409 (Verilog) Output Floating
Design Style
22001 Signal with Multiple Drivers 22002 Three-state Net Not Properly Driven 22007 Constant Connected to Instance 22008 (Verilog) Expression Connected to an Instance Port 22010 Latch to Latch Connected should be Enabled in Different Phase 22011 Combinational Loop 22013 Asynchronous Loop 22014 Synchronous Loop 22017 Module with No Output 22045 (Verilog) Use Localparam in Module or Interface 22053 Gated Clock 22054 Inverted Clock 22055 Buffered Clock 22056 Reset Driven by Combinational Logic 22057 Set Driven by Combinational Logic 22058 Reset is Driven by a Path with Potential Glitch 22059 Set Driven by Sequential Logic 22061 Unused Object 22063 Two-process Style Not Used for FSM 22067 FSM and Non-FSM Logic in the Same Module 22097 (Verilog) Function Call in Procedural Continuous Assignment 22105 Different Bits of Vector Driven in Different Blocks 22117 Synchronous or Asynchronous Reset Detected 22118 (Verilog) Flip-flops with and without Asynchronous Reset/Set Coexist 22120 (Verilog) Latch should Not Coexist with Other Logic in a Module 22122 (Verilog) Tri-state Buffer should Not Coexist with Other Logic in a Module 22123 (Verilog) Specify Asynchronous Reset Signal with Negedge 22124 (Verilog) Tri-state Output Mixed with Other Logic in a Module 22126 (Verilog) Tri-state Enable Mixed with Other Logic in a Module 22131 Clock Driven by Sequential Logic 22149 Direct Connection from Input to Output 22152 (Verilog) Output Signal Referenced 22153 (Verilog) Multiple Top Modules 22159 Non-constant Delay 22167 Bi-directional Port Declared 22168 (Verilog) Connection between Unidirectional Port and Bidirectional Port 22175 Signal Used as Synchronous and Asynchronous Reset 22176 Signal Used as Synchronous and Asynchronous Set 22181 Multiple Clock Signals
22201 Write Enable Signals for Memories should be Disabled in the Test Mode 22203 Reset Signal Used as Data Input 22204 Reset Signal Feeds into Primary Output 22205 Reset Driven by Sequential Logic 22221 Reset Signal Active High and Low 22223 Set Signal Active High and Low 22225 Clock Signal Used on Both Edges 22227 Set Signal Used as Data Input 22228 Set Signal Feeds into Primary Output 22229 Clock Signal Used as a Control 22231 Clock Signal Used as Set 22233 Signal Used as Set and Reset 22252 (Verilog) Multiple Concatenation Used 22254 (Verilog) Avoid Confusing Self-determined Expressions 22261 Tri-state Inferred in Non-top Module 22263 (Verilog) Null Port Used 22269 Combinational Path between Two Registers is Too Long 22271 Report Snake Path 22273 Separate Different Clock Source Triggered Register in Different Modules 22275 Separate Clock Generate Circuit in Different Modules 22277 Separate Reset Generate Circuit in Different Modules 23001 Bit Select in Sensitivity List 23035 (Verilog) Loop Variable Changed in 'for' Loop 23037 (Verilog) Blocking and Non-blocking Statements in the Same Always Block 23042 Bit of a Bus Signal Used as Special Type Signal 23043 Multiple Bits in Special Type Signal 23044 Special Type Port Connected to an Expression 23121 No Set or Reset Signal 23122 Unassigned in Data Clause 25001 Signal with No Driver 25003 Signal with No Load 25005 (Verilog) Signal has Never been Assigned or Referenced 25007 (Verilog) Signal has been Assigned in More than One Block 25009 Signal with Heavy Fan-out Loading 25011 Input with Heavy Transitive Fan Out of End Points 25013 Output with Heavy Transitive Fan In of Start Points 25015 Outputs Leaving Partition without been Driven by Register 25016 A Combinational Path between PI and PO without Being Registered 25017 (Verilog) Duplicated Names Detected in Ports 27327 (VHDL) Mixed Sequential and Combinational Logic in a PROCESS
27328 (Verilog) Combinational Logic Found in Sequential Block 27329 (Verilog) Unrecommended Continuous Assignment 27331 (VHDL) Constrained Return Expression in Unconstrained Return Type Function 27341 (VHDL) Place Entity, Architecture and Configuration into the Same File 27343 (Verilog) Integer Type Used on Port Instance 27359 (Verilog) Unused Macro 27361 No Falling Active Clock Used 27369 Integer Type Object Detected 27401 Mix Combinational Logic with Sequential Logic 27413 Mutiple Clock Source Not Recommended 27417 No Glue Logic Allowed in Top Module 27421 (Verilog) FSM Stuck in State 27423 (Verilog) Un-reached State from Initial State of FSM 27425 (Verilog) FSM without Initial State 27427 (Verilog) Next State In Default Branch 27827 (Verilog) Declaration of Variable with Assignment 29108 (Verilog) Usage of Specific Keyword(s) Not Allowed 29110 (Verilog) Signals Names of an Identical Signal should Remain the Same throughout the Design Hierarchy. 29114 (Verilog) A Signal is Connected to Both Input and Output Ports of an Instance 29802 (Verilog) Constant Value Assigned to Case Default Clause 29803 (Verilog) Filp-flop Reset Logic in 'for' Loop 29808 (Verilog) Fixed Value of Case Selection Expression 29809 (Verilog) Negative Value Assigned to an Integer 29813 (Verilog) Logical/Arithmetic/BitWise Operation in Case Selection Expression 29814 (Verilog) One Statement in a Single Always Block 29815 (Verilog) Logical Operators Used in Single-bit Operations 29816 (Verilog) Describe Combinational Logic with Functions and an Assignment 29817 (Verilog) Function Called in an Always Block
Language Construct
22003 Bit Width Mismatch in Assignment 22004 Bit Width Mismatch in Bitwise Operation 22005 Loss of Significant Bit 22006 (Verilog) Significant Bits Extended by X/Z/? 22009 (Verilog) Non-zero Bit(s) Truncated 22012 Bit Width Mismatch between Module Port and Instance Port 22015 (Verilog) Zero Bit(s) Omitted 22018 (Verilog) Logic '1' Used to Extend Significant Bits of Constants 22019 (Verilog) Bit Index out of Bus Range 22022 (Verilog) Suspicious Use of Semicolon 22024 (Verilog) Logic '0' Used to Extend Significant Bits of Constants 22026 (Verilog) Zero Bit(s) Truncated 22083 Parameter Bit-width Too Long 22085 No Return Value in a Conditional Branch of a Function 22089 (Verilog) Vector Used in a Single-bit Logical Operation 22091 (Verilog) Multi-bit Expression when One Bit Expression Expected 22098 (Verilog) Deassign with Function Argument 22101 (Verilog) Bit Range Specified for Parameter 22103 (Verilog) Case Label out of Boundary 22104 Bit Width Mismatch in Logic Comparison Operation 22106 (Verilog) Bit Width Mismatch in Comparison of Case Statement 22109 (Verilog) Logical or Bitwise OR Used in Event Control 22119 (Verilog) Logic Expression Used in Sensitivity List 22121 (Verilog) Duplicate Signal Found in Sensitivity List 22125 (Verilog) Bit Range Used on Non-vector Object 22139 (Verilog) Constant Event Expression 22151 (Verilog) Assignment to an Input Signal 22155 Empty Block 22157 Empty Process 22165 Signal Driven by Constant 22169 Unassigned Bits in Function's Return Value 22187 (Verilog) Negative Delay 22199 (Verilog) Reduction Operation on Single-bit Signal 22209 Insufficient Index Variable 22210 (Verilog) Oversized Index Variable 22219 (Verilog) x/z? Used in Case Label 22220 (Verilog) Casez Label Contains X 22243 (Verilog) Default Not Used as the Last Case Label 22249 (Verilog) Variables with Different Bit Widths Used in Conditional Assignment Branches
22251 (Verilog) Integer Used in Concatenation 22255 Task or Function Refers to a Non-local Variable 22259 (Verilog) Loop Variable Not an Integer 22265 (Verilog) Operand Bit Size Mismatch in Addition or Subtraction 22267 (Verilog) Possible Loss of Carry or Borrow in Addition or Subtraction 22268 (Verilog) Possible Loss Value in Multiplication 22301 (Verilog) Zero Implicitly Filled to Higher Bits of LHS Variable in Assignment 22303 (Verilog) Unpacked Signal Bit Width Mismatch in Assignment 23006 (Verilog) Incomplete Case Expression with Default Clause 23007 (Verilog) Case Statement Not Fully Specified 23010 (Verilog) Incomplete Case Expression with Default Clause and Synopsys 'full_case' Directive 23028 (Verilog) Memory is Read and Written at Same Time 23029 Race Condition in Sequential Logic 23030 Race Condition in Combinational Logic 23031 Z or X Used in Conditional Expression 24011 (Verilog) Include Compiler Directive Used 24013 (Verilog) Conditional Compiler Directive Used 24015 Unknown Directive 24019 'dc_shell' Commands Detected 24021 (Verilog) Define Statements should be Put into One File 26001 (Verilog) Too Many Words in Memory 26003 (Verilog) Matching Deassign Statement Not Found 26005 (Verilog) Supply Signal Assigned 26007 (Verilog) Matching Assign Statement Not Found 26009 (Verilog) Event Type Tested by Posedge or Negedge 26011 (Verilog) Matching Release Statement Not Found 26013 (Verilog) Matching Force Statement Not Found 26015 (Verilog) Too Many Bits in Memory 27333 (Verilog) Variables Declared in Automatic Tasks Used with Incorrect Constructs 27345 (Verilog) Size Constant should be Specified for Integer 27665 (Verilog) Bit Width Mismatch in Logical Operation 29805 (Verilog) Use Case for Cases without 'Don't Care' Values 29806 (Verilog) Negative Value Assignment 29807 (Verilog) Fractional Delay Value
HDL Translation
24001 (Verilog) VHDL Reserved Words 24003 (VHDL) Verilog Reserved Words 24005 (Verilog) SystemVerilog Reserved Words 24007 (Verilog) Signal Names Distinguished Only by Letter Case 24011 (Verilog) Include Compiler Directive Used 24013 (Verilog) Conditional Compiler Directive Used 27143 (VHDL) BLOCK Statement Used 27144 (VHDL) GENERATE Statement Used
Coding Style
21023 Unconventional Vector Range Definition 21043 More than One Module Declared in a File 21044 Module Name Different from File Name 22021 Implicit and Confusing Operator Precedence 22023 More than One Statement per Line 22025 Line Too Long 22027 Improper Indentation 22029 TAB Used in Indentation 22031 One Port per Line 22032 Comment Not Found Following Port Declaration 22033 Interspersed Input and Output Declarations 22035 Unconventional Port Declaration Order 22038 Declare One Signal per Line with Comment 22039 Inconsistent Port Order in Definition and Instantiation 22041 (Verilog) Implicit Port Declaration 22043 Connection Ports by Ordered List 22044 Use Explicit Mapping for Parameters 22049 Literal Constant in Range Definition 22107 (Verilog) Redundant Case Labels 22108 (Verilog) Dangling Else 22161 (Verilog) Wire Not Explicitly Declared 22246 (Verilog) Non-blocking Assignment with Delay in Sequential Block 22306 (Verilog) Ambiguous Extension of X/Z 23009 (Verilog) Unreachable Default Branch of Case Statement 24009 Objects with Same Name of Object in Outer Scope 27001 (VHDL) Keywords Not Kept in the Same Line 27027 (VHDL) Pre-defined Identifier Redefined 27028 User Reserved Words Redefined 27029 (VHDL) Missing Entity Name in the END Statement 27031 (VHDL) Missing Architecture Name in the END Statement 27033 (VHDL) Missing Configuration Name in the END Statement 27035 (VHDL) Missing Package Declaration Name in the END Statement 27037 (VHDL) Missing Package Name in the END Statement of Package Body 27039 (VHDL) Missing Sub-program Name in the END Statement 27041 (VHDL) Missing Block Label in the END Statement 27043 (VHDL) Missing Process Label in the END Statement 27044 (VHDL) Missing Generate Statement Label in the END Statement 27045 (VHDL) Missing If Statement Label in the END Statement 27047 (VHDL) Missing Case Statement Label in the END Statement
27049 (VHDL) Missing Loop Statement Label in the END Statement 27051 (VHDL) Missing Component Name in the END Statement 27055 Too Many Lines in a Source File 27069 (VHDL) User-defined Logic Type and its Subtype Not Recommended 27071 (VHDL) Bit or Bit_vector Type Not Recommended 27077 (VHDL) Enumeration Literal Used in Range Specification 27081 (VHDL) 'std_ulogic_vector' Not Recommended 27083 (VHDL) Resolved/Unresolved Type Not Recommended 27085 (VHDL) Constrained Range Used for Array Type 27093 (VHDL) NEXT Statement Used in Loop 27095 (VHDL) EXIT Statement Used in Loop 27099 (VHDL) Composite Record Used as Trigger 27101 (VHDL) Function Returning Dynamically Allocated Memory may Lead to Memory Leak 27105 (VHDL) Attribute Leads to Bad Simulation Performance 27107 (VHDL) WAIT Statement Not the First Statement 27109 (VHDL) Non-event Attribute on Sensitive Signal 27111 (VHDL) Should Rising_Edge or Falling_Edge Function 27115 (VHDL) Integer Type Used 27119 (VHDL) BUFFER Port Used 27124 (VHDL) Initialized Variable Used as a Constant 27130 (Verilog) Variable Updated Twice in Same Time Point 27131 (Verilog) Assignment is Redundant 27143 (VHDL) BLOCK Statement Used 27144 (VHDL) GENERATE Statement Used 27338 (Verilog) Mixed Signed and Unsigned Operands Not Recommended 27339 (Verilog) Sign/Unsigned Conversion in Assignment 27347 Nested Synopsys Translate_on or Translate_off Directive Found 27349 (Verilog) No Comment Added after End Statement 27351 Operator Not Allowed 27353 (Verilog) No Escape Name Used 27357 (Verilog) Module Defined More than Once 27363 (Verilog) 'for' Loop Detected 27365 (Verilog) Casex or Casez Detected 27367 (Verilog) Conditional Assignment Detected 27371 Synopsys Synthesis Directive Detected 27377 Empty Module 27379 (Verilog) Unsigned Vector Compared with a Negative Value 27389 (Verilog) Timescale Missing 27391 (Verilog) 'reg' Declaration Detected 27393 (Verilog) Wire Declaration Detected
27394 (Verilog) 'tri' Declaration Detected 27395 (Verilog) No Direct Usage of Specified Data Types 27397 (Verilog) `define Used to Define Constants 27399 Comment on Synchronous Set or Reset 27411 (Verilog) Use Parameters for FSM State Coding 27412 (Verilog) Too Many States in a FSM 27675 (Verilog) Simple Signal Names for Array Index 27807 (Verilog) Non-void Function Not Declared as Automatic 27815 (Verilog) Incremented/Decremented Variables Used More than Once in the Same Expression 27817 (Verilog) 'always_ff' Not Used for Sequential Blocks 27819 (Verilog) Use 'always_comb' to Model Combinational Behavior 29003 (Verilog) Bus Direction Consist on Port Binding 29005 (Verilog) Too Many Levels of Nested If 29006 (Verilog) Too Many Levels of Nested Case 29100 (Verilog) Preserve Port Order 29101 (Verilog) Declaration of All Internal Nets should Follow the Port I/O Declaration at the Top of the Module 29102 (Verilog) Need Comment before Functional Block 29103 (Verilog) Use One Line Comment 29104 (Verilog) Comment on Cell Instantiation 29105 (Verilog) Comment Synthesis Directives 29106 (Verilog) Check File Header Format 29107 (Verilog) Comment Compiler Directives 29111 (Verilog) Check Construct Header Format 29206 (Verilog) Real Value Compared in Case Item 29801 (Verilog) Nested Text Macro 29804 (Verilog) Number Not execced threshold value 29811 (Verilog) Parameter Base Not Specified Explicitly 29812 (Verilog) Specify Constant Bit Width Explicitly
Naming Convention
21001 Signal Name Case 21003 Variable Name Case 21005 Port Name Case 21007 Signal Name Too Long 21009 Variable Name Too Long 21011 Port Name Too Long 21013 Clock Name Prefix or Suffix 21014 Latch Name Prefix or Suffix 21015 Reset Name Prefix or Suffix 21017 Set Name Prefix or Suffix 21019 Current State Name Prefix or Suffix 21020 Active Low Signal Name Prefix or Suffix 21021 Active High Signal Name Prefix or Suffix 21022 Regular of Active High Signal and Active Low Signal 21025 (Verilog) Port Name does Not Follow the Connected Signal 21027 Register Output Name Prefix or Suffix 21029 Asynchronous Signal Name Prefix or Suffix 21031 Tri-state Signal Name Prefix or Suffix 21035 Register Input Signal Name Prefix or Suffix 21041 Parameter Name Case 21045 File Name Too Long 21047 (Verilog) Names Easy to Get Confused 21049 Process Label Prefix or Suffix 21050 Missing Process Label Name 21051 Instance Name Prefix or Suffix 21053 (Verilog) Gate Name Prefix or Suffix 21055 (Verilog) Identical Module Name and Instance Name 21057 Use the Same Name for All Clocks from Same Source 24007 (Verilog) Signal Names Distinguished Only by Letter Case 27007 (VHDL) Keyword Case 27015 Unconventional File Extension 27063 (VHDL) Name Case of Number Literal 27201 (VHDL) ENTITY Name Length 27203 (VHDL) ENTITY Name Case 27205 (VHDL) ENTITY Name Prefix or Suffix 27209 MODULE Name Length 27211 MODULE Name Case 27213 MODULE Name Prefix or Suffix 27217 (VHDL) PACKAGE Name Length
27219 (VHDL) PACKAGE Name Case 27221 (VHDL) PACKAGE Name Prefix or Suffix 27225 (VHDL) CONFIGURATION Name Length 27227 (VHDL) CONFIGURATION Name Case 27229 (VHDL) CONFIGURATION Name Prefix or Suffix 27233 INSTANCE Name Length 27235 INSTANCE Name Case 27241 (VHDL) COMPONENT Name Length 27245 (VHDL) COMPONENT Name Prefix or Suffix 27249 PROCESS Name Length 27251 PROCESS Name Case 27257 (VHDL) CONSTANT Name Length 27259 (VHDL) CONSTANT Name Case 27261 (VHDL) CONSTANT Name Prefix or Suffix 27265 TYPE Name Length 27267 Case of TYPE Name 27269 Prefix or Suffix of TYPE Name 27273 PARAMETER Name Length 27277 PARAMETER Name Prefix or Suffix 27285 SIGNAL Name Prefix or Suffix 27287 (Verilog) VARIBLE Name 27288 (Verilog) VARIABLE Name Length 27289 (Verilog) FIELD Name 27290 (Verilog) FIELD Name Length 27293 VARIABLE Name Prefix or Suffix 27297 FUNCTION Name Length 27299 FUNCTION Name Case 27301 FUNCTION Name Prefix or Suffix 27305 TASK Name Length 27307 TASK Name Case 27309 TASK Name Prefix or Suffix 27313 (VHDL) BLOCK Name Length 27315 (VHDL) BLOCK Name Case 27317 (VHDL) BLOCK Name Prefix or Suffix 27321 (VHDL) ATTRIBUTE Name Length 27325 (VHDL) ATTRIBUTE Name Prefix or Suffix 27373 Next State Name Prefix or Suffix 27375 IDENTIFIER Name 27415 (Verilog) Specified Delay should be Used 29001 (Verilog) User Defined Primitive should be Named in Lower Case
29002 (Verilog) Instance Name Related to Module Name 29004 (Verilog) Module Name Follow Predefined Pattern 29109 (Verilog) Macro Naming Convention 29204 (Verilog) Instance Name Required for Module
VITAL Compliant
27155 (VHDL) Port Name with Underscore in Top Entity 27159 (VHDL) Range Constraint on Port in Top Entity 27163 (VHDL) Non-std_logic_1164 Type Used on Port in Top Entity
Clock
22051 (Verilog) Generated Reset 22052 (Verilog) Generated Clock 22130 Clock Feeds into Primary Output 22133 (Verilog) Reconverged Clock 27419 Mutiple Resolved Point Not Recommended 28009 End Point Not Generated from a Single Clock Source 28011 Inputs of a Tri-state Bus Not Generated from a Single Clock Source 28015 Tri-state Buffer in a Clock Path
Block Interconnect
27355 (Verilog) Conflict of Hierarchy Interconnection 27356 (Verilog) Block Assembly Error in the Same Hierarchy Level
CTS
25019 (Verilog) Set Sync/Ignore Pin Attribute on Output 25021 (Verilog) CTS ignore pin Attribute Set for All Fan-out Logics of an Instance
21001 (Verilog) Signal Name Case 21001 (VHDL) SIGNAL Name Case
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: SIGNAL "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the signal names, including wires and regs, are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (A, b, C); input A, b; //warning on 'A' if CASE_LOWER output C; wire C; //warning on 'C' if CASE_LOWER and and1(C,A,b); endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(2): Warning 21001: signal "A" should be named in CASE_LOWER case. (Naming Convention) document.v(4): Warning 21001: signal "C" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is signal E : bit :='0'; --warning on 'E' if CASE_LOWER end top_ety; architecture arch of top_ety is signal s : bit :='0'; signal A : bit :='0'; --warning on 'A' if CASE_LOWER begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(2): Warning 21001: SIGNAL "E" should be named in CASE_LOWER case. (Naming Convention) document.vhd(7): Warning 21001: SIGNAL "A" should be named in CASE_LOWER case. (Naming Convention)
21003 (Verilog) Variable Name Case 21003 (VHDL) VARIABLE Name Case
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: VARIABLE "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the variable names, including integer, real and realtime variables, are all in lower (or upper) case. (VHDL) This rule checks whether the variable names are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (a, b, r, y); input [7:0] a, b; output [7:0] y; reg [7:0] y; integer N; //warning on 'N' if CASE_LOWER always @(a) begin y=0; for (N=0; N<=7; N=N+1) y[N] = a[N] & b[N]; end endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(5): Warning 21003: variable "N" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is shared variable x: integer :=0; shared variable Y: integer :=0; --warning on 'Y' if CASE_LOWER end top_ety; architecture arch of top_ety is shared variable v1: integer :=0; shared variable V2: integer :=0; --warning on 'V2' if CASE_LOWER begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(3): Warning 21003: VARIABLE "Y" should be named in CASE_LOWER case. (Naming Convention) document.vhd(8): Warning 21003: VARIABLE "V2" should be named in CASE_LOWER case. (Naming Convention)
21005 (Verilog) Port Name Case 21005 (VHDL) PORT Name Case
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: port "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: PORT "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the port names are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test (.PA(a), b, .Pc(c)); //suggest to use ".pa(a), .pc(c)" input a, b; output c; and and1(c, a, b); endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(1): Warning 21005: port "Pc" should be named in CASE_LOWER case. (Naming Convention) document.v(1): Warning 21005: port "PA" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is port(signal s1: in bit :='0'; signal S2: out bit :='0' --warning on 'S2' if CASE_LOWER ); end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(3): Warning 21005: PORT "S2" should be named in CASE_LOWER case. (Naming Convention)
21007 (Verilog) Signal Name Too Long 21007 (VHDL) SIGNAL Name Too Long
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of signal name "%s" should not exceed %d characters. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of SIGNAL name "%s" should not exceed %d characters. Configurable Parameter Rule group: Naming Convention; Argument type: integer; Argument description: specify the maximum number of characters in a signal name; Default value: "16" for Verilog, "16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the length of the signal name exceeds 'length' characters. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; reg a1234567890123456, b; //warning on 'a1234567890123456' wire c; initial begin end endmodule
nLint reports following if the argument value is ("16"): document.v(2): Warning 21007: the length of signal name "a1234567890123456" should not exceed 16 characters. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is signal c1234567890123456 : bit :='0'; --warning on "c1234567890123456" signal c: bit :='0'; end top_ety; architecture arch of top_ety is signal a1234567890123456 : bit :='0'; --warning on "a1234567890123456" signal a : bit :='0'; begin end arch;
nLint reports following if the argument value is ("16"): document.vhd(2): Warning 21007: the length of SIGNAL name "c1234567890123456" should not exceed 16 characters. (Naming Convention) document.vhd(7): Warning 21007: the length of SIGNAL name "a1234567890123456" should not exceed 16 characters. (Naming Convention)
21009 (Verilog) Variable Name Too Long 21009 (VHDL) VARIABLE Name Too Long
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of variable name "%s" should not exceed %d characters. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of VARIABLE name "%s" should not exceed %d characters. Configurable Parameter Rule group: Naming Convention; Argument type: integer; Argument description: specify the maximum number of characters in a variable name; Default value: "16" for Verilog, "16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the length of the variable name exceeds 'length' characters. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (a, b, r, y); input [7:0] a, b; input [2:0] r; output [7:0] y; reg [7:0] y; integer n1234567890123456; // warning on 'n1234567890123456' endmodule
nLint reports following if the argument value is ("16"): document.v(6): Warning 21009: the length of variable name "n1234567890123456" should not exceed 16 characters. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is shared variable e1234567890123456 : bit :='0'; --warning on -- "e1234567890123456" shared variable e : bit :='0'; constant c1234567890123456 : integer :=0; end entity top_ety; architecture arch of top_ety is shared variable a1234567890123456 : bit :='0'; --warning on -- "a1234567890123456" shared variable a : bit :='0'; begin end architecture arch;
nLint reports following if the argument value is ("16"): document.vhd(2): Warning 21009: the length of VARIABLE name "e1234567890123456" should not exceed 16 characters. (Naming Convention) document.vhd(10): Warning 21009: the length of VARIABLE name "a1234567890123456" should not exceed 16 characters. (Naming Convention)
21011 (Verilog) Port Name Too Long 21011 (VHDL) PORT Name Too Long
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of port name "%s" should not exceed %d characters. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of PORT name "%s" should not exceed %d characters. Configurable Parameter Rule group: Naming Convention; Argument type: integer; Argument description: specify the maximum number of characters in a port name; Default value: "16" for Verilog, "16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the length of the port name exceeds 'length' characters. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test(.pa123456789012345(a), b, .pc(c));// warning on //'pa123456789012345' input a, b; output c; endmodule
nLint reports following if the argument value is ("16"): document.v(1): Warning 21011: the length of port name "pa123456789012345" should not exceed 16 characters. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is port(signal a : in bit :='0'; signal a1234567890123456 : out bit --warning on --"a1234567890123456" ); end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports following if the argument value is ("16"): document.vhd(3): Warning 21011: the length of PORT name "a1234567890123456" should not exceed 16 characters. (Naming Convention)
21013 Clock Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: clock signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","clk_" for Verilog, "PREFIX","clk_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the clock signal names have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (clock, data, y); input clock, data; output y; reg y; always @(posedge clock) //warning on 'clock', //'clk_XXX' recommended y = data; endmodule
nLint reports following if the argument value is ("PREFIX","clk_"): document.v(6): Warning 21013: clock signal name "clock" does not match to regular expression "clk_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 entity top_ety is port ( reset : in bit; clock : in bit; d: in bit; q: out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then q<='0'; elsif (clock'event and clock='1') then --warning on 'clock', --'clk_XXX' recommended q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("PREFIX","clk_"): document.vhd(15): Warning 21013: clock signal name "clock" does not match to regular expression "clk_.*". (Naming Convention)
21014 Latch Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: latch signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_lat" for Verilog, "SUFFIX","_lat" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the latch signal names have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test; wire clk, rw, data; reg latch; always @(rw) begin if (rw == 1) //warning here latch = data; end endmodule
nLint reports following if the argument value is ("SUFFIX","_lat"): document.v(5): Warning 21014: latch signal name "latch" does not match to regular expression ".*_lat". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is signal clk,latch,data : bit; begin process (clk) begin if (clk='1') then --warning here latch <= data; end if; end process; end arch;
nLint reports following if the argument value is ("SUFFIX","_lat"): document.vhd(9): Warning 21014: latch signal name "latch" does not match to regular expression ".*_lat". (Naming Convention)
21015 Reset Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: reset signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","rst_" for Verilog, "PREFIX","rst_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the reset signal names have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (clock, reset, count); input clock, reset; output [8:0] count; reg [8:0] count; always @(posedge clock or negedge reset) begin if (~reset) //warning on 'reset', //'rst_XXX' recommended count = 0; else count= count + 1; end endmodule
nLint reports following if the argument value is ("PREFIX","rst_"): document.v(8): Warning 21015: reset signal name "reset" does not match to regular expression "rst_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d: in std_logic; q: out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then --warning on 'reset',
17 18 19 20 21 22 23
-- 'rst_XXX' recommended q<='0'; elsif (rising_edge(clock)) then q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("PREFIX","rst_"): document.vhd(16): Warning 21015: reset signal name "reset" does not match to regular expression "rst_.*". (Naming Convention)
21017 Set Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: set signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","set_" for Verilog, "PREFIX","set_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the set signal names have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (clock, preset, data, q); input clock, preset, data; output q; reg q; always @(posedge clock or negedge preset) begin if (~preset) //warning on 'preset', //'rst_XXX' recommended q <= 1'b1; else q <= data; end endmodule
nLint reports following if the argument value is ("PREFIX","set_"): document.v(7): Warning 21017: set signal name "preset" does not match to regular expression "set_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is port ( preset : in bit; clock : in bit; d: in bit; q: out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,preset) is begin if (preset='1') then --warning on 'preset', -- 'set_XXX' recommended q<='1'; elsif (clock'event and clock='1') then q<=d;
18 19 20
end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("PREFIX","set_"): document.vhd(13): Warning 21017: set signal name "preset" does not match to regular expression "set_.*". (Naming Convention)
21019 Current State Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: state register name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_cs" for Verilog, "SUFFIX","_cs" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the current state register names have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 module fsm(out, in, clock, reset); output out; input in, clock, reset; reg out; reg [1:0] current, next; always @(in or current) begin out = ~current[1] & current[0]; next = 0; if (current == 0) if (in) next = 1; if (current == 1) if (in) next = 3; if (current == 3) if (in) next = 3; else next = 1; end always @(posedge clock or negedge reset) begin if (~reset) current <= 0; else current <= next; //warning here; good style if using "_cs" //as suffix of current state register "current" end endmodule
nLint reports following if the argument value is ("SUFFIX","_cs"): document.v(27): Warning 21019: state register name "current" does not match to regular expression ".*_cs". (Naming Convention)
(VHDL) -------------------example : document.vhd-------------
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
entity test is port ( reset : in bit; clock : in bit; s: out integer ); end entity test; architecture arch of test is type state_T is (a,b,c,d); begin p1: process (clock,reset) is variable v : state_T :=a; begin if (reset='1') then s<=0; v:=a; elsif (clock'event and clock='1') then case (v) is --warning here; good style if using '_cs' --as suffix of current state signal "v" when a=> s<=1; v:=b; when b=> s<=2; v:=c; when c=> s<=3; v:=d; when others => s<=0; v:=a; end case; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_cs"): document.vhd(22): Warning 21019: state register name "v" does not match to regular expression ".*_cs". (Naming Convention)
21020 Active Low Signal Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: active low signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_n" for Verilog, "SUFFIX","_n" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the active low signals have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (clk,rst_n,count); input clk,rst_n; output [8:0] count; reg [8:0] count; reg [8:0] nextCount; always @(posedge clk or negedge rst_n) if (~rst_n) //good style for using '_n' for active low reset count <= 0; else count <= nextCount; endmodule
nLint reports following if the argument value is ("SUFFIX","_n"):
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is port ( r: in bit; s: out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process(r) is begin if (r='0') then --warning here: good style if using '_n' --for active low reset s<='0'; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_n"):
document.vhd(11): Warning 21020: active low signal name "r" does not match to regular expression ".*_n". (Naming Convention)
21021 Active High Signal Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: active high signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_p" for Verilog, "SUFFIX","_p" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the active high signals have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (clk,rst_p,count); input clk,rst_p; output [8:0] count; reg [8:0] count; reg [8:0] nextCount; always @(posedge clk or negedge rst_p) if(rst_p) //good style for using '_p' for active high reset count <= 0; else count <= nextCount; endmodule
nLint reports following if the argument value is ("SUFFIX","_p"):
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is port ( r : in bit; s: out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (r) is begin if (r='1') then --warning on "r", --good style if using '_p' for active high reset s<='0'; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_p"):
document.vhd(11): Warning 21021: active high signal name "r" does not match to regular expression ".*_p". (Naming Convention)
21022 Regular of Active High Signal and Active Low Signal

Message <filename>(<line no.>): <severity> <rule no.>: %s signal name "%s" does not follow the regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: a list of 3-elements : boolean (RESET_LOW, RESET_HIGH, SET_LOW, SET_HIGH,LATCH_ENABLE_LOW, LATCH_ENABLE_HIGH, TRI_ENABLE_LOW, TRI_ENABLE_HIGH) <regular expression strings>;; Argument description: The argument specify regular expression (for clarification, see Regular Expression Help in the end of Rule documentation); o. The argument of this rule has 8 multiselected lists, e.g. RESET_LOW means to check active low reset signal, LATCH_ENABLE_HIGH means to check active high latch-enable signal etc. o. Each list is seperated by ";" and has several string item. Each string item is seperated by ",". o. User can select one or more lists in the argument by modifing the first string item in the list from "FALSE" to "TRUE". o. The second string item is the name of the list. o. The rest string items are the regular expressions, which should be compatible by the signal name. o. The number of regular expression can be more than 1 and separated by ;; Default value: "TRUE,RESET_LOW,rst_.*_n;FALSE,RESET_HIGH, rst_.*_p;TRUE,SET_LOW,set_.*_n; TRUE,SET_HIGH,set_.*_p; FALSE, LATCH_ENABLE_LOW; FALSE,LATCH_ENABLE_HIGH; FALSE,TRI_ENABLE_LOW; FALSE,TRI_ENABLE_HIGH" for Verilog, "TRUE,RESET_LOW,rst_.*_n;FALSE,RESET_HIGH, rst_.*_p;TRUE,SET_LOW,set_.*_n; TRUE,SET_HIGH,set_.*_p; FALSE, LATCH_ENABLE_LOW; FALSE,LATCH_ENABLE_HIGH; FALSE,TRI_ENABLE_LOW; FALSE,TRI_ENABLE_HIGH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any active high or low signal name does not follow the regular expression. This rule is another representation for two sets of rules. One are 21020 and 21021, and the other are 21015, 21017, etc. This rule can be used to replace both the two sets of rules. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module test; wire clk, rst1; wire rst2, rst_test_n; reg [8:0] count; always @(posedge clk or negedge rst1) begin if (~rst1) //warning here count = 0; else count = count + 1; end always @(posedge clk or negedge rst2) begin if (rst2) //no warning count = 0; else count = count + 1; end always @(posedge clk or negedge rst_test_n) begin
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if (~rst_test_n) //no warning count = 0; else count = count + 1; end endmodule
nLint reports following if the argument value is ("TRUE,RESET_LOW,rst_.*_n;FALSE,RESET_HIGH, rst_.*_p;TRUE,SET_LOW,set_.*_n; TRUE,SET_HIGH,set_.*_p; FALSE, LATCH_ENABLE_LOW; FALSE,LATCH_ENABLE_HIGH; FALSE,TRI_ENABLE_LOW; FALSE,TRI_ENABLE_HIGH"): document.v(7): Warning 21022: active low reset signal name "rst1" does not follow the regular expression "rst_.*_n". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 entity top_ety is end top_ety; architecture arch of top_ety is signal rst,rst1,rst_test_n: bit; signal s,s1,s2: bit; begin p1: process(rst) is begin if (rst='0') then --warning here s<='0'; end if; end process p1; p2: process(rst1) is begin if (rst1='1') then s1<='0'; end if; end process p2;
--no warning
p3: process(rst_test_n) is begin if (rst_test_n='0') then s2<='0'; end if; end process p3; end arch;
--no warning
nLint reports following if the argument value is ("TRUE,RESET_LOW,rst_.*_n;FALSE,RESET_HIGH, rst_.*_p;TRUE,SET_LOW,set_.*_n; TRUE,SET_HIGH,set_.*_p; FALSE, LATCH_ENABLE_LOW; FALSE,LATCH_ENABLE_HIGH; FALSE,TRI_ENABLE_LOW; FALSE,TRI_ENABLE_HIGH"): document.vhd(10): Warning 21022: active low reset signal name "rst" does not follow the regular expression "rst_.*_n". (Naming Convention)
21023 Unconventional Vector Range Definition

Message <filename>(<line no.>): <severity> <rule no.>: %s are not used for range declaration of "%s". Configurable Parameter Rule group: Coding Style; Argument type: (ZERO_BOUND, POSITIVE_BOUND, NEGATIVE_BOUND) (TO, DOWN_TO, NOT_CARE); Argument description: The first argument, ZERO_BOUND, POSTIVE_BOUND or NEGATIVE_BOUND, allows users to define what kind of boundary value can be used in the range index. User can select more than one type of options for this argument. The second argument allows users to specify the ascending or descending vector range definition. They could be descending (DOWN_TO), ascending (TO) or both (NOT_CARE); Default value: "ZERO_BOUND","DOWN_TO" for Verilog, "ZERO_BOUND","DOWN_TO" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether the vector range definition follows the conventional way, such as positive index or indexing by descending bit order (e.g. [high#:low#]). Following the same vector range convention could reduce the mistakes of bus vector assignments. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (A,B,C,Q,LINE); input [7:0] A; input [0:7] B; //warning input [8:1] C; //warning output[5:-2] Q; //warning inout LINE; endmodule
nLint reports following if the argument value is ("ZERO_BOUND","DOWN_TO"): document.v(3): Warning 21023: descending bit order and zero bound are not used for range declaration of "B". (Coding Style) document.v(4): Warning 21023: descending bit order and zero bound are not used for range declaration of "C". (Coding Style) document.v(5): Warning 21023: descending bit order and zero bound are not used for range declaration of "Q". (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is end entity top_ety; architecture arch of top_ety is type array1 is array (1 to 8) of bit; --warning on "(1 to 8)", --"(7 downto 0)" is recommended type array2 is array (natural range<>) of bit; subtype array2_s is array2 (1 to 16); --warning on "(1 to 16)", --"(15 downto 0)" is recommended signal s1 : array1; signal s2 : array2_s; signal s3 : array2(1 to 32); --warning on "(1 to 32)", --"(31 downto 0)" is recommended begin end architecture arch;
nLint reports following if the argument value is ("ZERO_BOUND","DOWN_TO"): document.vhd(5): Warning 21023: descending bit order and zero bound are not used for range declaration of "array1". (Coding Style) document.vhd(8): Warning 21023: descending bit order and zero bound are not used for range declaration of "array2_s". (Coding Style) document.vhd(13): Warning 21023: descending bit order and zero bound are not used for range declaration of "s3". (Coding Style)
21025 (Verilog) Port Name does Not Follow the Connected Signal
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: port "%s" and its connection "%s" should be similar. Configurable Parameter Rule group: Naming Convention; Argument type: (CHECK_LIB_CELL, IGNORE_LIB_CELL); Argument description: When checking port with the low-connected net, the argument will only be valid when the option -lint_cell_lib is turned ON, because the port and the low-connected net are both in the same module. Set the argument to IGNORE_LIB_CELL to filter the violations in lib cells; or set it as CHECK_LIB_CELL to check lib cells. When checking port instance with highconnected net, if the module of the instance is a lib cell and the instance itself is not in the lib cell, set the argument as CHECK_LIB_CELL to check the port instance name, or set it as IGNORE_LIB_CELL to not check the port instance name. If the instance itself is also included in a lib cell, the port instance name will be checked only when the -lint_lib_cell option is turned ON; Default value: "IGNORE_LIB_CELL" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether names of ports follow their connected signals. For a port and its low connection, checking of this rule is case insensitive. The port name should be the same as its lower signal name, or be sub-string of the signal name, and vice versa. For a port instance and its high connection, checking of this rule is case sensitive, and the lower name should be the same as the upper name, or be a sub-string of the upper name. Example
(Verilog) ///////////////example : document.v//////////// 1 module test; 2 reg ck,reset; 3 wire [8:0] count; 4 5 block cc (.clk(ck),.RESET(reset),.counti(count)); //warning on clk, RESET and counti 6 endmodule 7 8 module block(.clk(clock),.RESET(reset),.counti(count)); //warning on clk 9 input clock,reset; 10 output [8:0] count; 11 reg [8:0] count; 12 13 initial 14 count<=0; 15 16 always@( posedge clock or negedge reset) begin 17 if ( ~reset ) 18 count = 0; 19 else 20 count= count + 1; 21 end 22 endmodule
nLint reports following if the argument value is ("IGNORE_LIB_CELL"): document.v(5): Warning 21025: port "counti" and its connection "count" should be similar. (Naming Convention) document.v(5): Warning 21025: port "RESET" and its connection "reset" should be similar. (Naming Convention)
document.v(5): Warning 21025: port "clk" and its connection "ck" should be similar. (Naming Convention) document.v(8): Warning 21025: port "clk" and its connection "clock" should be similar. (Naming Convention)
21027 Register Output Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: register ouput name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_r" for Verilog, "SUFFIX","_r" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the register output signals have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (clk, datain, dataout); input clk, datain; output dataout; reg dataout; always @( posedge clk ) dataout = datain; //warning on 'dataout', 'dataout_r' recommended endmodule
nLint reports following if the argument value is ("SUFFIX","_r"): document.v(6): Warning 21027: register ouput name "dataout" does not match to regular expression ".*_r". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity top_ety is port ( reset : in bit; clock : in bit; d: in bit; q: out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then q<='0'; --warning on 'q', 'q_r' recommended elsif (clock'event and clock='1') then q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_r"): document.vhd(14): Warning 21027: register ouput name "q" does not match to regular
expression ".*_r". (Naming Convention)
21029 Asynchronous Signal Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: asynchronous signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_a" for Verilog, "SUFFIX","_a" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the asynchronous signals have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (clk,rst_pa,count); input clk,rst_pa; output[7:0] count; reg[7:0] count; reg[7:0] nextCount; always @(posedge clk or posedge rst_pa) if (rst_pa) //using _p for active high //reset as well as _a for //asynchronous reset count <= 0; else count <= nextCount; endmodule
nLint reports following if the argument value is ("SUFFIX","_a"): document.v(8): Warning 21029: asynchronous signal name "rst_pa" does not match to regular expression ".*_a". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is port ( reset : in bit; clock : in bit; d: in bit; q: out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then --using _p for active high reset --as well as _a for asynchronous reset q<='0'; elsif (clock'event and clock='1') then
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q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_a"): document.vhd(13): Warning 21029: asynchronous signal name "reset" does not match to regular expression ".*_a". (Naming Convention)
21031 Tri-state Signal Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: tri-state ouput signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_z" for Verilog, "SUFFIX","_z" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the tri-state output signals have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (q, rst, en, d); input rst, d, en; output q; reg q; //warning on 'q', 'q_z' is recommended always @(en or rst or d) begin if (~rst) q <= 0; else if ( en ) q <= d; else q <= 'bz; end endmodule
nLint reports following if the argument value is ("SUFFIX","_z"): document.v(9): Warning 21031: tri-state ouput signal name "q" does not match to regular expression ".*_z". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( enable : in bit; d: in std_ulogic; q: out std_ulogic ); end entity top_ety; architecture arch of top_ety is begin p1: process (enable,d) is begin
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if (enable='1') then q<=d; --warning on 'q', 'q_z' is recommended else q<='Z'; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_z"): document.vhd(16): Warning 21031: tri-state ouput signal name "q" does not match to regular expression ".*_z". (Naming Convention)
21035 Register Input Signal Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: register input signal name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_nxt" for Verilog, "SUFFIX","_nxt" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the register input signals have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (clock, datain, q); input clock, datain; output q; reg q; always @(posedge clock) q = datain; //warning on 'datain', 'datain_nxt' is recommended endmodule
nLint reports following if the argument value is ("SUFFIX","_nxt"): document.v(7): Warning 21035: register input signal name "datain" does not match to regular expression ".*_nxt". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity top_ety is port ( reset : in bit; clock : in bit; d: in bit; q: out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then q<='0'; elsif (clock'event and clock='1' ) then q<=d; --warning on 'd', 'd_nxt' is recommended end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_nxt"):
document.vhd(16): Warning 21035: register input signal name "d" does not match to regular expression ".*_nxt". (Naming Convention)
21041 (Verilog) Parameter Name Case 21041 (VHDL) GENERIC Name Case
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: parameter "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: GENERIC "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_UPPER" for Verilog, "CASE_UPPER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the parameters are all in upper (or lower) case. (VHDL) This rule checks whether the generics are all in upper (or lower) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (clock, reset, control, y); input clock, reset, control; output [2:0] y; parameter st0 = 0; //warning on st0; ST0 is recommended reg [1:0] current, next; endmodule
nLint reports following if the argument value is ("CASE_UPPER"): document.v(5): Warning 21041: parameter "st0" should be named in CASE_UPPER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is generic (n: integer := 10; --warning on 'n', 'N' is recommended M: bit :='0' ); begin end top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports following if the argument value is ("CASE_UPPER"): document.vhd(2): Warning 21041: GENERIC "n" should be named in CASE_UPPER case. (Naming Convention)
21043 (Verilog) More than One Module Declared in a File 21043 (VHDL) More than One Primary Unit in a File
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: only one module can be declared in a file, modules: "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: only one primary unit can be declared in a file, primary units: "%s". Configurable Parameter Rule group: Coding Style; Argument type: (CHECK_LOCALTOP_ONLY, CHECK_ALL_MODULE); Argument description: select CHECK_ALL_MODULE to check all modules in a file;select CHECK_LOCALTOP_ONLY to check only local top modules in a file; Default value: "CHECK_ALL_MODULE" for Verilog, "CHECK_ALL_MODULE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether each source file contains only one module.If argument CHECK_ALL_MODULE is selected,all modules will be checked. While if argument CHECK_LOCALTOP_ONLY is selected,only local top modules will be checked, and all other modules will be ignored. Local top module means the first hierarchy module comparing with others in the same file. Under argument CHECK_LOCALTOP_ONLY,if more than one local top module is defined in a file,this rule will be violated; if more than one module is defined,but only one is local top module,this rule will not be violated. (VHDL) This rule checks whether each source file contains only one primary unit (package, entity, configuration). Example
(Verilog) ///////////////example : document.v//////////// 1 //only one local top module is defined in the file 2 //specify argument CHECK_LOCALTOP_ONLY, so 21043 does not report any warning 3 module testini; 4 wire a,b,c; 5 test u_test_0 (a,b,c); 6 endmodule 7 8 module test(a,b,c); 9 input a,b; 10 output c; 11 and and1 (c,a,b); 12 endmodule 13
nLint reports following if the argument value is ("CHECK_LOCALTOP_ONLY"):
(VHDL) -------------------example : document.vhd------------1 2 3 library IEEE; use IEEE.std_logic_1164.all;
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entity EA is --warning on 'EA' end entity EA; architecture arch of EA is begin end architecture arch; entity top_ety is --warning on 'top_ety' end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports following if the argument value is ("CHECK_ALL_MODULE"): document.vhd(1): Warning 21043: only one primary unit can be declared in a file, primary units: "ea, top_ety, ...". (Coding Style)
21044 (Verilog) Module Name Different from File Name 21044 (VHDL) Primary Unit Name Different from File Name
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: module name "%s" should be same as file name. (VHDL) <filename>(<line no.>): <severity> <rule no.>: primary unit name "%s" should be same as file name. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the module name is the same as the file name. This rule is associated with the rule 21043. If the original design violates 21043,this rule will be ignored and nLint only report rule 21043. (VHDL) This rule checks whether the file name is the same as the primary unit (entity, package) name . Example
(Verilog) ///////////////example : document.v//////////// 1 will 2 3 4 5 6 7 8 9 10 11 12 13 14 15 //in rs file, specify agrument CHECK_LOCALTOP_ONLY for rule 21043,so nLint //only check local top module //in current file, there is only one local top module is declared, //that is "testini", so 21043 is not violated and 21044 will report warning module testini; wire a,b,c; test u_test_0 (a,b,c); endmodule module test(a,b,c); input a,b; output c; and and1 (c,a,b); endmodule
nLint reports: document.v(6): Warning 21044: module name "testini" should be same as file name. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 -- File Name document.vhd entity top_ety is --warning on 'top_ety' end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports: document.vhd(2): Warning 21044: primary unit name "top_ety" should be same as file name. (Coding Style)
21045 File Name Too Long

Message <filename>(<line no.>): <severity> <rule no.>: the length of file name "%s" should not exceed %d.%d characters. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: for the first argument, specify the maximum number of characters in file base name; for the second argument, specify the maximum number of characters in file extension name; Default value: "8","3" for Verilog, "8","3" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the length of the file name exceeds 8.3 characters (file name: 8, file type: 3) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 //the file name document.v is satisfied module document(); endmodule
nLint reports following if the argument value is ("8","3"): ///////////////example : document.verilog//////////// 1 2 3 4 //File: document.verilog //the extension is too long module test(); endmodule
nLint reports following if the argument value is ("8","3"): document.verilog(1): Warning 21045: the length of file name "document.verilog" should not exceed 8.3 characters. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 --the file name document.vhd is satisfied entity top_ety is end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("8","3"): -------------------example : document123.vhdl------------1 2 -- File: document123.vhdl --do not use such filename. entity top_ety is
3 4 5 6 7
end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("8","3"): document123.vhdl(1): Warning 21045: the length of file name "document123.vhdl" should not exceed 8.3 characters. (Naming Convention)
21047 (Verilog) Names Easy to Get Confused

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s name "%s" is confusing%s and should not be used. Configurable Parameter Rule group: Naming Convention; Argument type: string; Argument description: 1. The argument is a list of comparison set, which is separated by semicolon. 2. In each set, every item is separated by comma. 3. If there's only one item in the set, the rule will be reported only if the identifier name match the item string exactly; Default value: "O,0;I,1,l" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any confusing name. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 //vlog_val="a1,a2,a3; b1,b2; c1,c2; o" module test; reg ta1m; reg ta2m; //warning, confusing with "ta1m" reg o; //warning, the signal name is confusing itself test1 tb1m(); test1 tb2m(); test1 ta3m();
//warning, confusing with "tb1m" //no warning, although confusing with "ta1m" //but "ta1m" is signa, and "ta3m" is instance
function integer aa1; ; endfunction task aa2; //warning, confusing with "aa1" ; endtask always begin :ba1 end always begin :ba2 end endmodule module test1; endmodule
//warning, confusing with "ba1"
nLint reports following if the argument value is ("a1,a2,a3; b1,b2; c1,c2; o"): document.v(4): Warning 21047: signal name "ta2m" is confusing with "ta1m", and should not be used. (Naming Convention) document.v(5): Warning 21047: signal name "o" is confusing, and should not be used. (Naming Convention) document.v(8): Warning 21047: instance name "tb2m" is confusing with "tb1m", and should not be used. (Naming Convention) document.v(15): Warning 21047: procedure name "aa2" is confusing with "aa1", and should not be used. (Naming Convention) document.v(21): Warning 21047: block name "ba2" is confusing with "ba1", and should not be used. (Naming Convention)
21049 Process Label Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: process name "%s" does not match regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_PROC" for Verilog, "SUFFIX","_PROC" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the process label names have the recommended prefix or suffix. Process here means initial, always (always_comb, always_ff and always_latch are inclusive) and generate (gen-for, gen-if and gen-case are inclusive) statements. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (clk,rst_p,q); inout clk,rst_p; output q; reg q; reg q_nxt; always @(posedge clk) begin: Dff_PROC //a meaningful name is attached on process if ( rst_p ) q = 0; else q = q_nxt; end endmodule
nLint reports following if the argument value is ("SUFFIX","_PROC"):
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is end entity top_ety; architecture arch of top_ety is begin p1: process is --warning on 'p1', using a meaningful name --like XXX_PROC begin wait; end process; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_PROC"): document.vhd(9): Warning 21049: process name "p1" does not match regular expression ".*_PROC". (Naming Convention)
21050 Missing Process Label Name

Message <filename>(<line no.>): <severity> <rule no.>: process should be named. Configurable Parameter Rule group: Naming Convention; Argument type: (INITIAL, ALWAYS, ALWAYS_COMB, ALWAYS_FF, ALWAYS_LATCH, GENERATE, IF); Argument description: select expected arguments to enable corresponding language constructs; Default value: "INITIAL, ALWAYS, ALWAYS_COMB, ALWAYS_FF, ALWAYS_LATCH, GENERATE, IF" for Verilog, "" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the process block is given a name explicitly. Process here means initial, always (always_comb, always_ff and always_latch are inclusive), generate (gen-for, gen-if and gen-case are inclusive) and if statements. This rule does not check processes without "begin ... end" blocks as there would be too many violations. For example, "always a = 0;" is not treated as a violation, but "always begin a = 0; end" is treated as a violation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (clk); input clk; always @(posedge clk) begin //warning here( should name the out-most begin-end block) //...... end endmodule
nLint reports following if the argument value is ("INITIAL, ALWAYS, ALWAYS_COMB, ALWAYS_FF, ALWAYS_LATCH, GENERATE, IF"): document.v(4): Warning 21050: process should be named. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is end entity top_ety; architecture arch of top_ety is begin process --warning here( should name the process) begin wait; end process; end architecture arch;
nLint reports following if the argument value is (""): document.vhd(9): Warning 21050: process should be named. (Naming Convention)
21051 Instance Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: module instance name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","U_" for Verilog, "PREFIX","U_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the name of module instance has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module top (c,a,b); input a, b; output c; block test_0(c, a, b); //warning on test_0, suggest to use u_test_0 endmodule module block (c, a, b); input a, b; output c; endmodule
nLint reports following if the argument value is ("PREFIX","U_"): document.v(5): Warning 21051: module instance name "test_0" does not match to regular expression "U_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 library IEEE; use IEEE.std_logic_1164.all; entity EA is end EA; architecture arch of EA is begin end arch; entity top_ety is end entity top_ety; architecture arch of top_ety is component EA end component EA; begin u: component EA; --warning on 'u', using 'u_EA_0' instead end architecture arch;
nLint reports following if the argument value is ("PREFIX","U_"): document.vhd(18): Warning 21051: module instance name "u" does not match to regular expression "U_.*". (Naming Convention)
21053 (Verilog) Gate Name Prefix or Suffix

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: gate or primitive instance name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","gate_" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the name of gate or primitive instance has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test (a, b, c); input a, b; output c; and and1(c, a, b); //warning on 'and1' endmodule
nLint reports following if the argument value is ("PREFIX","gate_"): document.v(4): Warning 21053: gate or primitive instance name "and1" does not match to regular expression "gate_.*". (Naming Convention)
21055 (Verilog) Identical Module Name and Instance Name

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: instance name "%s" should not be the same as the module name. Configurable Parameter Rule group: Naming Convention; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any module instantiation statement in which the instance name and the module name are the same. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module top (o, a, b); input a, b; output o; test test(o, a, b); //instance name should not be //the same as module name, //"u_test_1" is recommended endmodule module test (o, a, b); input a, b; output o; and and1 (o,a,b); endmodule
nLint reports: document.v(4): Warning 21055: instance name "test" should not be the same as the module name. (Naming Convention)
21057 Use the Same Name for All Clocks from Same Source
Message <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" is not named same or similar with the name of clock source "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR); Argument description: select PREFIX to specify that the clock signal should be named with clock source name as prefix; select SUFFIX to specify that the clock signal should be named with clock source name as suffix; select SUB_STRING to specify that the clock signal should be named with clock source name as sub-string; Default value: "PREFIX" for Verilog, "PREFIX" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any clock signal is not named the same or similar with its clock source. This rule will be only checked after clock domain is available. Only the resolved clock domain will be checked. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module MyReg (cp, in, out); input cp, in; output out; reg out; always @ ( posedge cp ) begin out = in; end endmodule module test (clk, in, out); input clk, in; output out; MyReg i_reg ( clk, in, out ); endmodule
nLint reports following if the argument value is ("PREFIX"): document.v(2): Warning 21057: clock signal "test.i_reg.cp" is not named same or similar with the name of clock source "test.clk". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 library ieee; use ieee.std_logic_1164.all; entity top_ety is port(clock : in std_logic; reset : in std_logic; data_in : in std_logic; data_out : out std_logic ); end;
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
architecture arch of top_ety is signal clock_b : std_logic; -- warning here begin process (clock_b, reset) begin if (reset = '0' ) then data_out <= '0'; elsif ( clock_b'event and clock_b = '1' ) then data_out <= data_in; end if; end process; clock_b <= not(clock); end; -- rs: vhdl_val = SUFFIX
nLint reports: document.vhd(12): Warning 21057: clock signal "top_ety.clock_b" is not named same or similar with the name of clock source "top_ety.clock". (Naming Convention)
22001 Signal with Multiple Drivers

Message <filename>(<line no.>): <severity> <rule no.>: multiple drivers for signal "%s" are detected. Configurable Parameter Rule group: Design Style, DFT; Argument type: (CHECK_FLOATING, IGNORE_FLOATING); Argument description: If a signal is driven by a floating net, which only has net assignments but no driving instance, user may enable IGNORE_FLOATING option to invalidate the floating net as a driver. Alternatively, user may enable CHECK_FLOATING option to treat floating net as a driver; Default value: "IGNORE_FLOATING" for Verilog, "IGNORE_FLOATING" for VHDL; Default severity : Level3 (Error) Description This rule checks for the existence of signal with multiple drivers. The checking is only applied to synthesizable source code. Non-synthesizable constructs, such as initial blocks, will be ignored. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module test (a, b, c, d); input b, c, d; output a; wire a; //mulltiple driver detected wire z; //driven by floating net assign a = b; nand u_n1(a, c, d); sub u1(.Z(z)); sub u2(.Z(z)); endmodule module sub(Z); output Z; //here the output port 'Z' is floating endmodule //The second warning shows if the argument is set to if choose //CHECK_FLOATING. //Alternatively, if the argument is set to CHECK_FLOATING, //the message won't be shown
nLint reports following if the argument value is ("CHECK_FLOATING"): document.v(4): Error 22001: multiple drivers for signal "a" are detected. (DFT) document.v(5): Error 22001: multiple drivers for signal "z" are detected. (DFT)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is end entity top_ety; architecture signal s0: signal s1: signal s2: signal en: begin arch of top_ety is std_logic:='0'; std_logic:='0'; std_logic:='0'; --multiple driver detected on 's2' std_logic;
13 14 15 16 17 18 19 20 21 22 23 24 25 26
p1: process(s0,en) is begin if (en = '1') then s2<=s0; end if; end process p1; p2: process(s1,en) is begin if (en = '1') then s2<=s1; end if; end process p2; end architecture arch;
nLint reports following if the argument value is ("IGNORE_FLOATING"): document.vhd(10): Error 22001: multiple drivers for signal "s2" are detected. (DFT,Design Style)
22002 Three-state Net Not Properly Driven

Message <filename>(<line no.>): <severity> <rule no.>: three-state net "%s" is not properly driven. Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description This rule checks whether any three-state net is not properly driven. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (i1, i2, e, o); input i1, i2, e; output o; assign o = i1; assign o = e ? i2 : 1'bz; //warning on "o" endmodule
nLint reports: document.v(3): Error 22002: three-state net "o" is not properly driven. (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library ieee; use ieee.std_logic_1164.all; entity top_ety is port(e : in std_logic; d1 : in std_logic; d2 : in std_logic; q : out std_logic); end top_ety; architecture arch of top_ety is begin q <= d2; process(e, d1) is begin if (e = '1') then q <= d1; else q <= 'Z'; end if; end process; end arch;
nLint reports: document.vhd(8): Error 22002: three-state net "q" is not properly driven. (DFT,Design Style)
22003 Bit Width Mismatch in Assignment

Message <filename>(<line no.>): <severity> <rule no.>: bit width of left-hand-side variable "%s"(%d) does not match that of right-hand-side variable "%s"(%d) in the assignment. Configurable Parameter Rule group: Language Construct; Argument type: (LHS_EQ_RHS, LHS_GE_RHS) (VAR_EQ_CON, VAR_GE_CON); Argument description: The first argument allows users to specify the bit width constraint of assignments. LHS_EQ_RHS indicates that bit width of variables on left-hand and right-hand side of assignment must be equal, and LHS_GE_RHS indicates that the bit width of LHS variable can be greater than or equal to the bit width of RHS variable; The second argument is valid when the first argument is LHS_EQ_RHS and RHS variable is a constant expression. Select VAR_EQ_CON to specify that the bit width of LHS equal to the bit width of RHS(constant expression); select VAR_GE_CON to specify that the bit width of LHS greater than or equal to the bit width of RHS(constant expression); Default value: "LHS_GE_RHS","VAR_GE_CON" for Verilog, "LHS_GE_RHS","VAR_GE_CON" for VHDL; Default severity : Level3 (Error) Description This rule checks whether there is any bit width mismatch in the assignment statements. This rule ignores the checking for integer loop variables in for-loops, real, realtime, time, access, sub-type of integers. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; wire [3:0] a; wire [2:0] b; assign a = b; //warning on "a" and "b" endmodule
nLint reports following if the argument value is ("LHS_EQ_RHS"): document.v(5): Error 22003: bit width of left-hand-side variable "a"(4) does not match that of right-hand-side variable "b"(3) in the assignment. (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 library IEEE; use IEEE.STD_Logic_1164.all,IEEE.Numeric_STD.all; entity top_ety is end entity top_ety; architecture arch of top_ety is signal A : bit_vector(1 downto 0); signal B : bit_vector(2 downto 0); begin process( A ) begin B <= A; -- warning here end process; end architecture arch;
nLint reports following if the argument value is ("LHS_EQ_RHS" ):
22004 Bit Width Mismatch in Bitwise Operation

Message <filename>(<line no.>): <severity> <rule no.>: bit width of operand "%s"(%d) does not match that of operand "%s"(%d) in bitwise operation. Configurable Parameter Rule group: Language Construct; Argument type: (VAR_EQ_CON, VAR_GE_CON); Argument description: If either one operand of bitwise operation is a constant, the argument can specify the bit width checking for constant and variable operands. VAR_EQ_CON specifies that the bit width of variable operand must be equal to the bit width of constant operand. VAR_GE_CON specifies that the bit width of variable operand can be greater than or equal to the bit width of constant operand. Note: this argument is only for Verilog; Default value: "VAR_GE_CON" for Verilog, "VAR_GE_CON" for VHDL; Default severity : Level3 (Error) Description This rule checks whether any bit widths mismatch between operands of a bitwise operation. Note that the checking will not be done if both two operands are constants. If one of the operand is a constant, the checking will be done based on the rule argument setting. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (result, a, b); input [2:0] a; input [3:0] b; output [3:0] result; reg [3:0] result; always @(a or b) result = a & b; //warning on "a" and "b" endmodule
nLint reports following if the argument value is ("VAR_GE_CON"): document.v(8): Error 22004: bit width of operand "a"(3) does not match that of operand "b"(4) in bitwise operation. (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 library IEEE; use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; entity top_ety is port ( Bus1: in unsigned(5 downto 0) ); end top_ety; architecture arch of top_ety is signal Bus2: unsigned(23 downto 0); signal Bus12: unsigned(5 downto 0); begin PRC1: process (Bus1, Bus2) begin Bus12 <= Bus1 and Bus2; -- warning on "Bus1" and "Bus2" end process PRC1; end arch;
nLint reports following if the argument value is ("VAR_GE_CON"): document.vhd(16): Error 22004: bit width of operand "Bus1"(6) does not match that of operand "Bus2"(24) in bitwise operation. (Language Construct)
22005 Loss of Significant Bit

Message <filename>(<line no.>): <severity> <rule no.>: significant bit of operand "%s" lost due to mismatched width assignment or shift operation. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: (CONSTANT, VARIABLE); Argument description: The argument allows users to limit the checking on shift operations with different types of operands. CONSTANT limits the checking on the data loss of shift operation with left-hand side constant operand. VARIABLE limits the checking on the data loss of shift operation with left-hand side variable operand; Default value: "CONSTANT" for Verilog, "CONSTANT" for VHDL; Default severity : Level3 (Error) Description This rules checks whether there is any significant bit loss due to mismatched width assignment or shift operations. Example
(Verilog) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (b, a); parameter WIDTH = 3; input [WIDTH-1:0] a; output [WIDTH-2:0] b; reg [WIDTH-1:0] b; wire [1:0] c; assign c = 7; //warning on "7" always @(a) b = a; endmodule
nLint reports following if the argument value is ("CONSTANT"): document1.v(8): Error 22005: significant bit of operand "7" lost due to mismatched width assignment or shift operation. (Simulation,Language Construct) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 module test (clk, y); input clk; output [7:0] y; reg [7:0] y; parameter a = 8'b00111101; always @(posedge clk) y = a << 3; //warning on "a" endmodule
nLint reports following if the argument value is ("CONSTANT"): document2.v(7): Error 22005: significant bit of operand "a" lost due to mismatched width assignment or shift operation. (Simulation,Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 entity top_ety is end top_ety; architecture arch of top_ety is
5 6 7 8 9 10 11 12
signal C : bit_vector(1 downto 0); begin process begin C <= 6; -- warning here end process; end arch;
nLint reports following if the argument value is ("CONSTANT"):
22006 (Verilog) Significant Bits Extended by X/Z/?

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: x/z/? used to extend the significant bits of constant "%s". Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there is an x, a z or a "?" padding to the significant bits of a constant value. This is due to the leftmost bit specified to a constant is an x, a z or a "?" (e.g. 8'bx101). Then an x, a z or a "?" shall be used to pad to the left respectively (e.g. 8'bxxxx_x101). Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; wire [7:0] a; wire b; assign a = 8'bx001; //warning endmodule
nLint reports: document.v(5): Warning 22006: x/z/? used to extend the significant bits of constant "8'bx001". (Simulation,Language Construct)
22007 Constant Connected to Instance

Message <filename>(<line no.>): <severity> <rule no.>: port should not be connected to a constant "%s". Configurable Parameter Rule group: Design Style, DFT; Argument type: (INPUT, OUTPUT, INOUT); Argument description: three argument values INPUT,OUTPUT and INOUT can be selected independently, which respectively indicates input port or output port or inout port connecting to constant. Default is INPUT and OUTPUT enable; Default value: "INPUT,OUTPUT" for Verilog, "INPUT,OUTPUT" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any constant is directly connected to a port of instance. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; wire a; wire c; and and1(c, a, 1); //warning on "1" as port instance; //it can be reduced to c=a; endmodule
nLint reports following if the argument value is ("INPUT,OUTPUT"): document.v(4): Warning 22007: port should not be connected to a constant "1". (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 library IEEE; use IEEE.std_logic_1164.all; entity Com is port (s1:in bit; s2: in bit; s3: out bit); end Com; architecture arch of Com is begin process begin s3 <= s1 & s2; end process; end arch; entity top_ety is end entity top_ety; architecture signal s1: signal s2: signal s3: arch of top_ety is bit:='0'; bit:='0'; bit:='0';
component Com is port (s1:in bit; s2: in bit; s3: out bit); end component Com; begin u_Com_0: component Com
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port map (s1=>s1, s2=>'0', --warning on "0" as actual part s3=>s3); end architecture arch;
nLint reports following if the argument value is ("INPUT,OUTPUT"): document.vhd(30): Warning 22007: port should not be connected to a constant "0". (DFT,Design Style)
22008 (Verilog) Expression Connected to an Instance Port

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the instance port is connected to an expression "%s". Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether any logic expressions are used in any port connections. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test; wire a,b1,b2; wire c; and and1(c, a, b1+b2); //warning on "b1+b2" as port instance; endmodule
nLint reports: document.v(4): Warning 22008: the instance port is connected to an expression "(b1 + b2)". (DFT,Design Style)
22009 (Verilog) Non-zero Bit(s) Truncated

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: non-zero bit(s) truncated by the size specified in literal "%s". Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule checks whether there is (are) any non-zero significant bit(s) of a sized constant being truncated. This is due to the size specified for the constant is smaller than the value given to the constant. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test (ok,ow,i,j); output [6:0] ok,ow; input i; input [6:0] j; reg [6:0] ok,ow; always @(i or j) if (i == 1'b1) begin ok [6:0] = 7'h7F; // Zero bit(s) truncated is OK ow [6:0] = 7'hFE; // warning on "7'hFE" end else begin ok [6:0] = j; ow [6:0] = j; end endmodule
nLint reports: document.v(11): Error 22009: non-zero bit(s) truncated by the size specified in literal "7'hFE". (Simulation,Language Construct)
22010 Latch to Latch Connected should be Enabled in Different Phase

Message <filename>(<line no.>): <severity> <rule no.>: latch "%s"(%s(%d)) to latch "%s" should be enabled in different phase. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule requires that any connection between latches should be enabled in different phase. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module top (a3); output a3; wire [1:0] tri_,latch; wire c; wire a1; sub s1(latch[0], c, a2); assign a1=a2; sub s2(latch[0], a1, a3); endmodule module sub (latch , c, q); input latch, c; output q; wire latch, c; reg q; always @(latch or c) begin if(latch) begin q=c; end end endmodule
nLint reports: document.v(16): Warning 22010: latch "top.s1.q"(document.v(16)) to latch "top.s2.q" should be enabled in different phase. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 library ieee; use ieee.std_logic_1164.all; entity sub is port (latch, c: in std_logic; q : out std_logic); end sub; architecture arch of sub is begin Process (latch, c) begin if (latch = '1') then q <= c; end if; end Process;
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end arch; library ieee; use ieee.std_logic_1164.all; entity top_ety is port (a3: out std_logic ); end top_ety; architecture arch of top_ety is component sub port (latch, c : in std_logic; q : out std_logic); end component; signal a1, a2, c : std_logic; signal tri, latch : std_logic_vector(1 downto 0); begin sub1 : sub port map (latch => latch(0), c => c, q => a2); sub2 : sub port map (latch => latch(0), c => a1, q => a3); a1 <= a2; end arch;
nLint reports: document.vhd(11): Warning 22010: latch "top_ety.sub1.q"(document.vhd(11)) to latch "top_ety.sub2.q" should be enabled in different phase. (Design Style)
22011 Combinational Loop

Message <filename>(<line no.>): <severity> <rule no.>: combinational loop is detected on signal "%s". Configurable Parameter Rule group: Design Style, DFT, Simulation; Argument type: (COMB, SYNC); Argument description: The argument allows users to treat a latch as a synchronization logic or not. Select COMB to regard a latch as a combinational logic. Select SYNC to regard a latch as a synchronization logic; Default value: "SYNC" for Verilog, "SYNC" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether there is any combinational loop in the design. The combinational loop may cause improper timing loop when doing static timing analysis. Note that the argument setting for this rule controls the behavior of 22013, 22014, 25016 as well. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; reg b; wire a, c; assign a = c; and and1(c, a, b); //warning on "c->a->c" endmodule
nLint reports following if the argument value is ("SYNC"): document.v(5): Warning 22011: combinational loop is detected on signal "test.c". (Simulation,DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 entity com_T is port (a1 : in bit; a2 : out bit ); end entity com_T; architecture arch of com_T is begin a2<=a1; end architecture arch; use work.all; entity top_ety is port (s1 : in bit; s2 : out bit ); end entity top_ety; architecture arch of top_ety is signal x : bit; signal y : bit; component com_T is port (a1 : in bit; a2 : out bit );
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end component com_T; begin u0: component com_T port map (a1=>x,a2=>y); process (s1) is begin x<=y; --warning on 'x->y->x' s2<=s1 and x; end process; end architecture arch;
nLint reports following if the argument value is ("SYNC"): document.vhd(30): Warning 22011: combinational loop is detected on signal "top_ety.x". (Simulation,DFT,Design Style)
22012 Bit Width Mismatch between Module Port and Instance Port
Message <filename>(<line no.>): <severity> <rule no.>: instant port size "%s"(%d) differs from module port declaration "%s"(%d). Configurable Parameter Rule group: Language Construct; Argument type: (VAR_EQ_CON, VAR_GE_CON); Argument description: The argument allows users to loosen the mismatch checking. Setting the argument to VAR_GE_CON allows bit width of module port to be greater or equal to instance port. Otherwise, default argument VAR_EQ_CON teats any bit width mismatch as a violation; Default value: "VAR_EQ_CON" for Verilog, "VAR_EQ_CON" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether there is any mismatch of bit width between instance port and its connected module port. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module Example7_16b_ff (q, ck, d); // synopsys template parameter w = 1; input ck; input [w-1:0] d; output [w-1:0] q; reg [w-1:0] q; always @(posedge ck) q <= d; endmodule // Example7_16b_ff module Example7_16b (r_head, r_head2, ck, c_head); output [3:0] r_head; output [3:0] r_head2; input ck; input [3:0] c_head; Example7_16b_ff #(3) reg_head ( .d(c_head), .ck(ck), .q(r_head)); Example7_16b_ff #(5) reg_head2 ( .d(c_head), .ck(ck), .q(r_head2)); endmodule // Example7_16b //warning
//warning
nLint reports following if the argument value is document.v(18): Warning 22012: instant port size port declaration "q"(3). (Language Construct) document.v(18): Warning 22012: instant port size port declaration "d"(3). (Language Construct) document.v(23): Warning 22012: instant port size port declaration "q"(5). (Language Construct) document.v(23): Warning 22012: instant port size port declaration "d"(5). (Language Construct)
("VAR_EQ_CON"): "r_head"(4) differs from module "c_head"(4) differs from module "r_head2"(4) differs from module "c_head"(4) differs from module
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 library ieee; use ieee.std_logic_1164.all; entity rom0 is generic (N : integer := 1); port (dout : out std_logic_vector(N downto 0)); end; architecture arch of rom0 is begin end; library ieee; use ieee.std_logic_1164.all; entity top_ety is end; architecture arch of top_ety is component rom0 generic (N : integer := 1); port( dout: out std_logic_vector(N downto 0)); end component; signal i_dff300_creg_l304_1_port : std_logic_vector(3 downto 0); begin i_rom0 : rom0 generic map (N => 2) port map (dout =>i_dff300_creg_l304_1_port); --warning i_rom1 : rom0 generic map (N => 4) port map (dout =>i_dff300_creg_l304_1_port); --warning end;
nLint reports following if the argument value is ("VAR_EQ_CON"): document.vhd(26): Warning 22012: instant port size "i_dff300_creg_l304_1_port"(4) differs from module port declaration "dout"(3). (Language Construct) document.vhd(28): Warning 22012: instant port size "i_dff300_creg_l304_1_port"(4) differs from module port declaration "dout"(5). (Language Construct)
22013 Asynchronous Loop

Message <filename>(<line no.>): <severity> <rule no.>: asynchronous loop detected on signal "%s". Configurable Parameter Rule group: Design Style, DFT, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any asynchronous loops in the design. It is determined by the option of 22011 for either the latch is treated as synchronous or asynchronous. For performance consideration, the warning number of this rule is limit to 10 by default. The number can be modified by command line option -max_loop. The same scheme also apply to rSyncLoop and rCriticalPathBetweenReg. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module test (count, clk); parameter number = 10; output [3:0] count; input clk; reg [3:0] count; reg i_rst; always @(posedge clk or posedge i_rst) //warning on //"count->i_rst->count" if ( i_rst ) count <= 0; else count <= count + 1; always @( count ) if ( count == number ) i_rst = 1; else i_rst = 0; endmodule
nLint reports: document.v(16): Warning 22013: asynchronous loop detected on signal "test.count". (Simulation,DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is port (clk : in bit; count : out integer); end entity top_ety; architecture arch of top_ety is signal i_rst: bit:='0'; signal c: integer:=0; begin p1 : process (i_rst, clk) begin if (i_rst = '1') then c <= 0; elsif (clk'event and clk = '1') then c <= c + 1;
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end if; end process p1; p2: process ( c ) is begin if (c >= 10) then i_rst <= '1'; --warning on 'i_rst->c->i_rst' else i_rst <= '0'; end if; count<=c; end process; end architecture arch;
nLint reports: document.vhd(21): Warning 22013: asynchronous loop detected on signal "top_ety.c". (Simulation,DFT,Design Style)
22014 Synchronous Loop

Message <filename>(<line no.>): <severity> <rule no.>: synchronous loop without set/reset detected on signal "%s". Configurable Parameter Rule group: Design Style, DFT, Simulation; Argument type: (TRUE, FALSE); Argument description: If the argument is true, nLint will check if there exists any fanin in the logic cone of register input other than the state itself. If it finds any other fanin, the loop will not be reported; Default value: "FALSE" for Verilog, "FALSE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any synchronous loops in which all the registers without set/reset. It is determined by the option of 22011 for either the latch is treated as synchronous or asynchronous. For performance consideration, the warning number of this rule is limit to 10 by default. The number can be modified by command line option -max_loop. The same scheme is also applied to 22269 and 22013. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (count, clk); parameter number = 10; output [3:0] count; input clk; reg [3:0] count; reg i_rst; always @(posedge clk) count <= count + 1; //warning here endmodule
nLint reports following if the argument value is ("FALSE"): document.v(9): Warning 22014: synchronous loop without set/reset detected on signal "test.count". (Simulation,DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is port (clk : in bit; count : out integer); end entity top_ety; architecture arch of top_ety is signal i_rst: bit:='0'; signal c: integer:=0; begin p1 : process (clk) begin if ( clk'event and clk = '1' ) then c <= c + 1; -- warning here end if; end process p1; count <= c;
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end architecture arch;
nLint reports following if the argument value is ("FALSE"): document.vhd(13): Warning 22014: synchronous loop without set/reset detected on signal "top_ety.c". (Simulation,DFT,Design Style)
22015 (Verilog) Zero Bit(s) Omitted

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: zero bit(s) omitted in literal "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any zero bit(s) omitted. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test ; wire clock ; reg a,b ; reg[1:0] c,d,e; wire reset ; always @(posedge clock) begin c <= 2'b1 ; // Want warning message that it should be 01 e <= 2'b01 ; // no warning d <= 2'b0 ; // no warning message is it is all 0 end endmodule
nLint reports: document.v(9): Warning 22015: zero bit(s) omitted in literal "2'b1". (Language Construct)
22016 (Verilog) Apparent Loop

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: apparent feedback detected on signal "%s". Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any apparent feedback in the design. The apparent loop is a superset of combinational loop of 22011. It is used on RTL design checking only. The difference to 22011 is that, it assumes that all inputs of always block will impact all outputs of the same always block, however in fact, an input of always block may not be related to an output of the always block. If there is any apparent loop in the design, it will degrade simulation performance by additional oscillation in simulator. To fix the problem, the designer needs to look into the path information provided by the engine and finds out the always block in which not all inputs are related to the outputs, and then divides the always block into small always blocks. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module test (a, d); input a; output d; reg b, d; wire c; always @(a or c) begin b = a; d = c; end assign c = a & b; endmodule //In above case, the change of 'c' will cause the always block be //evaluated again. Following is a way to fix the problem. module test2 (a, d); input a; output d; wire b, d; wire c; assign b = a; assign d = c; assign c = a & b; endmodule //After modification, the change of 'c' will only cause the assignment of //'d' to be evaluated again, which is expected.
nLint reports: document.v(9): Warning 22016: apparent feedback detected on signal "test.c". (Simulation) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 module test (a, d); input a; output d; reg b, d; wire c; always @(a or c) begin
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b = a; d = c; end assign c = a & b; endmodule //In above case, the change of 'c' will cause the always block be //evaluated again. Following is a way to fix the problem.
nLint reports: document1.v(9): Warning 22016: apparent feedback detected on signal "test.c". (Simulation) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (a, d); input a; output d; wire b, d; wire c; assign b = a; assign d = c; assign c = a & b; endmodule //After modification, the change of 'c' will only cause the //assignment of 'd' to be evaluated again, which is expected.
nLint reports:
22017 (Verilog) Module with No Output 22017 (VHDL) Entity with No Output
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: no output found for module "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: no output found for entity "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there are any modules without output ports. (VHDL) This rule checks whether there are any entities without output ports. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test (a, b, c); //no output for module test input a, b, c; endmodule
nLint reports: document.v(1): Warning 22017: no output found for module "test". (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is port (clk : in bit; reset : in bit); --warning here, no output port for --entity 'top_ety' end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports: document.vhd(1): Warning 22017: no output found for entity "top_ety". (Design Style)
22018 (Verilog) Logic '1' Used to Extend Significant Bits of Constants

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: logic '1' is used to extend the significant bits of constant "%s". Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether logic 1s are used to extend the significant bits of a constant. The extension is needed because the specified size is larger than the given bits for the constant. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test(); wire [7:0] a,b,c,d,e,f,g,h,i,j; assign a = 8'sb100; assign b = 8'b100; assign c = 8'sb011; assign d = 8'so10; assign e = 8'so40; assign f = 8'o40; assign assign assign assign endmodule g h i j = = = = 8'sh7; 8'sh8; 8'h7; 8'h8; // 1 extend // 0 extend // 0 extend // 0 extend // 1 extend // 0 extend // // // // 0 1 0 0 extend extend extend extend
nLint reports: document.sv(4): Warning 22018: logic '1' is used to extend the significant bits of constant "8'sb100". (Simulation,Language Construct) document.sv(9): Warning 22018: logic '1' is used to extend the significant bits of constant "8'so40". (Simulation,Language Construct) document.sv(13): Warning 22018: logic '1' is used to extend the significant bits of constant "8'sh8". (Simulation,Language Construct)
22019 (Verilog) Bit Index out of Bus Range

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: bit index "%s" is out of the declared bus range for signal "%s". Configurable Parameter Rule group: Language Construct, Simulation, Synthesis; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule checks whether bit index of a bus is out of bus range declared for the signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (a, b, c); input [1:0] a; input b; output c; reg c; always @(a) begin: test_PROC if (a[2]) //warning c = b; else c = 0; end endmodule
nLint reports: document.v(9): Error 22019: bit index "[2]" is out of the declared bus range for signal "a[2]". (Simulation,Synthesis,Language Construct)
22020 Multiple Tri-state Cause Potential Bus Contention

Message <filename>(<line no.>): <severity> <rule no.>: multiple tri-states detected on signal "%s". Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description Multiple drivers from tri-state buffer will possibly cause bus contention, it is recommended to avoid them. For example, no more than one output of the tri-state buffer drives the shared bus, no wired OR logic or wired AND logic is activated. However, for soft IP, only the tri- state devices will cause bus contention, so this rule is only defined to avoid tri-state devices. The engine will not report some determined cases, in which there is no bus contention. One is that the data source of all tri-state buffer comes from the same signal. In such case, even the enabled pin of the tri-state buffer is not well decoded, the output signal will not cause problem. The other is that there are two tri-state buffers and the enabled pin is logically inverted. For other un-determined cases, the engine will report warning message. Example
(Verilog) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 //Ex1 module test2 (sel1, sel2, a, b, out); input sel1, sel2, a, b; output out; wire out; //warning here assign out = sel1? a: 1'bz; assign out = sel2? b: 1'bz; endmodule
nLint reports: document1.v(5): Warning 22020: multiple tri-states detected on signal "out". (DFT) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 //Ex2 module test1 (sel1, sel2, a, out); input sel1, sel2, a; output out; wire out,temp; assign out = sel1? temp: 1'bz; //the data source is 'a' assign out = sel2? a: 1'bz; //the data source is also 'a', no warning assign temp = a; endmodule
nLint reports: ///////////////example : document3.v//////////// 1 2 3 4 5 //Ex3 module test4 (sel1, a, b, out); input sel1, a, b; output out; wire out, tmp;
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assign out = sel1? a: 1'bz; assign out = tmp? b: 1'bz; not (tmp, sel1); //the enable pin of 'sel1' and 'tmp' are //logically inverted, no warning. endmodule
nLint reports: ///////////////example : document4.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 of the 13 14 //Ex4 module test3 (sel1, sel2, a, b, TM, out); input sel1, sel2, a, b, TM; output out; wire tmp1, tmp2; not U_1(tmp1, TM); assign tmp2 = sel1 & tmp1; assign out = tmp2? a: 1'bz; assign out = sel2? b: 1'bz; endmodule //no warning, if we set TM as 1. the 'tmp2' becomes 0, thus one //driver will be high-impendence.
nLint reports:
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 library ieee; use ieee.std_logic_1164.all; entity top_ety is port (sel1: in std_logic; sel2: in std_logic; a: in std_logic; b: in std_logic; q: out std_logic); --warning here end top_ety; architecture arch of top_ety is begin process(sel1, a) is begin if (sel1 = '1') then q <= a; else q <= 'Z'; end if; end process; process(sel2, b) is begin if (sel2 = '1') then q <= b; else q <= 'Z'; end if; end process; end arch;
nLint reports: document.vhd(9): Warning 22020: multiple tri-states detected on signal "q". (DFT)
22021 Implicit and Confusing Operator Precedence

Message <filename>(<line no.>): <severity> <rule no.>: the operator precedence in the expression is suspicious; it is interpreted as "%s". Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any suspicious usage of implicit operator precedence. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (f1, f2, f3, a, b, c, d, e, f, g, h, i, j); input a, b, c, d, e, f, g, h, i, j; output f1, f2, f3; reg f1, f2, f3; always @(a or b or c or d or e or f or g or h or i or j) begin if ( a != b & c) //warning here, compiler regards as (a != b) & c f1 = a << 2 | b; //warning here, compiler regards as (a<<2)|b else f1 = b << 2 + c; //warning here, compiler regards as b<<(2+c) f3 = g + h ? i : j; //warning here, compiler regards as (g+h)?i:j end endmodule
nLint reports: document.v(8): Warning 22021: the operator precedence in the expression is suspicious; it is interpreted as "((a != b) & c)". (Coding Style) document.v(9): Warning 22021: the operator precedence in the expression is suspicious; it is interpreted as "((a << 2) | b)". (Coding Style) document.v(11): Warning 22021: the operator precedence in the expression is suspicious; it is interpreted as "(b << (2 + c))". (Coding Style) document.v(12): Warning 22021: the operator precedence in the expression is suspicious; it is interpreted as "((g + h) ? i : j)". (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity top_ety is port ( A : in bit_vector(3 downto 0); B : in bit_vector(3 downto 0); C : out integer; D : out bit_vector(3 downto 0) ); end top_ety; architecture arch of top_ety is begin process (A, B) begin if ( A /= (B or "1111") ) then -- good style C <= 5 + 2 ** 2; elsif ( (A or B) = "0000" ) then -- good style C <= 0; end if; D <= A and B sll 2; -- warning here;
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-- compiler treat it as "A and (B sll 2)" end process; end arch;
nLint reports: document.vhd(19): Warning 22021: the operator precedence in the expression is suspicious; it is interpreted as "(A and (B sll 2))". (Coding Style)
22022 (Verilog) Suspicious Use of Semicolon

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: suspicious usage of semicolon detected. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any suspicious usage of semicolons. Example
(Verilog) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 module initval; reg sel; reg [7:0] a,b,c; wire [7:0] y; initial begin $monitor($time,,,,,,,"sel=%d,a=%d,b=%d,c=%d,y=%d",sel, a, b, c, y); a<=12; b<=13; c<=14; sel<=1; #200 $finish; end always # 20 sel = ~sel; test cc (sel,a,b,c,y); endmodule module test (sel,a,b,c,y); input sel; input [7:0] a,b,c; output [7:0] y; reg [7:0] y; reg [7:0] temp; always@( sel or a or b or c) begin temp = 0; if ( sel ); //warning here temp = b; //else; // temp = c; y = a+temp; end endmodule
nLint reports: document1.v(29): Warning 22022: suspicious usage of semicolon detected. (Language Construct) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 module initval; reg sel; reg [7:0] a,b,c; wire [7:0] y; initial begin $monitor($time,,,,,,,"sel=%d,a=%d,b=%d,c=%d,y=%d",sel, a, b, c, y);
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
a<=12; b<=13; c<=14; sel<=1; #200 $finish; end always # 20 sel = ~sel; test cc (sel,a,b,c,y); endmodule module test (sel,a,b,c,y); input sel; input [7:0] a,b,c; output [7:0] y; reg [7:0] y; reg [7:0] temp; always@( sel or a or b or c) begin temp = 0; if ( sel ) temp = b; else; //warning here temp = c; y = a+temp; end endmodule
nLint reports: document2.v(31): Warning 22022: suspicious usage of semicolon detected. (Language Construct)
22023 More than One Statement per Line

Message <filename>(<line no.>): <severity> <rule no.>: Only one statement is allowed per line. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are multiple statements on a line. However, following items are exceptions: 1)"begin" is allowed on the line creating the block (if/always/generate block) 2)"end" is allowed with "else" and "else" with "begin", in any combination 3)Single-assignments are allowed with the generating block statement (if/always), but "begin <command> end" is flagged as a violator 4)For struct/union/enum type declaration, the first element declaration is allowed on the line creating the stuct/union/enum structure (VHDL) This rule checks whether there are multiple statements on a line. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 module test(a, b, c, d, e, clk, assignA, assignB, combA, combB, combC, combD, combE, alwaysA, alwaysB, alwaysC); input [7:0] c; input clk; output [7:0] assignA, assignB, combA, combB, combC, combD, combE, alwaysA, alwaysB, alwaysC; typedef struct{ logic [1:0] FFF1; //OK logic [1:0] FFF2; } t_my_struct ; logic en3, en4, combJ; assign assignA = c; assign assignB = c + 1; //WARNING always_comb begin combA = c; end //WARNING always_comb combB = c - 1; //OK always @(c) begin combC = c; //WARNING end always_comb begin combD = c + 3; end //WARNING always @(posedge clk) begin //OK alwaysA <= c - 1; alwaysC <=0; //WARNING end always_comb begin if (en3) begin //OK combJ = 0; end else if (en4) begin //OK combJ = 1; end else begin //OK combJ = 2; end end endmodule
nLint reports: document.sv(12): Style) document.sv(13): Style) document.sv(16): Style) document.sv(20):
Warning 22023: Only one statement is allowed per line. (Coding Warning 22023: Only one statement is allowed per line. (Coding Warning 22023: Only one statement is allowed per line. (Coding Warning 22023: Only one statement is allowed per line. (Coding
Style) document.sv(22): Warning 22023: Only one statement is allowed per line. (Coding Style) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (a, inc_dec, sum); input a, inc_dec; output [7:0] sum; reg [7:0] sum; always @(a or inc_dec) begin: COMBINATIONAL_PROC if ( inc_dec == 0) sum = a + 1; else sum = a - 1; end //good coding style using separate line for each HDL statement endmodule
nLint reports:
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end entity top_ety; architecture arch of top_ety is signal a,b : bit; begin a<='0'; b<='1'; --warning here end architecture arch;
nLint reports: document.vhd(7): Warning 22023: Only one statement is allowed per line. (Coding Style)
22024 (Verilog) Logic '0' Used to Extend Significant Bits of Constants

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: logic '0' is used to extend the significant bits of constant "%s". Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether logic 0s are used to extend the significant bits of a constant. The extension is needed because the specified size is larger than the given bits for the constant. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test(); wire [7:0] a,b,c,d,e,f,g,h,i,j; assign a = 8'sb100; assign b = 8'b100; assign c = 8'sb011; assign d = 8'so10; assign e = 8'so40; assign f = 8'o40; assign assign assign assign endmodule g h i j = = = = 8'sh7; 8'sh8; 8'h7; 8'h8; // 1 extend // 0 extend // 0 extend // 0 extend // 1 extend // 0 extend // // // // 0 1 0 0 extend extend extend extend
nLint reports: document.sv(5): Warning 22024: logic '0' is used to extend the significant bits of constant "8'b100". (Simulation,Language Construct) document.sv(6): Warning 22024: logic '0' is used to extend the significant bits of constant "8'sb011". (Simulation,Language Construct) document.sv(8): Warning 22024: logic '0' is used to extend the significant bits of constant "8'so10". (Simulation,Language Construct) document.sv(10): Warning 22024: logic '0' is used to extend the significant bits of constant "8'o40". (Simulation,Language Construct) document.sv(12): Warning 22024: logic '0' is used to extend the significant bits of constant "8'sh7". (Simulation,Language Construct) document.sv(14): Warning 22024: logic '0' is used to extend the significant bits of constant "8'h7". (Simulation,Language Construct) document.sv(15): Warning 22024: logic '0' is used to extend the significant bits of constant "8'h8". (Simulation,Language Construct)
22025 Line Too Long

Message <filename>(<line no.>): <severity> <rule no.>: line length should not exceed %d characters. Configurable Parameter Rule group: Coding Style; Argument type: integer; Argument description: specify the maximum number of characters in one line; Default value: "80" for Verilog, "80" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the line length exceeds 'length' characters. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; reg sel; reg [7:0] a,b,c,d,e,f,g;
initial begin $monitor($time,,,,,,,"sel=%d,a=%d,b=%d,c=%d,d=%d,e=%d,f=%d,g=%d",sel, a, b, c,d,e,f,g);//do not type a line so long. 8 a<=12; 9 b<=13; 10 c<=14; 11 e<=15; 12 f<=16; 13 g<=17; 14 sel<=1; 15 #200 $finish; 16 end 17 always 18 # 20 sel = ~sel; 19 endmodule
nLint reports following if the argument value is ("80"): document.v(7): Warning 22025: line length should not exceed 80 characters. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port (s1: in bit; s2: out bit; s3: inout bit; s4: buffer bit); end entity top_ety; architecture arch of top_ety is begin b1: block is signal s : bit; signal x : bit; begin
17 l1: postponed s<=transport '0' after 5 ns,'1' after 10 ns,'0' after 15 ns; --do not type a line so long. 18 l2: postponed s3<=reject 3 ns inertial '0','1' after 10 ns, '0' after 15 ns when s1='0' else --do not type a line so long. 19 '1','0' after 5 ns when s1='1' else 20 unaffected; 21 22 l3: postponed with s1 select 23 x<= transport '1' after 5 ns when '0', 24 '0' after 10 ns when '1', 25 '0' when others; 26 end block b1; 27 end architecture arch;
nLint reports following if the argument value is ("80"): document.vhd(17): Warning 22025: line length should not exceed 80 characters. (Coding Style) document.vhd(18): Warning 22025: line length should not exceed 80 characters. (Coding Style)
22026 (Verilog) Zero Bit(s) Truncated

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: zero bit(s) truncated by the size specified in literal "%s". Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any '0' bits or 'X' bits or 'Z' bits of a sized constant are truncated. This occurs when the size specified for the constant is smaller than the actual width of the value given to the constant. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test(a,b, c,d); output [5:0] a, b, c, d; wire [5:0] a, b, c, d ; assign a = 6'h11; //warning assign b = 6'hxx; //warning assign c = 6'hzz; //warning assign d = 6'hff; //no warning endmodule
nLint reports: document.v(4): Warning 22026: zero bit(s) truncated by the size specified in literal "6'h11". (Simulation,Language Construct) document.v(5): Warning 22026: zero bit(s) truncated by the size specified in literal "6'hxx". (Simulation,Language Construct) document.v(6): Warning 22026: zero bit(s) truncated by the size specified in literal "6'hzz". (Simulation,Language Construct)
22027 Improper Indentation

Message <filename>(<line no.>): <severity> <rule no.>: use %d spaces for indentation. Configurable Parameter Rule group: Coding Style; Argument type: (INT_ARG INT_ARG) (FIRST_INDENT, BEGIN_INDENT, REPORT_ALL); Argument description: the first argument is used to specify the preferred number of space character(s) for indentation purpose. The second argument contains three options. Each option can be individually selected or unselected. Select FIRST_INDENT to indicate the first level of language construct in module, like port declaration, wire declaration, always statement, initial statement, function, etc., should be indented; unselect FIRST_INDENT to indicate the first level of language construct in module should be aligned with module declaration. Select BEGIN_INDENT to indicate keyword begin should be indented if it is put in a new line; unselect BEGIN_INDENT to indicate keyword begin should not be indented if it is put in a new line. Select REPORT_ALL to indicate to report all the violations; unselect REPORT_ALL to indicate to report once on each procedural block. The argument is valid only for Verilog; Default value: "2","FIRST_INDENT,BEGIN_INDENT" for Verilog, "2","FIRST_INDENT,BEGIN_INDENT" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any improper indentations. If select REPORT_ALL, nLint reports violations according to "right line", not "last line". This rule does not check macro. Example
(Verilog) ///////////////example : document.v//////////// 1 module ao4 (rst_n, clk, y, a, b, c, d, q, r); 2 output y, q, r; 3 input a, b, c, d; 4 input clk, rst_n; 5 reg y, tmp1, tmp2, q, r; 6 wire p; 7 always @ (posedge clk) begin 8 tmp1 = a & b; 9 if ( tmp1 ) 10 tmp2 <= c & d; 11 y <= tmp1 | tmp2; //warning here 12 end 13 assign p = ~tmp2; 14 15 always @(posedge clk or negedge rst_n) 16 begin //warning here 17 if(!rst_n) 18 q <= 1'b0; 19 else 20 q <= d; 21 end //warning here 22 23 always @ (posedge clk) //warning here 24 begin 25 r <= a | b; 26 end 27 endmodule 28 ///////////////example : document1.v//////////// 1 2 3 4 module ao4 (rst_n, clk, y, a, b, c, d, q, r); output y, q, r; input a, b, c, d; input clk, rst_n;
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
reg y, tmp1, tmp2, q, r; wire p; always @ (posedge clk) begin tmp1 = a & b; if ( tmp1 ) tmp2 <= c & d; y <= tmp1 | tmp2; //warning here end assign p = ~tmp2; always @(posedge clk or negedge rst_n) begin //warning here if(!rst_n) q <= 1'b0; else q <= d; end //warning here always @ (posedge clk) begin r <= a | b; end endmodule //warning here
nLint reports following if the argument value is ("2","FIRST_INDENT,BEGIN_INDENT,REPORT_ALL"): document1.v(11): Warning 22027: use 4 spaces for document1.v(16): Warning 22027: use 4 spaces for document1.v(21): Warning 22027: use 4 spaces for document1.v(23): Warning 22027: use 2 spaces for ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
indentation. indentation. indentation. indentation.
(Coding (Coding (Coding (Coding
Style) Style) Style) Style)
//Example2 module ao4 (clk, y, a, b, c, d); output y; //warning here if FIRST_INDENT is selected in the second argument input a, b, c, d; input clk; reg y, tmp1, tmp2; wire p; always @ (posedge clk) begin tmp1 = a & b; if ( tmp1 ) tmp2 <= c & d; y <= tmp1 | tmp2; end assign p = ~tmp2; endmodule
nLint reports following if the argument value is ("2","FIRST_INDENT"): document2.v(3): Warning 22027: use 2 spaces for indentation. (Coding Style) document2.v(4): Warning 22027: use 2 spaces for indentation. (Coding Style) document2.v(5): Warning 22027: use 2 spaces for indentation. (Coding Style) document2.v(6): Warning 22027: use 2 spaces for indentation. (Coding Style) document2.v(7): Warning 22027: use 2 spaces for indentation. (Coding Style) document2.v(9): Warning 22027: use 2 spaces for indentation. (Coding Style) document2.v(17): Warning 22027: use 2 spaces for indentation. (Coding Style) ///////////////example : document3.v//////////// 1 2 3 4 5 6 7 8 9 //Example3 module ao4 (clk, y, a, b, c, d); output y; //no warning if FIRST_INDENT not selected in the second argument input a, b, c, d; input clk; reg y, tmp1, tmp2; wire p; always @ (posedge clk)
10 11 12 13 14 15 16 17 18 19
begin //warning here if BEGIN_INDENT selected in the second argument tmp1 = a & b; if ( tmp1 ) tmp2 <= c & d; y <= tmp1 | tmp2; end assign p = ~tmp2; endmodule
nLint reports following if the argument value is ("2","BEGIN_INDENT"): document3.v(10): Warning 22027: use 2 spaces for indentation. (Coding Style) ///////////////example : document4.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 //Example4 module ao4 (clk, y, a, b, c, d); output y; input a, b, c, d; input clk; reg y, tmp1, tmp2; wire p; always @ (posedge clk) begin //no warning here even if //BEGIN_INDENT selected in the second argument tmp1 = a & b; if ( tmp1 ) //warning here since it should be aligned with last line tmp2 <= c & d; y <= tmp1 | tmp2; end assign p = ~tmp2; endmodule
nLint reports following if the argument value is ("2","BEGIN_INDENT"): document4.v(12): Warning 22027: use 2 spaces for indentation. (Coding Style) ///////////////example : document5.v//////////// 1 //Example5 2 //if select REPORT_ALL, nLint report violation based on "right line", not "last line" 3 //eg. when check line 3 4 module test (clk, rst_n, d, q); 5 output q; 6 input clk, rst_n, d; 7 reg q; 8 9 always @(posedge clk or negedge rst_n) //right line 10 begin //last line is a error line 11 if (!rst_n) 12 q <= 1'b0; 13 else 14 q <= d; 15 end 16 endmodule
nLint reports following if the argument value is document5.v(10): Warning 22027: use 0 spaces for document5.v(11): Warning 22027: use 2 spaces for document5.v(12): Warning 22027: use 4 spaces for document5.v(13): Warning 22027: use 2 spaces for document5.v(14): Warning 22027: use 4 spaces for document5.v(15): Warning 22027: use 0 spaces for
("2","REPORT_ALL"): indentation. (Coding indentation. (Coding indentation. (Coding indentation. (Coding indentation. (Coding indentation. (Coding
Style) Style) Style) Style) Style) Style)
(VHDL) -------------------example : document.vhd------------1 entity top_ety is
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
end top_ety; architecture arch of top_ety is begin p1: process is variable a : integer; variable b : integer; begin if (a>0) then b:=a; else b:=-a; end if; end process p1; --good coding style end arch;
nLint reports following if the argument value is ("2","FIRST_INDENT,BEGIN_INDENT"):
22029 TAB Used in Indentation

Message <filename>(<line no.>): <severity> <rule no.>: should not use TAB for indentation. Configurable Parameter Rule group: Coding Style; Argument type: (CHECK_BODY_ONLY, CHECK_WHOLE); Argument description: select CHECK_BODY_ONLY to only check within modules; select CHECK_WHOLE to check the whole design, including the comments outside modules; Default value: "CHECK_WHOLE" for Verilog, "CHECK_WHOLE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether TABs are used for indentation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (clock, data, y); input clock, data; output y; reg y; always @(posedge clock) y = data; //warning here, don't use TAB for indentation endmodule
nLint reports following if the argument value is ("CHECK_WHOLE"): document.v(7): Warning 22029: should not use TAB for indentation. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port (s1: in bit; s2: out bit; s3: inout bit; s4: buffer bit); end entity top_ety; architecture arch of top_ety is begin b1: block is signal s : bit; -- warning here, don't use TAB for indentation begin end block b1; end architecture arch;
nLint reports following if the argument value is ("CHECK_WHOLE"): document.vhd(14): Warning 22029: should not use TAB for indentation. (Coding Style)
22031 One Port per Line

Message <filename>(<line no.>): <severity> <rule no.>: more than one port is declared in one line. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are more than one port declared in one line, which is not a good coding style. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test(clock, reset, count); input clock; input reset; //warning here output count; //Good style: declare one port per line, // and every port followed by comment endmodule
nLint reports: document.v(4): Warning 22031: more than one port is declared in one line. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is --Good style declare one port per line, -- and every port followed by comment port ( reset : in bit; clock : in bit; --warning here q: out bit ); end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports: document.vhd(4): Warning 22031: more than one port is declared in one line. (Coding Style)
22032 Comment Not Found Following Port Declaration

Message <filename>(<line no.>): <severity> <rule no.>: comment is not found following port declaration. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the comment follows port declaration. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 //warning on line 3, 5 module test(clock, set, reset, count); input clock, set; input reset; //comment output count; endmodule
nLint reports: document.v(3): Warning 22032: comment is not found following port declaration. (Coding Style) document.v(5): Warning 22032: comment is not found following port declaration. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 --warning on line 4, 6 entity top_ety is --declare one port per line, every port followed by comment port ( reset : in bit; clock : in bit; --comment q: out bit ); end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports: document.vhd(4): Warning 22032: comment is not found following port declaration. (Coding Style) document.vhd(6): Warning 22032: comment is not found following port declaration. (Coding Style)
22033 Interspersed Input and Output Declarations

Message <filename>(<line no.>): <severity> <rule no.>: %s, %s and %s signals should be grouped%sin port declarations. Configurable Parameter Rule group: Coding Style; Argument type: (TRUE, FALSE) (OUTPUT,INPUT,INOUT); Argument description: For the first argument, select TRUE means a blank line should be inserted to separate the input/output declaration; select FALSE means the blank line is not necessary. For the second argument, it specifies the order of port type to be declared; Default value: "FALSE","INPUT, OUTPUT, INOUT, BUFFER, LINKAGE" for Verilog, "FALSE","INPUT, OUTPUT, INOUT, BUFFER, LINKAGE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the input, output and inout ports are declared in groups, and are properly separated with a blank line or not if it is required in argument. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (A,B,Q,LINE); input A; input B; //group input port together output Q; //separate the ports with different direction by a? //blank line if the first argument is TRUE. inout LINE; endmodule
nLint reports following if the argument value is ("TRUE","INPUT, OUTPUT, INOUT, BUFFER, LINKAGE"):
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is port (s1: in bit; s2: out bit; s3: inout bit; s4: buffer bit; s5: linkage bit; s6: buffer bit; -- warning here s7: inout bit; -- warning here s8: out bit; -- warning here s9: in bit); -- warning here end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports following if the argument value is ("TRUE","INPUT, OUTPUT, INOUT, BUFFER, LINKAGE"): document.vhd(3): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style)
document.vhd(4): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style) document.vhd(5): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style) document.vhd(6): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style) document.vhd(7): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style) document.vhd(8): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style) document.vhd(9): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style) document.vhd(10): Warning 22033: input, output and inout signals should be grouped and separated by blank line in port declarations. (Coding Style)
22035 Unconventional Port Declaration Order

Message <filename>(<line no.>): <severity> <rule no.>: ports should be declared in order of %s, %s, %s, %s and %s signal groups; and within each group, in order of %s, %s, %s, %s, %s and %s signals. Configurable Parameter Rule group: Coding Style; Argument type: (OUTPUT,INPUT,INOUT); Argument description: The first argument specifies the order of port by port direction; the second argument specifies the order of port by port type; Default value: "INPUT, OUTPUT, INOUT, BUFFER, LINKAGE","CLOCK, RESET, SET, ENABLE, TE, CONTROL" for Verilog, "INPUT, OUTPUT, INOUT, BUFFER, LINKAGE","CLOCK, RESET, SET, ENABLE, TE, CONTROL" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the ports are declared in the order of input, output and inout signal groups, and within each group, clock, reset, enable, control, data, and address signals. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 module test (control,clock,reset,y); input clock,reset,control; output [2:0] y; reg [2:0] y; //warning here
parameter ST0 = 0,ST1 = 1,ST2 = 2,ST3 = 3; reg[1:0] current, next; always@(control or current) begin case (current) ST0: begin y = 1; next = ST1; end ST1: begin y = 2; if (control) next = ST2; else next = ST3; end ST2: begin y = 3; next = ST3; end ST3: begin y = 4; next = ST0; end default: begin y = 1; next = ST0; end endcase end always @(posedge clock or posedge reset) begin if(reset) current = ST0; else current = next; end endmodule
nLint reports following if the argument value is ("INPUT, OUTPUT, INOUT, BUFFER, LINKAGE","CLOCK, RESET, SET, ENABLE, TE, CONTROL"): document.v(1): Warning 22035: ports should be declared in order of input, output, inout, buffer and linkage signal groups; and within each group, in order of clock, reset, set, enable, tri-enable and control signals. (Coding Style)
(VHDL) -------------------example : document.vhd-------------
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
entity top_ety is port (control: in bit; --warning here, the order of port --declaration should be clock, reset, --control, d1, d2, y d1 : in bit; d2 : in bit; clock: in bit; reset: in bit; y: out bit ); end entity top_ety; architecture arch of top_ety is begin p1 : process (reset, clock) begin if (reset = '1') then y <= '0'; elsif (clock'event and clock = '1') then if (control = '1') then y <= d1; else y <= d2; end if; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("INPUT, OUTPUT, INOUT, BUFFER, LINKAGE","CLOCK, RESET, SET, ENABLE, TE, CONTROL"): document.vhd(13): Warning 22035: ports should be declared in order of input, output, inout, buffer and linkage signal groups; and within each group, in order of clock, reset, set, enable, tri-enable and control signals. (Coding Style)
22038 Declare One Signal per Line with Comment

Message <filename>(<line no.>): <severity> <rule no.>: signals should be declared one per line with a comment at the end. Configurable Parameter Rule group: Coding Style; Argument type: (IGNORE_COMMENT, CHECK_COMMENT); Argument description: select IGNORE_COMMENT to allow no comment after declaration; select CHECK_COMMENT to specify that comment must be added after declaration; Default value: "IGNORE_COMMENT" for Verilog, "IGNORE_COMMENT" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the signals are declared one per line with a comment at the end. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (clock,data,y); input clock,data; output y; reg y; wire a,b; // warning here always @(posedge clock) y=data; endmodule
nLint reports following if the argument value is ("IGNORE_COMMENT"): document.v(6): Warning 22038: signals should be declared one per line with a comment at the end. (Coding Style) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 module test(clock, reset, count); input clock; //add comment here input reset; //add comment here output count;//add comment here // declare one port per line, every port followed by comment endmodule
nLint reports following if the argument value is ("IGNORE_COMMENT"):
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is signal s0 : bit; signal s1,s2 : bit; --warning here begin end arch;
nLint reports following if the argument value is ("IGNORE_COMMENT"): document.vhd(6): Warning 22038: signals should be declared one per line with a comment at the end. (Coding Style) -------------------example : document2.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is --declare one port per port ( reset : in bit; clock : in bit; q: out bit ); end top_ety;
line, --add --add --add
every port followed by comment comment here comment here comment here
architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("IGNORE_COMMENT"):
22039 Inconsistent Port Order in Definition and Instantiation

Message <filename>(<line no.>): <severity> <rule no.>: port instance order should be the same as port declaration order. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the port instances and port declarations are in the same order. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module testini; reg sel; reg [7:0] a,b,c; wire [8:0] y; test u_test_0(.pa(a),.pb(b),.pc(c),.py(y),.ps(sel));//warning here endmodule module test(.ps(sel),.pa(a),.pb(b),.pc(c),.py(y)); input sel; input [7:0] a,b,c; output [7:0] y; reg [7:0] y; reg [7:0] temp; always@( begin: temp if ( else temp = c; y = a+temp; end endmodule sel or a or b or c) tempa = 0; sel ) temp = b;
nLint reports: document.v(6): Warning 22039: port instance order should be the same as port declaration order. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 library IEEE; use IEEE.std_logic_1164.all; entity EA is port (s1 : in bit; s2 : out bit ); end entity EA; architecture arch of EA is begin end architecture arch;
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entity top_ety is end entity top_ety; architecture arch of top_ety is component EA is port (s1 : in bit; s2 : out bit ); end component EA; signal x,y : bit; begin u0: component EA port map (s2=>y,s1=>x); --warning here end architecture arch;
nLint reports: document.vhd(26): Warning 22039: port instance order should be the same as port declaration order. (Coding Style)
22041 (Verilog) Implicit Port Declaration

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: port "%s" should be declared by using explicit name. Configurable Parameter Rule group: Coding Style; Argument type: (CHECK_ANSI_PORT, IGNORE_ANSI_PORT); Argument description: select CHECK_ANSI_PORT to check ansi-style port declaration, select IGNORE_ANSI_PORT to ignore checking ansi-style port declaration. Default value: "IGNORE_ANSI_PORT" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether ports use explicit names for declaration. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 //good style for using explicit port name module adder0(.a(in1),.b(in2),.ci(carry_in),.outsum(sum),.co(carry_out)); output sum,carry_out; input in1,in2,carry_in; reg sum,carry_out; always @(in1 or in2 or carry_in) {carry_out,sum} = in1+in2+carry_in; endmodule //bad style for using implicit port declaration module adder1(in1, in2, carry_in, sum, carry_out); output sum,carry_out; input in1,in2,carry_in; reg sum,carry_out; always @(in1 or in2 or carry_in) {carry_out,sum} = in1+in2+carry_in; endmodule
nLint reports following if the document.v(12): Warning 22041: name. (Coding Style) document.v(12): Warning 22041: name. (Coding Style) document.v(12): Warning 22041: explicit name. (Coding Style) document.v(12): Warning 22041: name. (Coding Style) document.v(12): Warning 22041: explicit name. (Coding Style)
argument value is ("IGNORE_ANSI_PORT"): port "in1" should be declared by using explicit port "in2" should be declared by using explicit port "carry_in" should be declared by using port "sum" should be declared by using explicit port "carry_out" should be declared by using
22043 Connection Ports by Ordered List

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: port "%s" should be connected by name. (VHDL) <filename>(<line no.>): <severity> <rule no.>: port "%s" should be associated by name. Configurable Parameter Rule group: Coding Style; Argument type: (FUNCTION, TASK, MODULE); Argument description: The argument enables the checking for functions (FUNCTION), tasks (TASK), or modules (MODULE). They can be multiple selected; Default value: "MODULE" for Verilog, "MODULE" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether there are any ports connected by ordered list. The connection is made by the ports listed in a module instantiation and the ports defined by the instantiated module. The port connection is error prone when port number or port order is changed in module declaration. Connecting ports by name is suggested. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module testini; wire sel1, sel2, a, b, c; wire y; test u_test_0(sel1, a, b, y);//warning test u_test_1(.sel(sel2), .a(a), .b(b), .y(y) ); endmodule module test(sel, a, b, y); input sel, a, b; output y; endmodule
nLint reports following if the argument value is document.v(5): Warning 22043: port "y" should be document.v(5): Warning 22043: port "b" should be document.v(5): Warning 22043: port "a" should be document.v(5): Warning 22043: port "sel1" should Style)
("MODULE"): connected by connected by connected by be connected
name. (Coding Style) name. (Coding Style) name. (Coding Style) by name. (Coding
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 library IEEE; use IEEE.std_logic_1164.all; entity EA is port (s1 : in bit; s2 : out bit ); end entity EA; architecture arch of EA is begin end architecture arch; entity top_ety is end entity top_ety;
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architecture arch of top_ety is component EA is port (s1 : in bit; s2 : out bit ); end component EA; signal x,y : bit; begin u0: component EA port map (x,s2=>y); --warning on 'x' end architecture arch;
nLint reports following if the argument value is ("MODULE"): document.vhd(26): Warning 22043: port "x" should be associated by name. (Coding Style)
22044 (Verilog) Use Explicit Mapping for Parameters 22044 (VHDL) Use Explicit Mapping for Generic
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: parameter "%s" should be mapped by name. (VHDL) <filename>(<line no.>): <severity> <rule no.>: generic "%s" should be mapped by name. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the name association, rather than the positional association, is used on the parameter association. Example
(Verilog) ///////////////example : document.v2k//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module sub (i, o); parameter width = 1; input i; output o; assign o = i; endmodule module top (i, o); parameter width = 2; input [1:0] i; output [1:0] o; sub #(width) i_sub(.i(i), .o(o)); endmodule
nLint reports: document.v2k(12): Warning 22044: parameter "width" should be mapped by name. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity ram_dp is generic (addr_bits :integer); end ram_dp; architecture arch of ram_dp is begin end; entity top_ety is end; architecture arch of top_ety is component ram_dp generic (addr_bits :integer); end component; begin RAM0: end;
ram_dp generic map (15); --warning here
nLint reports: document.vhd(18): Warning 22044: generic "15" should be mapped by name. (Coding Style)
22045 (Verilog) Use Localparam in Module or Interface

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: use localparam instead of parameter to declare "%s" in module or interface "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) 'localparam' is suggested to be used inside modules or interfaces instead of 'parameter'. This rule won't be applied in root scope. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 parameter ROOT_OK1 = 1; localparam ROOT_OK2 = 2; interface simple; parameter NOT_OK = 0; // nLint gives warning on this declaration endinterface module test; parameter NOT_OK = 0; // nLint gives warning on this declaration localparam OK = 1; endmodule
nLint reports: document.sv(4): Warning 22045: use localparam instead of parameter to declare "NOT_OK" in module or interface "simple". (Design Style) document.sv(7): Warning 22045: use localparam instead of parameter to declare "NOT_OK" in module or interface "test". (Design Style)
22049 Literal Constant in Range Definition

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: literal numbers should not be used in specifying a range (in object "%s"). (VHDL) <filename>(<line no.>): <severity> <rule no.>: constant numbers should not be used in specifying a range (in object "%s"). Configurable Parameter Rule group: Coding Style; Argument type: (PACKAGE, ENTITY, ARCHITECTURE); Argument description: This is a multiple selection argument. Select PACKAGE to check this rule in package, select ENTITY to check this rule in entity, select ARCHITECTURE to check this rule in architecture. This argument is only for VHDL; Default value: "ENTITY,ARCHITECTURE" for Verilog, "ENTITY,ARCHITECTURE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any hard coded numbers are used in range declaration. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test; reg [7:0] q; //warning here(parameter WIDTH=8; reg [WIDTH-1:0] q;) endmodule
nLint reports following if the argument value is ("ENTITY,ARCHITECTURE"): document.v(2): Warning 22049: literal numbers should not be used in specifying a range (in object "q"). (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end entity top_ety; architecture arch of top_ety is type array1 is array (8 downto 1) of bit; -- warning on '8 downto 1' type array2 is array (natural range<>) of bit; signal s1 : array1; signal s2 : array2(32 downto 1); --warning on '32 downto 1' begin end architecture arch;
nLint reports following if the argument value is ("ENTITY,ARCHITECTURE"): document.vhd(5): Warning 22049: constant numbers should not be used in specifying a range (in object "array1"). (Coding Style) document.vhd(8): Warning 22049: constant numbers should not be used in specifying a range (in object "s2"). (Coding Style)
22051 (Verilog) Generated Reset

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: reset signal should not be driven by logic which is not in reset_gen module (reset: "%s" (%s(%d)); driving logic output: "%s"). Configurable Parameter Rule group: Clock; Argument type: (PASS_THROUGH_BUFFER_ASSIGNMENT, PASS_THROUGH_EVEN_INVERTERS); Argument description: select PASS_THROUGH_BUFFER_ASSIGNMENT to check case passing through buffer and assignment; select PASS_THROUGH_EVEN_INVERTERS to check case passing through even number of inverters. Default value: "PASS_THROUGH_BUFFER_ASSIGNMENT, PASS_THROUGH_EVEN_INVERTERS" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any reset signals driven by combinational logics. Note that you can specify a "global reset generator module" by the command line option "reset_gen_module" or with the Run-> Project Setting-> Lint-> Global Reset option. When a module is set as a "global reset generator module", all the modules instantiated by this module will be set as "global reset generator module" recursively. If the driving logic of a clock is in "global reset generator module", this rule does not report violation. You can specify more than one modules in option "-reset_gen_module" by using semicolon (":") as the delimiter or by specifying the option "-reset_gen_module" for multiple times. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 module test(a,b,clk,d,q); input a,b,clk,d; output q; rst_gen i1 (reset, a, b); test1 i2 (clk, reset, q, d); test2 i3 (clk, reset, q, d); test3 i4 (clk, reset, q, d); endmodule module rst_gen(out, a, b); input a,b; output out; wire a,b,out; and (out,a,b); endmodule module test1(clk,reset,q,d); input clk,reset,d; output q; wire reset,clk,d; reg q; always @(posedge clk or negedge reset) begin if (reset) q = 0; else q = d; end endmodule module test2(clk,reset,q,d); input clk,reset,d;
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output q; wire reset,clk,d,reset1; reg q; not (reset1,reset); always @(posedge clk or negedge reset1) begin if (reset1) q = 0; else q = d; end endmodule module test3(clk,reset,q,d); input clk,reset,d; output q; wire reset,clk,d,reset1,reset2; reg q; not (reset1,reset); not (reset2,reset1); always @(posedge clk or negedge reset2) begin if (reset2) q = 0; else q = d; end endmodule
nLint reports following if the argument value is ("PASS_THROUGH_BUFFER_ASSIGNMENT, PASS_THROUGH_EVEN_INVERTERS"): document.v(35): Warning 22051: reset signal should not be driven by logic which is not in reset_gen module (reset: "reset1" (document.v(37)); driving logic output: "reset1"). (Clock)
22052 (Verilog) Generated Clock

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: clock signal should not be driven by logic which is not in clock_gen module (clock: "%s" (%s(%d)); driving logic output: "%s"). Configurable Parameter Rule group: Clock; Argument type: (PASS_THROUGH_BUFFER_ASSIGNMENT, PASS_THROUGH_EVEN_INVERTERS); Argument description: select PASS_THROUGH_BUFFER_ASSIGNMENT to check case passing through buffer and assignment; select PASS_THROUGH_EVEN_INVERTERS to check case passing through even number of inverters. Default value: "PASS_THROUGH_BUFFER_ASSIGNMENT, PASS_THROUGH_EVEN_INVERTERS" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any clock signals driven by combinational logics. Note that you can specify a "global clock generator module" by the command line option "clock_gen_module" or with the Run-> Project Setting-> Lint-> Global Clock option. When a module is set as a "global clock generator module", all the modules instantiated by this module will be set as "global clock generator module" recursively. If the driving logic of a clock is in "global clock generator module", this rule does not report violation. You can specify more than one modules in option "-clock_gen_module" by using semicolon (":") as the delimiter or by specifying the option "-clock_gen_module" for multiple times. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 module test(a,b,reset,d,q); input a,b,reset,d; output q; clk_gen i1 (clk, a, b); test1 i2 (clk, reset, q, d); test2 i3 (clk, reset, q, d); test3 i4 (clk, reset, q, d); endmodule module clk_gen(out, a, b); input a,b; output out; wire a,b,out; and (out,a,b); endmodule module test1(clk,reset,q,d); input clk,reset,d; output q; wire reset,clk,d; reg q; always @(negedge clk or posedge reset) begin if (reset) q = 0; else q = d; end endmodule module test2(clk,reset,q,d); input clk,reset,d;
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output q; wire reset,clk,d,clk1; reg q; not (clk1,clk); always @(negedge clk1 or posedge reset) begin if (reset) q = 0; else q = d; end endmodule module test3(clk,reset,q,d); input clk,reset,d; output q; wire reset,clk,d,clk1,clk2; reg q; not (clk1,clk); not (clk2,clk1); always @(negedge clk2 or posedge reset) begin if (reset) q = 0; else q = d; end endmodule
nLint reports following if the argument value is ("PASS_THROUGH_BUFFER_ASSIGNMENT, PASS_THROUGH_EVEN_INVERTERS"): document.v(35): Warning 22052: clock signal should not be driven by logic which is not in clock_gen module (clock: "clk1" (document.v(36)); driving logic output: "clk1"). (Clock)
22053 Gated Clock

Message <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" (%s(%d) is driven by a combinational logic (output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether there is any gated clock in the design. The gated clock should be taken care to prevent from the difficulty of clock control in DFT. Note that latch enable is treated as a clock. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (q, clk, en, reset, d); output q; input clk, en, reset, d; reg q; wire clk, en, reset, d; wire clk_en; and U_and_1(clk_en, clk, en);//warning always @( posedge clk_en or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule
nLint reports: document.v(8): Warning 22053: clock signal "clk_en" (document.v(10) is driven by a combinational logic (output: "clk_en"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 entity top_ety is port ( rst : in bit; a : in bit; b : in bit; d : in integer; count : out integer); end top_ety; architecture arch of top_ety is signal clk : bit; begin clk <= a and b; --clk is output of gate p1 : process (rst, clk) begin if (rst='1') then count<=0; elsif (clk'event and clk='1') then --clk is used as clock signal count<=d; end if; end process p1; end arch;
nLint reports: document.vhd(13): Warning 22053: clock signal "clk" (document.vhd(19) is driven by a combinational logic (output: "clk"). (DFT,Design Style)
22054 Inverted Clock

Message <filename>(<line no.>): <severity> <rule no.>: clock signal should not be driven (gated) by inverted logic (clock: "%s" (%s(%d)); inverted logic output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any inverted clock in the design. Original in lint2.2, use 22229's argument to control if a latch enable is a clock or ctrl. In lint2.3, treate all latch enable as clock. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test ( q, clk, reset, d ); output q; input clk, reset, d; reg q; wire clk, reset, d; wire clk_i; inv U_buf_1(clk_i, clk);//warning on "clk_i", clk_i is drived //by an invertor always @( posedge clk_i or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule///////////////example : document1.v//////////// module test (q, clk, reset, d); output q; input clk, reset, d; reg q; wire clk, reset, d; wire clk_i; not U_buf_1(clk_i, clk); //warning on "clk_i", clk_i is drived //by an invertor always @( posedge clk_i or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule
nLint reports: document1.v(8): Warning 22054: clock signal should not be driven (gated) by inverted logic (clock: "clk_i" (document1.v(11)); inverted logic output: "clk_i"). (DFT,Design Style) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 module top (q, clk, reset, d); output q; input clk, reset, d; reg q; wire clk, reset, d; wire clk_i;
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inv U_buf_1(clk_i, clk); //warning on "clk_i", clk_i is drived //by an invertor always @( posedge clk_i or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule module inv ( b, a); output b; inout a; reg b; always @(a) begin b = ~a; end endmodule
nLint reports: document2.v(23): Warning 22054: clock signal should not be driven (gated) by inverted logic (clock: "clk_i" (document2.v(11)); inverted logic output: "b"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 entity top_ety is port ( rst : in bit; a : in bit; d : in integer; count : out integer); end top_ety; architecture arch of top_ety is signal clk : bit; begin clk <= not a;--clk is output of invertor p1 : process (rst, clk) begin if (rst='1') then count<=0; elsif (clk'event and clk='1') then --clk is used as clock signal count<=d; end if; end process p1; end arch;
nLint reports: document.vhd(12): Warning 22054: clock signal should not be driven (gated) by inverted logic (clock: "clk" (document.vhd(18)); inverted logic output: "clk"). (DFT,Design Style)
22055 Buffered Clock

Message <filename>(<line no.>): <severity> <rule no.>: clock signal should not be buffered manually (clock: "%s" (%s(%d)); buffer logic output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any explicit buffered clock in the design. Original in lint2.2, use 22229's argument to control if a latch enable is a clock or ctrl. In lint2.3, treate all latch enable as clock. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (q, clk, reset, d); output q; input clk, reset, d; reg q; wire clk, reset, d; wire clk_i; buf U_buf_1(clk_i, clk);//warning on "clk_i", clk_i is drived //by a buffer always @( posedge clk_i or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule
nLint reports: document.v(8): Warning 22055: clock signal should not be buffered manually (clock: "clk_i" (document.v(11)); buffer logic output: "clk_i"). (DFT)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 library ieee; use ieee.std_logic_1164.all; library buf; use buf.all; entity top_ety is port (clock : in std_logic; rst : in std_logic; d : in integer; count : out integer); end top_ety; architecture arch of top_ety is signal clk : std_logic; component BUF1 is port (a : in std_logic; b : out std_logic); end component; begin
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--assumed that BUF1 is buffer cell u_BUF1 : component BUF1 port map( a=>clock, b=>clk ); p1 : process (rst, clk) begin if (rst='1') then count<=0; elsif (clk'event and clk='1') then count<=d; end if; end process p1; end arch;
--clk is used as clock signal
nLint reports: document.vhd(22): Warning 22055: clock signal should not be buffered manually (clock: "clk" (document.vhd(28)); buffer logic output: "clk"). (DFT)
22056 Reset Driven by Combinational Logic

Message <filename>(<line no.>): <severity> <rule no.>: reset signal should not be driven by combinational logic (reset: "%s" (%s(%d)); combinational logic output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any reset signal is driven by a combinational logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (q, clk, en, reset, d); output q; input clk, en, reset, d; reg q; wire clk, en, reset, d; wire rst_en; and U_and_1(rst_en, reset, en);//warning on "rst_en", is gated always @( posedge clk or negedge rst_en ) if ( ~rst_en ) q <= 1'b0; else q <= d; endmodule
nLint reports following if the argument value is ("BOTH"): document.v(8): Warning 22056: reset signal should not be driven by combinational logic (reset: "rst_en" (document.v(11)); combinational logic output: "rst_en"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is port ( reset : in bit; clock : in bit; d : in bit; q : out bit ); end entity top_ety; architecture arch of top_ety is signal rst : bit; begin p0 : process (clock,reset) begin rst<= clock and reset; --warning on 'rst' end process p0; p1: process (rst,clock) is
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begin if (rst='1') then q<='0'; elsif (clock'event and clock='1') then q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(14): Warning 22056: reset signal should not be driven by combinational logic (reset: "rst" (document.vhd(19)); combinational logic output: "rst"). (DFT,Design Style)
22057 Set Driven by Combinational Logic

Message <filename>(<line no.>): <severity> <rule no.>: set signal should not be driven by combinational logic (set: "%s" (%s(%d)); combinational logic output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any set signal is driven by a combinational logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (q, clk, en, set, d); output q; input clk, en, set, d; reg q; wire clk, en, set, d; wire set_en; and U_and_1(set_en, set, en); //warning on "set_en", is gated always @( posedge clk or negedge set_en ) if ( ~set_en ) q <= 1'b1; else q <= d; endmodule
nLint reports following if the argument value is ("BOTH"): document.v(8): Warning 22057: set signal should not be driven by combinational logic (set: "set_en" (document.v(11)); combinational logic output: "set_en"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is port ( set : in bit; clock : in bit; d : in bit; q : out bit ); end entity top_ety; architecture arch of top_ety is signal st : bit; begin p0 : process (clock,set) begin st<= clock and set; --warning on 'st' end process p0; p1: process (st,clock) is
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begin if (st='1') then q<='1'; elsif (clock'event and clock='1') then q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(14): Warning 22057: set signal should not be driven by combinational logic (set: "st" (document.vhd(19)); combinational logic output: "st"). (DFT,Design Style)
22058 Reset is Driven by a Path with Potential Glitch

Message <filename>(<line no.>): <severity> <rule no.>: the set/reset signal should not be driven by a path with potential glitch (set/reset:"%s"; path:"%s" (%s(%d))). Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any reset signal is driven by a path with potential glitch. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (q, clk, en, reset, d); output q; input clk, en, reset, d; reg q; wire clk, en, reset, d; wire rst_en; and U_and_1(rst_en, reset, en); //warning on "rst_en" always @( posedge clk or negedge rst_en ) if ( ~rst_en ) q <= 1'b0; else q <= d; endmodule
nLint reports: document.v(11): Warning 22058: the set/reset signal should not be driven by a path with potential glitch (set/reset:"rst_en"; path:"rst_en" (document.v(8))). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 entity top_ety is port ( reset : in bit; clock : in bit; d : in bit; q : out bit ); end entity top_ety; architecture arch of top_ety is signal rst : bit; begin p0 : process (clock,reset) begin rst<= clock and reset; --warning on 'rst' end process p0; p1: process (rst,clock) is begin if (rst='1') then q<='0'; elsif (clock'event and clock='1') then q<=d; end if;
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end process p1; end architecture arch;
nLint reports: document.vhd(19): Warning 22058: the set/reset signal should not be driven by a path with potential glitch (set/reset:"rst"; path:"rst" (document.vhd(14))). (DFT,Design Style)
22059 Set Driven by Sequential Logic

Message <filename>(<line no.>): <severity> <rule no.>: set signal should not be driven by sequential logic (set: "%s" (%s(%d)); sequential logic output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any set signal is driven by a sequential logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module test (q, clk, c, d); output q; output [3:0] c; input clk, d; reg q; reg [3:0] c; always @(posedge clk) c <= c + 1; //warning on "c[3]", set //signal is an output of //sequential device always @(posedge clk or posedge c[3]) if (c[3]) q <= 1; else q <= d; endmodule
nLint reports following if the argument value is ("BOTH"): document.v(9): Warning 22059: set signal should not be driven by sequential logic (set: "c[3]" (document.v(14)); sequential logic output: "c[3]"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port ( set : in bit; clock : in bit; d : in bit; q : out bit ); end entity top_ety; architecture arch of top_ety is signal st : bit; begin p0 : process (set,clock) begin if (clock'event and clock='1') then
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st<=set;
--warning on 'st', 'st' is an output of sequential --logic and used as set signal in below logic
end if; end process p0; p1 : process (st,clock) is begin if (st='1') then --'st' used as set signal q<='1'; elsif (clock'event and clock='1') then q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(15): Warning 22059: set signal should not be driven by sequential logic (set: "st" (document.vhd(22)); sequential logic output: "st"). (DFT,Design Style)
22061 Unused Object

Message <filename>(<line no.>): <severity> <rule no.>: object "%s" is declared but not used %s. Configurable Parameter Rule group: Design Style; Argument type: (CHECK_TYPE_DETAIL, IGNORE_TYPE_DETAIL); Argument description: The argument could be specified as CHECK_TYPE_DETAIL or IGNORE_TYPE_DETAIL. CHECK_TYPE_DETAIL means that this rule checks the sub field of a struct or union type. IGNORE_TYPE_DETAIL means that this rule ignores the sub field of a struct or union type. The argument makes sense only for SystemVerilog since struct and union type are introduced in SystemVerilog; Default value: "CHECK_TYPE_DETAIL" for Verilog, "CHECK_TYPE_DETAIL" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any objects, including signal, variable, parameter, type define, UDP, task, and function/procedure are declared but not used. Note that if a parameter is defined in a module through an ìnclude directive and not used in the current module but if it is included again and used by another module, this rule is not violated; however, if a parameter is defined through an ìnclude directive in a module but never used in the design, this rule is violated. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 //CHECK_TYPE_DETAIL is set to the argument in rs file module test; typedef int INT; typedef struct{ logic field; }STU_TYP; STU_TYP stu; endmodule
nLint reports following document.sv(3): Warning current module. (Design document.sv(5): Warning current module. (Design document.sv(7): Warning current module. (Design
if the 22061: Style) 22061: Style) 22061: Style)
argument value is ("CHECK_TYPE_DETAIL"): object "INT" is declared but not used in the object "field" is declared but not used in the object "stu" is declared but not used in the
///////////////example : document.v//////////// 1 2 3 4 module test; reg NotUseReg; parameter pa = 0; endmodule
nLint reports following if the argument value is ("CHECK_TYPE_DETAIL"): document.v(2): Warning 22061: object "NotUseReg" is declared but not used in the current module. (Design Style) document.v(3): Warning 22061: object "pa" is declared but not used in the current module. (Design Style) ///////////////example : document2.v//////////// 1 2 3 module top; ìnclude "document2.h"
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wire [7:0] r1; assign r1 = P1; endmodule module test(); ìnclude "document2.h" wire [7:0] r2; assign r2 = P2; endmodule
nLint reports following if the argument value is ("CHECK_TYPE_DETAIL"): document2.h(3): Warning 22061: object "P3" is declared but not used in the module "top" within file "document2.v"(1). (Design Style) document2.h(3): Warning 22061: object "P3" is declared but not used in the module "test" within file "document2.v"(8). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end entity top_ety; architecture arch of top_ety is constant c : integer :=10; --warning on 'c' signal s : bit; --warning on 's' shared variable v : integer; --warning on 'v' procedure proc is begin null; end procedure proc; begin end architecture arch; --warning on 'proc'
nLint reports following if the argument value document.vhd(5): Warning 22061: object "c" is module. (Design Style) document.vhd(6): Warning 22061: object "s" is module. (Design Style) document.vhd(7): Warning 22061: object "v" is module. (Design Style) document.vhd(9): Warning 22061: object "proc" current module. (Design Style)
is ("CHECK_TYPE_DETAIL"): declared but not used in the current declared but not used in the current declared but not used in the current is declared but not used in the
22063 Two-process Style Not Used for FSM

Message <filename>(<line no.>): <severity> <rule no.>: FSM is not implemented using two-process coding. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether finite state machines are implemented by using two-process coding style: one process implements the combinational logics for next state and the other process implements the storage register for current state. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 module block (clock,reset,control,y); parameter WIDTH = 3; input clock,reset,control; output [WIDTH-1:0] y; reg [WIDTH-1:0] y; parameter ST0 = 0,ST1 = 1,ST2 = 2,ST3 = 3; reg[1:0] current, next; always @(posedge clock or posedge reset) //warning here, FSM is inferred in one process begin if(reset) current = ST0; else begin case (current) ST0: begin y = 1; next = ST1; end ST1: begin y = 2; if (control) next = ST2; else next = ST3; end ST2: begin y = 3; next = ST3; end ST3: begin y = 4; next = ST0; end default: begin y = 1; next = ST0; end endcase current = next; end end endmodule
nLint reports: document.v(10): Warning 22063: FSM is not implemented using two-process coding. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is port ( reset : in bit; clock : in bit; s: out integer ); end entity top_ety;
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architecture arch of top_ety is type state_T is (a,b,c,d); begin p1: process (clock,reset) is --warning here, FSM is inferred --in one process variable v : state_T :=a; begin if (reset='1') then s<=0; v:=a; elsif (clock'event and clock='1') then case (v) is when a=> s<=1; v:=b; when b=> s<=2; v:=c; when c=> s<=3; v:=d; when others => s<=0; v:=a; end case; end if; end process p1; end architecture arch;
nLint reports: document.vhd(11): Warning 22063: FSM is not implemented using two-process coding. (Design Style)
22067 (Verilog) FSM and Non-FSM Logic in the Same Module 22067 (VHDL) FSM and Non-FSM Logic in the Same Architecture
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: FSM logic and non-FSM "%s" logic should be put in separate modules. (VHDL) <filename>(<line no.>): <severity> <rule no.>: FSM logic and non-FSM "%s" logic should be put in separate architectures. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether FSM logic and non-FSM logic are placed in separate modules. The output signal of the non-FSM logic is reported here to represent the non-FSM logic. (VHDL) This rule checks whether FSM logic and non-FSM logic are placed in separate architectures. The output signal of the non-FSM logic is reported here to represent the non-FSM logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 module test (y, q, clock, reset, control, datain); input clock, reset, control, datain; output [2:0] y; reg [2:0] y; output q; reg q; parameter ST0 = 0,ST1 = 1,ST2 = 2,ST3 = 3; reg[1:0] current, next; always @(control or current) begin case (current) 0: begin y = 1; next = 1; end 1: begin y = 2; if (control) next = 2; else next = 3; end 2: begin y = 3; next = 3; end 3: begin y = 4; next = 0; end default: begin y = 1; next = 0; end endcase end always @(posedge clock or posedge reset) begin if (reset) current = 0; else current = next; end always @(posedge clock) //warning here, a FSM independent logic
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//is inferred in the same module q = datain; endmodule
nLint reports: document.v(36): Warning 22067: FSM logic and non-FSM "q" logic should be put in separate modules. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 entity top_ety is port ( reset : in bit; clock : in bit; data : in bit; q : out bit; y : out bit ); end entity top_ety; architecture arch of top_ety is type state_T is (a,b,c,d); begin p1: process (clock,reset) is variable v : state_T :=a; begin if (reset='1') then v:=a; q<='0'; elsif (clock'event and clock='1') then case (v) is when a=> v:=b; when b=> v:=c; when c=> v:=d; when others => v:=a; end case; if (v=a) then q<='0'; else q<='1'; end if; end if; end process p1; p2 : process( clock, reset ) --warning here, a FSM independent --logic is inferred in the same --architecture begin if ( reset = '1' ) then y <= '0'; elsif ( clock'event and clock = '1' ) then y <= data; end if; end process p2; end architecture arch;
nLint reports: document.vhd(43): Warning 22067: FSM logic and non-FSM "y" logic should be put in separate architectures. (Design Style)
22075 (Verilog) Nested Edge-triggers

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: nested edge-triggered constructs "%s" should not be used. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level3 (Error) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any nested edge-triggered construct. Example
(Verilog) ///////////////example : document.v//////////// 1 module initval; 2 reg clock,reset; 3 wire [8:0] count,y; 4 5 initial 6 begin 7 $monitor($time,,,"clock=%d,count=%d,reset=%d,y=%d",clock,count,reset,y); 8 clock=0; 9 reset=0; 10 #20 reset=1; 11 #10 reset=0; 12 #50 $finish; 13 end 14 always 15 #4 clock=!clock; 16 17 test cc (y,clock,reset,count); 18 endmodule 19 20 module test (y,clock,reset,count); 21 input clock,reset; 22 output [8:0] count,y; 23 reg [8:0] count,y; 24 25 initial 26 count<=0; 27 always @(posedge clock) 28 begin 29 if ( reset ) 30 count = 0; 31 else 32 count= count + 1; 33 @(posedge clock) //warning here 34 y=count; 35 end 36 endmodule
nLint reports: document.v(33): Error 22075: nested edge-triggered constructs "posedge clock" should not be used. (Synthesis)
22077 (Verilog) Edge-trigger in Task

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: edge-triggered construct "%s" should not be used in task "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any edge-triggered construct used in a task. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 module initval; reg clock; reg [12:0] a,b; wire [12:0] y; initial begin $monitor($time,,,"clock=%b,a=%b,b=%b,y=%b", clock ,a,b,y); clock=0; b=12'b 011100111101; a=12'b 101010001111; #150 $finish; end always #10 clock =~clock; test cc (y,clock,a,b); endmodule module test (y,clock,a,b); output [12:0] y; input clock; input [12:0] a,b; reg [12:0] y; always @(posedge clock) multiply(clock,a,b,y); task multiply; input clock; input [12:0] a; input [12:0] b; output [12:0] y1; begin: serialMult reg [5:0] mcnd, mpy; mpy = b[5:0]; mcnd = a[5:0]; y1 = 0; repeat (2)@(posedge clock) begin if (mpy[0]) y1 = y1 + {mcnd, 6'b000000}; mpy = mpy+1; end end endtask endmodule
//warning here
nLint reports: document.v(39): Warning 22077: edge-triggered construct "posedge clock" should not be used in task "multiply". (Synthesis)
22079 Constant Conditional Expression

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: conditional expression "%s" is always %s, or implied to be always %s from context. (VHDL) <filename>(<line no.>): <severity> <rule no.>: conditional expression "%s" yields a constant value. Configurable Parameter Rule group: Simulation; Argument type: (CHECK_PARAMETER, IGNORE_PARAMETER); Argument description: The argument allows users to enable the checking for parameter or not. CHECK_PARAMETER includes parameters as constants whereas IGNORE_PARAMETER excludes parameters as constants; Default value: "IGNORE_PARAMETER" for Verilog, "IGNORE_PARAMETER" for VHDL; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether any conditional expression is always TRUE/FALSE, or implied to be always TRUE/FALSE from context, which causes the opposite part of condition unreachable or causes the condition redundant. (VHDL) This rule checks whether any conditional expression yields a constant value. If the conditional expression is a constant, the resultant condition will be always TRUE or FALSE, which causes the opposite part of condition unreachable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (out, in); output out; input in; reg [7:0] out; wire [7:0] in; always @( in ) begin : local integer i; for (i=7; 3>=0; i=i-1) //warning on "3>=0", condition is constant out[i-2] = in[i]; end endmodule
nLint reports following if the argument value is ("IGNORE_PARAMETER"): document.v(9): Warning 22079: conditional expression "(3 >= 0)" is always true, or implied to be always true from context. (Simulation) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (out, in1, in2); output [7:0] out; input [7:0] in1, in2; reg [7:0] out; always @( if (in1 out = else out = end endmodule in1 or in2 ) begin != 0) in1; (in1 && in2) ? in1&in2 : in1|in2;
nLint reports following if the argument value is ("IGNORE_PARAMETER"):
document2.v(10): Warning 22079: conditional expression "(in1 && in2)" is always false, or implied to be always false from context. (Simulation)
(VHDL) -------------------example : document.vhd------------1 entity top_ety is 2 end top_ety; 3 4 architecture arch of top_ety is 5 constant A : boolean := true; 6 begin 7 if ( A ) then --warning here 8 C <= '1'; 9 elsif ( false ) then --warning here 10 C <= '0'; 11 end if; 12 13 while ( A ) loop --warning here 14 C <= '1'; 15 end loop; 16 17 for A in 0 to 1 loop --no warning because A is not constant 18 Var := Var + A; 19 end loop; 20 21 case A is --warning here 22 when '1' => C <= '1'; 23 when '0' => C <= '0'; 24 end case; 25 26 while ( 3 > 1 ) loop --warning here 27 C <= '1'; 28 end loop; 29 30 end arch; -------------------example : document1.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -- nLint testcase for warning 22079 -library IEEE; use IEEE.STD_Logic_1164.all,IEEE.Numeric_STD.all; entity top_ety is port( Clock : in bit; C : out bit ); end entity top_ety; architecture arch of top_ety is constant A : boolean := true; begin process( Clock ) begin if ( A ) then C <= '1'; elsif ( not A ) then C <= '0'; end if; end process; end arch;
nLint reports following if the argument value is ("IGNORE_PARAMETER"): document1.vhd(18): Warning 22079: conditional expression "a" yields a constant value. (Simulation) document1.vhd(20): Warning 22079: conditional expression "( not A)" yields a constant value. (Simulation) -------------------example : document2.vhd------------1 2 -- nLint testcase for warning 22079 --
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library IEEE; use IEEE.STD_Logic_1164.all,IEEE.Numeric_STD.all; entity top_ety is port( Clock : in bit; C : out bit ); end entity top_ety; architecture arch of top_ety is constant A : boolean := true; begin process( Clock ) begin while ( A ) loop C <= '1'; end loop; end process; end arch;
nLint reports following if the argument value is ("IGNORE_PARAMETER"): document2.vhd(18): Warning 22079: conditional expression "a" yields a constant value. (Simulation) -------------------example : document3.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -- nLint testcase for warning 22079 -library IEEE; use IEEE.STD_Logic_1164.all,IEEE.Numeric_STD.all; entity top_ety is port( Clock : in bit; C : out integer ); end entity top_ety; architecture arch of top_ety is constant A : integer := 5; begin process( Clock ) variable Var : integer := 0; begin for A in 0 to 1 loop --no warning becase this A is not constant A Var := Var + A; end loop; C <= Var; end process; end arch;
nLint reports following if the argument value is ("IGNORE_PARAMETER"): -------------------example : document4.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 -- nLint testcase for warning 22079 -library IEEE; use IEEE.STD_Logic_1164.all,IEEE.Numeric_STD.all; entity top_ety is port( Clock : in bit; C : out bit ); end entity top_ety; architecture arch of top_ety is constant A : bit := '1'; begin process( Clock ) begin case A is
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when '1' => C <= '1'; when '0' => C <= '0'; end case; end process; end architecture arch;
nLint reports following if the argument value is ("IGNORE_PARAMETER"): document4.vhd(19): Warning 22079: conditional expression "1" yields a constant value. (Simulation) document4.vhd(20): Warning 22079: conditional expression "0" yields a constant value. (Simulation) -------------------example : document5.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 -- nLint testcase for warning 22079 -library IEEE; use IEEE.STD_Logic_1164.all,IEEE.Numeric_STD.all; entity top_ety is port( Clock : in bit; C : out bit ); end entity top_ety; architecture arch of top_ety is constant A : boolean := true; begin process( Clock ) begin while ( 3 > 1 ) loop C <= '1'; end loop; end process; end arch;
nLint reports following if the argument value is ("IGNORE_PARAMETER"): document5.vhd(18): Warning 22079: conditional expression "(3 > 1)" yields a constant value. (Simulation)
22082 Port Not Connected

Message <filename>(<line no.>): <severity> <rule no.>: port "%s" is not connected. Configurable Parameter Rule group: Simulation; Argument type: (INPUT, OUTPUT, INOUT); Argument description: select INPUT to check input port; select OUTPUT to check output port; select INOUT to check inout port Default value: "INPUT,OUTPUT,INOUT" for Verilog, "INPUT,OUTPUT,INOUT" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any ports are not connected. It checks hierarchy module instance. See also 22279, 22281, 22283. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test; wire ta, tb; uu u_uu_1( .a(ta), .b() ); //warning here for r22279 uu u_uu_2( .a(ta) ); //warning here for r22082 uu u_uu_3( ta, ); //warning here for r22082 endmodule module uu( a, b ); input a; output b; wire a, b; assign b = a; endmodule
nLint reports following if the argument value is ("INPUT,OUTPUT,INOUT"): document.v(4): Warning 22082: port "b" is not connected. (Simulation) document.v(5): Warning 22082: port "b" is not connected. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 entity EA is port ( r1: in bit; r2: out bit ); end EA; architecture arch of EA is begin end arch; entity top_ety is port ( s1: in bit; s2: out bit ); end top_ety; architecture arch of top_ety is component EA is port ( r1: in bit; r2: out bit );
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end component EA; begin u0: component EA port map (r1=>s1); --warning 22082 on 'r2' u1: component EA port map (r1=>s1, r2=>open); --warning 22279 on 'r2' end arch;
nLint reports following if the argument value is ("INPUT,OUTPUT,INOUT"): document.vhd(24): Warning 22082: port "r2" is not connected. (Simulation)
22083 (Verilog) Parameter Bit-width Too Long 22083 (VHDL) Generic Bit-width Too Long
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the bit width of parameter "%s" should not exceed %d. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the bit width of generic "%s" should not exceed %d. Configurable Parameter Rule group: Simulation, Synthesis, Language Construct; Argument type: integer; Argument description: specify the maximum bit width of parameter value; Default value: "32" for Verilog, "32" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the bit width of the parameter exceeds 'length'. (VHDL) This rule checks whether the bit width of the generic exceeds 'length'. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test; parameter TW=33'b100000000000000000000000000000000; //warning here endmodule
nLint reports following if the argument value is ("32"): document.v(2): Warning 22083: the bit width of parameter "TW" should not exceed 32. (Simulation,Synthesis,Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is generic ( g1: integer; g2: bit_vector :="01010101001010100110101010101010101" --warning on 'g2' ); end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports following if the argument value is ("32"): document.vhd(4): Warning 22083: the bit width of generic "g2" should not exceed 32. (Simulation,Synthesis,Language Construct)
22085 No Return Value in a Conditional Branch of a Function

Message <filename>(<line no.>): <severity> <rule no.>: function "%s" does not return a value in every conditional branch. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether every conditional branch in a function returns a value. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module test; reg clk; reg En; reg [4:0] y; reg [1:0] in; always@( posedge clk ) y = decode2_4(En, in); function [3:0] decode2_4; input En; input [1:0] a; integer n; begin if (!En) decode2_4 = 4'b0; else begin if (a == 1) begin //Lack "else" statement for (n=0; n<4; n=n+1) decode2_4[n] = 1; end end end endfunction endmodule
nLint reports: document.v(9): Warning 22085: function "decode2_4" does not return a value in every conditional branch. (Simulation,Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end top_ety; architecture arch of top_ety is function ADD( A : integer; B : integer ) return integer is begin if ( A > 0 and B > 0 ) then return A + B; end if; -- if without else branch end ADD; begin end arch;
nLint reports: document.vhd(5): Warning 22085: function "ADD" does not return a value in every conditional branch. (Simulation,Language Construct)
22089 (Verilog) Vector Used in a Single-bit Logical Operation

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: Vector "%s" is used in a single-bit logical operation. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule checks whether there are any vectors used as operands for a single-bit logical operator (&&, || or !). Logical operators interpret the vector operand as FALSE (1'b0) if the operand equals to zero or as TRUE (1'b1) if the operand does not equal to zero. The operand evaluation induces comparators implicitly and could be problematic as the design gets larger and vector bit width gets wider. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (.pc(c), .pa(a), .pb(b)); input [2:0] a, b; output [2:0] c; reg [2:0] c; always @(a or b) begin if (a && b) //warning on "a" and "b" c = 1; if (!(a || b)) //warning on "a" and "b" c = 0; end endmodule
nLint reports: document.v(8): Error 22089: Vector "b" is used in a single-bit logical operation. (Simulation,Language Construct) document.v(8): Error 22089: Vector "a" is used in a single-bit logical operation. (Simulation,Language Construct) document.v(10): Error 22089: Vector "b" is used in a single-bit logical operation. (Simulation,Language Construct) document.v(10): Error 22089: Vector "a" is used in a single-bit logical operation. (Simulation,Language Construct)
22091 (Verilog) Multi-bit Expression when One Bit Expression Expected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: condition expression is wider than single-bit. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any condition expression is wider than single-bit. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (a, c); input [1:0] a; output c; reg c; always @(a) begin if (a) //warning here, one bit expression expected, //"a != 2'b00" is desired c = 1; else c = 0; end endmodule
nLint reports: document.v(8): Warning 22091: condition expression is wider than single-bit. (Simulation,Language Construct)
22097 (Verilog) Function Call in Procedural Continuous Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: function call "%s" should not be used in procedural continuous assignment. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any function call is used in a procedural continuous assignment. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module test; reg clock; reg [12:0] a; reg [15:0] b; reg [12:0] y; always @(posedge clock) assign y = multiply(a,b); function [12:0] multiply; input [12:0] a; input [15:0] b; begin: serialMult reg [5:0] mcnd, mpy; mpy = b[5:0]; mcnd = a[5:0]; multiply = 0; repeat (6) begin if (mpy[0]) multiply = multiply + {mcnd, 6'b000000}; multiply = multiply+1; mpy = mpy+1; end end endfunction endmodule
//warning here
nLint reports: document.v(8): Warning 22097: function call "multiply(a, b)" should not be used in procedural continuous assignment. (Design Style)
22098 (Verilog) Deassign with Function Argument

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: function "%s" should not be used in deassign statement. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a function is deassigned. Such a deassignment is unconventional and its semantics are not clearly defined in the language. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 module test; reg clock; reg [12:0] a; reg [15:0] b; reg [12:0] y; always @(posedge clock) begin assign y = multiply(a,b); deassign multiply; //warning on "multiply", no meaning end function [12:0] multiply; input [12:0] a; input [15:0] b; begin: serialMult reg [5:0] mcnd, mpy; mpy = b[5:0]; mcnd = a[5:0]; multiply = 0; repeat (6) begin if (mpy[0]) multiply = multiply + {mcnd, 6'b000000}; multiply = multiply+1; mpy = mpy+1; end end endfunction endmodule
nLint reports: document.v(10): Warning 22098: function "multiply" should not be used in deassign statement. (Language Construct)
22101 (Verilog) Bit Range Specified for Parameter

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: bit range is specified for parameter "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether bit range specification is used for parameters. Parameters are constants and do not belong to either the variable or the net group in Verilog. Hence, bit range specification is not allowed. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; reg b; parameter a = 20; assign b = a[0]; //warning on "a[0]" endmodule
nLint reports: document.v(5): Warning 22101: bit range is specified for parameter "a[0]". (Language Construct)
22103 (Verilog) Case Label out of Boundary

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the value of case label "%s" exceeds the range of the case variable "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there is a case label whose value exceeds the boundary of case variable. The statements associated with the violated case label would never be executed because the value of case label never matches the value of case expression. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (Clock); input Clock; reg [3:0] state; reg [2:0] data; always@(Clock) begin case (state) 16: data <= 3'b111; //warning 15: data <= 3'b110; default: data <= 3'b000; endcase end endmodule
nLint reports: document.v(9): Warning 22103: the value of case label "16" exceeds the range of the case variable "state". (Language Construct)
22104 Bit Width Mismatch in Logic Comparison Operation

Message <filename>(<line no.>): <severity> <rule no.>: width of operand "%s"(%d) does not match that of operand "%s"(%d) in logic comparison operation. Configurable Parameter Rule group: Language Construct; Argument type: (VAR_EQ_CON, VAR_GE_CON); Argument description: select VAR_EQ_CON to specify that the width of variable expression must be equal to the width of cosntant expression; select VAR_GE_CON to specify that the width of variable expression must be larger than or equal to the width of constant expression. Note: this argument is only for Verilog; Default value: "VAR_GE_CON" for Verilog, "VAR_GE_CON" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any width mismatch in logic comparison operations. It checks as follows: 1. Constant vs Constant, no checking 2. Variable vs Constant i. Variable's width != Constant's width, and VAR_EQ_CON chosen, warning ii. Variable's width < Constant's width, warning no matter which argument chosen 3. Variable vs Variable, do checking Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (result, a, b, c, d); output [1:0] result; input [2:0] a, b; input [3:0] c, d; reg [1:0] result; always @(a or b or c or d) if ((a+b) > (c+d)) //warning on "a+b"(3) and "c+d"(4) result = a + c; else if ((a+b) == (c+d)) //warning on "a+b"(3) and "c+d"(4) result = 'b1; else result = 'b11; endmodule
nLint reports following if the argument value is ("VAR_GE_CON"): document.v(8): Warning 22104: width of operand "(a + b)"(3) does not match that of operand "(c + d)"(4) in logic comparison operation. (Language Construct) document.v(11): Warning 22104: width of operand "(a + b)"(3) does not match that of operand "(c + d)"(4) in logic comparison operation. (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 library IEEE; use IEEE.STD_Logic_1164.all,IEEE.Numeric_STD.all; entity top_ety is port(
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A : in bit_vector(1 downto 0); B : in bit_vector(2 downto 0); C : out bit ); end entity top_ety; architecture arch of top_ety is begin process( A, B ) begin if (A=B) then -- warning here C <= '1'; elsif (A/=B) then -- warning here C <= '0'; end if; end process; end architecture arch;
nLint reports following if the argument value is ("VAR_GE_CON"): document.vhd(16): Warning 22104: width of operand "A"(2) does not match that of operand "B"(3) in logic comparison operation. (Language Construct) document.vhd(18): Warning 22104: width of operand "A"(2) does not match that of operand "B"(3) in logic comparison operation. (Language Construct)
22105 (Verilog) Different Bits of Vector Driven in Different Blocks 22105 (VHDL) Different Bits of Vector Driven in Different Concurrent Statements
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: different bits of signal "%s" and "%s" should not be driven in different blocks (at line %d). (VHDL) <filename>(<line no.>): <severity> <rule no.>: different bits of signal "%s" should not be driven in different concurrent statements (at line %d). Configurable Parameter Rule group: Design Style; Argument type: (CHECK_PORT_INST, CHECK_CONT_ASSIGN, CHECK_UNPACKED); Argument description: select CHECK_PORT_INST means to check the rule for the signal connected to portInst; select CHECK_CONT_ASSIGN means to check the rule for the signal in continuous assignment; select CHECK_UNPACKED means to check the rule for unpacked signal, while packed signal is always checked; Default value: "" for Verilog, "" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether different bits of a signal are driven in different blocks. (VHDL) This rule checks whether different bits of a signal are driven in different concurrent statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (a, b, c); input a, b; output [2:0] c; reg [2:0] c; initial c[2] = 1; always@(a) c[0]=a; always@(b) c[1]=b;
//warning here //warning here, "c[1]" and "c[0]" are used //in different always blocks
endmodule
nLint reports following if the argument value is (""): document.v(9): Warning 22105: different bits of signal "c[0]" and "c[1]" should not be driven in different blocks (at line 11). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 entity top_ety is end entity top_ety; architecture arch of top_ety is
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
type array1 is array (1 to 8) of bit; signal s1 : array1; signal a, b: bit; begin p1 : process (a) is begin s1(1)<=a; end process p1; p2 : process (b) is begin s1(2)<=b; --warning here, "s1[1]" and "s1[2]" are used --in different processes end process p2; end architecture arch;
nLint reports following if the argument value is (""): document.vhd(11): Warning 22105: different bits of signal "s1" should not be driven in different concurrent statements (at line 16). (Design Style)
22106 (Verilog) Bit Width Mismatch in Comparison of Case Statement

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: width of "%s"(%d) does not match that of "%s"(%d) in the comparison of case statement. Configurable Parameter Rule group: Language Construct; Argument type: (VAR_EQ_CON, VAR_GE_CON); Argument description: select VAR_EQ_CON to specify that the width of variable expression must be equal to the width of cosntant expression; select VAR_GE_CON to specify that the width of variable expression must be larger than or equal to the width of constant expression; Default value: "VAR_GE_CON" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any width mismatch in the comparison of case statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test; reg [8:0] out, b; reg [1:0] a; reg [1:0] se; always @( a or b ) case (a[1:0]) 2'b00, 2'b01: out 2'b10: out 2'b11: out 3'b100: out endcase endmodule
= = = =
1; (b << 2) + 1; b << 6; b << 4;
nLint reports following if the argument value is ("VAR_GE_CON"): document.v(12): Warning 22106: width of "a[1:0]"(2) does not match that of "3'b100"(3) in the comparison of case statement. (Language Construct)
22107 (Verilog) Redundant Case Labels

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: case label "%s" is redundant. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any case label containing two or more expressions that result in the same value. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 module test (y,clock,reset,control); input clock,reset,control; output [2:0] y; reg [2:0] y; wire clock,reset,control; parameter ST0 = 0,ST1 = 1,ST2 = 2,ST3 = 3; reg[1:0] current, next; always @(control or current) begin case (current) ST0,ST0: begin y <= 1; next <= ST1; end //warning here, redundant case expression ST1: begin y <= 2; if (control) next <= ST2; else next = ST3; end ST2: begin y <= 3; next <= ST3; end ST3: begin y <= 4; next <= ST0; end default: begin y <= 1; next <= ST0; end endcase end always @(posedge clock or posedge reset) begin if(reset) current = ST0; else current = next; end endmodule
nLint reports: document.v(13): Warning 22107: case label "ST0" is redundant. (Coding Style)
22108 (Verilog) Dangling Else

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the "else" clause should be explicitly associated with the proper "if" clause at line %d. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any "else" part which is associated with the "if" part by virtue of the language's default rule. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (a,b,c); input a,b; output[2:0] c; reg [2:0] c; parameter para=10; always@(a) begin if(b) if (a) c= 1; else //warning here //designer want this else belong to the first if, but due to //the second if was not enveloped by " begin end " statement, //compiler will misuse the else as the second if, this may //cause wrong result. c= 2; end endmodule
nLint reports: document.v(11): Warning 22108: the "else" clause should be explicitly associated with the proper "if" clause at line 8. (Coding Style)
22109 (Verilog) Logical or Bitwise OR Used in Event Control

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: 'or' (rather than |, ||) should be used in event expression "%s". Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether '|' or '||' is used in an event expression. The correct usage is 'or'. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module test (clk, rst, set, Data, q1, q2); input clk, rst, set; input Data; output [1:0] q1, q2; reg [1:0] q1, q2; //should be always@(posedge clk or posedge rst) always@(clk | rst) begin if (rst) q1 <= '0; else q1 <= Data; end //should be @(posedge clk or posedge set) always@(clk || set) begin if (set) q2 <= '1; else q2 <= Data; end endmodule
nLint reports: document.v(8): Warning 22109: 'or' (rather than |, ||) should be used in event expression "(clk | rst)". (Simulation,Language Construct) document.v(17): Warning 22109: 'or' (rather than |, ||) should be used in event expression "(clk || set)". (Simulation,Language Construct)
22112 (Verilog) Zero Loop Count

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the for-loop never iterates because expression "%s" is always false. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule evaluates conditional expressions of for-loops. A violation will be reported if the expression is always false which means statements in the for-loop will never be executed. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (a, b, c); input [7:0] a, b; output [7:0] c; reg [7:0] c; integer i; always @(a) for (i=8; i<4; i=i+1) //warning c[i] = 0; endmodule
nLint reports: document.v(8): Error 22112: the for-loop never iterates because expression "(i < 4)" is always false. (Simulation)
22113 Infinite Loop

Message <filename>(<line no.>): <severity> <rule no.>: infinite for-loop is detected. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level3 (Error) Description This rule checks whether the conditional expression of a for-loop is always true which makes the for-loop never stop. The infinite loop causes the simulation to never end. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (a,c); input [7:0] a; output [7:0]c; reg [7:0]c; integer i; always@(a) begin for (i=0;i<7;i=i-1) //warning c[i]=1; end endmodule
nLint reports: document.v(8): Error 22113: infinite for-loop is detected. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity top_ety is port (Clock : in bit; Data : in integer); end top_ety; architecture arch of top_ety is begin process (Clock) variable V : integer; begin loop --warning here V := Data + 1; end loop; loop --no warning here V := Data + 1; exit; end loop; end process; end arch;
nLint reports: document.vhd(11): Error 22113: infinite for-loop is detected. (Simulation)
22115 (Verilog) Undefined Repeat Expression

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: repeat expression "%s" evaluates to X or Z, causing it to repeat zero or unknown times. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any repeat expression is evaluated to X or Z, causing it to repeat zero or unknown times. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (clk,b,c); input clk; input [7:0] b; output [7:0]c; reg [7:0]c; always @(clk) begin repeat (4'b0x10) //repeat zero times c=b; end endmodule
nLint reports: document.v(8): Warning 22115: repeat expression "4'b0x10" evaluates to X or Z, causing it to repeat zero or unknown times. (Simulation)
22117 Synchronous or Asynchronous Reset Detected

Message <filename>(<line no.>): <severity> <rule no.>: "%s" reset "%s" is detected. Configurable Parameter Rule group: Design Style; Argument type: (ASYNC, SYNC, BOTH); Argument description: The argument allows users to configure the rule detecting asynchronous reset (ASYNC), synchronous reset (SYNC) or both (BOTH); Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether there are any synchronous or asynchronous resets in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (count, clock, reset); output [8:0] count; reg [8:0] count; input clock, reset; initial count<=0; always @(posedge clock or negedge reset) begin if (~reset) //warning count = 0; else count = count + 1; end endmodule
nLint reports following if the argument value is ("BOTH"): document.v(11): Warning 22117: "Asynchronous" reset "reset" is detected. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d: in std_logic; q: out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then --warning on 'reset' q<='0'; elsif (rising_edge(clock)) then q<=d; end if; end process p1;
22
nLint reports following if the argument value is ("BOTH"): document.vhd(16): Warning 22117: "Asynchronous" reset "reset" is detected. (Design Style)
22118 (Verilog) Flip-flops with and without Asynchronous Reset/Set Coexist

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: Do not describe flip-flop "%s" with asynchronous reset/set and flip-flop "%s" without asynchronous reset/set in the same always construct. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any flip-flops with asynchronous reset/set co-exist with flipflops without asynchronous reset/set in the same always construct. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module smp(RES,CK,FIN1,FIN2,FOUT1,FOUT2); input RES,CK,FIN1,FIN2; output FOUT1,FOUT2; reg FOUT1,FOUT2; always@(negedge RES or posedge CK) //report 22118 if(~RES) FOUT1 <= 1'b0; else begin FOUT1 <= FIN1; FOUT2 <= FIN2; end endmodule
nLint reports: document.v(5): Warning 22118: Do not describe flip-flop "FOUT1" with asynchronous reset/set and flip-flop "FOUT2" without asynchronous reset/set in the same always construct. (Design Style)
22119 (Verilog) Logic Expression Used in Sensitivity List

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: logic expression "%s" is used in the sensitivity list. Configurable Parameter Rule group: Language Construct, Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether any logic expressions are used in any sensitivity list. Simple identifiers are recommended instead. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (count, clk1, clk2, rst_p); input clk1, clk2, rst_p; output [7:0] count; reg [7:0] count; always @(posedge (clk1 | clk2) or //warning posedge rst_p) if (rst_p) count = 0; else count = count + 1; endmodule
nLint reports: document.v(6): Warning 22119: logic expression "(clk1 | clk2)" is used in the sensitivity list. (Synthesis,Language Construct)
22120 (Verilog) Latch should Not Coexist with Other Logic in a Module
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: latch "%s" should not be mixed with combinational logics or other latches in the module "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether only one latch exists in a module at the RTL level. If any latch co-exists with other logic in the same module, or if there are multiple latches in a module, a violation will be reported. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module example(Q,G,DATA,Q1,G1,DATA1); output Q,Q1; input G,DATA,G1,DATA1; reg Q, Q1; always @(G or DATA1) if(G) Q <= DATA1; always @(G1 or DATA1) if(G1) Q1 = DATA1; else Q1 = 1'b0; endmodule //report 22120
nLint reports: document.v(6): Warning 22120: latch "Q" should not be mixed with combinational logics or other latches in the module "example". (Design Style)
22121 (Verilog) Duplicate Signal Found in Sensitivity List

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: duplicate signal "%s" found in sensitivity list. Configurable Parameter Rule group: Language Construct, Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether any duplicate signal is used in sensitivity list. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (count, clk, rst_p); input clk, rst_p; output [7:0] count; reg [7:0] count; always @(posedge clk or clk //warning on "clk" or posedge rst_p) if (rst_p) count = 0; else count = count + 1; endmodule
nLint reports: document.v(6): Warning 22121: duplicate signal "clk" found in sensitivity list. (Synthesis,Language Construct)
22122 (Verilog) Tri-state Buffer should Not Coexist with Other Logic in a Module
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: tri-state buffer "%s" should not be mixed with other combinational logics or other tri-state buffers in the module "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether only one tri-state buffer exists in a module at RTL level. If any tri-state buffers co-exist with other logics in the same module, or if there are multiple tri-state buffers in a module, a violation will be reported. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module TriState(y,en,data,Q,G,DATA); output y,Q; input en,data,G,DATA; reg y,Q; always @(en or data) //warning 22122 if(en) y = data; else y = 1'bz; always @(G or DATA) if(G) Q <= DATA; endmodule
nLint reports: document.v(7): Warning 22122: tri-state buffer "y" should not be mixed with other combinational logics or other tri-state buffers in the module "TriState". (Design Style)
22123 (Verilog) Specify Asynchronous Reset Signal with Negedge

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: asynchronous reset signal "%s" should be specified only by negedge. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rules checks asynchronous reset at RTL level. A violation is reported if the asynchronous reset is not triggered by negative edge. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module Reg(q,clk,reset,set,d); output q; input clk, reset, set, d; reg q; always @( posedge clk or posedge reset or negedge set) begin if ( reset ) //warning 22123 because asynchronous reset use posedge q <= 1'b0; else if (~set) q <= 1'b1; else q <= d; end endmodule
nLint reports: document.v(6): Warning 22123: asynchronous reset signal "reset" should be specified only by negedge. (Design Style)
22124 (Verilog) Tri-state Output Mixed with Other Logic in a Module

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: fan-out logic of tri-state "%s"(%d) should be in a separate module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rules checks whether the fan-out logic of a tri-state buffer is multi input. A violation is reported if the multi input fan-out logic and the tri-state buffer are in the same module. However, if the fan-out logic is single input such as buffer, inverter, or assignment, a violation will not be reported. Example
(Verilog) ///////////////example : document.v//////////// 1 module smp(RDE, WRE, CNT0, CNT1, BUSI, BUSO); 2 3 input RDE, WRE; 4 input CNT0, CNT1; 5 input[1:0] BUSI; 6 output[1:0] BUSO ; 7 8 smp1 smp1 (.rden(RDE), .wren(WRE), .data(BUSI[0]), .tri_out1(BUSO[0]), .cnt1(CNT0)); 9 smp2a smp2a(.rden(RDE), .data(BUSO[1]), .tri_out1(BUSO[1])); 10 smp2b smp2b(.wren(WRE), .din(BUSO[1]), .cnt1(CNT1)); 11 12 endmodule 13 14 15 module smp1(rden, wren, data, tri_out1, cnt1); 16 17 input rden, wren, data; 18 output tri_out1; 19 output cnt1; 20 21 assign tri_out1 = ( rden ) ? data : 1'bz; 22 assign cnt1 = tri_out1 & wren; //warning here 23 24 endmodule 25 26 module smp2a(rden, data, tri_out1); 27 28 input rden, data; 29 output tri_out1; 30 31 assign tri_out1 = ( rden ) ? data : 1'bz; 32 33 endmodule 34 35 module smp2b(wren, din, cnt1); 36 37 input wren; 38 input din; 39 output cnt1; 40 41 assign cnt1 = din & wren; 42 43 endmodule
nLint reports: document.v(22): Warning 22124: fan-out logic of tri-state "tri_out1"(21) should be in a separate module. (DFT) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module top; wire a,b,c,f,g; test u1 (a,b,c); test1 u2 (c,f,g); endmodule module test(a,b,c); input a,b; output c; wire a,b,c; assign c = b ? a : 1'bz; endmodule module test1(d,f,g); input d,f; output g; wire d,e,f,g; buf (e,d); and (g,e,f); endmodule
nLint reports: document1.v(19): Warning 22124: fan-out logic of tri-state "c"(11) should be in a separate module. (DFT)
22125 (Verilog) Bit Range Used on Non-vector Object

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: bit range should not be used on nonvector object "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether bit select is used on a non-vector object, e.g. integer, event, real, time, etc.. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module test (d, clk, rst_p, q); input d, clk, rst_p; output q; reg q; reg [1:0] a; integer N; time T; always @(posedge clk) if (!rst_p) q = 0; else q = d; always @(d or N[1])//warning on 'N[1]' begin a[0] = N[0]; //warning on 'N[0]' a[1] = T[0]; //warning on 'T[0]' end endmodule
nLint reports: document.v(15): Warning 22125: bit range should not be used on non-vector object "N[1]". (Language Construct) document.v(17): Warning 22125: bit range should not be used on non-vector object "N[0]". (Language Construct) document.v(18): Warning 22125: bit range should not be used on non-vector object "T[0]". (Language Construct)
22126 (Verilog) Tri-state Enable Mixed with Other Logic in a Module

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: logic in enable condition of tri-state "%s"(%d) should be in a separate module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rules checks whether the driving logics for the enable condition of a tri-state buffer is multi input. A violation is reported if the multi input driving logic and the tri-state buffer are in the same module. However, if the driving logic is single input such as buffer, inverter, or assignment, a violation will not be reported. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test(tri_out1,data,a,b); input data,a,b; output tri_out1; wire tri_out1, rden, data; assign tri_out1 = ( rden ) ? data : 1'bz; and (rden,a,b); //warning here endmodule
nLint reports: document.v(6): Warning 22126: logic in enable condition of tri-state "tri_out1"(5) should be in a separate module. (DFT)
22127 Clock Signal Used as Data Input

Message <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" (%s(%d)) is used as a data input ("%s"). Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether any clock signals are used as a data input of any storage elements. The checking passes through all combinational logic until a storage element is reached. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (clock2, clock1, data, y1, y2); input clock2, clock1, data; output y1, y2; reg y1, y2; always @(posedge clock1) y1 = clock2; //warning always @(posedge clock2) y2 = data; endmodule
nLint reports: document.v(7): Warning 22127: clock signal "clock2" (document.v(9)) is used as a data input ("clock2"). (DFT)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock, clock1 : in std_logic; d : in std_logic; q : out std_logic; s : out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then q<='0'; elsif (rising_edge(clock)) then --warning here, 'clock' is --used as clock signal q<=d; end if; end process p1; p2: process (clock1) is begin if (rising_edge(clock1)) then s<=clock; --'clock' is used as data signal end if;
30 31
end process p2; end architecture arch;
nLint reports: document.vhd(28): Warning 22127: clock signal "clock" (document.vhd(19)) is used as a data input ("clock"). (DFT)
22128 Clock Signal Feeds into Macro

Message <filename>(<line no.>): <severity> <rule no.>: clock signal feeds transitively to macro(clock: "%s" (%s(%d)); macro: "%s"). Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any clock signal feeds into macro. The rule checking will pass through any combinational logic. Here "macro cell" are those cell which is embraced by `celldefine/èndcelldefine, the module imported with option -v/-y, the cell defined as macro in symbol library, the module specified as macro cell by option -bb. For a clock signal, if it transitively feeds to more than one macro, we will report violations of all the macro, each violation for each macro. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 //example 1 module test; wire clk, d; reg y; always @(posedge clk) begin y <= d; end test1 u1 (clk); //warning here endmodule `celldefine module test1(in); input in; wire in; endmodule èndcelldefine //example 2 module test2; wire clk, z1, z2, d; reg y; B2I u1 (.A(clk), .Z1(z1), .Z2(z2)); //B2I is MACRO, warning here always @(posedge clk) begin y <= d; end endmodule
nLint reports: document.v(8): Warning 22128: clock signal feeds transitively to macro(clock: "clk" (document.v(5)); macro: "clk"). (DFT) document.v(20): Warning 22128: clock signal feeds transitively to macro(clock: "clk" (document.v(21)); macro: "clk"). (DFT) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 //example 1 module test; wire clk, d; reg y; always @(posedge clk) begin y <= d; end test1 u1 (clk); //warning here
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endmodule `celldefine module test1(in); input in; wire in; endmodule èndcelldefine
nLint reports: document1.v(8): Warning 22128: clock signal feeds transitively to macro(clock: "clk" (document1.v(5)); macro: "clk"). (DFT) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 //example 2 module test; wire clk, z1, z2, d; reg y; B2I u1 (.A(clk), .Z1(z1), .Z2(z2)); //B2I is MACRO, warning here always @(posedge clk) begin y <= d; end endmodule
nLint reports: document2.v(5): Warning 22128: clock signal feeds transitively to macro(clock: "clk" (document2.v(6)); macro: "clk"). (DFT)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is end entity top_ety; architecture arch of top_ety is component B2I is port ( A : in std_logic; Z1: out bit; z2: out bit); end component B2I; signal clk: std_logic; signal q: bit; signal d: bit; signal z11,z21: bit; begin p1: process (clk) is begin if (rising_edge(clk)) then q<=d; end if; end process p1; u0: component B2I port map (A=>clk, Z1=>z11, Z2=>z21); --warning here end architecture arch;
nLint reports: document.vhd(25): Warning 22128: clock signal feeds transitively to macro(clock: "clk" (document.vhd(21)); macro: "clk"). (DFT)
22129 Clock Signal Used as Reset

Message <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" (%s(%d)) is used as a reset signal ("%s"). Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether there is any clock signal which is also used as a reset signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module test (clock, clock2, reset, count, d); input clock, clock2, reset, d; output [8:0] count; reg [8:0] count; reg a; initial count<=0; always @(posedge clock or negedge reset) begin if (reset) count = 0; else count= count + 1; end always @(posedge clock2) if (~clock) //warning a=0; else a=d; endmodule //"clock" is used as clock
nLint reports: document.v(19): Warning 22129: clock signal "clock" (document.v(10)) is used as a reset signal ("clock"). (DFT)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( clock : in std_logic; clock2 : in std_logic; d : in std_logic; q : out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock) is begin if (rising_edge(clock)) then --'clock' is used as clock q<=d; end if;
19 20 21 22 23 24 25 26 27 28 29 30 31
end process p1; p2: process (clock2) is begin if (rising_edge(clock2)) then if (clock='1') then --warning on 'clock', used as reset q<='0'; else q<=not d; end if; end if; end process p2; end architecture arch;
nLint reports: document.vhd(24): Warning 22129: clock signal "clock" (document.vhd(16)) is used as a reset signal ("clock"). (DFT)
22130 Clock Feeds into Primary Output

Message <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" (%s(%d)) feeds the output signal ("%s") directly or indirectly. Configurable Parameter Rule group: DFT, Clock; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether any clock signals feed into primary outputs directly or indirectly by passing through combinational logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test (clock, reset, count, clk_out); input clock, reset; output [8:0] count; output clk_out; reg [8:0] count; initial count<=0; always @(posedge clock or negedge reset)//"clock" is used as clock begin if (reset) count = 0; else count= count + 1; end assign clk_out = clock; //warning endmodule
nLint reports: document.v(20): Warning 22130: clock signal "clock" (document.v(12)) feeds the output signal ("clk_out") directly or indirectly. (DFT,Clock)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( clock : in std_logic; d : in std_logic; q : out std_logic; clk_out : out std_logic ); end top_ety; architecture arch of top_ety is begin p1: process (clock) is begin if (rising_edge(clock)) then --'clock' is used as clock q<=d; end if; end process;
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p2: process (clock) is begin clk_out <= clock; --//warning here; end process; end arch;
nLint reports: document.vhd(23): Warning 22130: clock signal "clock" (document.vhd(16)) feeds the output signal ("clk_out") directly or indirectly. (DFT,Clock)
22131 Clock Driven by Sequential Logic

Message <filename>(<line no.>): <severity> <rule no.>: clock signal should not be driven by sequential logic (clock: "%s" (%s(%d)); sequential logic output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any clock signal is driven by a sequential logic. Originally in lint2.2, use 22229's argument to control if a latch enable is a clock or ctrl. In lint2.3, treate all latch enable as clock. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (count, reset, clock, data); input clock, reset, data; output [8:0] count; reg [8:0] count; reg qc; always @(posedge clock) qc = data; //"qc" is output of register, warning on "qc" always @(posedge qc or negedge reset) begin //qc is used as clock signal and drived //by above sequential logic if (~reset) count = 0; else count= count + 1; end endmodule
nLint reports: document.v(8): Warning 22131: clock signal should not be driven by sequential logic (clock: "qc" (document.v(10)); sequential logic output: "qc"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : inout std_logic ); end entity top_ety; architecture arch of top_ety is signal s : std_logic; begin p1: process (clock) is begin if (rising_edge(clock)) then
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s<=d; -- 's' is output of register,warning on 's' end if; end process p1; p2: process (reset,s) is begin if (reset='1') then q<='0'; elsif (rising_edge(s)) then --'s' used as clock here q<=not q; end if; end process p2; end architecture arch;
nLint reports: document.vhd(18): Warning 22131: clock signal should not be driven by sequential logic (clock: "s" (document.vhd(26)); sequential logic output: "s"). (DFT,Design Style)
22132 Clock Active on Both Edges

Message <filename>(<line no.>): <severity> <rule no.>: clock source "%s" should not trigger flip-flops on both rising and falling edges. Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether a clock source triggers flip-flops on both rising and falling edges. Such usage can cause DFT problems. This rule will be check only when clock source tree is extracted. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test(clk, d, q); input clk, d; output q; wire clk, d; reg q1, q; always @(posedge clk) q1 = d; always @(negedge clk) q = q1; endmodule
nLint reports: document.v(1): Warning 22132: clock source "test.clk" should not trigger flipflops on both rising and falling edges. (DFT)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 entity top_ety is port (clk : in bit; d : in bit; q : out bit); end top_ety; architecture arch of top_ety is signal q1 : bit; begin process (clk) begin if (clk'event and clk = '1') then q1 <= d; end if; end process; process (clk) begin if (clk'event and clk = '0') then q <= q1; end if; end process; end arch;
nLint reports: document.vhd(2): Warning 22132: clock source "top_ety.clk" should not trigger
flip-flops on both rising and falling edges. (DFT)
22133 (Verilog) Reconverged Clock

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: reconverged clock "%s" found. Configurable Parameter Rule group: Clock; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any reconverged clock is found. This rule is checked only if clock domain is extracted and the option "-pass_gated_clk" is off. Here "reconverged clock" means: 1. come from different source node 2. come from same source node, but from different path Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 //1. come from different source node module test; wire a,b,c,d,d1,f; reg y; always @(posedge a) y=d; always @(posedge b) y=d; always @(posedge c) y=d; and (b,a,f); and (c,a,f); and (d1,b,c); //warning here always @(posedge d1) y=d; always @(negedge d1) y=d; endmodule
nLint reports: document.v(13): Warning 22133: reconverged clock "test.d1" found. (Clock) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 //2. come from same source node, but from different path module test; wire a,b,c,d,d1,f; reg y; always @(posedge a) y=d; and (b,a,f); and (c,a,f); and (d1,b,c); //warning here always @(posedge d1) y=d; always @(negedge d1) y=d; endmodule
nLint reports: document1.v(9): Warning 22133: reconverged clock "test.d1" found. (Clock)
22134 (Verilog) Clock Feeds into Floating Gate

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: clock signal feeds transitively to floating gate (clock: "%s" (%s(%d)); floating gate output: "%s"). Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any clock signal feeds into a floating gate. The rule checking will pass through any combinational logic. For a clock signal, if it transitively feeds to more than one floating gate, violations are reported on all the floating gates, each violation for each floating gate. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module top(clk,d1,out1); input clk,d1; output out1; wire n1; FD1 u1(.CP(clk),.D(d1),.Q(out1)); IV u2(.A(clk),.Z()); //warning here AN2 u3(.A(n1),.B(d1),.Z()); //warning here IV u4(.A(clk),.Z(n1)); endmodule
nLint reports: document.v(7): Warning 22134: clock signal feeds transitively to floating gate (clock: "clk" (document.v(6)); floating gate output: "clk"). (DFT) document.v(8): Warning 22134: clock signal feeds transitively to floating gate (clock: "clk" (document.v(6)); floating gate output: "n1"). (DFT)
22139 (Verilog) Constant Event Expression

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: constant "%s" is used as event control. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule checks whether any constant is used as an event control. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (a, y); input [7:0] a; output [7:0] y; reg [7:0] y; parameter c = 1; always @(c) //warning y = a; endmodule
nLint reports: document.v(7): Error 22139: constant "c" is used as event control. (Simulation,Language Construct)
22149 Direct Connection from Input to Output

Message <filename>(<line no.>): <severity> <rule no.>: input port "%s" and output port "%s" should not be connected directly. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any input signal is connected directly to an output signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (a, b, c); input a; //warning on 'a', is directly connected to output signal 'c' output c; reg c; always @(a) c = a; endmodule
nLint reports: document.v(1): Warning 22149: input port "a" and output port "c" should not be connected directly. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is port ( x : in integer; --warning on 'x', is directly connected to --output 'y' y : out integer ); end entity top_ety; architecture arch of top_ety is begin y<=x; end architecture arch;
nLint reports: document.vhd(2): Warning 22149: input port "x" and output port "y" should not be connected directly. (Design Style)
22151 (Verilog) Assignment to an Input Signal

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: an assignment is given to an input signal "%s". Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule checks whether any input signals are assigned with a value inside the module. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (a, b, c); input [7:0] a, b; output [7:0] c; reg [7:0] c; wire [7:0] a; assign a[2] = 0; //warning on "a[2]", input signal is assigned always @(a) c = b; endmodule
nLint reports: document.v(7): Error 22151: an assignment is given to an input signal "a[2]". (Simulation,Language Construct)
22152 (Verilog) Output Signal Referenced

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: output signal "%s" should not be referenced inside the module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level1 (Information) This rule is turned OFF by default; Description (Verilog) This rule checks whether any output signal is referenced inside the module. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (a,b,c,d); input a,b ; output c,d; wire c,d,e; assign e= a & b ; assign e = d; //warning here assign c = a & e; endmodule
nLint reports: document.v(7): Information 22152: output signal "d" should not be referenced inside the module. (Design Style)
22153 (Verilog) Multiple Top Modules

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: more than one top module detected, top modules: "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is more than one top module in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 module initval; reg clock, reset; wire [8:0] count; initial begin clock=0; reset=0; $monitor($time,,,"count=%d,reset=%d",count,reset); #200 $finish; end always #4 clock=!clock; //test cc (clock, reset, count); endmodule module test (clock, reset, count); //warning on 'test', //another top module input clock, reset; output [8:0] count; reg [8:0] count; initial count <= 0; always @(posedge clock or posedge reset) begin if (reset) count = 0; else count= count + 1; end endmodule
nLint reports: document.v(1): Warning 22153: more than one top module detected, top modules: "initval, test, ...". (Design Style)
22155 Empty Block

Message <filename>(<line no.>): <severity> <rule no.>: empty block is detected. Configurable Parameter Rule group: Language Construct; Argument type: string; Argument description: The argument allows users to configure a string to suppress the checking. If the configured string matches with the first string found the in the first comment inside the block, the violation won't be reported; Default value: "" for Verilog, "" for VHDL; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there are any blocks without statements. The blocks may be functions, tasks or always blocks. (VHDL) This rule checks whether there are any blocks without statements. The blocks may be blocks or procedures. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (clock,q_nxt,q); input clock,q_nxt; output q; reg q; function integer adder; //warning input a, b; ; endfunction endmodule
nLint reports following if the argument value is (""): document.v(6): Warning 22155: empty block is detected. (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is procedure Proc ( D : in bit; Q : out bit ) is --warning on 'procedure' begin end procedure; begin BLK1 : block --warning on 'block' begin end block BLK1; end arch;
nLint reports following if the argument value is (""): document.vhd(5): Warning 22155: empty block is detected. (Language Construct) document.vhd(10): Warning 22155: empty block is detected. (Language Construct)
22157 Empty Process

Message <filename>(<line no.>): <severity> <rule no.>: empty process is detected. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there are any empty always blocks in the design. (VHDL) This rule checks whether there are any empty processes in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (clock, q_nxt, q); input clock, q_nxt; output q; reg q; always @(posedge clock) //warning ; endmodule
nLint reports: document.v(5): Warning 22157: empty process is detected. (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is port (Clock : in bit; Reset : in bit); end top_ety; architecture arch of top_ety is begin process( Clock , Reset ) --warning on 'process' begin end process; end arch;
nLint reports: document.vhd(8): Warning 22157: empty process is detected. (Language Construct)
22159 Non-constant Delay

Message <filename>(<line no.>): <severity> <rule no.>: delay value "%s" is not a constant. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any non-constant delay values. If a delay value is a variable or a value with "x" or "z", nLint reports the violation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (clock, q_nxt, q); input clock, q_nxt; output q; reg q; reg [2:0] a; initial a = 2; always #4 a = ~a; always @(posedge clock) q = #a q_nxt; //warning on "a", //delay value is not static constant endmodule
nLint reports: document.v(11): Warning 22159: delay value "a" is not a constant. (Design Style) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 `timescale 1ns/100ps module test(in1, in2, out1, out2, out3); input in1, in2; output out1, out2, out3; integer i; assign #(0.987) out1= in1& in2; assign #(1'bz) out2 = in1 & in2; //warning, delay has x or z assign #(i) out3 = in1 & in2; //warning, delay is not a constant endmodule
nLint reports: document1.v(8): Warning 22159: delay value "1'bz" is not a constant. (Design Style) document1.v(9): Warning 22159: delay value "i" is not a constant. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is port (Clock : in bit; A : in bit; S : out bit ); end top_ety; architecture arch of top_ety is signal Time_Dly : time := 20 ns;
10 11 12 13 14 15 16 17 18 19
begin process (Clock) begin if (Clock'event and Clock = '1') then S <= A after Time_Dly; --warning on "Time_Dly", --delay value is not constant else end if; end process; end arch;
nLint reports: document.vhd(14): Warning 22159: delay value "time_dly" is not a constant. (Design Style)
22161 (Verilog) Wire Not Explicitly Declared

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: wire "%s" should be explicitly declared. Configurable Parameter Rule group: Coding Style; Argument type: IMPLICIT_WIRE_ARG; Argument description: Select CHECK_ALL to specify that the rule 22161 is violated if any wires are declared implicitly; select CHECK_GENERATE_ONLY to specify that the rule 22161 is violated only if the wires are declared implicitly in generated instantiations; Default value: "CHECK_ALL" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether all wires are declared explicitly. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (a, b, c, d, f); input a, b, c, d; output f; //wire f1, f2; assign d = f; and and1(f1, a, b); //warning on "f1", implicit wire or or1(f2, c, d); //warning on "f2", implicit wire or or2(f, f1, f2); endmodule
nLint reports following if the argument value is ("CHECK_ALL"): document.v(8): Warning 22161: wire "f1" should be explicitly declared. (Coding Style) document.v(9): Warning 22161: wire "f2" should be explicitly declared. (Coding Style) ///////////////example : document2.v2k//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module top(clk, a, b, Din); input clk; input [3:0] a, b, Din; genvar k; generate for (k = 0; k<4; k = k+1) begin: GEN_FF sub inst_DFF (.D(Din[k]),.Q(Qout[k]),.CK(clk) ); end endgenerate assign out = a + b; endmodule //no warning on "out"
//warning on "Qout"
module sub(input CK, input D, reg Q; always @(posedge CK) begin Q <= D; end endmodule
output Q);
nLint reports following if the argument value is ( CHECK_GENERATE_ONLY):
document2.v2k(8): Warning 22161: wire "Qout" should be explicitly declared. (Coding Style)
22165 Signal Driven by Constant

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" is driven by a constant. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether any signal is driven by a constant. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; parameter W = 2; wire [3:0] q; assign q = 2 * W; endmodule //warning
nLint reports: document.v(5): Warning 22165: signal "q" is driven by a constant. (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : inout std_logic ); end entity top_ety; architecture arch of top_ety is begin p2: process (reset,clock) is begin if ( reset = '1' ) then q <= '0'; --warning on "q", data input is constant "0" and "1" elsif ( rising_edge(clock) ) then q<='1'; end if; end process p2; end architecture arch;
nLint reports: document.vhd(17): Warning 22165: signal "q" is driven by a constant. (Language Construct)
22167 Bi-directional Port Declared

Message <filename>(<line no.>): <severity> <rule no.>: bi-directional port "%s" declared. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level1 (Information) This rule is turned OFF by default; Description This rule checks whether there are any bi-directional ports. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test (a, b, c, d, f, f1, f2); input a, b, c, d; output f; inout f1, f2; //warning on "f1", "f2" endmodule
nLint reports: document.v(1): Information 22167: bi-directional port "f2" declared. (Design Style) document.v(1): Information 22167: bi-directional port "f1" declared. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : out std_logic; q : inout std_logic --warning on "q" ); end entity top_ety; architecture arch of top_ety is begin end architecture arch;
nLint reports: document.vhd(8): Information 22167: bi-directional port "q" declared. (Design Style)
22168 (Verilog) Connection between Unidirectional Port and Bidirectional Port

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: a %s signal "%s"(%d) is connected to a %s port. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any connections exist between a bidirectional port and a unidirectional port. If an input or output signal is connected to an inout port, this rule is violated; or if an inout signal is connected to an input or output port, this rule is violated. The connection between an inout port and an input or output port may be caused by an error typing "input" as "inout" or vice versa. Example
(Verilog) ///////////////example : document.v//////////// 1 module test1(rst, rst_i, io1, io2, ctrl); 2 3 inout rst; //Warning: rst is defined as input at celldefine, but used as inout 4 output rst_i; 5 input ctrl; 6 inout io1, io2; //OK: two inout signals are connected to inout ports 7 8 PDISDGZ PRESET_B(.PAD(rst), .C(rst_i), .IO1(io1), .IO2(io2), .CTRL(ctrl)); 9 10 endmodule 11 12 `celldefine 13 module PDISDGZ (PAD, C, IO1, IO2, CTRL); 14 input PAD, CTRL; 15 output C; 16 inout IO1, IO2; 17 18 buf #0 (C, PAD); 19 tranif1 t1 (IO1, IO2, CTRL); 20 endmodule 21 èndcelldefine
nLint reports: document.v(8): Warning 22168: a bidirectional signal "rst"(3) is connected to a unidirectional port. (Design Style)
22169 Unassigned Bits in Function's Return Value

Message <filename>(<line no.>): <severity> <rule no.>: bit(s) of a function's return value "%s" are not assigned with a value. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule checks whether all bits of a function's return value are properly assigned with a value. It will not trace whether the assigned value has been correctly initialized. Also, it will not report violations if: a function's return value is never assigned a value; or a function's return value is conditionally assigned in some branches but not all. This is already a rule 22085 to check whether every conditional branch in a function returns a value, which can catch the violations in the above cases. Rule 22169 will only check unconditional assignment to a function's return value, or conditional assignment with the value being assigned in every branch. (VHDL) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test (a,b,y); input [3:0] a,b; output [7:0] y; reg [7:0] y; integer N; always@(a or b) y=funtest(a,b); function [7:0] funtest; //warning on "funfest[7]" input [3:0] a,b; begin:fun1 for (N=0;N<4;N=N+1) funtest[N]=a[N]; //assign "funfest[0:3]" for (N=4;N<7;N=N+1) funtest[N]=b[N-4]; //assign "funfest[4:6]" end endfunction endmodule
nLint reports: document.v(10): Error 22169: bit(s) of a function's return value "funtest[7]" are not assigned with a value. (Simulation,Language Construct)
(VHDL)
22175 Signal Used as Synchronous and Asynchronous Reset

Message <filename>(<line no.>): <severity> <rule no.>: asynchronous reset should not be used as synchronous reset (asynchronous reset: "%s" (%s(%d)); synchronous reset: "%s"). Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any signal is used as synchronous and asynchronous reset simultaneously. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module test (clock1, reset, data, count, y); input clock1, reset, data; output [8:0] count; reg [8:0] count; output y; reg y; initial count <= 0; always @(posedge clock1 or negedge reset)//asynchronous "reset" begin if (~reset) count = 0; else count = count + 1; end always @(posedge clock1)//synchronous "reset", mixed begin if (~reset) y = 0; else y = data; end endmodule
nLint reports: document.v(21): Warning 22175: asynchronous reset should not be used as synchronous reset (asynchronous reset: "reset" (document.v(13)); synchronous reset: "reset"). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is port ( reset : in bit; clock : in bit; d : in bit; x : out bit; y : out bit ); end entity top_ety; architecture arch of top_ety is
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
begin p1 : process (reset,clock) is begin if (reset='1') then -- warning here, asynchronous "reset" x<='0'; elsif (clock'event and clock='1') then x<=d; end if; end process p1; p2 : process (clock) is begin if (clock'event and clock='1') then if (reset='1') then -- synchronous "reset" here y<='0'; else y<=d; end if; end if; end process p2; end architecture arch;
nLint reports: document.vhd(24): Warning 22175: asynchronous reset should not be used as synchronous reset (asynchronous reset: "reset" (document.vhd(14)); synchronous reset: "reset"). (Design Style)
22176 Signal Used as Synchronous and Asynchronous Set

Message <filename>(<line no.>): <severity> <rule no.>: asynchronous set should not be used as synchronous set (asynchronous set: "%s" (%s(%d)); synchronous set: "%s"). Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any signal is used as synchronous and asynchronous set simultaneously. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module test (y1, y2, data, clock, preset, clear); input data, clock, preset, clear; output y1, y2; reg y1, y2; always @(posedge clock or posedge clear or posedge preset) //asynchronous set signal "preset" begin: forset if (clear) y1 = 0; else if (preset) y1 = 1; else y1 = data; end always @(posedge clock) begin if (clear) y2 = 0; else if (preset)//synchronous set "preset", mixed y2 = 1; else y2 = data; end endmodule
nLint reports: document.v(23): Warning 22176: asynchronous set should not be used as synchronous set (asynchronous set: "preset" (document.v(12)); synchronous set: "preset"). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is port ( set : in bit; clock : in bit; d : in bit; x : out bit; y : out bit ); end entity top_ety;
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
architecture arch of top_ety is begin p1 : process (set,clock) is begin if (set='1') then -- warning here, asynchronous "set" x<='1'; elsif (clock'event and clock='1') then x<=d; end if; end process p1; p2 : process (clock) is begin if (clock'event and clock='1') then if (set='1') then -- synchronous "set" here y<='1'; else y<=d; end if; end if; end process p2; end architecture arch;
nLint reports: document.vhd(24): Warning 22176: asynchronous set should not be used as synchronous set (asynchronous set: "set" (document.vhd(14)); synchronous set: "set"). (Design Style)
22177 (Verilog) Signal Driven by Both Blocking and Non-blocking Assignments

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" is assigned by both blocking and non-blocking assignments (at line %d). Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level3 (Error) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether any signals are assigned by both blocking and non-blocking statements. This may cause different results in pre_synthesis and post_synthesis simulations. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (c, a, b, en); input a, b, en; output c; reg c; always @(a or b) if (~en) c = a; //blocking assignment on "c" else c <= #2 b; //non-blocking assignment on "c" endmodule
nLint reports: document.v(10): Error 22177: signal "c" is assigned by both blocking and nonblocking assignments (at line 8). (Synthesis)
22179 Signal in Sensitivity List Changed in the Block

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" in the sensitivity list is assigned within the same block. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level3 (Error) Description This rule checks whether any signal in the sensitivity list is changed its value in the same block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test (a, b, c, d, f); input a, b, c, d; output f; reg f, f1, f2; always @(a or b or c or d) begin f1 = a & b; f2 = c | d; end always @(f1 or f2) begin f1 = 0; //warning f = f1 ^ f2; end endmodule
nLint reports: document.v(14): Error 22179: signal "f1" in the sensitivity list is assigned within the same block. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is port( A : inout bit; Clock : in bit; D : out bit ); end top_ety; architecture arch of top_ety is begin process(A, Clock ) --A is sensitive signal begin if (Clock = '1' ) then D <= A; else A <= '1'; --warning on 'A', assigned end if; end process; end arch;
nLint reports: document.vhd(14): Error 22179: signal "A" in the sensitivity list is assigned within the same block. (Simulation)
22181 Multiple Clock Signals

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: more than one clock signal detected in the module, clocks: %s. (VHDL) <filename>(<line no.>): <severity> <rule no.>: more than one clock signal detected in the architecture, clocks: %s. Configurable Parameter Rule group: DFT, Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is more than one clock signal in a module. Originally in lint2.2, use 22229's argument to control if a latch enable is a clock or ctrl. In lint2.3, treate all latch enable as clock. (VHDL) Check to see if there is more than one clock signal in an architecture. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 module test (clock1,clock2,clock3,reset,count,data,data1,y,y1); input clock1, clock2, clock3, reset, data, data1; output [8:0] count; reg [8:0] count; output y, y1; reg y, y1; always @(posedge clock1 or negedge reset)//clock signal "clock1" begin if (~reset) count = 0; else count= count + 1; end always @(posedge clock2)//warning on "clock2", another clock signal begin if (~reset) y = 0; else y = data; end always @(posedge clock3)//warning on "clock3", another clock signal begin if (~reset) y1 = 0; else y1 = data1; end endmodule
nLint reports: document.v(16): Warning 22181: more than one clock signal detected in the module, clocks: "clock2 (16), clock3 (24), clock1 (8)". (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 entity top_ety is port ( reset : in bit;
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
clock1 : in bit; clock2 : in bit; d : in bit; x : out bit; y : out bit ); end entity top_ety; architecture arch of top_ety is begin p1 : process (reset,clock1) is begin if (reset='1') then x<='1'; elsif (clock1'event and clock1='1') then --warning here, clock --signal "clock1" x<=d; end if; end process p1; p2 : process (reset,clock2) is begin if (reset='1') then y<='1'; elsif (clock2'event and clock2='1') then --another clock --signal "clock2" y<=d; end if; end process p2; end architecture arch;
nLint reports: document.vhd(17): Warning 22181: more than one clock signal detected in the architecture, clocks: "clock1 (17), clock2 (27)". (DFT,Design Style)
22187 (Verilog) Negative Delay

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: delay expression "%s" should not be negative. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any negative delay. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (a,b,c,d); input a,b; output [1:0] c; output d; reg [1:0] c; wire d; parameter DELAY=-5; always @(a or b) if (a) #(-5) c = (a+b); //warning on "-5" else #(DELAY) c = a; //warning on "DELAY" and #(-3,5) and1(d,a,b); //warning on "-3" endmodule
nLint reports: document.v(11): Warning 22187: delay expression "-5" should not be negative. (Simulation,Language Construct) document.v(13): Warning 22187: delay expression "DELAY" should not be negative. (Simulation,Language Construct) document.v(14): Warning 22187: delay expression "-3" should not be negative. (Simulation,Language Construct)
22193 (Verilog) Recursive Function Call

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: recursive function or task call "%s" detected. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any recursive function or task call, which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 module test (y,sig); input [3:0] sig; output [16:0] y; wire [16:0] y; parameter n=10; function [16:0] nmulti; input [3:0] sig; input [16:0] n; //warning on "funtemp->nmulti->funtemp" nmulti=funtemp(sig,n-1) * sig; endfunction function [16:0] funtemp; input [3:0] s; input [16:0] m; //warning on "nmulti->funtemp->nmulti" funtemp=nmulti(s,m); endfunction endmodule
nLint reports: document.v(12): Warning 22193: recursive function or task call "funtemp(sig, (n 1))" detected. (Synthesis) document.v(20): Warning 22193: recursive function or task call "nmulti(s, m)" detected. (Synthesis)
22194 (Verilog) Function Call Stack Exceeds Maximum Depth

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: function call stack exceeds maximum depth %d. Configurable Parameter Rule group: Synthesis; Argument type: integer; Argument description: specify the maximum depth of function call stack; Default value: "1000" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether the function call stack of a recursive function exceeds the maximum depth. Exceeding maximum depth may cause synthesis problem in function call. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module t(in, out); input [31:0] in; output [63:0] out; assign out=factorial(1001) * in; function automatic [63:0] factorial; input [31:0] n; if ( n == 1 ) factorial = 1; else factorial = n * factorial(n-1); endfunction endmodule
nLint reports following if the argument value is ("1000"): document.sv(5): Warning 22194: function call stack exceeds maximum depth 1000. (Synthesis)
22195 Signal Assigned to Self

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" should not be assigned to itself. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any signal is assigned to itself, which is redundant and may cause latch inferred. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (out, in); output [3:0] out; input [3:0] in; reg [3:0] out; always @( in or out ) begin out[0] = out[0]; //warning on "out[0]" out[1] = out[1] & 1; //warning on "out[1]" out[2] = out[2] | 'h0; //warning on "out[2]" out[3] = in[3]; end endmodule
nLint reports: document.v(7): Warning 22195: signal "out[0]" should not be assigned to itself. (Simulation) document.v(8): Warning 22195: signal "out[1]" should not be assigned to itself. (Simulation) document.v(9): Warning 22195: signal "out[2]" should not be assigned to itself. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is signal Self : bit := '1'; begin Self <= Self; --warning here Self <= not Self; end arch;
nLint reports: document.vhd(7): Warning 22195: signal "Self" should not be assigned to itself. (Simulation)
22199 (Verilog) Reduction Operation on Single-bit Signal

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: reduction operation should not be performed on single-bit signal "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any reduction operation (including unary &, |, ^, ~&, ~|, ~^, ^~), which is redundant, on single bit signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (c, a); input a; output c; reg c; always @(a) c = (&a); //warning on "&a", //reduction operation on one bit signal endmodule
nLint reports: document.v(7): Warning 22199: reduction operation should not be performed on single-bit signal "a". (Language Construct)
22201 Write Enable Signals for Memories should be Disabled in the Test Mode
Message <filename>(<line no.>): <severity> <rule no.>: write enable signal "%s" for memories should be disabled in the test mode. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description Write enable signals for memories should be disabled in the test mode. If user specifies following command line option or defines preference setting in GUI mode, this rule will be checked if it is not disabled in rule setting. -we_mem <signal>=<value> Here the <value> means as the value the <signal> will be active. This rule is used to check under testing mode the <signal> should be inactive. The testing mode case can be specified by -vs port_name=value It is said that if the constant set by "-vs" which can make the signal to be the value different with the value set by "-we_mem", there is no violation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 //in command line, when specify: //-we_mem test.WE_mem=1 -vs test.test_mode=0 //nLint will detect that test.WE_mem can not be resolved as 0. //So the memory write enable signal test.WE_mem is not disabled //by test.test_mode. module test(test_mode, WE, WE_mem); input test_mode; input WE; output WE_mem; assign WE_mem = test_mode | WE; //code inferred to memory operation //... endmodule
nLint reports: document.v(10): Warning 22201: write enable signal "test.WE_mem" for memories should be disabled in the test mode. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -----in command line, when specify: -we_mem top_ety.WE_mem=1 -vs top_ety.test_mode=0 nLint will detect that top_ety.WE_mem can not be resolved as 0. So the memory write enable signal top_ety.WE_mem is not disabled by top_ety.test_mode.
entity top_ety is port (test_mode : in bit; WE : in bit; WE_mem : out bit); end top_ety; architecture arch of top_ety is begin WE_mem <= test_mode or WE;
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end;
nLint reports: document.vhd(10): Warning 22201: write enable signal "top_ety.WE_mem" for memories should be disabled in the test mode. (Design Style)
22203 Reset Signal Used as Data Input

Message <filename>(<line no.>): <severity> <rule no.>: reset signal should not be used as data (reset: "%s" (%s(%d)); data: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any reset signal is also used as a data signal. The rule checking will pass through any combinational logic, so combinational data will not be treated as data. Only sequential data will be treated as data. For a reset signal, if it transitively feeds to more than one sequential data, violations are reported on all the data, each violation for each datum. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test (.py(y), .co(count), .cl(clock), .re(reset)); input clock, reset; output [8:0] count; reg [8:0] count; output y; reg y; initial count <= 0; always @(posedge clock) begin if (~reset)//"reset" is reset signal count = 0; else count = count + 1; end always @(posedge clock) y = reset; //warning here, "reset" is used as data input endmodule
nLint reports following if the argument value is ("BOTH"): document.v(20): Warning 22203: reset signal should not be used as data (reset: "reset" (document.v(13)); data: "reset"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic;
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q : out std_logic ); end top_ety; architecture arch of top_ety is signal rst : std_logic; begin p1: process (clock,reset) is begin if (reset='1') then -- "reset" is reset signal q<='0'; elsif (rising_edge(clock)) then q<=d; end if; end process p1; p2: process (clock) is begin if (rising_edge(clock)) then q<=reset; --"reset" is used as data input end if; end process p2; end arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(27): Warning 22203: reset signal should not be used as data (reset: "reset" (document.vhd(17)); data: "reset"). (DFT,Design Style)
22204 Reset Signal Feeds into Primary Output

Message <filename>(<line no.>): <severity> <rule no.>: reset signal should not feed into primary output (reset: "%s" (%s(%d)); output signal: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any reset signal feeds into primary output. The rule checking will pass through any combinational logic. For a reset signal, if it transitively feeds to more than one primary output, violations are reported on all the outputs, each violation for each output. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module test (.py(y), .co(count), .cl(clock), .re(reset)); input clock, reset; output [8:0] count; reg [8:0] count; output y; initial count <= 0; always @(posedge clock) begin if (~reset) count = 0; else count = count + 1; end assign y = endmodule reset; //"reset" feed into primary output
nLint reports following if the argument value is ("BOTH"): document.v(18): Warning 22204: reset signal should not feed into primary output (reset: "reset" (document.v(12)); output signal: "y"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic; s : out std_logic );
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end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then q<='0'; elsif (rising_edge(clock)) then q<=d; end if; end process p1; p2: process (reset) is begin s<=reset; --"reset" feed into primary output end process p2; end architecture arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(26): Warning 22204: reset signal should not feed into primary output (reset: "reset" (document.vhd(17)); output signal: "s"). (DFT,Design Style)
22205 Reset Driven by Sequential Logic

Message <filename>(<line no.>): <severity> <rule no.>: reset signal should not be driven by sequential logic (reset: "%s" (%s(%d)); sequential logic output: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any reset signal is driven by a sequential logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (count, c, clk, a, b); input clk, a, b; output [8:0] count; output c; reg c; reg [8:0] count; always @( posedge clk ) c = a & b; //"c" is output of registe, warning here always @(posedge clk) begin if (~c) //"c" is used as reset count = 0; else count = count + 1; end endmodule
nLint reports following if the argument value is ("BOTH"): document.v(9): Warning 22205: reset signal should not be driven by sequential logic (reset: "c" (document.v(13)); sequential logic output: "c"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic); end entity top_ety; architecture arch of top_ety is signal s : std_logic; begin p1: process (clock,reset) is
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begin if (rising_edge(clock)) then s<=reset; --warning here, dff output "s" end if; end process p1; p2: process (clock,s) is begin if (s='1') then --"s" used as reset signal q<='0'; elsif (rising_edge(clock)) then q<=d; end if; end process p2; end architecture arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(17): Warning 22205: reset signal should not be driven by sequential logic (reset: "s" (document.vhd(23)); sequential logic output: "s"). (DFT,Design Style)
22207 (Verilog) Non-constant Shift Amount

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: number of bits to shift ("%s") should be a constant. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any non-constant shift amount. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (a, clk, num, b); input clk; input [7:0] a, num; output [7:0] b; reg [7:0] b; always @(posedge clk) b = a << num; //warning on "num", not a static constant endmodule
nLint reports: document.v(8): Warning 22207: number of bits to shift ("num") should be a constant. (Synthesis)
22209 Insufficient Index Variable

Message <filename>(<line no.>): <severity> <rule no.>: index variable "%s" is too small to address all bits in the signal "%s". Configurable Parameter Rule group: Language Construct; Argument type: (CHECK_ADDR,IGNORE_ADDR); Argument description: the arguments allows users to check the index variable (address) for multidimensional arrays or not. Select CHECK_ADDR to enable the checking for index variable for multi-dimensional arrays. Otherwise, the default argument IGNORE_ADDR disables the checking; Default value: "IGNORE_ADDR" for Verilog, "IGNORE_ADDR" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether index signals are wide enough to address all the bits in the indexed vector signals. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (a, clk, num, b); input clk; input [7:0] a; input [1:0] num; output b; reg b; always @(posedge clk) b = a[num]; //warning endmodule
nLint reports following if the argument value is ("IGNORE_ADDR"): document.v(9): Warning 22209: index variable "num" is too small to address all bits in the signal "a". (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is end top_ety; architecture arch of top_ety is subtype Int3_0 is integer range 3 downto 0; subtype Int7_0 is integer range 7 downto 0; signal A : bit_vector(7 downto 0); signal B : bit; begin process variable Index : Int3_0; begin B <= A(Index); --warning here wait; end process; end arch;
nLint reports following if the argument value is ("IGNORE_ADDR"): document.vhd(13): Warning 22209: index variable "Index" is too small to address all bits in the signal "A". (Language Construct)
22210 (Verilog) Oversized Index Variable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the value of the index variable "%s" exceeds the declared range value of the signal "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the index signal exceeds the range of bus signals or multiple dimensional arrays. Note that it may be caused by the maximum or minimum value of the index signal being larger or smaller than the declared range of the indexed signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test(a, clk, num, b); input clk; input [3:0] a; input [4:0] num; output b; reg b; always @(posedge clk) b = a[num]; //warning on "a[num]" endmodule
nLint reports: document.v(9): Warning 22210: the value of the index variable "num" exceeds the declared range value of the signal "a[num]". (Language Construct)
22211 Signal Stuck at Logic 1

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" is stuck at logic 1. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level3 (Error) Description This rule checks whether there is a signal whose value is always logic 1. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (d, e, a, b); input a, b; output d, e; reg d, e; wire a, b; always @( a ) begin d = 1; //warning e = a | ~a; //warning end endmodule
nLint reports: document.v(9): Error 22211: signal "d" is stuck at logic 1. (Synthesis) document.v(10): Error 22211: signal "e" is stuck at logic 1. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end entity top_ety; architecture arch of top_ety is signal s : bit; signal x : bit; signal y : bit; begin s<='1'; --warning here y<=x xnor x; --warning here end architecture arch;
nLint reports: document.vhd(9): Error 22211: signal "s" is stuck at logic 1. (Synthesis) document.vhd(10): Error 22211: signal "y" is stuck at logic 1. (Synthesis)
22213 Signal Stuck at Logic 0

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" is stuck at logic 0. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level3 (Error) Description This rule checks whether there is a signal whose value is always logic 0. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (d, e, a, b); input a, b; output d,e; reg d,e; always @( a ) begin d = 0; //warning e = a & ~a; //warning end endmodule
nLint reports: document.v(8): Error 22213: signal "d" is stuck at logic 0. (Synthesis) document.v(9): Error 22213: signal "e" is stuck at logic 0. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end entity top_ety; architecture arch of top_ety is signal s : bit; signal x : bit; signal y : bit; begin s<='0'; --warning here y<=x and (not x); --warning here end architecture arch;
nLint reports: document.vhd(9): Error 22213: signal "s" is stuck at logic 0. (Synthesis) document.vhd(10): Error 22213: signal "y" is stuck at logic 0. (Synthesis)
22217 (Verilog) Event Never Triggered

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: event "%s" is never triggered. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any never-triggered event (due to no event enable statement found, or the event enable statement is dead code). Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 module test (count, carry, clk, rst); input clk, rst; output [7:0] count; output carry; reg [7:0] count; reg carry; event start, stop, full; always @(posedge clk) if (!rst) ->stop; else if (count == 256) carry <= 1; else ->start; always @(start) if (count == 256) carry <= 1; else count <= count+1; always @(stop) count = 0; always @(full) //warning on "full", it is never enabled #4 carry = 0; endmodule
nLint reports: document.v(7): Error 22217: event "full" is never triggered. (Simulation)
22218 (Verilog) Ignore Do Not Care Values in Case Expressions

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s is detected in %s expression "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether 'x', 'z' or '?' is used in any casex expressions and whether 'z'or '?' is used in any casez expressions. Case expressions with x, z or ? are not synthesizable. Example
(Verilog) ///////////////example : document.sv//////////// 1 module top; 2 3 int ns, ps; 4 logic en; 5 6 always 7 begin 8 casex ({1'b0,1'b?,1'b1 }) //waning here, '?' is used in casex expression 9 3'b?xz: ns = 1; 10 3'b00x: ns = 2; 11 default: ns = 0; 12 endcase 13 end 14 15 always 16 begin 17 casez (en? 1'b1: 1'bz) //warning here, 'z' is used in casez expression 18 1'b?: ps = 1; 19 1'b0: ps = 2; 20 default: ps = 0; 21 endcase 22 end 23 24 endmodule
nLint reports: document.sv(8): Error 22218: X/Z/? is detected in casex expression "1'b0, 1'b?, 1'b1". (Synthesis) document.sv(17): Error 22218: Z/? is detected in casez expression "(en ? 1'b1 : 1'bz)". (Synthesis)
22219 (Verilog) x/z? Used in Case Label

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: case label "%s" contains x, z or ?. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level3 (Error) Description (Verilog) This rule checks whether any x, z, or ? is used in case labels of case statements. Casex or casez is recommended to use if there is any x, z, or ? in case labels. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (out, clk, in, cas); input clk, in, cas; output out; reg out; always @(posedge clk) case (cas) 1'b0: out = !in; 1'b1: out = in; 1'bz: out = 1; //warning on "1'bz" 1'bx: out = 0; //warning on "1'bx" default: out = 1; endcase endmodule
nLint reports: document.v(10): Error 22219: case label "1'bz" contains x, z or ?. (Language Construct) document.v(11): Error 22219: case label "1'bx" contains x, z or ?. (Language Construct)
22220 (Verilog) Casez Label Contains X

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: X detected in casez label "%s" (should use casex). Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any casez item that contains x (should use casex, instead.) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (out, clk, in, cas); input clk, in, cas; output out; reg out; always @(posedge clk) casez (cas) 1'b0: out = !in; 1'b1: out = in; 1'bz: out = 1; 1'bx: out = 0; //warning on "1'bx" default: out = 1; endcase endmodule
nLint reports: document.v(11): Warning 22220: X detected in casez label "1'bx" (should use casex). (Language Construct)
22221 Reset Signal Active High and Low

Message <filename>(<line no.>): <severity> <rule no.>: high active reset should not be used as low active reset (high active reset: "%s" (%s(%d)); low active reset: "%s"). Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any reset signal is both active high and active low. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module test (clock1, clock2, reset, count, data, y); input clock1,clock2,reset,data; output [8:0] count; reg [8:0] count; output y; reg y; initial count <= 0; always @(posedge clock1 or negedge reset) begin if (~reset) //low active "reset", warning on "reset" count = 0; else count = count + 1; end always @(posedge clock2) if (reset) //high active "reset" y = 0; else y = data; endmodule
nLint reports: document.v(13): Warning 22221: high active reset should not be used as low active reset (high active reset: "reset" (document.v(20)); low active reset: "reset"). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port ( reset : in bit; clock : in bit; d : in bit; q : out bit; s : out bit ); end entity top_ety; architecture arch of top_ety is begin p1 : process (reset, clock) begin if (reset='1') then --active high
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q<='0'; elsif (clock'event and clock='1') then q<=d; end if; end process p1; p2 : process (reset, clock) begin if (reset='0') then --active low s<='0'; elsif (clock'event and clock='1') then s<=d; end if; end process p2; end architecture arch;
nLint reports: document.vhd(23): Warning 22221: high active reset should not be used as low active reset (high active reset: "reset" (document.vhd(14)); low active reset: "reset"). (Design Style)
22223 Set Signal Active High and Low

Message <filename>(<line no.>): <severity> <rule no.>: high active set should not be used as low active set (high active set: "%s" (%s(%d)); low active set: "%s"). Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any set signal is both active high and active low. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 module test (y1, y2, data1, data2, enable, preset, clear); input data1, data2, enable, preset, clear; output y1, y2; reg y1, y2; always @(enable or clear or preset or data1) begin: forset1_PROC if (clear) y1 = 0; else if (preset) //high active "preset" y1 = 1; else if (enable) y1 = data1; end always @(enable or clear or preset or data2) begin: forset2_PROC if (clear) y2 = 0; else if (!preset) //low active "preset", warning on "preset" y2 = 1; else if (enable) y2 = data2; end endmodule
nLint reports: document.v(23): Warning 22223: high active set should not be used as low active set (high active set: "preset" (document.v(11)); low active set: "preset"). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is port ( set : in bit; clock : in bit; d : in bit; q : out bit; s : out bit ); end entity top_ety;
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architecture arch of top_ety is begin p1 : process (set, clock) begin if (set='1') then --active high q<='1'; elsif (clock'event and clock='1') then q<=d; end if; end process p1; p2 : process (set, clock) begin if (set='0') then --active low s<='1'; elsif (clock'event and clock='1') then s<=d; end if; end process p2; end architecture arch;
nLint reports: document.vhd(23): Warning 22223: high active set should not be used as low active set (high active set: "set" (document.vhd(14)); low active set: "set"). (Design Style)
22225 Clock Signal Used on Both Edges

Message <filename>(<line no.>): <severity> <rule no.>: clock signal is used on both rising edge ("%s" (%s(%d)) and falling edge ("%s"). Configurable Parameter Rule group: Design Style; Argument type: (TRUE, FALSE); Argument description: The argument allows users to limit the rule checking within the same module. Select TRUE to apply the checking within the same module. Select FALSE for the whole design; Default value: "TRUE" for Verilog, "TRUE" for VHDL; Default severity : Level3 (Error) Description This rule checks whether any clock signals are used on both rising edge and falling edge. This checking passes through "assignment", "buffer", "pair of inverter" of clock signals whereas it will not pass through combinational logic. For users looking for more complex clock checking, please refer to rule 22132. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module test (clock, reset, count, data, y); input clock, reset, data; output [8:0] count; reg [8:0] count; output y; reg y; initial count <= 0; always @(posedge clock or negedge reset)//posedge "clock" begin if (~reset) count = 0; else count= count + 1; end always @(negedge clock)//negedge "clock", warning begin if (~reset) y = 0; else y = data; end endmodule
nLint reports following if the argument value is ("TRUE"): document.v(19): Error 22225: clock signal is used on both rising edge ("clock" (document.v(11)) and falling edge ("clock"). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 entity top_ety is port ( reset : in bit; clock : in bit; d : in bit; q : out bit;
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s : out bit ); end entity top_ety; architecture arch of top_ety is begin p1 : process (reset, clock) begin if (reset='1') then q<='0'; elsif (clock'event and clock='1') then --rising edge clock q<=d; end if; end process p1; p2 : process (reset, clock) begin if (reset='1') then s<='0'; elsif (clock'event and clock='0') then --falling edge clock, mixed s<=d; end if; end process p2; end architecture arch;
nLint reports following if the argument value is ("TRUE"): document.vhd(25): Error 22225: clock signal is used on both rising edge ("clock" (document.vhd(16)) and falling edge ("clock"). (Design Style)
22227 Set Signal Used as Data Input

Message <filename>(<line no.>): <severity> <rule no.>: set signal should not be used as data (set: "%s" (%s(%d)); data: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any set signal is also used as a data signal. The rule checking will pass through any combinational logic, so combinational data will not be treated as data. Only sequential data will be treated as data. For a set signal, if it transitively feeds to more than one sequential data, violations are reported on all the data, each violation for each datum. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (clock2, set, data, y1, y2); input clock2, data, set; output y1, y2; reg y1, y2; always if ( y1 else y1 @(posedge clock2 or negedge set ) ~set )//"set" is used as set signal <= 1'b1; <= data;
always @(posedge clock2) y2 = set;//"set" is used as data input, warning on "set" endmodule
nLint reports following if the argument value is ("BOTH"): document.v(13): Warning 22227: set signal should not be used as data (set: "set" (document.v(7)); data: "set"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( set : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic; s : out std_logic ); end entity top_ety; architecture arch of top_ety is signal rst : std_logic;
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begin p1: process (clock,set) is begin if (set='1') then --"set" is used as set signal q<='1'; elsif (rising_edge(clock)) then q<=d; end if; end process p1; p2: process (clock) is begin if (rising_edge(clock)) then q<=set; -- "set" is used as data input end if; end process p2; end architecture arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(28): Warning 22227: set signal should not be used as data (set: "set" (document.vhd(18)); data: "set"). (DFT,Design Style)
22228 Set Signal Feeds into Primary Output

Message <filename>(<line no.>): <severity> <rule no.>: set signal should not feed into primary output (set: "%s" (%s(%d)); output signal: "%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous type may violate this rule; select SYNC to specify that only synchronous type may violate this rule; select BOTH to specify that both asynchronous type and synchronous type may violate this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any set signal feeds into a primary output. The rule checking will pass through any combinational logic. For a set signal, if it transitively feeds to more than one primary output, violations are reported on all the outputs, each violation for each output. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test (.py(y), .d(data), .co(count), .cl(clock), .se(set)); input clock, set; input [8:0] data; output [8:0] count; reg [8:0] count; output y; initial count <= 0; always @(posedge clock) begin if (set) count = 1; else count = data; end assign y = endmodule set; //"set" feed into primary output
nLint reports following if the argument value is ("BOTH"): document.v(19): Warning 22228: set signal should not feed into primary output (set: "set" (document.v(13)); output signal: "y"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( set : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic;
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s : out std_logic ); end entity top_ety; architecture arch of top_ety is signal rst : std_logic; begin p1: process (clock,set) is begin if (set='1') then --"set" is used as set signal q<='1'; elsif (rising_edge(clock)) then q<=d; end if; end process p1; p2: process (rst) is begin if (rst='1') then s<='0'; else s<=set; --"set" feeds into primary output, warning on "set" end if; end process p2; end architecture arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(28): Warning 22228: set signal should not feed into primary output (set: "set" (document.vhd(18)); output signal: "s"). (DFT,Design Style)
22229 Clock Signal Used as a Control

Message <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" (%s(%d)) is used as a control signal ("%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether any clock signals are used as control signals. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (clock2, data, y1, y2); input clock2, data; output y1, y2; reg y1, y2; always @(posedge clock2) //"clock2" is used as clock y1 = data; always if ( y2 else y2 endmodule @( data or clock2 ) clock2 ) //warning = data; = ~data;
nLint reports: document.v(10): Warning 22229: clock signal "clock2" (document.v(6)) is used as a control signal ("clock2"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( set : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic; s : out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,set) is begin if (set='1') then q<='1'; elsif (rising_edge(clock)) then --"clock" is used as clock q<=d; end if; end process p1; p2: process (clock) is begin if (clock='1') then --"clock" is used as control input,
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--warning on "clock" s<=d; end if; end process p2; end architecture arch;
nLint reports:
22231 Clock Signal Used as Set

Message <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" (%s(%d)) is used as a set signal ("%s"). Configurable Parameter Rule group: Design Style, DFT; Argument type: none; Default severity : Level2 (Warning) Description This rule checks whether any clock signals are used as set signals. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module test (q1, q2, clk_1, clk_2, set, d1, d2); output q1, q2; input clk_1, clk_2, set, d1, d2; reg q1, q2; wire clk_1, clk_2, set, d1, d2; always if ( q1 else q1 always if ( q2 else q2 endmodule @( posedge clk_1 or negedge set ) ~set ) <= 1'b1; <= d1; @( posedge clk_2 or posedge clk_1 ) clk_1 ) //warning <= 1'b1; <= d2;
nLint reports: document.v(14): Warning 22231: clock signal "clk_1" (document.v(7)) is used as a set signal ("clk_1"). (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( set : in std_logic; clk_1 : in std_logic; clk_2 : in std_logic; d1 : in std_logic; d2 : in std_logic; q1 : out std_logic; q2 : out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clk_1,set) is begin if (set = '1') then q1 <= '1'; elsif (rising_edge(clk_1)) then --"clk_1" is used as clock signal q1 <= d1;
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end if; end process p1; p2: process (clk_1, clk_2) is begin if (clk_1='1') then --warning here, "clk_1" is also used --as set signal q2 <= '1'; elsif (rising_edge(clk_2)) then q2 <= d2; end if; end process p2; end architecture arch;
nLint reports: document.vhd(28): Warning 22231: clock signal "clk_1" (document.vhd(21)) is used as a set signal ("clk_1"). (DFT,Design Style)
22233 Signal Used as Set and Reset

Message <filename>(<line no.>): <severity> <rule no.>: reset signal should not be used as set (reset: "%s" (%s(%d)); set: "%s"). Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any reset signal is also used as a set signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module test (q1, q2, clk_1, enable, d1, d2); output q1, q2; input clk_1, enable, d1, d2; reg q1, q2; wire clk_1, enable, d1, d2; always if ( q1 else q1 @( posedge clk_1 or negedge enable ) ~enable ) //"enable" is used as reset <= 1'b0; <= d1;
always @( posedge clk_1 or posedge enable ) if ( enable ) //warning here, "enable" is also used as //set signal q2 <= 1'b1; else q2 <= d2; endmodule
nLint reports: document.v(14): Warning 22233: reset signal should not be used as set (reset: "enable" (document.v(8)); set: "enable"). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic; s : out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock, reset) is begin if (reset='1') then --"reset" is used as reset signal q <= '0'; elsif (rising_edge(clock)) then
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q <= d; end if; end process p1; p2: process (reset) is begin if (reset = '1') then --warning here, "reset" is also used --as set signal s <= '1'; elsif (rising_edge(clock)) then s <= not d; end if; end process p2; end architecture arch;
nLint reports: document.vhd(26): Warning 22233: reset signal should not be used as set (reset: "reset" (document.vhd(17)); set: "reset"). (Design Style)
22235 All Bits Shifted Out

Message <filename>(<line no.>): <severity> <rule no.>: all bits in signal "%s" are shifted out. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description This rule checks whether there is any shift operation that has all the bits in the signal shifted out. Example
(Verilog) ///////////////example : document.v//////////// 1 reg [7:0] sig; 2 reg [7:0] q; 3 ... 4 q = sig << 8;//all 8 bits of sig are shifted out, warning case: 5 module test; 6 7 reg clk; 8 reg q; 9 10 initial begin 11 $monitor( "%t : q=%b", $time, q); 12 q = 0; 13 clk = 0; 14 #1 clk = 1; 15 #5 $finish; 16 end 17 18 always @ (posedge clk) begin 19 if ( ( ( 1'b1 << 1 ) > 2'b01 ) | 1'b0 ) //no warning here 20 q <= 1; 21 end 22 endmodule 23 24 The simulation result is: q will be set to '1' after #1. 25 It is conflict with standard. nLint will follow industry tool.///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 module test (q, sig); input [7:0] sig; output [7:0] q; reg [7:0] q; always @(sig) q = sig << 8; endmodule
Here a special
//all 8 bits of sig are shifted out, warning
nLint reports: document1.v(7): Error 22235: all bits in signal "sig" are shifted out. (Simulation) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 //Here a special case: module test; reg clk; reg q; initial begin $monitor( "%t : q=%b", $time, q); q = 0;
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clk = 0; #1 clk = 1; #5 $finish; end always @ (posedge clk) begin if ( ( ( 1'b1 << 1 ) > 2'b01 ) | 1'b0 ) q <= 1; end endmodule
//no warning here
//The simulation result is: q will be set to '1' after #1. //It is conflict with standard. nLint will follow industry tool.
nLint reports:
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is signal S1 : bit_vector(1 downto 0) := "11"; signal S2 : bit_vector(1 downto 0); constant N : integer := 3; begin S2 <= S1 sll N; --warning here, all bits of S1 is shifted out end arch;
nLint reports: document.vhd(9): Error 22235: all bits in signal "S1" are shifted out. (Simulation)
22239 (Verilog) Non-constant Case Label 22239 (VHDL) Non-constant Select Label
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: case label "%s" is not a constant. (VHDL) <filename>(<line no.>): <severity> <rule no.>: select label "%s" is not a constant. Configurable Parameter Rule group: Synthesis; Argument type: (CHECK_CONSTCASEEXPR, IGNORE_CONSTCASEEXPR); Argument description: The argument allows users to ignore the rule checking for case statements whose case expression is a constant. Select CHECK_CONSTCASEEXPR to enable the checking for case statements with constant case expression. Select IGNORE_CONSTCASEEXPR to ignore the checking for case statements with constant case expression; Default value: "IGNORE_CONSTCASEEXPR" for Verilog, "IGNORE_CONSTCASEEXPR" for VHDL; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether any non-constant case labels are used in case statements. (VHDL) This rule checks whether any non-constant select labels are used in case statements. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (out, sel, tmp, data); output out; input [2:0] sel, data; input [1:0] tmp; reg out; always @(sel or data or tmp) casex (sel) // Synopsys full_case 3'bx0: out = data[0]; 3'b01: out = data[1]; tmp: out = data[2]; //warning default: out = 0; endcase endmodule
nLint reports following if the argument value is ("IGNORE_CONSTCASEEXPR"): document.v(11): Warning 22239: case label "tmp" is not a constant. (Synthesis) ///////////////example : document_1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module smp(zo,sel); input[3:0] sel; output[3:0] zo; reg [3:0] zo;
always@( sel ) case(1'b1) sel[0]: sel[1]: sel[2]: sel[3]: default: endcase
zo zo zo zo zo
= = = = =
4'b0001; //warning if argument is CHECK_CONSTCASEEXPR 4'b0010; 4'b0100; 4'b1000; 4'b0000;
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endmodule
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is type FSM is ( start, run, stop ); signal n_dout : bit; shared variable aa : FSM := stop; shared variable bb : FSM := start; begin with bb select n_dout <= '1' when start | run, '0' when aa; --warning here end arch;
nLint reports following if the argument value is ("IGNORE_CONSTCASEEXPR"): document.vhd(12): Warning 22239: select label "aa" is not a constant. (Synthesis)
22243 (Verilog) Default Not Used as the Last Case Label

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: default label is not the last label in the case statement. Configurable Parameter Rule group: Simulation, Language Construct; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether the default label is used as the last label in a case statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module test (out, sel, in); input [2:0] sel; input [5:1] in; output out; reg out; wire [2:0] sel; wire [5:1] in; always @(sel case (sel) 0: out = 1: out = 2: out = 3: out = default: 4: out = endcase endmodule or in) in[1]; in[2]; in[3]; in[4]; out = 0; //warning in[5];
nLint reports: document.v(15): Warning 22243: default label is not the last label in the case statement. (Simulation,Language Construct)
22246 (Verilog) Non-blocking Assignment with Delay in Sequential Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: delay should not be used on the righthand side of non-blocking assignment in sequential always blocks. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any delay control is used on the right-hand side of nonblocking assignment in sequential always blocks. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test; wire d, clk; reg c, out; always @ (posedge clk) begin c <= #1 d; //Warning out <= c; end endmodule
nLint reports: document.v(6): Warning 22246: delay should not be used on the right-hand side of non-blocking assignment in sequential always blocks. (Coding Style)
22247 (Verilog) Delay in Non-blocking Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: delay should not be used in a nonblocking assignment. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: (CHECK_DEPEND,IGNORE_DEPEND); Argument description: warning will only on nonblocking assignment which has dependency when argument is CHECK_DEPEND; Default value: "IGNORE_DEPEND" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any delay is used in a non-blocking assignment. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (q, clock, reset, d); output q; input clock, reset, d; reg q; wire clock, reset, d; parameter D_RQ = 1, D_CQ = 2; always @(posedge clock or negedge reset) if (~reset) #D_RQ q <= 0; //delay control "#D_RQ" may cause //non-blocking effect invalid, warning else #D_CQ q <= d; //delay control "#D_CQ" may cause //non-blocking effect invalid, warning endmodule
nLint reports following if the argument value is ("IGNORE_DEPEND"): document.v(10): Warning 22247: delay should not be used in a non-blocking assignment. (Simulation,Synthesis) document.v(13): Warning 22247: delay should not be used in a non-blocking assignment. (Simulation,Synthesis)
22249 (Verilog) Variables with Different Bit Widths Used in Conditional Assignment Branches
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the bit widths of the conditional assignment operands "%s"(%d) and "%s"(%d) are different. Configurable Parameter Rule group: Language Construct; Argument type: (VAR_EQ_CON, VAR_GE_CON) (ORIG_MUL_WIDTH, EXPAND_MUL_WIDTH); Argument description: The first argument determines whether to report warning if the width of variable is larger than that of constant. Select VAR_EQ_CON to specify that the width of variable expression must be equal to the width of constant expression; select VAR_GE_CON to specify that the width of variable expression must be larger than or equal to the width of constant expression. The second argument determines how to calculate the bit width of the multiplication result. Select ORIG_MUL_WIDTH to specify that the bit width of multiplication follows LRM; select EXPAND_MUL_WIDTH to specify that the bit width of multiplication is the sum of two operators' bit width, and the carry bits from addition/subtraction are also counted in. Besides, the integer constant's bit width is optimized; Default value: "VAR_GE_CON","ORIG_MUL_WIDTH" for Verilog; Default severity : Level3 (Error) Description (Verilog) This rule checks whether operands in conditional assignment are of the same size. The checking won't be done if both operands are constants. If one operand is a constant and the other operand is a variable, the checking is done according to the argument setting. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (a, b, c, d); input b; input [2:0] c; input [3:0] d; output [3:0] a; reg [3:0] a; assign a = b ? c[2:1] : d[3:0]; //warning endmodule
nLint reports following if the argument value is ("VAR_GE_CON","ORIG_MUL_WIDTH"): document.v(8): Error 22249: the bit widths of the conditional assignment operands "c[2:1]"(2) and "d[3:0]"(4) are different. (Language Construct) ///////////////example : document2.v2k//////////// 1 2 3 4 5 6 7 8 9 10 11 module mult(a,b,test, prod1, prod2, prod3, prod4); input [9:0] a; input [7:0] b; input test; output [24:0] prod1, prod2, prod3, prod4; assign prod1 assign prod2 assign prod3 assign prod4 endmodule [19:0] [19:0] [19:0] [19:0] = = = = test test test test ? ? ? ? a a a 0 : : : : (2'b0 * {2'b0, b[7:0]}); (b[1:0] * b[7:0]); b + 1; (a[9:2]*b[7:0]);
nLint reports following if the argument value is ( "VAR_GE_CON",
"EXPAND_MUL_WIDTH"): document2.v2k(7): Error 22249: the bit widths of the conditional assignment operands "a"(10) and "(2'b0 *..."(12) are different. (Language Construct) document2.v2k(9): Error 22249: the bit widths of the conditional assignment operands "a"(10) and "(b + 1)"(9) are different. (Language Construct)
22251 (Verilog) Integer Used in Concatenation

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: integer "%s" is used in concatenation. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether any integer is used in a concatenation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (out, in); output [7:0] out; input in; wire [7:0] out; integer i; assign out = {in, i}; //warning endmodule
nLint reports: document.v(7): Warning 22251: integer "i" is used in concatenation. (Language Construct)
22252 (Verilog) Multiple Concatenation Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: multiple concatenation "%s" is used. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether multiple concatenations are used which stop the placement and routing flow. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test(); reg [1:0] b; wire [1:0] a = {2{1'b1}}; //22252 warning always b = {2{1'b1}}; //22252 warning endmodule
nLint reports: document.v(3): Warning 22252: multiple concatenation "21'b1" is used. (Design Style) document.v(5): Warning 22252: multiple concatenation "21'b1" is used. (Design Style)
22254 (Verilog) Avoid Confusing Self-determined Expressions

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: confusing self-determined expressions should not be used. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any confusing self-determined expressions are used. Use intermediate signals and additional assignments to clarify the widths of arithmetic expressions (context-determined expressions). Only multiplication expressions are currently checked. Example
(Verilog) ///////////////example : document.v2k//////////// 1 2 3 4 5 6 module mul(input [1:0] a, [1:0] b, output [3:0] c); assign c = {a*b}; endmodule
nLint reports: document.v2k(3): Warning 22254: confusing self-determined expressions should not be used. (Design Style)
22255 Task or Function Refers to a Non-local Variable

Message <filename>(<line no.>): <severity> <rule no.>: function/task "%s" refers to a non-local variable "%s". Configurable Parameter Rule group: Language Construct; Argument type: (REFERENCE, MODIFICATION, BOTH) (CHECK_VOIDFUNC, IGNORE_VOIDFUNC); Argument description: The combination of REFMOD_ENUM_ARG and VOID_FUNC_ARG Default value: "BOTH","CHECK_VOIDFUNC" for Verilog, "BOTH","CHECK_VOIDFUNC" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether any non-local variables are referred to in any functions or tasks. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module test (out, clock, reset, in); output [7:0] out; input [7:0] in; input clock, reset; reg [7:0] out; wire [7:0] in; wire clock, reset; always @(posedge clock or negedge reset) if (~reset) out = 0; else out = shift(in); //variable "out" function [7:0] shift; input [7:0] in; integer i; begin for (i=1; i<8; i=i+1) out[i] = in[i-1]; //warning out[0] = in[7]; end endfunction endmodule
nLint reports following if the argument value is ("BOTH","CHECK_VOIDFUNC"): document.v(15): Warning 22255: function/task "shift" refers to a non-local variable "out". (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety signal S : bit; procedure ABC ( signal A : signal B : begin B <= A and S; --warning end ABC; begin is in bit; out bit ) is here
12
end arch;
nLint reports following if the argument value is ("BOTH","CHECK_VOIDFUNC"): document.vhd(9): Warning 22255: function/task "ABC" refers to a non-local variable "S". (Language Construct)
22259 (Verilog) Loop Variable Not an Integer

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: loop variable "%s" should be an integer. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any loop variable that is not an integer. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test (q, clock, reset, d); output [7:0] q; input clock, reset; input [7:0] d; reg [7:0] q; reg [2:0] index; wire [7:0] d; wire clock, reset; always @(posedge clock or negedge reset) if (~reset) q <= 0; else begin // "index" used as loop variable but not an integer for (index=0; index<7; index=index+1) //warning here q[index+1] <= d[index]; q[0] <= d[7]; end endmodule
nLint reports: document.v(16): Warning 22259: loop variable "index" should be an integer. (Language Construct)
22261 Tri-state Inferred in Non-top Module

Message <filename>(<line no.>): <severity> <rule no.>: tri-state "%s" should not be inferred in a non-top module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any tri-state is inferred in a non-top module. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 module top(count, clock, reset, load, data); output [3:0] count; input [3:0] data; input clock, reset, load; wire [3:0] data; wire clock, reset, load; wire [3:0] count; up_counter u_up_counter_1(count, clock, reset, load, data); down_counter u_down_counter_1(count, clock, reset, ~load, data); endmodule module up_counter(out, clock, reset, load, data); output [3:0] out; input [3:0] data; input clock, reset, load; wire [3:0] data; wire clock, reset, load; wire [3:0] out; reg [3:0] count; //a tri-state "out" inferred in non-top module; and except //internal bus logic and IO pin, the 'z' value is not //propagatable; warning assign out = load ? 4'bz : count; always @(posedge clock or negedge reset) if (~reset) count = 0; else if (load) count = data; else count = count + 1; endmodule module down_counter(out, clock, reset, load, data); output [3:0] out; input [3:0] data; input clock, reset, load; wire [3:0] data; wire clock, reset, load; wire [3:0] out; reg [3:0] count; //a tri-state "out" inferred in non-top module; and except //internal bus logic and IO pin, the 'z' value is not //propagatable; warning assign out = load ? 4'bz : count; always @(posedge clock or negedge reset) if (~reset)
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count else if count else count endmodule
= 0; (load) = data; = count - 1;
nLint reports: document.v(25): module. (Design document.v(48): module. (Design
Warning 22261: tri-state "out" should not be inferred in a non-top Style) Warning 22261: tri-state "out" should not be inferred in a non-top Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 library IEEE; use IEEE.std_logic_1164.all; entity EA is port ( en : in std_logic; d : in std_logic; q : out std_logic ); end entity EA; architecture arch of EA is begin p1: process (en, d) is begin if (en = '1') then q <= d; else q <='Z'; --a tri-state inferred, "EA" is not top --architecture, warning here end if; end process p1; end architecture arch; library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic ); end entity top_ety; architecture arch of top_ety is component EA is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic ); end component EA; begin u0 : component EA port map (reset=>reset, clock=>clock, d=>d , q=>q); end architecture arch;
nLint reports: document.vhd(16): Warning 22261: tri-state "q" should not be inferred in a non-top module. (Design Style)
22263 (Verilog) Null Port Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: null port is used in the module definition. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether any null ports are used in a module definition. The violation is reported when an extra comma is used in the module definition. Users can simply remove the redundant comma from the port list to fix the violation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test (clk, d, q, ); input clk, d; output q; endmodule //a null port after "q" is used
nLint reports: document.v(1): Warning 22263: null port is used in the module definition. (Design Style)
22265 (Verilog) Operand Bit Size Mismatch in Addition or Subtraction

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: bit width of left-hand-side operand "%s"(%d) does not match the right-hand-side operand "%s"(%d) in addition or subtraction operation. Configurable Parameter Rule group: Language Construct; Argument type: (VAR_EQ_CON, VAR_GE_CON); Argument description: Select VAR_EQ_CON to specify that the width of the variable expression must be equal to the width of the constant expression. Select VAR_GE_CON to specify that the width of the variable expression must be larger than or equal to the width of the constant expression; Default value: "VAR_GE_CON" for Verilog; Default severity : Level3 (Error) Description (Verilog) This rule checks whether bit width mismatches occur between operands of addition or subtraction. The checking won't be done if both operands are constants. If one operand is a variable and the other operand is a constant, the checking follows the argument setting to match bit widths of constants and variables. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module wire wire wire test; [7:0] a; [7:0] b; [1:0] c; //warning
assign a = b + c; endmodule
nLint reports following if the argument value is ("VAR_GE_CON"): document.v(6): Error 22265: bit width of left-hand-side operand "b"(8) does not match the right-hand-side operand "c"(2) in addition or subtraction operation. (Language Construct)
22267 (Verilog) Possible Loss of Carry or Borrow in Addition or Subtraction

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: possible loss of carry or borrow in addition or subtraction left operand "%s" and right operand "%s". Configurable Parameter Rule group: Language Construct; Argument type: (CHECK_INCRDECR, IGNORE_INCRDECR); Argument description: select CHECK_INCRDECR to specify checking addition or subtraction expression including incremental or decremental operation; select IGNORE_INCRDECR to specify checking addition or subtraction expression without incremental or decremental operation; Default value: "IGNORE_INCRDECR" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any possible loss of carry or borrow in addition or subtraction. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module wire wire wire test; [7:0] a; [7:0] b; [1:0] c; //warning on "b" and "c"
assign a = b + c; endmodule
nLint reports following if the argument value is ("IGNORE_INCRDECR"): document.v(6): Warning 22267: possible loss of carry or borrow in addition or subtraction left operand "b" and right operand "c". (Language Construct) ///////////////example : document_1.v//////////// 1 2 3 4 module test; wire [7:0] a; assign a = a + 1; endmodule
//warning on "a" and "1" if argument is CHECK_INCRDECR
22268 (Verilog) Possible Loss Value in Multiplication

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: possible loss value between left operand "%s" and right operand "%s" in multiplication. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any possible value loss in multiplication. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module wire wire wire test; [7:0] a; [7:0] b; [7:0] c; //warning on "b" and "c"
assign a = b * c; endmodule
nLint reports: document.v(6): Warning 22268: possible loss value between left operand "b" and right operand "c" in multiplication. (Language Construct)
22269 Combinational Path between Two Registers is Too Long

Message <filename>(<line no.>): <severity> <rule no.>: the number of combinational logic between register "%s" and register "%s" (%s(%d)) is %d (should not exceed %d). Configurable Parameter Rule group: Design Style, DFT, Simulation; Argument type: (COMB, SYNC), integer; Argument description: for the first argument, select COMB to treat the latch as combinational logic while finding the path; and select SYNC to treat the latch as sequential logic; the second argument is an integer number as threshold; if the number of logic unit in the path between two storage elements exceed the value of the second argument, the violation will be reported; Default value: "SYNC","30" for Verilog, "SYNC","30" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any combinational path is too long between two registers. For performance consideration, the warning number of this rule is limited to 10 by default. The number can be modified by command line option -max_loop. The same scheme also apply to 22014 and 22013. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test (clk, a, tri_, R); input clk, a, tri_; output R; wire clk, a; reg R, R1; wire c, d, e; always @(posedge clk) R1 = a; assign c = R1; assign d = tri_ ? c : 1'bz; always @(posedge clk) R = d; endmodule
nLint reports following if the argument value is ("SYNC","1" ): document.v(8): Warning 22269: the number of combinational logic between register "test.test:Always2#Always0:8:9:Reg" and register "test.test:Always3#Always1:14:15:Reg" (document.v(14)) is 2 (should not exceed 1). (Simulation,DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 entity top_ety is port (clk : in bit; a : in bit; R : out bit); end top_ety;
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
architecture arch of top_ety is signal c, d, e, R1 : bit; begin process(clk) begin if (clk'event and clk='1') then R1 <= a; end if; end process; c <= R1; d <= c; process(clk) begin if (clk'event and clk='1') then R <= d; end if; end process; end arch;
nLint reports following if the argument value is ("SYNC","1" ): document.vhd(10): Warning 22269: the number of combinational logic between register "top_ety.top_ety(arch):Process0#line__10:10:15:Reg" and register "top_ety.top_ety(arch):Process3#line__20:20:25:Reg" (document.vhd(20)) is 2 (should not exceed 1). (Simulation,DFT,Design Style)
22271 Report Snake Path

Message <filename>(<line no.>): <severity> <rule no.>: snake path detected between register "%s" and register "%s"(%s(%d)), and the number of comb logic between the two regs is %d(should not exceed %d). Configurable Parameter Rule group: Design Style, DFT, Simulation; Argument type: integer; Argument description: specify the maximum length of snake path; Default value: "10" for Verilog, "10" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any snake path. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module dff (clk, i, o); input clk, i; output o; reg o; always @(posedge clk) o <= i; endmodule module comb (i1, i2, o); input i1, i2; output o; assign o = i1 & i2; endmodule module top (clk, i, o); input clk, i; output o; wire a1, a2, b1, b2, c1, c2, d; dff a_dff (.clk(clk), .i(i), .o(a1)); comb a_comb (.i1(a1), .i2(a2), .o(b1)); comb b_comb (.i1(b1), .i2(b2), .o(c1)); comb c_comb (.i1(c1), .i2(c2), .o(d)); dff c_dff (.clk(clk), .i(d), .o(o)); endmodule
nLint reports following if the argument value is ("10"): document.v(5): Warning 22271: snake path detected between register "top.a_dff.dff:Always0#Always0:5:6:Reg" and register "top.c_dff.dff:Always0#Always0:5:6:Reg"(document.v(5)), and the number of comb logic between the two regs is 3(should not exceed 1). (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 library ieee; use ieee.std_logic_1164.all; entity dff is port (clk, i : in std_logic; o : out std_logic); end dff;
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
architecture arch of dff is begin Process(clk) begin if (clk'event and clk = '1') then o <= i; end if; end Process; end arch; library ieee; use ieee.std_logic_1164.all; entity comb is port (i1, i2 : in std_logic; o : out std_logic); end comb; architecture arch of comb is begin o <= i1 and i2; end arch; library ieee; use ieee.std_logic_1164.all; entity top_ety is port (clk, i : in std_logic; o : out std_logic); end top_ety; architecture arch of top_ety is component dff port (clk, i : in std_logic; o : out std_logic); end component; component comb port (i1, i2 : in std_logic; o : out std_logic); end component; signal a1, a2, b1, b2, c1, c2, d : std_logic; begin a_dff : dff port map ( a_comb : comb port map b_comb : comb port map c_comb : comb port map c_dff : dff port map ( end arch;
clk => clk, ( i1 => a1, ( i1 => b1, ( i1 => c1, clk => clk,
i => i, o i2 => a2, i2 => b2, i2 => c2, i => d, o
=> a1 ); o => b1 ); o => c1 ); o => d ); => o );
nLint reports following if the argument value is ("10"): document.vhd(11): Warning 22271: snake path detected between register "top_ety.a_dff.dff(arch):Process0#line__11:11:16:Reg" and register "top_ety.c_dff.dff(arch):Process0#line__11:11:16:Reg"(document.vhd(11)), and the number of comb logic between the two regs is 3(should not exceed 1). (Simulation)
22273 Separate Different Clock Source Triggered Register in Different Modules

Message <filename>(<line no.>): <severity> <rule no.>: registers clocked by "%s" (with clock source "%s") should be separated with registers clocked by "%s" (clock source "%s") in different module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description This rule checks whether any register with different clock sources is instanciated in the same module. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (clk, i, o1, o2); input clk, i; output o1, o2; reg o1, o2; always @( posedge clk ) o1 <= i; always @( negedge clk ) o2 <= i; endmodule
nLint reports: document.v(2): Error 22273: registers clocked by "test.clk" (with clock source "test.clk") should be separated with registers clocked by "test.clk" (clock source "test.clk") in different module. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 entity top_ety is port (clk : in bit; i : in bit; o1 : out bit; o2 : out bit); end top_ety; architecture arch of top_ety is begin process (clk,i) begin if (clk'event and clk = '1') then o1 <= i; end if; end process; process (clk,i) begin if (clk'event and clk = '0') then o2 <= i; end if; end process; end arch;
nLint reports: document.vhd(2): Error 22273: registers clocked by "top_ety.clk" (with clock source "top_ety.clk") should be separated with registers clocked by "top_ety.clk" (clock source "top_ety.clk") in different module. (Design Style)
22275 Separate Clock Generate Circuit in Different Modules

Message <filename>(<line no.>): <severity> <rule no.>: the clock generate circuit should be separated in different module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description This rule checks whether any clock generate circuit is mixed with other normal logic. For all gated clock or sequential clock violation, if the module of the gate(or module of the sequential logic) and the module of the clock are same, a violation is reported. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; wire clk, c1, c2; reg d, q; assign clk = c1 & c2; always @(posedge clk) q = d; endmodule
nLint reports: document.v(5): Error 22275: the clock generate circuit should be separated in different module. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is end top_ety; architecture arch of top_ety is signal clk, c1, c2 : bit; signal d, q : bit; begin clk <= c1 and c2; process(clk, d) begin if (clk'event and clk = '1') then q <= d; end if; end process; end arch;
nLint reports: document.vhd(11): Error 22275: the clock generate circuit should be separated in different module. (Design Style)
22277 Separate Reset Generate Circuit in Different Modules

Message <filename>(<line no.>): <severity> <rule no.>: the reset generate circuit should be separated in different module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description This rule checks whether any reset generate circuit is mixed with other normal logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (C1, reset, data, TDB, error_in); input error_in; input C1; input reset; inout [7:0] data; output [7:0] TDB; reg [7:0] TDB; wire error_reset; assign #1 error_reset = reset & error_in; always @(data or C1 or error_reset) if (error_reset) TDB = 8'h00; else if (C1) TDB = data; endmodule
nLint reports: document.v(14): Error 22277: the reset generate circuit should be separated in different module. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity top_ety is port ( data : inout std_logic_vector(7 downto 0); error_in : in std_logic; C1 : in std_logic; reset : in std_logic ); end top_ety; architecture arch signal n_din10 signal clk_en1 signal dout01 begin of top_ety is : std_logic_vector(7 downto 0); : std_logic; : std_logic;
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
dout01 <= error_in and clk_en1; process (C1, dout01, data) begin if (dout01 = '1' or dout01 = 'H') then n_din10 <= "00000000"; elsif (dout01 = '0' or dout01 = 'L') then if (C1 = '1' or C1 = 'H') then n_din10 <= data; end if; else n_din10 <= (others => 'X'); end if; end process; end arch;
nLint reports: document.vhd(24): Error 22277: the reset generate circuit should be separated in different module. (Design Style)
22279 Port is Deliberately Not Connected

Message <filename>(<line no.>): <severity> <rule no.>: port "%s" is deliberately not connected. Configurable Parameter Rule group: Simulation; Argument type: (INPUT, OUTPUT, INOUT); Argument description: select INPUT to check input port; select OUTPUT to check output port; select INOUT to check inout port Default value: "INPUT,OUTPUT,INOUT" for Verilog, "INPUT,OUTPUT,INOUT" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any port is deliberately unconnected. "Deliberately" here means the designer does know there is a port but leave it not connected deliberately. This is used to check hierarchy module instance. See also 22082, 22281, and 22283. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test; wire ta, tb; uu u_uu_1( .a(ta), .b() ); //warning here for r22279 uu u_uu_2( .a(ta) ); //warning here for r22082 uu u_uu_3( ta, ); //warning here for r22082 endmodule module uu (a, b); input a; output b; wire a, b; assign b = a; endmodule
nLint reports following if the argument value is ("INPUT,OUTPUT,INOUT"): document.v(3): Warning 22279: port "b" is deliberately not connected. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 entity EA is port ( r1: in bit; r2: out bit ); end EA; architecture arch of EA is begin end arch; entity top_ety is port ( s1: in bit; s2: out bit ); end top_ety; architecture arch of top_ety is component EA is port ( r1: in bit; r2: out bit );
22 23 24 25 26
end component; begin u0: component EA port map (r1=>s1); --warning 22082 on 'r2' u1: component EA port map (r1=>s1, r2=>open); --warning 22279 on 'r2' end arch;
nLint reports following if the argument value is ("INPUT,OUTPUT,INOUT"): document.vhd(25): Warning 22279: port "r2" is deliberately not connected. (Simulation)
22281 (Verilog) Gate Port is Not Connected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: gate port "%s" is not connected. Configurable Parameter Rule group: Simulation; Argument type: (INPUT, OUTPUT, INOUT); Argument description: select INPUT to check input port; select OUTPUT to check output port; select INOUT to check inout port Default value: "INPUT,OUTPUT,INOUT" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any gate port is not connected. The gate here includes primitive, library cell and symbol instance. See also 22082, 22279, and 22283. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test; wire ta, tb; uu u_uu_2( .a(ta) ); uu u_uu_3( ta, ); endmodule `celldefine primitive uu( a, b ); output a; input b; table ? : 1; endtable endprimitive èndcelldefine
// warning here // warning here
nLint reports following if the argument value is ("INPUT,OUTPUT,INOUT"): document.v(3): Warning 22281: gate port "b" is not connected. (Simulation) document.v(4): Warning 22281: gate port "b" is not connected. (Simulation)
22283 (Verilog) Gate Port is Deliberately Not Connected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: gate port "%s" is deliberately not connected. Configurable Parameter Rule group: Simulation; Argument type: (INPUT, OUTPUT, INOUT); Argument description: select INPUT to check input port; select OUTPUT to check output port; select INOUT to check inout port Default value: "INPUT,OUTPUT,INOUT" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any gate port is deliberately unconnected. The gate here includes primitive, library cell and symbol instance. "Deliberately" here means the designer does know there is a port but leave it not connected deliberately. See also 22082, 22281, and 22283. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test(); wire ta, tb; uu u_uu_1( .a(ta), .b() ); // warning here endmodule `celldefine primitive uu( a, b ); output a; input b; table ? : 1; endtable endprimitive èndcelldefine
nLint reports following if the argument value is ("INPUT,OUTPUT,INOUT"): document.v(3): Warning 22283: gate port "b" is deliberately not connected. (Simulation)
22301 (Verilog) Zero Implicitly Filled to Higher Bits of LHS Variable in Assignment
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: zero is implicitly assigned to higher %d bits of left-hand-side variable "%s"(%d), and the remaining bits are exactly assigned with the right-hand-side expression "%s"(%d) in the assignment. Configurable Parameter Rule group: Language Construct; Argument type: (IGNORE_CONST_RHS, CHECK_CONST_RHS) (ORIG_MUL_WIDTH, EXPAND_MUL_WIDTH); Argument description: The first argument determines whether to check constant RHS. Select CHECK_CONST_RHS to specify that the rule 22301 should be checked if RHS is a constant expression, and the bit width of integer constant is optimized; select IGNORE_CONST_RHS to specify that the rule 22301 doesn't need to be checked if RHS is a constant expression. The second argument determines how to calculate the bit width of the multiplication result. Select ORIG_MUL_WIDTH to specify that the bit width of multiplication follows LRM; select EXPAND_MUL_WIDTH to specify that the bit width of multiplication is the sum of two operators' bit width, and the carry bits from addition/subtraction are also counted in. Besides, the integer constant's bit width is optimized; Default value: "IGNORE_CONST_RHS","ORIG_MUL_WIDTH" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether zero is implicitly assigned to the left-hand-side (LHS) variable in an assignment. If the bit width of the LHS variable is larger than the right-hand-side (RHS) expression, including carry bits or borrow bits, the extra bits of the LHS variable are implicitly assigned with '0', which is an unexpected behavior. This rule doesn't need to be checked if the RHS expression is a signed expression since tools will automatically extend the signed bits to match the target width. Example
(Verilog) ///////////////example : document.v2k//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test1(a, b, c, d, e, out1, out2, out3, out4, out5, out6, out7); input [1:0] a, b; input signed [1:0] c, d; input [1:0] e; output [7:0] out1, out2, out3, out4, out5, out6, out7; assign assign assign assign out1 out2 out3 out4 = = = = a * b; {2'b0,a} * {2'b0,b}; {2'b01,a} * {2'b10,b}; a; //warning, //warning, //warning, //warning, 8 8 8 8 bits bits bits bits V.S. V.S. V.S. V.S. 4 4 7 2 bits bits bits bits
assign out5 = c; assign out6 = c + d; assign out7 = c + e; endmodule
//no warning on signed expression //no warning on signed expression //warning, 8 bits V.S. 3 bits
nLint reports following if the argument value is ("IGNORE_CONST_RHS","ORIG_MUL_WIDTH"): document.v2k(8): Warning 22301: zero is implicitly assigned to higher 4 bits of left-hand-side variable "out1"(8), and the remaining bits are exactly assigned with the right-hand-side expression "(a * b)"(4) in the assignment. (Language Construct)
document.v2k(9): Warning 22301: zero is implicitly assigned to higher 4 bits of left-hand-side variable "out2"(8), and the remaining bits are exactly assigned with the right-hand-side expression "(2'b0, a * 2'b0, b)"(4) in the assignment. (Language Construct) document.v2k(10): Warning 22301: zero is implicitly assigned to higher 1 bits of left-hand-side variable "out3"(8), and the remaining bits are exactly assigned with the right-hand-side expression "(2'b01, a * 2'b10, b)"(7) in the assignment. (Language Construct) document.v2k(11): Warning 22301: zero is implicitly assigned to higher 6 bits of left-hand-side variable "out4"(8), and the remaining bits are exactly assigned with the right-hand-side expression "a"(2) in the assignment. (Language Construct) document.v2k(15): Warning 22301: zero is implicitly assigned to higher 5 bits of left-hand-side variable "out7"(8), and the remaining bits are exactly assigned with the right-hand-side expression "(c + e)"(3) in the assignment. (Language Construct) ///////////////example : document2.v2k//////////// 1 2 3 4 5 6 module test(a, b); output [3:0] a; output [33:0] b; assign a = 3'b110; endmodule //no warning if select argument "IGNORE_CONST_RHS"
nLint reports following if the argument value is ( IGNORE_CONST_RHS ): ///////////////example : document3.v2k//////////// 1 2 3 4 5 6 7 module test(a, b); output [3:0] a; output [33:0] b; assign a = 3'b110; assign b = 2; endmodule //warning if select argument "CHECK_CONST_RHS" //no warning on signed expression
nLint reports following if the argument value is ( CHECK_CONST_RHS ): document3.v2k(5): Warning 22301: zero is implicitly assigned to higher 1 bits of left-hand-side variable "a"(4), and the remaining bits are exactly assigned with the right-hand-side expression "3'b110"(3) in the assignment. (Language Construct) ///////////////example : document4.v2k//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module mult(a, b, prod1, prod2, prod3, prod4); input input output assign assign assign assign endmodule [9:0] [7:0] [17:0] a; b; prod1, prod2, prod3, prod4;
prod1 = {2'b0, a[9:2]} * b; prod2 = {1'd1, a[7:0]} * b; prod3[7:0] = {4'b0, a[9:8]} * a[1:0]; prod4[4:0] = (a[0]+1) * {1'b0, b[1]};
nLint reports following if the argument value is ( "CHECK_CONST_RHS", "EXPAND_MUL_WIDTH"): document4.v2k(8): Warning 22301: zero is implicitly assigned to higher 1 bits of left-hand-side variable "prod2"(18), and the remaining bits are exactly assigned with the right-hand-side expression "(1'd1, a[7:0] * b)"(17) in the assignment. (Language Construct) document4.v2k(10): Warning 22301: zero is implicitly assigned to higher 1 bits of left-hand-side variable "prod4[4:0]"(5), and the remaining bits are exactly assigned with the right-hand-side expression "((a[0] + 1) * 1'b0, b[1])"(4) in the assignment. (Language Construct)
22303 (Verilog) Unpacked Signal Bit Width Mismatch in Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: bit width of left-hand side variable "%s"(%d) does not match that of right-hand side variable "%s"(%d) in the assignment. Configurable Parameter Rule group: Language Construct; Argument type: (LHS_EQ_RHS, LHS_GE_RHS) (VAR_EQ_CON, VAR_GE_CON); Argument description: The first argument allows users to specify the bit width constraint of assignments. LHS_EQ_RHS indicates that bit width of variables on left-hand and right-hand side of assignment must be equal, and LHS_GE_RHS indicates that the bit width of LHS variable can be greater than or equal to the bit width of RHS variable; The second argument is valid when the first argument is LHS_EQ_RHS and RHS variable is a constant expression. Select VAR_EQ_CON to specify that the bit width of LHS equal to the bit width of RHS(constant expression); select VAR_GE_CON to specify that the bit width of LHS greater than or equal to the bit width of RHS(constant expression); Default value: "LHS_GE_RHS","VAR_EQ_CON" for Verilog; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any bit width mismatch in the assignment statements. Note that the left-hand side variable must be unpacked, where an unpacked variable can be any of the following three types: unpacked array, structure without "packed" modifier in its definition, and union without "packed" modifier in its definition. The rule ignores the checking for integer loop variables in for-loops, real, realtime, time, access, sub-type of integers. Example
(Verilog) ///////////////example : document.sv//////////// 1 module top; 2 3 logic foo [1:0] = { '0, 0 }; 4 5 logic var1 [3:0] = { 0, 1, 1, {2} }; // warning on var1[0] if the default argument value ("LHS_GE_RHS","VAR_EQ_CON") is used and "-actualwidth" is set 6 7 struct { int a [2:0]; } var2_S; 8 assign var2_S = { {0, 7, 1} }; 9 10 struct { logic a; int b; } var3_S; 11 assign var3_S = { {2}, 1 }; // warning on var3_S.a if the default argument value ("LHS_GE_RHS","VAR_EQ_CON") is used and "-actualwidth" is set 12 13 endmodule
nLint reports following if the argument value is ("LHS_GE_RHS","VAR_EQ_CON"): document.sv(5): Error 22303: bit width of left-hand side variable "var1[0]"(1) does not match that of right-hand side variable "2"(2) in the assignment. (Language Construct) document.sv(11): Error 22303: bit width of left-hand side variable "var3_S.a"(1) does not match that of right-hand side variable "2"(2) in the assignment. (Language Construct) ///////////////example : document1.sv//////////// 1 2 3 /* rule 22303 */ module test;
4 5 bit [31:0] h; 6 bit [15:0] i; 7 bit [31:0] j; 8 9 int a1 [2:0] = {h, i, j}; // warning on a1[1] if the argument value is ("LHS_EQ_RHS","VAR_EQ_CON") 10 logic [1:0] a2 [2:0] = {1'b1, 2'b0, 3'b1}; // warning on a2[2] and a2[0] if the argument value is ("LHS_EQ_RHS","VAR_EQ_CON") 11 12 endmodule
nLint reports following if the argument value is ( "LHS_EQ_RHS", "VAR_EQ_CON"): document1.sv(9): Error 22303: bit width of left-hand side variable "a1[1]"(32) does not match that of right-hand side variable "i"(16) in the assignment. (Language Construct) document1.sv(10): Error 22303: bit width of left-hand side variable "a2[2]"(2) does not match that of right-hand side variable "1'b1"(1) in the assignment. (Language Construct) document1.sv(10): Error 22303: bit width of left-hand side variable "a2[0]"(2) does not match that of right-hand side variable "3'b1"(3) in the assignment. (Language Construct) ///////////////example : document2.sv//////////// 1 /* rule 22303 */ 2 3 module test; 4 5 bit [31:0] h; 6 bit [15:0] i; 7 bit [31:0] j; 8 9 int a1 [2:0] = {h, i, j}; // warning on a1[1] if the argument value is ("LHS_EQ_RHS","VAR_GE_CON") 10 logic [1:0] a2 [2:0] = {1'b1, 2'b0, 3'b1}; // warning on a2[0] if the argument value is ("LHS_EQ_RHS","VAR_GE_CON") 11 12 endmodule
nLint reports following if the argument value is ( "LHS_EQ_RHS", "VAR_GE_CON"): document2.sv(9): Error 22303: bit width of left-hand side variable "a1[1]"(32) does not match that of right-hand side variable "i"(16) in the assignment. (Language Construct) document2.sv(10): Error 22303: bit width of left-hand side variable "a2[0]"(2) does not match that of right-hand side variable "3'b1"(3) in the assignment. (Language Construct)
22306 (Verilog) Ambiguous Extension of X/Z

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: literal constant "%s" should not be assigned to variable "%s"(%d), because it may result in ambiguous extension of significant bits over 32. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether literal constant "'bX" or "'bZ" is assigned to a variable whose bit width is over 32. The bit extension for "'bX" or "'bZ" over 32 bits is ambiguous since the behavior is different in Verilog-1995 and Verilog-2001; in Verilog-1995, '0' is extended over 32 bits, and in Verilog-2001, 'X' is extended for "'bX" and 'Z' is extended for "'bZ" over 32 bits. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 module test(d1, d2, d3); output [63:0] d1, d2, d3; //warning, higher bits over 32 are filled with '0' //and with 'z' in Verilog2k //warning, higher bits over 32 are filled with '0' //and with 'x' in Verilog2k //OK, higher bits over 32 are filled with '0'
assign d1 = 'bz; in Verilog95 5 6 7 assign d2 = 'bx; in Verilog95 8 9 10 assign d3 = 32'bz; 11 endmodule
nLint reports: document.v(4): Warning 22306: variable "d1"(64), because it bits over 32. (Coding Style) document.v(7): Warning 22306: variable "d2"(64), because it bits over 32. (Coding Style)
literal constant "'bz" should not be assigned to may result in ambiguous extension of significant literal constant "'bx" should not be assigned to may result in ambiguous extension of significant
23001 Bit Select in Sensitivity List

Message <filename>(<line no.>): <severity> <rule no.>: bit range of sensitive signal "%s" should not be used in sensitivity list. Configurable Parameter Rule group: Synthesis, Design Style; Argument type: (CHECK_IN_COMB, IGNORE_IN_COMB); Argument description: select CHECK_IN_COMB to check in combinational block; select IGNORE_IN_COMB to ignore checking in combinational block; and COMB_ENUM_ARG is only used for Verilog; Default value: "IGNORE_IN_COMB" for Verilog, "IGNORE_IN_COMB" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any bit select (e.g. a[3]) or part select (e.g., a[3:0]) of sensitive signal in sensitivity list. (VHDL) This rule checks whether there is any bit select (e.g. a(3)) or part select (e.g., a(3 downto 0)) of sensitive signal in sensitivity list. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (d, clock, reset, q); input d; input [1:0] clock, reset; output q; reg q; always @( posedge clock[0] or negedge reset[1] ) //warning here if ( ~reset[1] ) q <= 1'b0; else q <= d; endmodule
nLint reports following if the argument value is ("IGNORE_IN_COMB"): document.v(7): Warning 23001: bit range of sensitive signal "reset[1]" should not be used in sensitivity list. (Synthesis,Design Style) document.v(7): Warning 23001: bit range of sensitive signal "clock[0]" should not be used in sensitivity list. (Synthesis,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port ( Clock : in bit_vector(1 downto 0); Reset : in bit_vector(1 downto 0); D : in bit; Q : out bit ); end top_ety; architecture arch of top_ety is begin process( Clock(1), Reset(1) ) --warning here begin if ( Reset(1) = '1' ) then Q <= '0'; elsif ( Clock(1)'event and Clock(1) = '1' ) then
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Q <= D; end if; end process; end arch;
nLint reports following if the argument value is ("IGNORE_IN_COMB"): document.vhd(10): Warning 23001: bit range of sensitive signal "Reset(1)" should not be used in sensitivity list. (Synthesis,Design Style) document.vhd(10): Warning 23001: bit range of sensitive signal "Clock(1)" should not be used in sensitivity list. (Synthesis,Design Style)
23002 (Verilog) Inferred Storage Not in Library 23002 (VHDL) Inferred Storage
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s inferred on signal "%s" not in library. (VHDL) <filename>(<line no.>): <severity> <rule no.>: %s inferred on signal "%s". Configurable Parameter Rule group: Synthesis; Argument type: (REGISTER, LATCH, MEMORY, COUNTER); Argument description: This is a multiple selection argument. Select REGISTERto check register inferred; select LATCH to check latch inferred; select MEMORY to specify to check memory inferred; select COUNTER to check counter inferred Default value: "REGISTER,LATCH,MEMORY,COUNTER" for Verilog, "REGISTER,LATCH,MEMORY,COUNTER" for VHDL; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks and reports violations on all inferred storages not in library. Any code in -y/-v files or embraced by `celldefine, èndcelldefine will be treated as legal to this rule. (VHDL) This rule checks and reports violations on all inferred storages. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; // register inferred not in library endmodule
nLint reports following if the argument value is ("REGISTER,LATCH,MEMORY,COUNTER"): document.v(7): Warning 23002: register inferred on signal "q" not in library. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is
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begin if (reset='1') then q<='0'; elsif (clock'event and clock='1') then q<=d; -- a asynchronous register inferred end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("REGISTER,LATCH,MEMORY,COUNTER"): document.vhd(17): Warning 23002: register inferred on signal "q". (Synthesis)
23003 Inferred Latch

Message <filename>(<line no.>): <severity> <rule no.>: latch is inferred on signal "%s". Configurable Parameter Rule group: Synthesis; Argument type: (TRUE, FALSE); Argument description: If the argument is TRUE, nLint will check latches declared in always_latch blocks, otherwise nLint will ignore this kind of latches.The default argument is FALSE; Default value: "FALSE" for Verilog, "FALSE" for VHDL; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description This rule checks whether there are any latches inferred in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (c, a, b); input [1:0] a, b; output [1:0] c; reg [1:0] c; always @(a or b) if (a) c = b; //latch "c" inferred endmodule
nLint reports following if the argument value is ("FALSE"): document.v(7): Warning 23003: latch is inferred on signal "c". (Synthesis) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 //the argument is specified FALSE module test(input d,clk, output reg q1, q2); always_latch begin if(clk) //this latch not be flagged q1 <= d; end always begin if(clk) q2 <= d; //this latch flagged end endmodule
nLint reports following if the argument value is ("FALSE"): document.sv(8): Warning 23003: latch is inferred on signal "q2". (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( reset : in std_logic; clock : in std_logic; d : in std_logic; q : out std_logic );
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end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset='1') then q<='0'; elsif (clock='1') then q<=d; -- a latch inferred, warning on "q" end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("FALSE"): document.vhd(18): Warning 23003: latch is inferred on signal "q". (Synthesis)
23004 Inferred Mux

Message <filename>(<line no.>): <severity> <rule no.>: mux inferred on signal "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description This rule checks and reports on all inferred mux logics. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (q, c, a, b); input [1:0] a, b, c; output [1:0] q; reg [1:0] q; always @(a or b or c) if (a) q = b; else q = c; //a mux "c" inferred endmodule
nLint reports: document.v(8): Warning 23004: mux inferred on signal "q". (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 entity top_ety is port ( en : in bit; d1 : in bit; d2 : in bit; q : out bit); end top_ety; architecture arch of top_ety is begin p1: process (en, d1, d2) is begin if (en = '1') then q <= d1; else q<=d2; --a mux "q" inferred, warning here end if; end process p1; end architecture arch;
nLint reports: document.vhd(13): Warning 23004: mux inferred on signal "q". (Synthesis)
23005 Inferred Tri-state

Message <filename>(<line no.>): <severity> <rule no.>: tri-state logic is inferred on signal "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description This rule checks whether tri-state logic is inferred from the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (c, a, b); input [1:0] a, b; output [1:0] c; reg [1:0] c; always @(a or b) if (a) c = b; else c = 1'bz; //tri-state "c" inferred endmodule
nLint reports: document.v(8): Warning 23005: tri-state logic is inferred on signal "c". (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port ( en : in std_logic; d : in std_logic; q : out std_logic ); end entity top_ety; architecture arch of top_ety is begin p1: process (en, d) is begin if (en = '1') then q <= d; else q<='Z'; --a tri-state "q" inferred, warning here end if; end process p1; end architecture arch;
nLint reports: document.vhd(16): Warning 23005: tri-state logic is inferred on signal "q". (Synthesis)
23006 (Verilog) Incomplete Case Expression with Default Clause

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: not all possible values of the case expression are covered but a default clause exists. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level1 (Information) This rule is turned OFF by default; Description (Verilog) When case labels do not cover all possible values of case expression, default clause could be exercised. The default clause could be used to catch x or z. If the rule is violated, the missing case labels could be caught by the default clause as well. Example
(Verilog) ///////////////example : document.v//////////// 1 module test; 2 wire [1:0] a; 3 reg b; 4 5 always @(a) 6 casez (a[1:0]) //warning here, 2'b11 is not covered but default exists. 7 2'b00: b = 1'b1; 8 2'b01: b = 1'b0; 9 2'b10: b = 1'bx; 10 default: b = 1'bz; 11 endcase 12 endmodule
nLint reports: document.v(6): Information 23006: not all possible values of the case expression are covered but a default clause exists. (Language Construct)
23007 (Verilog) Case Statement Not Fully Specified

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: not all possible values of the case expression are covered by the case items. Configurable Parameter Rule group: Language Construct; Argument type: ( CHECK_IN_SEQ, IGNORE_IN_SEQ) (FOLLOW_FULL_CASE_DIRECTIVE, IGNORE_FULL_CASE_DIRECTIVE); Argument description: The first argument specifies whether to check rule 23007 in sequential blocks. Select CHECK_IN_SEQ to enable checking in sequential blocks; select IGNORE_IN_SEQ to disable checking in sequential blocks. The second argument specifies whether to check cases with Synopsys full_case directive. Select FOLLOW_FULL_CASE_DIRECTIVE to treat a case with Synopsys full_case directive as a full case and skip checking; select IGNORE_FULL_CASE_DIRECTIVE to ignore the Synopsys full_case directive and to check whether the case is complete or not; Default value: "IGNORE_IN_SEQ","FOLLOW_FULL_CASE_DIRECTIVE" for Verilog; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether all possible values of the case expression are covered by the case items. This rule is not violated if the default clause exists. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (out0, in1, in2, in3, sel); input [1:0] in1, in2, in3, sel; output [1:0] out0; reg [1:0] out0; always @(in1 or in2 or sel) case (sel) //warning 2'b00: out0 = in1; 2'b01: out0 = in2; 2'b10: out0 = in3; endcase endmodule
nLint reports following if the argument value is ("IGNORE_IN_SEQ","FOLLOW_FULL_CASE_DIRECTIVE"): document.v(7): Warning 23007: not all possible values of the case expression are covered by the case items. (Language Construct) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (in,out,clk); input [1:0] in; input clk; output out; reg out; always @(posedge clk) begin case(in) //synopsys full_case 2'b00: out=0; 2'b01: out=1; 2'b10: out=0; endcase end endmodule
nLint reports following if the argument value is ( CHECK_IN_SEQ,
IGNORE_FULL_CASE_DIRECTIVE): document2.v(8): Warning 23007: not all possible values of the case expression are covered by the case items. (Language Construct)
23008 (Verilog) Default is Not Found

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: all cases are covered but no default label found. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: (CHECK_IN_SEQ, IGNORE_IN_SEQ); Argument description: select CHECK_IN_SEQ to check in sequential block; select IGNORE_IN_SEQ to ignore checking in sequential block Default value: "IGNORE_IN_SEQ" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any default clause in a full case statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module test (sel,a,c); input [1:0] a ; input [1:0] sel; output [1:0] c; reg [1:0] c; `define ZERO 0 `define ONE 1 `define TWO 2 `define THREE 3 always @ (a or sel) case (sel) //warning here, default item is lost //If sel signal is X or Z , it may cause problem `ZERO: c = 2'b00; ÒNE : c = 2'b01; `TWO : c = a; `THREE: c= 2'b11; endcase endmodule
nLint reports following if the argument value is ("IGNORE_IN_SEQ"): document.v(12): Warning 23008: all cases are covered but no default label found. (Simulation,Synthesis)
23009 (Verilog) Unreachable Default Branch of Case Statement

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: default branch is unreachable because case alternatives have covered all the possibilities of case expression. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks if all the possibilities of the case expression are covered by case alternatives. The default statement of case is unreachable in two-state ("0" and "1") RTL and its gate-level equivalent. Mismatches could be caused when case expression happens to be unknown in four-state ("0", "1", "x" and "z") simulation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test(foo, bar, bar_0, bar_1, bar_2, bar_3); input [5:0] foo; input [35:0] bar_0, bar_1, bar_2, bar_3; output [35:0] bar; reg [35:0] bar; always @( foo or bar_0 or bar_1 or bar_2 or bar_3 ) begin case (foo[1:0]) 2'd0 : bar = bar_0; 2'd1 : bar = bar_1; 2'd2 : bar = bar_2; 2'd3 : bar = bar_3; default : bar = 36'd0; //warning here endcase end endmodule
nLint reports: document.v(13): Warning 23009: default branch is unreachable because case alternatives have covered all the possibilities of case expression. (Coding Style)
23010 (Verilog) Incomplete Case Expression with Default Clause and Synopsys 'full_case' Directive
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: not all possible values of the case expression are covered in a full case but a default clause exists. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level1 (Information) This rule is turned OFF by default; Description (Verilog) This rule checks whether all possible values of a case expression are covered in a case where a default clause and "synopsys full_case" directive exists. The default clause should be used to catch x or z. If the rule is violated, the missing case labels would be caught by the default clause as well. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test; wire [1:0] a; reg b; always @(a) casez (a[1:0]) // synopsys full_case 2'b00: b = 1'b1; 2'b01: b = 1'b0; 2'b10: b = 1'bx; default: b = 1'bz; //2'b11 is not covered but default exists. endcase endmodule
nLint reports: document.v(7): Information 23010: not all possible values of the case expression are covered in a full case but a default clause exists. (Language Construct)
23011 Incomplete Sensitivity List

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" should be included in the sensitivity list. Configurable Parameter Rule group: Synthesis, Simulation; Argument type: none; Default severity : Level3 (Error) Description This rule checks whether all right-hand-side variables of a combinational always block are included in the sensitivity list. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; reg a,b,c; always @(a) //warning c = a + b; endmodule
nLint reports: document.v(5): Error 23011: signal "b" should be included in the sensitivity list. (Simulation,Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 ex1: process(A) --warning here, "B" should be put in sensitivity list C = A and B; ex2: package mmm is type my_record is record a : bit; b: integer; end record; end mmm; use work.mmm.all; entity rec is port ( s : in my_record; s1 : out my_record ); end rec; architecture arch of rec is begin p1 : process (s.a) is --warning here, "s.b" should be put in --sensitivity list begin s1 <= s; end process p1; end arch;-------------------example : document1.vhd------------entity top_ety is end top_ety; architecture arch of top_ety is signal A, B, C : bit; begin process (A) --warning here, "B" should be put in sensitivity list
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begin C <= A and B; end process; end arch;
nLint reports: document1.vhd(9): Error 23011: signal "B" should be included in the sensitivity list. (Simulation,Synthesis) -------------------example : document2.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 package mmm is type my_record is record a : bit; b: integer; end record; end mmm; use work.mmm.all; entity top_ety is port ( s : in my_record; s1 : out my_record ); end top_ety; architecture arch of top_ety is begin p1 : process (s.a) is --warning here, "s.b" should be put in --sensitivity list begin s1 <= s; end process p1; end arch;
nLint reports: document2.vhd(20): Error 23011: signal "s.b" should be included in the sensitivity list. (Simulation,Synthesis)
23013 Extra Signal in Sensitivity List

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" should not be included in the sensitivity list. Configurable Parameter Rule group: Simulation; Argument type: (SYNC, COMB, BOTH), (CHECK_PART_SEL, IGNORE_PART_SEL); Argument description: for first argument, select COMB to check combinational logic; select SYNC to check sequence logic, for example, a redundant level sensitive signal in edge-sensitive block; for the second argument, if partial bits of the signal is not used in the block, select CHECK_PART_SEL to report the violation; select IGNORE_PART_SEL to ignore the violation; Default value: "BOTH","IGNORE_PART_SEL" for Verilog, "BOTH","IGNORE_PART_SEL" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any extra signal in the sensitivity list. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (in1,in2,in3,out); input in1,in2,in3; output out; reg out; always @(in1 or in2 or in3) //"in3" is not referenced in block, //not a sensitive signal, warning out <= in1 & in2; endmodule
nLint reports following if the argument value is ("BOTH","IGNORE_PART_SEL"): document.v(6): Warning 23013: signal "in3" should not be included in the sensitivity list. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ex1: process(A,B,C) --warning here, "C" is not a sensitive signal D <= A and B; ex2: package mmm is type my_record is record a : bit; b: integer; end record; end mmm; use work.mmm.all; entity rec is port ( s : in my_record; s1 : out my_record ); end rec; architecture arch of rec is begin p1 : process (s) is --warning here, "s.b" is not a --sensitive signal
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begin s1.a <= s.a; end process p1; end arch;-------------------example : document1.vhd------------entity top_ety is port ( A : in bit; B : in bit; C : in bit; D : out bit ); end top_ety; architecture arch of top_ety is begin process(A,B,C) --warning here, "C" is not a sensitive signal begin D <= A and B; end process; end arch;
nLint reports following if the argument value is ("BOTH","IGNORE_PART_SEL"): document1.vhd(11): Warning 23013: signal "C" should not be included in the sensitivity list. (Simulation) -------------------example : document2.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 package mmm is type my_record is record a : bit; b: integer; end record; end mmm; use work.mmm.all; entity top_ety is port ( s : in my_record; s1 : out my_record ); end top_ety; architecture arch of top_ety is begin p1 : process (s) is -- "s.b" is not used here --warning here if set argument "CHECK_PART_SEL" --no warning if set argument "IGNORE_PART_SEL" begin s1.a <= s.a; end process p1; end arch;
nLint reports following if the argument value is ("BOTH","CHECK_PART_SEL"): document2.vhd(17): Warning 23013: signal "s.b" should not be included in the sensitivity list. (Simulation)
23015 (Verilog) Blocking/Non-blocking Assignment in Edge-triggered Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s assignment is used in an edge triggered block. Configurable Parameter Rule group: Synthesis; Argument type: (BLOCKING, NONBLOCKING) (TEMP_ASSIGN, REG_INFER_ASSIGN); Argument description: The first argument allows users to specify reporting on either blocking (BLOCKING) or non-blocking (NONBLOCKING) assignments in the edge-triggered blocks. The second argument takes effect only when the first argument is BLOCKING. Enable TEMP_ASSIGN to report blocking assignments used for temporary variables. Enable REG_INFER_ASSIGN to report blocking assignments which induce storage elements; Default value: "BLOCKING","REG_INFER_ASSIGN" for Verilog; Default severity : Level3 (Error) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether there are any blocking or non-blocking assignments used in an edge-triggered block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test; reg clock; reg a,b,c,d,f; //if BLOCKING is not allowed in edge-trigger block always @(posedge clock) begin a = b; //"a" is like a temporary variable because of the next statement //report warning if "TEMP_ASSIGN" is selected c = a; //"c" and "d" are not temporary variables. Report warning d = f; //if "REG_INFER_ASSIGN" is selected. end endmodule
nLint reports following if the argument value is ("BLOCKING","TEMP_ASSIGN,REG_INFER_ASSIGN"): document.v(7): Error 23015: BLOCKING assignment is used in an edge triggered block. (Synthesis) document.v(10): Error 23015: BLOCKING assignment is used in an edge triggered block. (Synthesis) document.v(11): Error 23015: BLOCKING assignment is used in an edge triggered block. (Synthesis) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test; reg clock; reg a,b,c; always @(posedge clock) begin a = b; c = a; //choose BLOCKING, IGNORE_DEPEND; //block assignment in edge-trigger block will cause //mismatch between pre-synthesis and //post-synthesis simulation end
13
endmodule
nLint reports following if the argument value is ("BLOCKING", "IGNORE_DEPEND"): document1.v(7): Error 23015: BLOCKING assignment is used in an edge triggered block. (Synthesis) document1.v(8): Error 23015: BLOCKING assignment is used in an edge triggered block. (Synthesis) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test; reg clock; reg a,b,c; always @(posedge clock) begin a = b; //warning here c = a; //choose BLOCKING, CHECK_DEPEND; //no warning here end endmodule
nLint reports following if the argument value is ("BLOCKING", "CHECK_DEPEND"): document2.v(7): Error 23015: BLOCKING assignment is used in an edge triggered block. (Synthesis)
23016 (Verilog) Blocking/Non-blocking Assignment in Combinational Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s assignment is used in a combinational block. Configurable Parameter Rule group: Synthesis; Argument type: (BLOCKING, NONBLOCKING) (TRUE, FALSE); Argument description: The first argument allows users to specify reporting on either blocking (BLOCKING) or non-blocking (NONBLOCKING) assignments in the combinational blocks. The second argument takes effect only when the first argument is NONBLOCKING. Select FALSE to report all non-blocking assignments regardless of whether they are temporary variables or not. Select TRUE to report only the non-blocking assignments which are used for temporary variable assignments; Default value: "NONBLOCKING","FALSE" for Verilog; Default severity : Level3 (Error) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether there are any blocking or non-blocking assignments used in combinational blocks. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test(b, c, d, f); input b, f; output c, d; reg a, c, d; //if NONBLOCKING is not allowed always @(b or f) begin a <= b; //"a" is like a temporary variable because the next statement. //report warning here c <= a; //"c" and "d" are not like temporary variables. Report warning d <= f; //if the second argument is FALSE. end endmodule
nLint reports following if the argument value is ("NONBLOCKING","FALSE"): document.v(7): Error 23016: NONBLOCKING assignment is used in a combinational block. (Synthesis) document.v(10): Error 23016: NONBLOCKING assignment is used in a combinational block. (Synthesis) document.v(11): Error 23016: NONBLOCKING assignment is used in a combinational block. (Synthesis) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test; reg in; reg a,o; always @(in) begin a <= in; o <= a; //choose NONBLOCKING, IGNORE_DEPEND; //non-block assignment in combinational block will //cause mismatch between pre-synthesis and //post-synthesis simulation end
12
endmodule
nLint reports following if the argument value is ("NONBLOCKING", "IGNORE_DEPEND"): document1.v(6): Error 23016: NONBLOCKING assignment is used in a combinational block. (Synthesis) document1.v(7): Error 23016: NONBLOCKING assignment is used in a combinational block. (Synthesis) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 module test; reg in; reg a,o; always @(in) begin a <= in; //warning o <= a; //choose NONBLOCKING, CHECK_DEPEND; //no warning end endmodule
nLint reports following if the argument value is ("NONBLOCKING", "CHECK_DEPEND"): document2.v(6): Error 23016: NONBLOCKING assignment is used in a combinational block. (Synthesis)
23017 Case-like If Statement

Message <filename>(<line no.>): <severity> <rule no.>: conditions in this if statement are not orderdependent; use case statement instead. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description This rule checks whether cascaded if-else statement should be re-written using a case statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test (out, sel, in); parameter SEL_WIDTH = 2, D_WIDTH = 4; output out; input [SEL_WIDTH-1:0] sel; input [D_WIDTH-1:0] in; reg out; always @(sel or in) if (sel == 0) //this "if" statement should be replaced with //case statement, which is parallel process; //warning out = in[0]; else if (sel == 1) out = in[1]; else if (sel == 2) out = in[2]; else out = in[3]; endmodule
nLint reports: document.v(9): Warning 23017: conditions in this if statement are not orderdependent; use case statement instead. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is port ( Sel : in bit_vector(1 downto 0); Din : in bit_vector(3 downto 0); Qout : out bit ); end top_ety; architecture arch of top_ety is begin process (Sel) begin if ( Sel = "00" ) then Qout <= Din(0); elsif ( Sel = "01" ) then Qout <= Din(1); elsif ( Sel = "10" ) then
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Qout <= Din(2); else Qout <= Din(3); end if; end process; end arch;
nLint reports: document.vhd(12): Warning 23017: conditions in this if statement are not orderdependent; use case statement instead. (Synthesis)
23021 (Verilog) Gate Instance Found

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s gate "%s" found %s. Configurable Parameter Rule group: Synthesis; Argument type: (NON_LEAF, DESIGN); Argument description: For the first argument,select NON_LEAF to check if gate instance only in the scope of non_leaf module, select DESIGN to check if gate instance in whole design; for the second argument, select LIB_CELL to check lib_cell gate inst, select SYMBOL_LIB to check symbol library gate inst, select UDP to check udp gate inst; always check primitive gate inst; Default value: "NON_LEAF","" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there's any instantiated gate. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 module top; reg a, b; wire c, d, e; initial begin a = 0; b = 1; #100 $finish; end always #5 a = ~a; and U_and(c, a, b); //gate "and" in non-leaf module will cause //systhesizer optimization problem, warning test U_test(a, b, d, e); endmodule module test (a,b,c,d); input a,b; output c,d; reg c; wire d; always @(a or b) c = ~b; and #(3,5) and1(d,a,b); endmodule
nLint reports following if the argument value is ("NON_LEAF",""): document.v(15): Warning 23021: primitive gate "U_and" found in non_leaf module. (Synthesis) document.v(30): Warning 23021: primitive gate "and1" found in non_leaf module. (Synthesis)
23025 Non-constant Bit Range

Message <filename>(<line no.>): <severity> <rule no.>: bit index or range "%s" should be a constant for signal "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description This rule checks whether any non-constant is used as an index or range of a signal because it is not synthesizable. (Note that the only thing allowed is bit-selection variable for traversing bits in a vectored signal.) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (out, s, in); parameter S_WIDTH = 3; parameter DATA_WIDTH = 8; output out; reg out; input [S_WIDTH-1:0] s; input [DATA_WIDTH-1:0] in; always @(in) out = in[s]; //"s" is not a constant in bits selection, warning endmodule
nLint reports: document.v(10): Warning 23025: bit index or range "[s]" should be a constant for signal "in[s]". (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is end top_ety; architecture arch of top_ety is signal clk : bit; signal in_s : bit_vector(2 downto 0); signal out_s : bit_vector(2 downto 0); begin process( clk ) variable index_v : integer := 1; begin out_s(index_v) <= in_s(index_v); --warning here for index_v in 0 to 2 loop out_s(index_v) <= in_s(index_v); --no warning here end loop; end process; end arch;
nLint reports: document.vhd(12): Warning 23025: bit index or range "(index_v)" should be a constant for signal "in_s(index_v)". (Synthesis) document.vhd(12): Warning 23025: bit index or range "(index_v)" should be a constant for signal "out_s(index_v)". (Synthesis)
23026 (Verilog) Loop Variable Not the Same in All Parts

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: loop variable not the same in all parts. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether the loop variable is the same in all parts. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; integer i; real r; always for (i=0; r<3; i=i+1) r = r+1; endmodule
nLint reports: document.v(5): Warning 23026: loop variable not the same in all parts. (Synthesis)
23027 Non-constant 'for' Loop Count

Message <filename>(<line no.>): <severity> <rule no.>: loop count should be a constant. Configurable Parameter Rule group: Synthesis; Argument type: (CHECK_SUBPROG, IGNORE_SUBPROG); Argument description: select CHECK_SUBPROG to specify checking in subprogram; select IGNORE_SUBPROG to ignore checking in subprogram. Note: this argument is only for VHDL; Default value: "IGNORE_SUBPROG" for Verilog, "IGNORE_SUBPROG" for VHDL; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description This rule checks whether there is any non-constant loop count. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (q, clk, s ); parameter WIDTH = 8; output [WIDTH:0] q; input [2:0] s; input clk; reg [WIDTH:0] q; integer I; always @(posedge clk) for (I=1; I<s; I = I+1) q[I] <= q[I-1]; //loop count is not constant, warning endmodule
nLint reports following if the argument value is ("IGNORE_SUBPROG"): document.v(11): Warning 23027: loop count should be a constant. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 entity Reg is port ( Clk : in bit; D : in bit; Q : out bit ); end Reg; architecture RTL_Reg of Reg is begin process( Clk ) begin if ( Clk'event and Clk = '1' ) then Q <= D; end if; end process; end RTL_Reg; entity top_ety is port ( Clk : in bit; Sig : inout bit_vector( 7 downto 0 );
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Qout: out bit_vector( 7 downto 0 ) ); end top_ety; architecture arch of top_ety is component Reg port ( Clk : in bit; D : in bit; Q : out bit ); end component; signal End_v : integer := 7; begin process begin for Index_v in 0 to End_v loop Sig(Index_v) <= '1' ; end loop; wait; end process;
--warning here
Gen_Lbl: for Index_v in 0 to End_v generate U_all: Reg port map( Clk => Clk, D => Sig(Index_v), Q => Qout(Index_v) ); end generate Gen_Lbl; end arch;
--warning here
nLint reports following if the argument value is ("IGNORE_SUBPROG"): document.vhd(36): Warning 23027: loop count should be a constant. (Synthesis) document.vhd(42): Warning 23027: loop count should be a constant. (Synthesis)
23028 (Verilog) Memory is Read and Written at Same Time

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: memory "%s" is written (at line %d) and read (at line %d) at same time. Configurable Parameter Rule group: Simulation, Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a memory is written in one block and, simultaneously, is read in another. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (clock,VMA,R_W,addr,data); input clock; input VMA; input R_W; input [7:0] addr; inout [7:0] data; reg [7:0] macroram [255:0]; reg [7:0] dataout; assign data = R_W ? dataout : 8'hz; always @(posedge (clock & VMA)) begin if (R_W == 1) dataout=macroram[addr]; macroram[addr]=data; //"macroram" is read and written at same time end endmodule
nLint reports: document.v(16): Warning 23028: memory "macroram[addr]" is written (at line 16) and read (at line 15) at same time. (Simulation,Language Construct)
23029 Race Condition in Sequential Logic

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" should not be assigned and referenced with the same conditions in different sequential blocks (at line %d). Configurable Parameter Rule group: Simulation, Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether a potential race condition exists when a signal is updated in one block and referenced in another simultaneously. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module test (y1, y2, clk, a, b); output y1, y2; input clk, a, b; reg y1, y2; always @( posedge clk ) begin : first y1 = a; //"y1" is assigned when "posedge clk" end always @( posedge clk ) begin : second if ( y1 == 1 ) //"y1" is referenced when "posedge clk", //the value will depend on simulator, warning y2 = b; else y2 = 0; end endmodule
nLint reports: document.v(8): Warning 23029: signal "y1" should not be assigned and referenced with the same conditions in different sequential blocks (at line 13). (Simulation,Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 entity top_ety is port (Clk : in bit; A : in bit; B : in bit); end top_ety; architecture rtl of top_ety is subtype AType is bit; shared variable Y1, Y2: AType; begin process(Clk) begin if ( Clk'event and Clk = '1' ) then Y1 := A; --"Y1" is assigned when "Clk" rising end if; end process; process(Clk)
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begin if ( Clk'event and Clk = '1' ) then if ( Y1 = '1' ) then --"Y1" is referenced when "Clk" rising, -- Only shared variable will violate this Y2 := B; else Y2 := '0'; end if; end if; end process; end rtl;
nLint reports: document.vhd(14): Warning 23029: signal "Y1" should not be assigned and referenced with the same conditions in different sequential blocks (at line 21). (Simulation,Language Construct)
23030 Race Condition in Combinational Logic

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" should not be assigned and referenced under same condition in different combinational blocks (at line %d). Configurable Parameter Rule group: Simulation, Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description If a signal is shared in two blocks under same condition, the simulation result will be implementdependent and difference. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (d2, a, b, sel); output d2; input a, b, sel; wire a, b, sel; reg d1, d2; always if ( d1 else d1 @( sel or a or b ) sel ) = a; = b; // "d1" assigned under @(a) when (!sel)
always @( sel or a ) if ( sel ) d2 = ~a; else d2 = ~d1; // "d1" referenced under @(a) when (!sel) endmodule
nLint reports: document.v(11): Warning 23030: signal "d1" should not be assigned and referenced under same condition in different combinational blocks (at line 17). (Simulation,Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity top_ety is port (A : in bit; B : in bit); end top_ety; architecture rtl of top_ety is subtype AType is bit; shared variable Y1, Y2: AType; begin process(A, B) begin Y1 := A; --"Y1" assigned end process; process(A, B) begin if ( Y1 = '1' ) then --"Y1" referenced, warning here Y2 := B; else
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Y2 := '0'; end if; end process; end rtl;
nLint reports: document.vhd(12): Warning 23030: signal "Y1" should not be assigned and referenced under same condition in different combinational blocks (at line 17). (Simulation,Language Construct)
23031 (Verilog) Z or X Used in Conditional Expression 23031 (VHDL) Meta-logic Value in Conditional Expression
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: conditional expression "%s" contains z or x. (VHDL) <filename>(<line no.>): <severity> <rule no.>: conditional expression "%s" contains meta-logic value. Configurable Parameter Rule group: Language Construct, Synthesis; Argument type: (CHECK_CASEEQ, IGNORE_CASEEQ); Argument description: Select CHECK_CASEEQ to enable checking for case expressions and case labels. Select IGNORE_CASEEQ to disable checking for case expressions and case labels; Default value: "IGNORE_CASEEQ" for Verilog, "IGNORE_CASEEQ" for VHDL; Default severity : Level3 (Error) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether 'x' or 'z' is used in any conditional expressions. The conditional expression with x or z is not synthesizable and it is treated as FALSE during simulation. (VHDL) This rule checks whether there are any meta-logic values used in conditional expressions. The conditional expression with meta-logic values causes mismatches between pre-synthesis and post-synthesis simulation results. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test (dataout, s, datain); parameter WIDTH = 4; output dataout; input s; input [WIDTH-1:0] datain; reg dataout; always @(s or datain) begin if (s == 'bz) //warning dataout = datain[0]; else if (s == 'bx) //warning dataout = datain[1]; else if (s == 'b0) dataout = datain[2]; else dataout = datain[3]; end endmodule
nLint reports following if the argument value is ("IGNORE_CASEEQ"): document.v(10): Error 23031: conditional expression "(s == 'bz)" contains z or x. (Synthesis,Language Construct) document.v(13): Error 23031: conditional expression "(s == 'bx)" contains z or x. (Synthesis,Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library IEEE; use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; entity top_ety is end top_ety; architecture arch of top_ety is signal S1 : std_logic; signal S2 : unsigned( 2 downto 0 ); begin process (S1, S2) variable V : integer := 10; begin if (S1 = 'X') then --warning here V := 0; elsif (S2(2) = 'Z') then --warning here V := 1; else V := 111; end if; end process; end arch;
nLint reports following if the argument value is ("IGNORE_CASEEQ"): document.vhd(14): Error 23031: conditional expression "X" contains meta-logic value. (Synthesis,Language Construct) document.vhd(16): Error 23031: conditional expression "Z" contains meta-logic value. (Synthesis,Language Construct)
23033 (Verilog) Non-constant Divisor

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: divisor "%s" of division or modulo operation should be a constant which is power of 2. Configurable Parameter Rule group: Synthesis; Argument type: (CHECK_POWER_OF_2, CHECK_CONSTANT); Argument description: select POWER_OF_2 to check constant which must be power of 2; select CONSTANT to specify only constant is satisfied. Default value: "CONSTANT" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any division or modulo operation taking a non-constant as its second operand. (It cannot be synthesized.) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (a, b, y); input [2:0] a, b; output [3:0] y; reg [3:0] y; always @(a or b) y = a / b ; //divisor "b" is not a constant, warning endmodule
nLint reports following if the argument value is ("CONSTANT"): document.v(7): Warning 23033: divisor "b" of division or modulo operation should be a constant which is power of 2. (Synthesis)
23034 (Verilog) Non-constant Dividend

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: dividend "%s" of division or modulo operation should be a constant. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any division or modulo operation taking a non-constant as its first operand. (It cannot be synthesized.) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (a, b, y); input [2:0] a, b; output [3:0] y; reg [3:0] y; always @(a or b) y = a / b ; //divisor "a" is not a constant, warning endmodule
nLint reports: document.v(7): Warning 23034: dividend "a" of division or modulo operation should be a constant. (Synthesis)
23035 (Verilog) Loop Variable Changed in 'for' Loop

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: loop variable "%s" should not be modified inside the for loop. Configurable Parameter Rule group: Synthesis, Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any loop variable is modified inside the for loop. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (a,b,y); parameter loopcount = 3; input [loopcount:0] a,b; output [loopcount:0] y; reg [loopcount:0] y; integer i; always @(a or b) begin for ( i=0; i<=loopcount; i=i+1) begin y[i] = a[i]; i = i+1; //loop variable "i" changed in loop, warning end end endmodule
nLint reports: document.v(11): Warning 23035: loop variable "i" should not be modified inside the for loop. (Synthesis,Design Style)
23037 (Verilog) Blocking and Non-blocking Statements in the Same Always Block
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: both blocking and non-blocking assignments (at line %d) are used in the same always block. Configurable Parameter Rule group: Synthesis, Design Style; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there is an always block containing both blocking and nonblocking statements. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module test (clk, rst, count, carry); input clk, rst; output [3:0] count; output carry; reg [3:0] count; reg carry; always @(posedge clk or posedge rst) begin if (~rst) begin count <= 0; carry = 0; //blocking end else if (count == 'b1111) begin carry = carry + 1; count <= 0; //non-blocking end else count = count +1; end endmodule
nLint reports: document.v(13): Warning 23037: both blocking and non-blocking assignments (at line 12) are used in the same always block. (Synthesis,Design Style)
23039 While Statement Not Synthesizable

Message <filename>(<line no.>): <severity> <rule no.>: while statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description This rule checks whether there is any while statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test (a, b, y); parameter WIDTH = 4; input [WIDTH-1:0] a, b; output [WIDTH+3:0] y; reg [WIDTH+3:0] y; integer i; always @(a or b) begin i = 0; while (i <= 3)//"while", warning begin y[i] = a[i]; i = i + 1; end end endmodule
nLint reports: document.v(11): Warning 23039: while statement should not be used because it is not synthesizable. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is port (Clk : in bit; D : out bit_vector( 4 downto 0 ) ); end top_ety; architecture arch of top_ety is signal S : bit_vector(4 downto 0) := "10101"; begin process (Clk) variable A : integer := 0; begin while A <= 5 loop --warning here D(A) <= S(A); A := A + 1; end loop; end process; end arch;
nLint reports:
document.vhd(12): Warning 23039: while statement should not be used because it is not synthesizable. (Synthesis)
23042 Bit of a Bus Signal Used as Special Type Signal

Message <filename>(<line no.>): <severity> <rule no.>: bit select "%s" should not be used as "%s". Configurable Parameter Rule group: Design Style, Synthesis; Argument type: (CLOCK, RESET, SET, LATCH_ENABLE, TRI_ENABLE); Argument description: This is a mutliple selection argument. Every argument represents one signal type Default value: "CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE" for Verilog, "CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any bit select is used as some special type signal (CLOCK, RESET, SET, LATCH_ENABLE, TRI_ENABLE) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (q, clk, rst, in); input in, clk; input [1:0] rst; output q; reg q; always @(posedge clk) if (~rst[1]) //reset signal "rst[1]" is a bit select q <= 0; else q <= in; endmodule
nLint reports following if the argument value is ("CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE"): document.v(8): Warning 23042: bit select "rst[1]" should not be used as "reset". (Synthesis,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity top_ety is port ( reset : in bit_vector(1 downto 0); clock : in bit; d : in bit; q : out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (clock,reset) is begin if (reset(0)='1') then --reset signal "reset(0)" is bit select q<='0'; elsif (clock'event and clock='1') then q<=d; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE"): document.vhd(13): Warning 23042: bit select "reset(0)" should not be used as "reset". (Synthesis,Design Style)
23043 Multiple Bits in Special Type Signal

Message <filename>(<line no.>): <severity> <rule no.>: bus signal "%s" should not be used as "%s". Configurable Parameter Rule group: Design Style, Synthesis; Argument type: (CLOCK, RESET, SET, LATCH_ENABLE, TRI_ENABLE); Argument description: This is a mutliple selection argument. Every argument represents one signal type Default value: "CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE" for Verilog, "CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any bus is used as some special type signal (CLOCK, RESET, SET, LATCH_ENABLE, TRI_ENABLE). Originally in lint2.2, use 22229's argument to control if a latch enable is a clock or ctrl. In lint2.3, treate all latch enable as clock. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (q, clk, rst, in); input in, clk; input [1:0] rst; output q; reg q; always @(posedge clk) if (~rst) //reset signal "rst" is multiple bit signal q <= 0; else q <= in; endmodule
nLint reports following if the argument value is ("CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE"): document.v(8): Warning 23043: bus signal "rst" should not be used as "reset". (Synthesis,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 entity top_ety is port ( reset : in bit; clock : in bit_vector(3 downto 0); d : in bit; q : out bit ); end entity top_ety; architecture arch of top_ety is begin p1: process (reset,clock) is begin if (reset='1') then q<='0'; elsif (clock'event and clock="1111") then q<=d; end if; end process p1;
19
nLint reports following if the argument value is ("CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE"): document.vhd(15): Warning 23043: bus signal "clock" should not be used as "clock". (Synthesis,Design Style)
23044 Special Type Port Connected to an Expression

Message <filename>(<line no.>): <severity> <rule no.>: "%s" port should not be connect to an expression "%s". Configurable Parameter Rule group: Design Style, Synthesis; Argument type: (CLOCK, LATCH_ENABLE, TRI_ENABLE); Argument description: select CLOCK to specify that clock expression should be checked; select LATCH_ENABLE means that latch enable expression should be checked; select TRI_ENABLE to specify that tri-state enable expression should be checked. Default value: "LATCH_ENABLE,TRI_ENABLE" for Verilog, "LATCH_ENABLE,TRI_ENABLE" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any special type port (CLOCK, LATCH_ENABLE, TRI_ENABLE) connects to an expression. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test ( a, b, c, y, d ); input a, b, c, y; output d; reg d; always @(a or b or c or y) if(a&b|c) // warning here if TRI_ENABLE is selected d = y; else d = 1'bz; endmodule
nLint reports following if the argument value is ("LATCH_ENABLE,TRI_ENABLE"): document.v(6): Warning 23044: "tri-state enable" port should not be connect to an expression "((a & b) | c)". (Synthesis,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 library ieee; use ieee.std_logic_1164.all; entity top_ety is end; architecture arch of top_ety is signal data : std_logic_vector(7 downto 0); signal output_en : std_logic; signal output_xs : std_logic; begin data <= "11111111" WHEN (output_en = '1') AND (output_xs ='0')ELSE "XXXXXXXX" WHEN (output_en = '0') AND (output_xs = '1') ELSE "ZZZZZZZZ"; -- warning end;
nLint reports following if the argument value is ("LATCH_ENABLE,TRI_ENABLE"): document.vhd(12): Warning 23044: "tri-state enable" port should not be connect to an expression "GEN4_data". (Synthesis,Design Style)
23045 (Verilog) Time Variable Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: time variable "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any time variable used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test; time timer;//non-synthesizable, warning endmodule
nLint reports: document.v(2): Warning 23045: time variable "timer" should not be used because it is not synthesizable. (Synthesis)
23047 Real Variable Not Synthesizable

Message <filename>(<line no.>): <severity> <rule no.>: real variable "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description This rule checks whether there is any real variable used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test; real real_b;//non-synthesizable, warning endmodule
nLint reports: document.v(2): Warning 23047: real variable "real_b" should not be used because it is not synthesizable. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end entity top_ety; architecture arch of top_ety is signal s : real; --warning here begin end architecture arch;
nLint reports: document.vhd(5): Warning 23047: real variable "s" should not be used because it is not synthesizable. (Synthesis)
23049 (Verilog) Realtime Variable Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: realtime variable "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) real time variable should be removed since it is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test; realtime rt;//non-synthesizable, warning endmodule
nLint reports: document.v(2): Warning 23049: realtime variable "rt" should not be used because it is not synthesizable. (Synthesis)
23050 (Verilog) Unpacked Union Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: unpacked union should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there are unpacked unions, which are not synthesizable, in the design. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module topmodule; union unsigned { int ii; logic fff; } um; union packed { bit t; } un; //no warning typedef struct packed { union packed { bit i; logic f; } m; union { bit hf; } n; //warning } number_type; number_type num; endmodule //warning
//no warning
nLint reports: document.sv(3): Warning 23050: unpacked union should not be used because it is not synthesizable. (Synthesis) document.sv(8): Warning 23050: unpacked union should not be used because it is not synthesizable. (Synthesis)
23051 (Verilog) Event Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: event "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any event used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 module test; event event_a; //non-synthesizable, warning //... endmodule
nLint reports: document.v(2): Warning 23051: event "event_a" should not be used because it is not synthesizable. (Synthesis)
23053 (Verilog) UDP Instance Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: UDP instance "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any UDP instance which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module top; reg a, b, cin; wire sum; test u_test_0(sum, cin, a, b); //non-synthesizable, warning endmodule primitive test(sum, cin, a, b); output sum; input cin,a,b; table 0 0 0 : 0; 0 0 1 : 1; 0 1 0 : 1; 0 1 1 : 0; 1 0 0 : 1; 1 0 1 : 0; 1 1 0 : 0; 1 1 1 : 1; endtable endprimitive
nLint reports: document.v(4): Warning 23053: UDP instance "u_test_0" should not be used because it is not synthesizable. (Synthesis)
23055 (Verilog) Specify Block Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: specify block should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any specify block which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 module test; specify //non-synthesizable, warning here endspecify endmodule
nLint reports: document.v(2): Warning 23055: specify block should not be used because it is not synthesizable. (Synthesis)
23057 (Verilog) Initial Block Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: initial block should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any initial block which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test; reg a, b; initial //non-synthesizable, warning begin a = 0; b = 1; end endmodule
nLint reports: document.v(3): Warning 23057: initial block should not be used because it is not synthesizable. (Synthesis)
23059 (Verilog) Task Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: task "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any task used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; task multiply; //non-synthesizable, warning begin end endtask endmodule
nLint reports: document.v(2): Warning 23059: task "multiply" should not be used because it is not synthesizable. (Synthesis)
23061 (Verilog) UDP Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: UDP declaration should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any UDP declaration which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 primitive test(sum, cin, a, b);//non-synthesizable, warning output sum; input cin, a, b; table 0 0 0 : 0; 0 0 1 : 1; 0 1 0 : 1; 0 1 1 : 0; 1 0 0 : 1; 1 0 1 : 0; 1 1 0 : 0; 1 1 1 : 1; endtable endprimitive
nLint reports: document.v(1): Warning 23061: UDP declaration should not be used because it is not synthesizable. (Synthesis)
23065 (Verilog) Macromodule Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: macromodule "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any "macromodule" which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 macromodule test( carry, sum, cin, a, b); //non-synthesizable, warning input carry, a, b; output sum; inout cin; endmodule
nLint reports: document.v(1): Warning 23065: macromodule "test" should not be used because it is not synthesizable. (Synthesis)
23069 (Verilog) Function with Integer Return Value

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: function with integer return value is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether there are any functions whose return value is an integer. These types of functions are not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test; function integer testfun; //warning input a, b, cin; testfun = a + b + cin; endfunction endmodule
nLint reports: document.v(3): Warning 23069: function with integer return value is not synthesizable. (Synthesis)
23071 Function Returning Real Not Synthesizable

Message <filename>(<line no.>): <severity> <rule no.>: function returning real type value should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any function returning real type value which is not synthesizable. (VHDL) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 module top; reg a,b; wire m; initial begin $monitor($time,,,"a=%b,b=%b, m=%b ",a,b,m ); a = 0; b = 0; #20 begin a = 1; b =1; end #50 $finish; end test u_test_0( m, a, b); endmodule module test (m, a, b); output m; input a,b; reg m; real mul; function real testfun; input a,b; testfun = a * b; endfunction always @(a or b ) mul = testfun(a,b); endmodule //warning here
nLint reports: document.v(22): Warning 23071: function returning real type value should not be used because it is not synthesizable. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 entity top_ety is end; architecture arch of top_ety is
4 5 6 7 8 9
function func1 (v : real) return real is --warning here begin return v; end function func1; begin end;
nLint reports: document.vhd(4): Warning 23071: function returning real type value should not be used because it is not synthesizable. (Synthesis)
23073 (Verilog) Net Types Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: net "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any net of type tri1, supply0, triand, tri0, supply1, trior, or trireg, which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test; tri1 tri1_t;//"tri1" non-synthesizable, warning tri0 tri0_t;//"tri0" non-synthesizable, warning supply0 supply0_t;//"supply0" non-synthesizable, warning supply1 supply1_t;//"supply1" non-synthesizable, warning triand triand_t;//"triand" non-synthesizable, warning trior trior_t;//"trior" non-synthesizable, warning trireg trireg_t;//"trireg" non-synthesizable, warning endmodule
nLint reports: document.v(2): synthesizable. document.v(3): synthesizable. document.v(4): synthesizable. document.v(5): synthesizable. document.v(6): synthesizable. document.v(7): synthesizable. document.v(8): synthesizable.
Warning 23073: (Synthesis) Warning 23073: (Synthesis) Warning 23073: (Synthesis) Warning 23073: (Synthesis) Warning 23073: (Synthesis) Warning 23073: (Synthesis) Warning 23073: (Synthesis)
net "tri1_t" should not be used because it is not net "tri0_t" should not be used because it is not net "supply0_t" should not be used because it is not net "supply1_t" should not be used because it is not net "triand_t" should not be used because it is not net "trior_t" should not be used because it is not net "trireg_t" should not be used because it is not
23075 (Verilog) Delay Ignored by Synthesis

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: delay is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any delay used because it is ignored by synthesis, which may cause different between simulation result of pre-synthesis and post-synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test (a,b,c); input a, b; output c; and #(3,5) and_test(c, a, b); //non-synthesizable, warning endmodule
nLint reports: document.v(5): Warning 23075: delay is ignored by synthesis. (Synthesis)
23077 (Verilog) Defparam Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: defparam "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any defparam used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module top (a,b,clk); input [6:0] a; input clk; output [6:0] b; sub m1 (.clk(clk), .in(a), .out(b)); endmodule module sub (in,clk,out); parameter size = 8,delay = 2; input [size-1:0] in; input clk; output [size-1:0] out; reg [size-1:0] out; always @(posedge clk) #delay assign out = in; endmodule module annotate; defparam //non-synthesizable, warning top.m1.size = 5 , top.m1.delay = 10; endmodule
nLint reports: document.v(23): Warning 23077: defparam "top.m1.size" should not be used because it is not synthesizable. (Synthesis) document.v(24): Warning 23077: defparam "top.m1.delay" should not be used because it is not synthesizable. (Synthesis)
23079 (Verilog) Memory Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: memory " %s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether the memory (i.e., 2D signals) exists, which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test; //... reg [7:0] mem [0:1023];//memory "mem" non-synthesizable, warning //... endmodule
nLint reports: document.v(3): Warning 23079: memory " mem" should not be used because it is not synthesizable. (Synthesis)
23083 (Verilog) Drive Strength Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: drive strength "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any drive strength which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (a, b); output a; input b; trireg (large) #(0,0,50) cap1; //"large" non-synthesizable assign (strong1,pull0) b = a; //"strong1,pull0" non-synthesizable endmodule
nLint reports: document.v(5): Warning 23083: drive strength "(large)" should not be used because it is not synthesizable. (Synthesis) document.v(6): Warning 23083: drive strength "(pull0, strong1)" should not be used because it is not synthesizable. (Synthesis)
23087 (Verilog) Repeat Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: repeat statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any repeat statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (y, c, d, a, b); input a, b; output c, d; output [1:0] y; reg c, d; reg [1:0] y; always @(a or b) begin repeat(3) {c, d} = {a, b};//"repeat" non-synthesizable, warning y = repeatfun(a, b); end function [1:0] repeatfun; input a, b; repeat(6) repeatfun = {b, a};//"repeat" non-synthesizable, warning endfunction endmodule
nLint reports: document.v(10): Warning 23087: repeat statement should not be used because it is not synthesizable. (Synthesis) document.v(16): Warning 23087: repeat statement should not be used because it is not synthesizable. (Synthesis)
23089 (Verilog) Delay Control Ignored by Synthesis

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: delay control "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any delay which may cause difference between simulation result of pre-synthesis and post-synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (clk, data, y); input clk, data; output y; reg y; always @(posedge clk) #10 y = data;//"#10" ignored by synthesis, warning endmodule
nLint reports: document.v(7): Warning 23089: delay control "10" is ignored by synthesis. (Synthesis)
23091 (Verilog) Event Control in Unsuitable Place is Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: event control "%s" in unsuitable place is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any event control in unsuitable place. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (clk, data, y); input clk, data; output y; reg y; always @(posedge clk) @( data ) y = data;//"@(data)" non-synthesizable, warning endmodule
nLint reports: document.v(7): Warning 23091: event control "data" in unsuitable place is not synthesizable. (Synthesis)
23095 (Verilog) Wait Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: wait statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any wait statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (out, clk, rst, in); input clk, rst, in; output out; reg out; always @(posedge clk) wait(rst) out = in; //"wait" non-synthesizable, warning endmodule
nLint reports: document.v(7): Warning 23095: wait statement should not be used because it is not synthesizable. (Synthesis)
23097 (Verilog) Event Enable Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: event enable statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any event enable statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module test (clk, rst, d, q); input clk, rst, d; output q; reg q; event event1,event2; always @(posedge clk) if ( !rst ) ->event1;//"->enent1" non-synthesizable, warning else ->event2;//"->enent2" non-synthesizable, warning always @event1 q <= 0; always @event2 q <= d; endmodule
nLint reports: document.v(9): Warning 23097: event enable statement should not be used because it is not synthesizable. (Synthesis) document.v(11): Warning 23097: event enable statement should not be used because it is not synthesizable. (Synthesis)
23099 (Verilog) Fork Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: fork statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any fork statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (out, clk, rst, in); input clk, rst, in; output out; reg out; always @(posedge clk) fork //"fork" non-synthesizable, warning if (~rst) out = 0; else out = in; join endmodule
nLint reports: document.v(7): Warning 23099: fork statement should not be used because it is not synthesizable. (Synthesis)
23101 (Verilog) Task Call Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: task call statement "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any task call statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module test; reg clock; reg a; reg b; reg y; always @(posedge clock) multiply(a, b, y); //"multiply" non-synthesizable, warning task multiply; input a; input b; output y1; begin: serialMult reg c, d; c = a; d = b; y1 = 0; repeat (5) begin y1 = c & d; end end endtask endmodule
nLint reports: document.v(8): Warning 23101: task call statement "multiply(a, b, y);" should not be used because it is not synthesizable. (Synthesis)
23103 (Verilog) System Task Call Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: system task call "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any system task call statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 module init; 2 reg clk, rst, in; 3 wire out; 4 5 initial begin 6 $monitor($time,,,"clk=%d,rst=%b,in=%b,out=%b",clk,rst,in,out); //warning here 7 clk = 0; 8 rst = 1; 9 in = 0; 10 #2 rst = 0; 11 #10 rst = 1; 12 #50 $finish; //warning here 13 end 14 always 15 #4 clk = !clk; 16 always 17 #10 in = !in; 18 test u_test( out, clk, rst, in ); 19 endmodule 20 21 module test (out, clk, rst, in); 22 input clk, rst, in; 23 output out; 24 reg out; 25 26 always @(posedge clk) 27 begin 28 wait(rst) out = in; 29 $finish; 30 end 31 endmodule
nLint reports: document.v(29): Warning 23103: system task call "$finish;" should not be used because it is not synthesizable. (Synthesis)
23105 (Verilog) Disable Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: disable statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any disable statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 module test; reg clock, reset; reg a; reg b; reg y; always @(posedge clock) multiply(a, b, y); always @( negedge reset ) disable multiply; //"disable" non-synthesizable, warning here task multiply; input a; input b; output y1; begin: serialMult reg c, d; c = a; d = b; y1 = 0; repeat (5) begin y1 = c & d; end end endtask endmodule
nLint reports: document.v(11): Warning 23105: disable statement should not be used because it is not synthesizable. (Synthesis)
23107 (Verilog) Force Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: force statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any force statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test; reg a,b,c,d,e; initial begin $monitor($time,,,"a=%d,b=%d,c=%d,d=%d,e=%d",a,b,c,d,e); assign d = a & b & c; a = 1; b = 0; c = 1; #10 force d = (a | b | c); //"force" non-synthesizable, warning force e = (a | b | c); //"force" non-synthesizable, warning release d; release e; #10 $finish; end endmodule
nLint reports: document.v(10): Warning 23107: force statement should not be used because it is not synthesizable. (Synthesis) document.v(11): Warning 23107: force statement should not be used because it is not synthesizable. (Synthesis)
23109 (Verilog) Release Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: release statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any release statement which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test; reg a, b, c, d, e; initial begin $monitor($time,,,"a=%d,b=%d,c=%d,d=%d,e=%d",a,b,c,d,e); assign d = a & b & c; a = 1; b = 0; c = 1; #10 force d = (a | b | c); force e = (a | b | c); release d; //"release" non-synthesizable, warning release e; //"release" non-synthesizable, warning #10 $finish; end endmodule
nLint reports: document.v(12): Warning 23109: release statement should not be used because it is not synthesizable. (Synthesis) document.v(13): Warning 23109: release statement should not be used because it is not synthesizable. (Synthesis)
23115 (Verilog) String Constant Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: string "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any string used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 module test (c,a,b); output c; input a,b; reg c; reg [8*14:1] strvar; always @(a or b) begin if (a == b) begin c = 'b1; strvar = "are equal."; //"are equal." non-synthesizable, warning end else begin c = 'b0; strvar = "are not equal."; //"are not equal." //non-synthesizable, warning end $display("a and b %s", strvar); end endmodule
nLint reports: document.v(12): Warning 23115: string "are equal." should not be used because it is not synthesizable. (Synthesis) document.v(17): Warning 23115: string "are not equal." should not be used because it is not synthesizable. (Synthesis)
23117 (Verilog) Real Constant Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: real number "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any real number used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test; real a, b; reg [64:1] neta_r, netb_r; always #5 begin assign a = 1.5; //"1.5" non-synthesizable, warning assign b = 1.2; //"1.2" non-synthesizable, warning assign neta_r = $realtobits(a); assign netb_r = $realtobits(b); end endmodule
nLint reports: document.v(6): Warning 23117: real number "1.5" should not be used because it is not synthesizable. (Synthesis) document.v(7): Warning 23117: real number "1.2" should not be used because it is not synthesizable. (Synthesis)
23119 (Verilog) Hierarchical Reference Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: hierarchical reference "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any hierarchical reference which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module top; reg a, b, dotc; wire c; always dotc = test1.c; //"test1.c" non-synthesizable, warning endmodule module test1; reg a,b,c; initial c = 'b1; endmodule
nLint reports: document.v(6): Warning 23119: hierarchical reference "test1.c" should not be used because it is not synthesizable. (Synthesis)
23121 No Set or Reset Signal

Message <filename>(<line no.>): <severity> <rule no.>: register "%s" should have a set or reset signal. Configurable Parameter Rule group: Design Style; Argument type: (ASYNC, SYNC, BOTH); Argument description: select ASYNC to specify that only asynchronous reset/set can satisfy this rule; select SYNC to specify that only synchronous reset/set can satisfy this rule; select BOTH to specify that both asynchronous and synchronous reset/set can satisfy this rule; Default value: "BOTH" for Verilog, "BOTH" for VHDL; Default severity : Level3 (Error) This rule is turned OFF by default; Description This rule checks whether there is any register without reset/set control. A register shall be reset/set with a determined value. Otherwise the initial value can remain x forever especially in a feedback circuit. As in the following example, q will be in an unknown state before the positive edge of clock comes. If such a register is used and there is a feedback from q to d through outside scope logic, there may be some problems. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module test (counter, clock, reset); input clock, reset; output [3:0] counter; reg [3:0] counter; wire [3:0] tmp; pure_dff( tmp, clock, tmp+4'b1 ); always @( reset or tmp ) if ( ~reset ) counter <= 0; else counter <= tmp; endmodule module pure_dff (q, clock, d); output [3:0] q; input clock; input [3:0] d; reg [3:0] q; always @(posedge clock) q = d; //when simulation begins, the value of "q" cannot //be easily determined, warning endmodule
nLint reports following if the argument value is ("BOTH"): document.v(23): Error 23121: register "q" should have a set or reset signal. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 library ieee; use ieee.std_logic_1164.all; entity com is port ( Q : out std_ulogic;
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
D : in std_ulogic; Clk : in std_ulogic ); end com; architecture RTL of com is begin process( Clk ) begin if (Clk'event and Clk = '1') then Q <= D; end if; end process; end RTL; library ieee; use ieee.std_logic_1164.all; entity top_ety is port ( Q : inout std_ulogic; Cout : out std_ulogic; Clock : in std_ulogic; Reset : in std_ulogic ); end top_ety; architecture arch of top_ety is component com is port ( Q : out std_ulogic; D : in std_ulogic; Clock : in std_ulogic ); end component; signal D : std_ulogic; begin U1: com port map ( Q, D, Clock ); process( Reset, Q ) begin if (Reset = '0') then Cout <= '0'; else Cout <= Q; end if; end process; end arch;
nLint reports following if the argument value is ("BOTH"): document.vhd(14): Error 23121: register "Q" should have a set or reset signal. (Design Style)
23122 Unassigned in Data Clause

Message <filename>(<line no.>): <severity> <rule no.>: register "%s" should be assigned in data clause. Configurable Parameter Rule group: Design Style; Argument type: (CHECK_NOTFULL, IGNORE_NOTFULL); Argument description: select IGNORE_NOTFULL to check lost assigned signals in data clause; select CHECK_NOTFULL to check lost assigned signals in data clause, in additional, to check signal not complete assigned in every data clause branch; Default value: "IGNORE_NOTFULL" for Verilog, "IGNORE_NOTFULL" for VHDL; Default severity : Level3 (Error) This rule is turned OFF by default; Description A register which has reset/set clause shall also be assigned in "data" clause. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module test (counter, clock, reset); input clock, reset; output [3:0] counter; reg [3:0] counter; wire [3:0] tmp; pure_dff( tmp, clock, tmp+4'b1 ); always @(posedge clock or negedge reset) if ( ~reset ) counter = 0; //warning here //else // counter = tmp; endmodule module pure_dff (q, clock, d); output [3:0] q; input clock; input [3:0] d; reg [3:0] q; always @(posedge clock) q = d; endmodule
nLint reports following if the argument value is ("IGNORE_NOTFULL"): document.v(11): Error 23122: register "counter" should be assigned in data clause. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 library ieee; use ieee.std_logic_1164.all; entity com is port ( Q : out std_ulogic; D : in std_ulogic; Clk : in std_ulogic ); end com; architecture arch of com is begin
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
process( Clk ) begin if Clk'event and Clk = '1' then Q <= D; end if; end process; end arch; library ieee; use ieee.std_logic_1164.all; use work.all; entity top_ety is port ( Din : in std_ulogic; Cout : out std_ulogic; Reset : in std_ulogic; Clock : in std_ulogic ); end top_ety; architecture arch of top_ety is component com is port ( Q : out std_ulogic; D : in std_ulogic; Clock : in std_ulogic ); end component; begin U1: com port map ( Cout, Din, Clock ); process begin wait until clock'event and clock = '1'; if Reset = '1' then Cout <= '0'; --warning here --elsif (rising_edge(Clock)) then -- Cout <= Din; end if; end process; end arch;
nLint reports following if the argument value is ("IGNORE_NOTFULL"): document.vhd(42): Error 23122: register "Cout" should be assigned in data clause. (Design Style)
23123 Overlapped Case Labels

Message <filename>(<line no.>): <severity> <rule no.>: the value of case label "%s" overlaps with the value of case label "%s"(at line %d). Configurable Parameter Rule group: Simulation, Synthesis; Argument type: (BOTH, PRIORITY, PARALLEL) (IGNORE_MULTI_CHOICE, CHECK_MULTI_CHOICE); Argument description: The first argument allows users to apply checking on priority case statements (PRIORITY), parallel case statements (PARALLEL) or both (BOTH). Select IGNORE_MULTI_CHOICE to ignore this rule on multiple choices in one case item; select CHECK_MULTI_CHOICE to check this rule on multiple choices in one case item; Default value: "BOTH","IGNORE_MULTI_CHOICE" for Verilog, "BOTH","IGNORE_MULTI_CHOICE" for VHDL; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there are any overlapped case labels used in the same case statement. (VHDL) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test(y,state); output [1:0]y; input [2:0]state; reg [1:0] y; always @(state) casex(state) 3'b101: y = 1; 3'b110: y = 2; 3'bx01: y = 3; //warning default: y = 0; endcase endmodule
nLint reports following if the argument value is ("BOTH","IGNORE_MULTI_CHOICE"): document.v(10): Warning 23123: the value of case label "3'bx01" overlaps with the value of case label "3'b101"(at line 8). (Simulation,Synthesis)
(VHDL)
23125 (Verilog) Procedural Continuous Assignment Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: procedural continuous assign statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any procedural continuous assign statement used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (q, clk, reset, d); output q; input clk, reset, d; reg q; wire clk, reset, d; always @(posedge clk) q <= d; always @(reset) if (~reset) assign q = 0; //procedural continuous assignment //non-synthesizable, warning else deassign q; endmodule
nLint reports: document.v(12): Warning 23125: procedural continuous assign statement should not be used because it is not synthesizable. (Simulation,Synthesis)
23127 (Verilog) Deassign Statement Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: deassign statement should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any deassign statement used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (q,d,clear,preset,clk); output q; input d,clear,preset,clk; reg q; always @(clear or preset) if (~clear ) assign q = 0; else if (!preset) assign q = 1; else deassign q; //"deassign" non-synthesizable, warning always @ (posedge clk) q = d; endmodule
nLint reports: document.v(12): Warning 23127: deassign statement should not be used because it is not synthesizable. (Synthesis)
23129 (Verilog) Case Equivalence Operator Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: operators "===" and "!==" should not be used because they are not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any "===" or "!==" used which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (q, clock, reset, d); output q; input clock, reset, d; reg q; wire clock, reset, d; always @(posedge clock or negedge reset) if (reset === 0) //case equal "===" non-synthesizable, warning q = 0; else q = 1; endmodule
nLint reports: document.v(8): Warning 23129: operators "===" and "!==" should not be used because they are not synthesizable. (Synthesis)
23131 (Verilog) Operation on X/Z

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: operation on X/Z or directly assigned by X/Z should not be used because it will result in simulation mismatch. Configurable Parameter Rule group: Simulation; Argument type: (IGNORE_DEFAULT, CHECK_DEFAULT); Argument description: select IGNORE_DEFAULT to specify no checking assignment with X value in default clause; select CHECK_DEFAULT to specify checking including assignment with X value in default clause; Default value: "IGNORE_DEFAULT" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any operation performed on meta-logic value X/Z or directly assigned by X/Z, which will cause simulation mismatch between pre-synthesis and postsynthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (a, b); input b; output a; wire c; assign c = 1'bz; //warning here, Z is directly assigned to some signal assign a = b & 1'bx | c; //warning here, X is operated endmodule
nLint reports following if the argument value is ("IGNORE_DEFAULT"): document.v(5): Warning 23131: operation on X/Z or directly assigned by X/Z should not be used because it will result in simulation mismatch. (Simulation) document.v(6): Warning 23131: operation on X/Z or directly assigned by X/Z should not be used because it will result in simulation mismatch. (Simulation)
23133 (Verilog) Redundant Asynchronous Signal

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: redundant asynchronous signal "%s" is specified in the sensitivity list. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether there is a redundant asynchronous signal specified in the sensitivity list but not referred in the succeeding statements of the always block. The coding style is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (clk, rst1, rst2, set, d, q); input clk, rst1, rst2, set; input d; output q; reg q; always @( posedge clk or negedge rst1 or posedge set ) //redundant asynchronous signal "set", warning if( ~rst1 ) q <= 1'b0; else q <= d; always @( posedge clk or negedge rst2 ) //redundant asynchronous signal "rst2", warning q <= d; endmodule
nLint reports: document.v(7): Warning 23133: redundant asynchronous signal "set" is specified in the sensitivity list. (Synthesis) document.v(14): Warning 23133: redundant asynchronous signal "rst2" is specified in the sensitivity list. (Synthesis)
23135 (Verilog) Different Polarity in Condition and Sensitivity List

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: polarity of asynchronous signal "%s" should not be different in condition "%s" and sensitivity list "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is an asynchronous signal with different polarity in condition and sensitivity list which is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (clk, rst, d, q); input clk, rst, d; output q; reg q; always @( posedge clk or negedge rst ) if( rst ) //polarity of "rst" here is different with //that in sensitivity list "negedge rst", warning here q <= 1'b0; else q <= d; endmodule
nLint reports: document.v(7): Warning 23135: polarity of asynchronous signal "rst" should not be different in condition "rst" and sensitivity list "negedge rst". (Synthesis)
23137 (Verilog) Both Edge and Non-edge Expressions in the Sensitivity List
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: edge and non-edge expressions are mixed in the sensitivity list. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; Description (Verilog) This rule checks whether a sensitivity list contains both edge and non-edge expressions. This coding style is not synthesizable. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (clk, rst, d, q); input clk, rst; input d; output q; reg q; always @( posedge clk or rst ) //warning if( rst ) q <= 1'b0; else q <= d; endmodule
nLint reports: document.v(7): Warning 23137: edge and non-edge expressions are mixed in the sensitivity list. (Synthesis)
23401 (Verilog) Floating Net

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: floating net "%s" detected. Configurable Parameter Rule group: ERC; Argument type: none; Default severity : Level1 (Information) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any floating net in the design. Only the net crossing hierarchy, but not connected to any cell, primary input, or primary output, will be reported. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module wire wire wire top; b; // "b" is floating to "test.u1.b" c; // "c" is floating to "test.d" d;
test1 u1 (b,c,d); endmodule module test1 (b,c,d); input b; input c; output d; assign d = c; endmodule
nLint reports: document.v(2): Information 23401: floating net "top.b" detected. (ERC) document.v(3): Information 23401: floating net "top.c" detected. (ERC)
23405 (Verilog) Input Floating

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s pin %s floating %s. Configurable Parameter Rule group: ERC; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether any input pins are floating in a cell. Please note that a primary output (PO) port is treated as a cell. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (c); output [7:0] c; test1 t1_i (c); endmodule module test1 (c); output [7:0] c; wire a; wire [7:0] c; not n1 (c[1], a); endmodule //warning on GATE inst "n1" //warning on PO "c"
nLint reports: document.v(1): Warning 23405: primary output pin "test.c" floating through wire "test.c[7:2]". (ERC) document.v(1): Warning 23405: primary output pin "test.c" floating through wire "test.c[0]". (ERC) document.v(12): Warning 23405: input pin "I" ("a") of "cell test1.n1" floating through wire "test1.a". (ERC)
23407 (Verilog) Partial Input Floating

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s pin %s partial floating %s. Configurable Parameter Rule group: ERC; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether partial floating inputs exist for a cell. "Floating" means a net is not connected to any cell, primary output (PO), or primary input (PI). "Cell input pin" drivers mean the pin drives nets which may cross hierarchy. If all the drivers of a "cell input pin" are floating nets, then nLint will report "input floating"; if some drivers of a "cell input pin" are floating nets and some are not, nLint will report "partial input floating". Please note that PO is treated as a cell. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module top(in1); input in1; wire in1; t1 u1 (in1); //warning, partial input floating test u2 (in1); endmodule module test(out); output out; wire a; assign out = a; endmodule `celldefine module t1(in); input in; endmodule èndcelldefine
nLint reports: document.v(4): Warning 23407: input pin "in" ("in1") of "cell top.u1" partial floating through wire "top.u2.a". (ERC) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test(d); input d; wire c,d,e; test1 u1 (c); test2 u2 (c); and (e,c,d); endmodule module test1(a); output a; wire a; endmodule module test2(b); output b; wire b; endmodule
nLint reports:
23409 (Verilog) Output Floating

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s pin %s floating %s. Configurable Parameter Rule group: ERC; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any output pins are floating in a cell. Please note that a primary input (PI) port is treated as a cell. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test (a, c); input a, c; wire b; not n1(b, c); //warning here endmodule
nLint reports: document.v(1): Warning 23409: primary input pin "test.a" floating through wire "test.a". (ERC) document.v(5): Warning 23409: output pin "O0" ("b") of "cell test.n1" floating through wire "test.b". (ERC)
24001 (Verilog) VHDL Reserved Words

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: a VHDL reserved word should not be used as object name "%s". Configurable Parameter Rule group: HDL Translation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any VHDL reserved word used. VHDL reserved words: "abs", "access", "after", "alias", "all", "and", "architecture", "array", "assert", "attribute", "begin", "block", "body", "buffer", "bus", "case", "component", "configuration", "constant", "disconnect", "downto", "else", "elsif", "end", "entity", "exit", "file", "for", "function", "generate", "generic", "group", "guarded", "if", "impure", "in", "inertial", "inout", "is", "label", "library", "linkage", "literal", "loop", "map", "mod", "nand", "new", "next", "nor", "not", "null", "of", "on", "open", "or", "others", "out", "package", "port", "postponed", "procedure", "process", "pure", "range", "record", "register", "reject", "rem", "report", "return", "rol", "ror", "select", "severity", "shared", "signal", "sla", "sll", "sra", "srl", "subtype", "then", "to", "transport", "type", "unaffected", "units", "until", "use", "variable", "wait", "when", "while", "with", "xnor", "xor" Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test (out, in); input [1:0] in; //warning on "in" output out; //warning on "out" wire c; endmodule
nLint reports: document.v(2): Warning 24001: a VHDL reserved word should not be used as object name "in". (HDL Translation) document.v(3): Warning 24001: a VHDL reserved word should not be used as object name "out". (HDL Translation)
24003 (VHDL) Verilog Reserved Words

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: a Verilog reserved word should not be used as object name "%s". Configurable Parameter Rule group: HDL Translation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) Do not use Verilog reserved words to avoid translation error. Verilog reserved words: "always", "and", "assign", "begin", "buf", "bufif0", "bufif1", "case", "casex", "casez", "cmos", "deassign", "default", "defparam", "disable", "edge", "else", "end", "endcase", "endmodule", "endfunction", "endprimitive", "endspecify", "endtable", "endtask", "event", "for", "force", "forever", "fork", "function", "highz0", "highz1", "if", "ifnono", "initial", "inout", "input", "integer", "join", "large", "macromodule", "medium", "module", "nand", "negedge", "nmos", "nor", "not", "notif0", "notif1", "or", "output", "parameter", "pmos", "posedge", "primitive", "pull0", "pull1", "pullup", "pulldown", "rcmos", "real", "realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "scalared", "small", "specify", "specparam", "strong0", "strong1", "supply0", "sypply1", "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand", "trior", "trireg", "vectored", "wait", "wand", "weak0", "weak1", "while", "wire", "wor", "xnor", "xor" Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end entity top_ety; architecture arch of top_ety is signal always : bit; --warning on "always" signal assign : bit; --warning on "assign" begin end architecture arch;
nLint reports: document.vhd(5): Warning 24003: a Verilog reserved word should not be used as object name "always". (HDL Translation) document.vhd(6): Warning 24003: a Verilog reserved word should not be used as object name "assign". (HDL Translation)
24005 (Verilog) SystemVerilog Reserved Words

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: SystemVerilog reserved word "%s" is used as an identifier in a Verilog design. Configurable Parameter Rule group: HDL Translation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any SystemVerilog reserved words are used as an identifier in a Verilog design. The SystemVerilog reserved words are listed below. alias, "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before", "begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle", "class", "clocking", "cmos", "config", "const", "constraint", "context", "continue", "cover", "covergroup", "coverpoint", "cross", "deassign", "default", "defparam", "design", "disable", "dist", "do", "edge", "else", "end", "endcase", "endclass", "endclocking", "endconfig", "endfunction", "endgenerate", "endgroup", "endinterface", "endmodule", "endpackage", "endprimitive", "endprogram", "endproperty", "endspecify", "endsequence", "endtable", "endtask", "enum", "event", "expect", "export", "extends", "extern", "final", "first_match", "for", "force", "foreach", "forever", "fork", "forkjoin", "function", "generate", "genvar", "highz0", "highz1", "if", "iff", "ifnone", "ignore_bins", "illegal_bins", "import", "incdir", "include", "initial", "inout", "input", "inside", "instance", "int", "integer", "interface", "intersect", "join", "join_any", "join_none", "large", "liblist", "library", "local", "localparam", "logic", "longint", "macromodule", "matches", "medium", "modport", "module", "nand", "negedge", "new", "nmos", "nor", "noshowcancelled", "not", "notif0", "notif1", "null", "or", "output", "package", "packed", "parameter", "pmos", "posedge", "primitive", "priority", "program", "property", "protected", "pull0", "pull1", "pulldown", "pullup", "pulsestyle_onevent", "pulsestyle_ondetect", "pure", "rand", "randc", "randcase", "randsequence", "rcmos", "real", "realtime", "ref", "reg", "release", "repeat", "return", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "scalared", "sequence", "shortint", "shortreal", "showcancelled", "signed", "small", "solve", "specify", "specparam", "static", "string", "strong0", "strong1", "struct", "super", "supply0", "supply1", "table", "tagged", "task", "this", "throughout", "time", "timeprecision", "timeunit", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand", "trior", "trireg", "type", "typedef", "union", "unique", "unsigned", "use", "var", "vectored", "virtual", "void", "wait", "wait_order", "wand",
"weak0", "weak1", "while", "wildcard", "wire", "with", "within", "wor", "xnor", "xor". Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test(); wire d,g,int; parameter alias = 1; modport new(d,g); endmodule module modport(d,g); input d; wire d; output g; reg g; always g = d; endmodule
nLint reports: document.v(2): Warning 24005: SystemVerilog reserved identifier in a Verilog design. (HDL Translation) document.v(3): Warning 24005: SystemVerilog reserved identifier in a Verilog design. (HDL Translation) document.v(4): Warning 24005: SystemVerilog reserved identifier in a Verilog design. (HDL Translation) document.v(7): Warning 24005: SystemVerilog reserved identifier in a Verilog design. (HDL Translation)
word "int" is used as an word "alias" is used as an word "new" is used as an word "modport" is used as an
24007 (Verilog) Signal Names Distinguished Only by Letter Case

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: naming for "%s" and "%s"(at line %d) is only distinguished by letter case. Configurable Parameter Rule group: HDL Translation, Naming Convention; Argument type: (CHECK_ALL,CHECK_SAME_TYPE_ONLY); Argument description: select CHECK_SAME_TYPE_ONLY to specify that the checking of rule 24007 is limited to the same type of objects. All objects are classified into three types: scope, signal and instance. The scope type includes: UDP, module, interface, block, task and void function; the signal type includes: port, modport, parameter, signal, variable, type declaration, event and non-void function; the instance type includes: module instance, gate instance, UDP instance and interface instance. Select CHECK_ALL to specify any two objects violating rule 24007 if their names are only differentiated by letter case regardless of their types; Default value: "CHECK_ALL" for Verilog; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether the names of different objects are only distinguished by letter cases (e.g. out and Out). This kind of naming could cause problems when languages or tools are case insensitive. Please note that the scopes of the objects are also considered when the rule is checked. If two objects are distinguished only by letter case and the scope of one object covers that of the other's, this rule will report violation on these two objects. The scopes could be modules, struct/union/enum, tasks/functions or blocks. But for a sub element of struct/union/enum, it never conflicts with other objects outside struct/union/enum. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 module m1(); typedef struct{ logic VAlid; logic Valid; }STU_TYP; logic VALID, valid; endmodule
nLint reports following document.sv(4): Warning distinguished by letter document.sv(6): Warning distinguished by letter
if the argument value is ("CHECK_ALL"): 24007: naming for "Valid" and "VAlid"(at line 3) is only case. (HDL Translation) 24007: naming for "valid" and "VALID"(at line 6) is only case. (HDL Translation)
///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test; reg VALID; function f_myfunc; input a; begin reg Valid; end endfunction always begin:b1 reg VAlid; end Test u_Test(); Test u_TEST(); //warning
14 15 16
endmodule module Test(); endmodule
nLint reports following if the argument value is ("CHECK_ALL"): document.v(1): Warning 24007: naming for "test" and "Test"(at line 15) is only distinguished by letter case. (HDL Translation) document.v(10): Warning 24007: naming for "VAlid" and "VALID"(at line 2) is only distinguished by letter case. (HDL Translation) document.v(13): Warning 24007: naming for "u_TEST" and "u_Test"(at line 12) is only distinguished by letter case. (HDL Translation) ///////////////example : document1.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module top(); wire a; //No warning if select argument "CHECK_SAME_TYPE_ONLY" sub A(); wire b; reg B; sub sub C(); c(); //Warning
//Warning
always begin : Top //Warning end endmodule module sub(); endmodule module TOP(); endmodule //Warning
nLint reports following if the argument value is ( CHECK_SAME_TYPE_ONLY): document1.sv(6): Warning 24007: naming for "B" and "b"(at line 5) is only distinguished by letter case. (HDL Translation) document1.sv(9): Warning 24007: naming for "c" and "C"(at line 8) is only distinguished by letter case. (HDL Translation) document1.sv(11): Warning 24007: naming for "Top" and "top"(at line 1) is only distinguished by letter case. (HDL Translation) document1.sv(18): Warning 24007: naming for "TOP" and "top"(at line 1) is only distinguished by letter case. (HDL Translation)
24009 Objects with Same Name of Object in Outer Scope

Message <filename>(<line no.>): <severity> <rule no.>: object "%s" should not share the same name with another object in the outer scope (at line %d). Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any objects sharing the same name with objects in the outer scope. Outer scope means the parent name scope. Object names in the outer scope are visible to objects in the current scope. If two objects belong to two scopes without parent-child relationship, the names of the two objects are invisible to each other and no violation is reported. For example, 1 module test(); 2 reg a; 3 4 always begin 5 reg a; //24009 fires here with line 2 6 end 7 endmodule In the above case, the register in line 2 shares the same name "a" with the register in line 5. Since the former has the parent name scope "test" and the later has the child name scope of an unnamed always block, the former register's name is visible to the later. Therefore, a violation is reported on line 5 with line 2. Another example is the field name of a structure or union: 1 module test(); 2 struct { logic a; } stru1; 3 struct { logic a; } stru2; 4 endmodule In this case, the two fields of variable "stru1" and "stru2" share the same name "a". However, fields of structures or unions have their own name scope. The field in line 2 has its name scope "stru1" and the field in line 3 has its name scope "stru2". Since both fields are invisible to each other, no violation should be reported. Checking on interface declarations is filtered out. For example, if a port of a function is declared with the same name as its connected signal, there is no violation because it is common to give the same name for a port and its connected signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test (sel,a,b,c,y); input sel; input [7:0] a,b,c; output [7:0] y; reg [7:0] y; //"y" in scope "block1"
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
reg [7:0] temp; always @( sel or a or b or c) begin: testb reg [7:0] y; //"y" in scope "testb", //duplicate with up-scope, warning temp = 0; if ( sel ) temp = b; else temp = c; y = a+temp; end endmodule
nLint reports: document.v(10): Warning 24009: object "y" should not share the same name with another object in the outer scope (at line 5). (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end entity top_ety; architecture arch of top_ety is shared variable v : integer; begin process is variable v : integer; --warning on "v" which is named --the same with "arch.v" begin wait; end process; end architecture arch;
nLint reports: document.vhd(8): Warning 24009: object "v" should not share the same name with another object in the outer scope (at line 5). (Coding Style)
24011 (Verilog) Include Compiler Directive Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: ìnclude compiler directive should not be used. Configurable Parameter Rule group: HDL Translation, Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any ìnclude used. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ìnclude "test.i"; //"ìnclude" directive unrecommended, warning module inival; reg a,b; wire c; initial begin $monitor($time,,,"a=%d, b=%d, c=%d",a,b,c); a=1; b=0; #10 a = 0; #10 a = 1; #10 b = 1; end test u_test(c, a, b); endmodule
nLint reports: document.v(1): Warning 24011: ìnclude compiler directive should not be used. (Language Construct,HDL Translation)
24013 (Verilog) Conditional Compiler Directive Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: "%s" conditional compiler directive should not be used. Configurable Parameter Rule group: HDL Translation, Language Construct; Argument type: (IFDEF,IFNDEF); Argument description: this is multiple selection argument; specify the type of the conditional compiler directive to be checked; Default value: "IFDEF,IFNDEF" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any specified conditional compiler directive used. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; ìfdef BYPASS_VLD_FIFO //"ìfdef" directive unrecommended, warning FLAG_BBE = FLAG_BBE_0 ; èlse //FLAG_BBE = DIS_VLD | FLAG_BBE_0 ; èndif endmodule
nLint reports following if the argument value is ("IFDEF,IFNDEF"): document.v(2): Warning 24013: "ìfdef" conditional compiler directive should not be used. (Language Construct,HDL Translation)
24015 Unknown Directive

Message <filename>(<line no.>): <severity> <rule no.>: unknown %s directive "%s" should not be used. Configurable Parameter Rule group: Language Construct; Argument type: LIST_ARG; Argument description: specify a string of several set of directives. Each set of directives are separated with semicolon. In a set of directives, the first word means <directive_comment_head>, and the remaining are <directives>. Each directive are separated with comma; Default value: "synopsys,translate_off,translate_on,parallel_case,full_case,state_vector,enum,template,dc_script_ begin, dc_script_end,map_to_module,return_port_name,sync_set_reset,async_set_reset,async_set_reset_l ocal,sync_set_reset_local, async_set_reset_local_all,sync_set_reset_local_all,one_hot,one_cold" for Verilog, "synopsys,translate_off,translate_on,parallel_case,full_case,state_vector,enum,template,dc_script_ begin, dc_script_end,map_to_module,return_port_name,sync_set_reset,async_set_reset,async_set_reset_l ocal,sync_set_reset_local, async_set_reset_local_all,sync_set_reset_local_all,one_hot,one_cold" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any unknown directive, which is not listed in the argument. Example
(Verilog) ///////////////example : document.v//////////// 1 2 module test(); // synopsys aaa endmodule warning here
nLint reports following if the argument value is ("synopsys,translate_off,translate_on,parallel_case,full_case,state_vector,enum,te mplate,dc_script_begin, dc_script_end,map_to_module,return_port_name,sync_set_reset,async_set_reset,async_ set_reset_local,sync_set_reset_local, async_set_reset_local_all,sync_set_reset_local_all,one_hot,one_cold"): document.v(1): Warning 24015: unknown synopsys directive "// synopsys aaa warning here" should not be used. (Language Construct)
(VHDL) -------------------example : document.vhd------------1 2 entity top_ety is --synopsys aaa end top_ety;
nLint reports following if the argument value is ("synopsys,translate_off,translate_on,parallel_case,full_case,state_vector,enum,te mplate,dc_script_begin, dc_script_end,map_to_module,return_port_name,sync_set_reset,async_set_reset,async_ set_reset_local,sync_set_reset_local, async_set_reset_local_all,sync_set_reset_local_all,one_hot,one_cold"): document.vhd(1): Warning 24015: unknown synopsys directive "--synopsys aaa" should not be used. (Language Construct)
24017 (Verilog) Synopsys Template Directive should be Used Before Parameter

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: synopsys template directive should be used before parameter "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there is synopsys template directive being used before parameter. Please reference the manual from Synopsys for detail information about the usage of the compiler directive. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test(); //synopsys template parameter w = 8; reg signal; parameter y = 4; //warning here, //there is no synopsys template comment endmodule
nLint reports: document.v(5): Warning 24017: synopsys template directive should be used before parameter "y". (Synthesis)
24019 'dc_shell' Commands Detected

Message <filename>(<line no.>): <severity> <rule no.>: dc_shell commands "%s" should not be used. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any dc_shell commands embedded in source code. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; // synopsys dc_script_begin // set_dont_touch find(cell) // set_dont_touch find(net) // synopsys dc_script_end endmodule // warning on the two lines between "scrip_begin" and "script_end"
nLint reports: document.v(3): Warning 24019: should not be used. (Language document.v(4): Warning 24019: should not be used. (Language
dc_shell commands "// Construct) dc_shell commands "// Construct)
set_dont_touch find(cell)" set_dont_touch find(net)"
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety is begin -- synopsys dc_script_begin -- set_dont_touch find(cell) -- set_dont_touch find(net) -- synopsys dc_script_end end arch; -- warning on the two lines between "scrip_begin" and "script_end"
nLint reports: document.vhd(7): Warning 24019: dc_shell commands "-should not be used. (Language Construct) document.vhd(8): Warning 24019: dc_shell commands "-should not be used. (Language Construct)
set_dont_touch find(cell)" set_dont_touch find(net)"
24021 (Verilog) Define Statements should be Put into One File

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: define statements should be put into one file. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether all the define statements are put into one file. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 --file1 `define bytesize 1 `define var_nand(dly) nand #dly --file2 `define wordsize 8 module a; endmodule
//warning here
25001 Signal with No Driver

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" has no driver. Configurable Parameter Rule group: Design Style, DFT; Argument type: (CHECK_PART_SEL,IGNORE_INITIALVALUE,CHECK_THROUGH_HIERARCHY); Argument description: The argument sets some variations for checking. Select CHECK_PART_SEL to check whether each individual bit of a bus signal has a driver or not. If not, a violation will be reported. Select CHECK_TOP_SIGNAL to check for signals located in the top module of the design without a driver. If a signal in a VHDL design has an initial value in the declaration but has no driver, select IGNORE_INITIALVALUE to report the violation. Select CHECK_THROUGH_HIERARCHY to check whether the driver crosses module boundaries. Select CHECK_NOT_THROUGH_ASSIGNMENT to check whether an assignment will be a driver or not; Default value: "CHECK_PART_SEL,IGNORE_INITIALVALUE,CHECK_TOP_SIGNAL" for Verilog, "CHECK_PART_SEL,IGNORE_INITIALVALUE,CHECK_TOP_SIGNAL" for VHDL; Default severity : Level3 (Error) Description This rule checks whether there are any signals without a driver. Note that non-synthesizable constructs will not be regarded as a driver, such as an initial block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (c, a, b); input [1:0] a, b; output [1:0] c; reg [1:0] c; wire[1:0] e; //warning wire d; assign d = 0; always @(a or b or e) c = a + b + e; endmodule
nLint reports following if the argument value is ("CHECK_PART_SEL,IGNORE_INITIALVALUE,CHECK_TOP_SIGNAL"): document.v(5): Error 25001: signal "e" has no driver. (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is signal x : bit; --warning on "x", which has never been driven signal y : bit; begin process (x) begin y<=x; end process; end arch;
nLint reports following if the argument value is ("CHECK_PART_SEL,IGNORE_INITIALVALUE,CHECK_TOP_SIGNAL"):
document.vhd(5): Error 25001: signal "x" has no driver. (DFT,Design Style)
25003 Signal with No Load

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" has no load. Configurable Parameter Rule group: Design Style, DFT; Argument type: (CHECK_PART_SEL,CHECK_TOP_SIGNAL,CHECK_THROUGH_HIERARCHY); Argument description: The argument sets some variations for checking. Select CHECK_PART_SEL to check whether each individual bit of a bus signal has a load or not. If not, a violation will be reported. Select CHECK_TOP_SIGNAL to check for signals located in the top module of the design without a load. Select CHECK_THROUGH_HIERARCHY to check whether the load crosses module boundaries. Select CHECK_NOT_THROUGH_ASSIGNMENT to check whether an assignment will be a load or not; Default value: "CHECK_TOP_SIGNAL,CHECK_THROUGH_HIERARCHY" for Verilog, "CHECK_TOP_SIGNAL,CHECK_THROUGH_HIERARCHY" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether there are any signals without a load. Note that non-synthesizable constructs will not be regarded as a load, such as initial block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (c, a, b); input [1:0] a, b; output [1:0] c; reg [1:0] c; wire e; //warning wire d; //warning assign e = 1; assign d = 0; always @(a or b) c = a + b; endmodule
nLint reports following if the argument value is ("CHECK_TOP_SIGNAL,CHECK_THROUGH_HIERARCHY"): document.v(5): Warning 25003: signal "e" has no load. (DFT,Design Style) document.v(6): Warning 25003: signal "d" has no load. (DFT,Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end entity top_ety; architecture arch of top_ety is signal x : bit; signal y : bit; --warning on "y", which has no load begin process ( x ) is begin y<=x; end process; end architecture arch;
nLint reports following if the argument value is ("CHECK_TOP_SIGNAL,CHECK_THROUGH_HIERARCHY"): document.vhd(5): Warning 25003: signal "x" has no load. (DFT,Design Style)
25005 (Verilog) Signal has Never been Assigned or Referenced

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" has never been %s. Configurable Parameter Rule group: Design Style; Argument type: (ASSIGN, REFERENCE, BOTH); Argument description: choose ASSIGN to check whether a signal has been assigned, choose REFERENCE to check whether a signal has been referenced, choose BOTH to check both cases; Default value: "BOTH" for Verilog; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any signal that has never been assigned or referenced. When a signal is assigned, which means that it is assigned a value in situations : continuous assignment statement; assignment statement in initial or always block; it is connected to an input or inout port of this module; and connected to an output or inout port of instance in this module. When a signal is referenced, which means that it is referenced in situations : in the right-hand side of continuous assignment statement; in the right-hand side of assignment in initial or always block; it is referenced in any index or range selection expression; or referenced in any condition expression; it is connected to an output or inout port of this module; or connected to an input or inout port of instance in this module. If there is no initial and always block in this module, this rule will not be checked. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; wire a, b, c; assign a=b; assign b=c; endmodule //"a" has never been referenced, warning //"c" has never been assigned, warning
nLint reports following if the argument value is ("BOTH"): document.v(2): Error 25005: signal "a" has never been referenced. (Design Style) document.v(2): Error 25005: signal "c" has never been assigned. (Design Style)
25007 (Verilog) Signal has been Assigned in More than One Block
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" has been assigned in more than one block. Configurable Parameter Rule group: Design Style; Argument type: (TRI, TRI1, TRI0, TRIAND, TRIOR, TRIREG); Argument description: select TRI to specify that multiple assignment to a tri net is allowed; select TRI1 to specify that multiple assignment to a tri1 net is allowed; select TRI0 to specify that multiple assignment to a tri0 net is allowed; select TRIAND to specify that multiple assignment to a triand net is allowed; select TRIOR to specify that multiple assignment to a trior net is allowed; select TRIREG to specify that multiple assignment to a trireg net is allowed; Default value: "" for Verilog; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether any signals are assigned in more than one block. "Assign" means a signal is assigned a value in one of the following situations: through a continuous assignment; through a procedural assignment in an initial or always block; by connection to an input port of this module; or by connection to an output port of an instance in this module. If a signal is connected to an inout port of this module and is assigned once using any of the above situations, this rule is not violated; if a signal is connected to an inout port of an instance in this module and is assigned once using any of the above situations, this rule is violated. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test; reg a, b, c; initial begin a=b; end initial begin a=c; //"a" has been assigned in more than one block, warning end endmodule
nLint reports following if the argument value is (""): document.v(2): Error 25007: signal "a" has been assigned in more than one block. (Design Style) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 /* rule 25007 */ module test(); tri1 bus; wire en1, en2, sig1, sig2; bus = en1 ? sig1 : 1'bz; bus = en2 ? sig2 : 1'bz;
assign (strong0,highz1) assign (strong0,highz1) if arg "TRI1" is specified 10 11 endmodule
//no warning on "bus"
nLint reports following if the argument value is ("TRI1"): ///////////////example : document2.v//////////// 1 module top(GND); 2 inout GND; 3 assign GND = 0; changed its value 4 endmodule
//no warning since GND is "inout" which means it can be
nLint reports following if the argument value is (""): ///////////////example : document3.v//////////// 1 module top; 2 wire GND; 3 assign GND = 0; 4 sub U_sub_1 (.GND(GND)); "inout" port instance 5 "U_sub_1" 6 endmodule 7 8 module sub (GND); 9 inout GND; 10 assign GND = 0; 11 endmodule
//warning because GND is connected to an //and maybe changed its value in instance
nLint reports following if the argument value is (""): document3.v(2): Error 25007: signal "GND" has been assigned in more than one block. (Design Style)
25009 Signal with Heavy Fan-out Loading

Message <filename>(<line no.>): <severity> <rule no.>: the fan-out number of signal "%s" is %d whereas the limitation is %d. Configurable Parameter Rule group: Design Style; Argument type: integer, (CLOCK, RESET, SET, LATCH_ENABLE, TRI_ENABLE); Argument description: The first argument is used to specify the maximum number of fan-outa that a signal can connect to. The second argument is used to ignore the checking for some special types of signals, such as clock (CLOCK), reset (RESET), set (SET), and enable signals of latches (LATCH_ENABLE) and tri-state buffers (TRI_ENALBE); Default value: "10","CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE, SCAN_ENABLE" for Verilog, "10","CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE, SCAN_ENABLE" for VHDL; Default severity : Level2 (Warning) Description This rule checks whether the fan-out of a signal exceeds the pre-defined number. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (d, y); input d; //warning if the first arguemnt is 5 output y; wire s1, s2, s3, s4, s5, s6; assign assign assign assign assign assign s1 s2 s3 s4 s5 s6 = = = = = = ~d; ~d; ~d; ~d; ~d; ~d;
assign y = s1 & s2 & s3 | s4 | s5 | s6; endmodule
nLint reports following if the argument value is ("5","CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE" ): document.v(2): Warning 25009: the fan-out number of signal "d" is 6 whereas the limitation is 5. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port (reset : in bit; clk : in bit; d: in bit; q: out bit); end top_ety; architecture arch of top_ety is signal s1,s2,s3,s4,s5 : bit; signal s: bit; -- warning here, FanOut=4 begin p1: process (reset,clk) is begin if (reset='1') then
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s<='0'; elsif (clk'event and clk='1') then s<=d; end if; end process p1; p2: process(s) is begin s1<=s; s2<=s; s3<=s; s4<=s; s5<=s; q<=s1 and s2 and s3 and s4 and s5; end process p2; end arch;
nLint reports following if the argument value is ("4","CLOCK,RESET,SET,LATCH_ENABLE,TRI_ENABLE" ): document.vhd(10): Warning 25009: the fan-out number of signal "s" is 5 whereas the limitation is 4. (Design Style)
25011 Input with Heavy Transitive Fan Out of End Points

Message <filename>(<line no.>): <severity> <rule no.>: %d end points detected in the transitive fan out of input "%s", which should not exceed %d. Configurable Parameter Rule group: Design Style; Argument type: integer; Argument description: the integer number is the maximum fan out number allowable; Default value: "10" for Verilog, "10" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any input with heavy transitive fan out of end points. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (a,clk, r1, r2, r3, r4); input a, clk; output r1, r2, r3, r4; wire a, clk; reg r1, r2, r3, r4; always @(posedge clk) r1=a; always @(posedge clk) r2=a; always @(posedge clk) r3=a; always @(posedge clk) r4=a; endmodule //if set arg_val = 3
nLint reports following if the argument value is ("3"): document.v(4): Warning 25011: 4 end points detected in the transitive fan out of input "a", which should not exceed 3. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library ieee; use ieee.std_logic_1164.all; entity top_ety is port (clk, a : in std_logic; r1, r2, r3, r4 : out std_logic); end top_ety; architecture arch of top_ety is begin Process (clk) begin if (clk'event and clk = '1') then r1 <= a; end if; end Process; Process (clk)
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begin if (clk'event and clk = '1') then r2 <= a; end if; end Process; Process (clk) begin if (clk'event and clk = '1') then r3 <= a; end if; end Process; Process (clk) begin if (clk'event and clk = '1') then r4 <= a; end if; end Process; end arch;
nLint reports following if the argument value is ("3"): document.vhd(5): Warning 25011: 4 end points detected in the transitive fan out of input "a", which should not exceed 3. (Design Style)
25013 Output with Heavy Transitive Fan In of Start Points

Message <filename>(<line no.>): <severity> <rule no.>: %d start points detected in the transitive fan in of output "%s", which should not exceed %d. Configurable Parameter Rule group: Design Style; Argument type: integer; Argument description: the integer number is the maximum fan in number allowable; Default value: "10" for Verilog, "10" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any output with heavy transitive fan in of start points. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test (a,clk, r1, r2, r3, r4, out); input a, clk; output r1, r2, r3, r4, out; wire a, clk, out; reg r1, r2, r3, r4; always @(posedge clk) r1=a; always @(posedge clk) r2=a; always @(posedge clk) r3=a; always @(posedge clk) r4=a; assign out=r1 & r2 &r3 &r4; endmodule // if set arg_val=3
nLint reports following if the argument value is ("3"): document.v(4): Warning 25013: 4 start points detected in the transitive fan in of output "out", which should not exceed 3. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 library ieee; use ieee.std_logic_1164.all; entity top_ety is port (clk, a : in std_logic; r1, r2, r3, r4, o : inout std_logic); end top_ety; architecture arch of top_ety is begin Process (clk) begin if (clk'event and clk = '1') then r1 <= a; end if; end Process;
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Process (clk) begin if (clk'event and clk = '1') then r2 <= a; end if; end Process; Process (clk) begin if (clk'event and clk = '1') then r3 <= a; end if; end Process; Process (clk) begin if (clk'event and clk = '1') then r4 <= a; end if; end Process; o <= r1 and r2 and r3 and r4; end arch;
nLint reports following if the argument value is ("3"): document.vhd(6): Warning 25013: 4 start points detected in the transitive fan in of output "o", which should not exceed 3. (Design Style)
25014 (Verilog) Input Signal Not Driven by Flip-Flop

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the input signal "%s" is not connected to register out directly. Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) It's impossible to ask designers to do register out for each module, it's only reasonable to do so for some critial paths. When checking this rule, user need specify which module or instance should be checked. If user specify a module, nLint will check all the instance of this module. For each instance, nLint will trace the drivers of its inputs. If the driver signal is not connected to register out directly, nLint will report violation. If no module or instance is specified, nLint will not check. Example
(Verilog)
25015 Outputs Leaving Partition without been Driven by Register

Message <filename>(<line no.>): <severity> <rule no.>: the output "%s" is not registered. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any output leaving partition without been driven by register. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (a,clk, r1, r2, r3, r4, out1, out2); input a, clk; output r1, r2, r3, r4, out1, out2; wire a, clk; reg r1, r2, r3, r4; always @(posedge r1=a; always @(posedge r2=a; always @(posedge r3=a; always @(posedge r4=a; clk) clk) clk) clk)
assign out1=r1 & r2 &r3 & 44; assign out2=a; endmodule
nLint reports: document.v(1): Warning 25015: the output "out2" is not registered. (Design Style) document.v(1): Warning 25015: the output "out1" is not registered. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 library ieee; use ieee.std_logic_1164.all; entity top_ety is port (clk, a : in std_logic; r1, r2, r3, r4, out1, out2 : inout std_logic); end top_ety; architecture arch of top_ety is begin Process (clk) begin if (clk'event and clk = '1') then r1 <= a; end if; end Process; Process (clk) begin if (clk'event and clk = '1') then
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r2 <= a; end if; end Process; Process (clk) begin if (clk'event and clk = '1') then r3 <= a; end if; end Process; Process (clk) begin if (clk'event and clk = '1') then r4 <= a; end if; end Process; out1 <= r1 and r2 and r3 and r4; out2 <= a; end arch;
nLint reports: document.vhd(6): Warning 25015: the output "out2" is not registered. (Design Style) document.vhd(6): Warning 25015: the output "out1" is not registered. (Design Style)
25016 A Combinational Path between PI and PO without Being Registered

Message <filename>(<line no.>): <severity> <rule no.>: direct path from primary input pin "%s" to primary output pin "%s" (%s(%d)) without flip-flops is not allowed. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is a combinational path between PI and PO without being registered. It is determined by the option of 22011 for either the latch is treated as synchronous or asynchronous. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (a, b, c, k); //warning on "c" and a, b, k input a; input b; output c; input [2:0] k; wire c; assign c = a & b & k[0]; endmodule
nLint reports: document.v(1): Warning 25016: direct path from primary input pin "k[0]" to primary output pin "c" (document.v(1)) without flip-flops is not allowed. (Design Style) document.v(1): Warning 25016: direct path from primary input pin "b" to primary output pin "c" (document.v(1)) without flip-flops is not allowed. (Design Style) document.v(1): Warning 25016: direct path from primary input pin "a" to primary output pin "c" (document.v(1)) without flip-flops is not allowed. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is port ( x1, x2 : in integer; --warning on "y" and "x1", "x2" y : out integer); end entity top_ety; architecture arch of top_ety is begin y<=x1+x2; end architecture arch;
nLint reports: document.vhd(2): Warning 25016: direct path from primary output pin "y" (document.vhd(3)) without flip-flops is document.vhd(2): Warning 25016: direct path from primary output pin "y" (document.vhd(3)) without flip-flops is
input pin "x2" to primary not allowed. (Design Style) input pin "x1" to primary not allowed. (Design Style)
25017 (Verilog) Duplicated Names Detected in Ports

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: duplicated name "%s" detected on port "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is duplicated names in ports. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test(a, b, a, c, k, .A({a, k[0]})); //warning on "a" and "k" input a; input b; output c; input [2:0] k; wire c; assign c = a & b & k; endmodule
nLint reports: document.v(1): Warning 25017: duplicated name "k" detected on port "A". (Design Style) document.v(1): Warning 25017: duplicated name "a" detected on port "A". (Design Style)
25019 (Verilog) Set Sync/Ignore Pin Attribute on Output

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: sync/ignore pin attribute should not be set on output "%s". Configurable Parameter Rule group: CTS; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any sync/ignore pin attributes set on output signals. The pin attributes has to be set on input ports. Note that input pins of hierarchy instance is not allowed, only input pins of primitive instances are allowed. Related command line option: -cts: specify the pin attribut file name -cts_spt: specify the seperator character between each hirachy instance name -cts_top: specify the user-defined top for CTS rules Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 module top(clk1,clk2,dout1,dout2,dout3); input clk1,clk2; output dout1,dout2,dout3; sub1 u_sub1(.clk1a(clk1_i),.clk2a(clk2),.dout1(dout1),.dout2(dout2)); IV U1(.A(clk1),.Z(clk1_i)); FD2 U2(.CP(clk2),.Q(dout3)); IV U3(.A(clk2),.Z()); //warning here endmodule module sub1(clk1a,clk2a,dout1,dout2); input clk1a,clk2a; output dout1,dout2; IV U4(.A(clk1a),.Z(n1)); FD2 U5(.CP(n1),.Q(dout1)); MUX21H U6(.A(clk1a),.B(clk2a),.Z(n3)); FD2 U7(.CP(n3),.Q(dout2)); //warning here endmodule
cts attributes for the example: dbDefineSyncPin (geGetEditCell) "U2" '(("CP" "nonInvertRise" 0)) dbDefineSyncPin (geGetEditCell) "u_sub1/U5" '(("CP" "InvertRise" 0)) dbDefineSyncPin (geGetEditCell) "u_sub1/U7" '(("Q" "InvertRise" 0)) //issue violation dbDefineIgnorePin (geGetEditCell) "U3" '("Z") //issue violation dbDefineIgnorePin (geGetEditCell) "u_sub1/U6" '("B")
nLint reports: document.v(9): Warning 25019: sync/ignore pin attribute should not be set on output "top.NULL". (CTS) document.v(19): Warning 25019: sync/ignore pin attribute should not be set on output "top.u_sub1.dout2". (CTS)
25021 (Verilog) CTS "ignore pin" Attribute Set for All Fan-out Logics of an Instance
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: all the fan-out logic of instance "%s" is set as ignore pin attribute. Configurable Parameter Rule group: CTS; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether all the fan-out logic of an instance is set as ignore pin attribute. It is recommended to set ignore pin attribute to the inputs of the violated instance. The checking passes through hierarchies and assignments. The pin attribute can only be set on a primitive gate instance. It can not be set on a hierarchy instance. The related command line option are: -cts: specify the pin attribute file name. -cts_spt: specify the hierarchy delimiter "." or "/". -cts_top: specify the user-defined top for CTS rules. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test; wire a,b,c,d,e,f,g,h,i,j,k,l,m; IV U1(.A(a),.Z(b)); FD2 U2(.CP(b), .D(), .Q(c), .QN()); FD2 U3(.CP(d), .D(), .Q(e), .QN(f)); FD2 U4(.CP(e), .D(), .Q(g), .QN()); FD2 U5(.CP(f), .D(), .Q(h), .QN()); FD2 U6(.CP(), .D(i), .Q(j), .QN(k)); FD2 U7(.CP(), .D(j), .Q(l), .QN()); FD2 U8(.CP(), .D(k), .Q(m), .QN()); endmodule //warning here
//warning here
cts attributes for the example: dbDefineIgnorePin (geGetEditCell) dbDefineIgnorePin (geGetEditCell) dbDefineIgnorePin (geGetEditCell) dbDefineIgnorePin (geGetEditCell)
"U2" "U4" "U7" "U8"
'("CP") '("CP") '("D") '("D")
nLint reports: document.v(3): Warning 25021: all the fan-out logic of instance "test.U1" is set as ignore pin attribute. (CTS) document.v(10): Warning 25021: all the fan-out logic of instance "test.U6" is set as ignore pin attribute. (CTS)
26001 (Verilog) Too Many Words in Memory

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: no dimension in "%s" should be more than %d. Configurable Parameter Rule group: Language Construct; Argument type: integer; Argument description: specify the maximum words number of memory; Default value: "1024" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the memory length exceeds the 'length' bits. This rule is used to set the usage limitation of 2 dimension array of register. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test(c,a,b); reg [7:0] mem[0:4096]; input [1:0] a,b; output [1:0] c; reg [1:0] c; always @( a or b ) c = {a[1], b[0]}; endmodule
//warning here, memory length too large
nLint reports following if the argument value is ("1024"): document.v(2): Warning 26001: no dimension in "mem" should be more than 1024. (Language Construct)
26003 (Verilog) Matching Deassign Statement Not Found

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" is assigned but not deassigned. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any assign statement that has no corresponding deassign statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module testini; reg [1:0] a, b, temp; wire [1:0] c; initial begin a = 2'b01; b = 2'b11; #50 a <= ~a; assign temp = a & b; //"temp" is assigned but never been //deassigned, warning #100 $finish; end test u_test(c, a, b); endmodule module test (c, a, b); input a, b; output c; assign c = a & b; endmodule
nLint reports: document.v(10): Warning 26003: signal "temp" is assigned but not deassigned. (Language Construct)
26005 (Verilog) Supply Signal Assigned

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: supply type wire "%s" should not be assigned. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any supply type wire is assigned with a value. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test(c, a, b); input a, b; output [1:0] c; reg [1:0] c; supply1 vcc1, vcc2; //"vcc1, vcc2" is supply1 supply0 ground1, ground2; //"ground1, ground2" is supply0 assign vcc1 = 1; //supply1 "vcc1" assigned, warning assign ground1 = 0; //supply0 "ground1" assigned, warning always @(a) begin assign ground2 = a; //supply0 "ground2" assigned, warning assign vcc2 = !a; //supply1 "vcc2" assigned, warning end endmodule
nLint reports: document.v(8): Warning 26005: supply type wire "vcc1" should not be assigned. (Language Construct) document.v(9): Warning 26005: supply type wire "ground1" should not be assigned. (Language Construct) document.v(13): Warning 26005: supply type wire "ground2" should not be assigned. (Language Construct) document.v(14): Warning 26005: supply type wire "vcc2" should not be assigned. (Language Construct)
26007 (Verilog) Matching Assign Statement Not Found

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" is deassigned but not assigned. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any deassign statement that has no corresponding assign statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module testini; reg [1:0] a, b, temp; wire [1:0] c; initial begin a = 2'b01; b = 2'b11; #50 a <= ~a; deassign temp; //"temp" is deassigned but never been assigned, //warning #100 $finish; end test u_test(c, a, b); endmodule module test (c, a, b); input a, b; output c; assign c = a & b; endmodule
nLint reports: document.v(10): Warning 26007: signal "temp" is deassigned but not assigned. (Language Construct)
26009 (Verilog) Event Type Tested by Posedge or Negedge

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: event type "%s" should not be used with posedge or negedge. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule check whether there is any event variable used in an edge-testing function. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module test (rst, clk, din, qout); input clk, rst; input din; output qout; reg qout; event e; always @(posedge (clk | e)) //warning here //event "e" used in edge expression if (!rst) qout <= 0; else qout <= din; always @(posedge e) //warning here //event "e" used in edge expression if (rst) qout <= 1; endmodule
nLint reports: document.v(8): Error 26009: event type "e" should not be used with posedge or negedge. (Language Construct) document.v(15): Error 26009: event type "e" should not be used with posedge or negedge. (Language Construct)
26011 (Verilog) Matching Release Statement Not Found

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" is forced but not released. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any force statement that has no corresponding release statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module top; reg a, b, c, d; wire e; initial begin assign d = a & b & c; a = 1; b = 0; c = 1; #10; force d = (a | b | c); //"d" is forced but never been //released, warning force e = (a | b | c); //"e" is forced but never been //released, warning #10 $finish; end test u_test_0(e, a, b, c); endmodule module test (e,a,b,c); output e; input a,b,c; wire e; and and1(e,a,b,c); endmodule
nLint reports: document.v(12): Warning 26011: signal "d" is forced but not released. (Language Construct) document.v(14): Warning 26011: signal "e" is forced but not released. (Language Construct)
26013 (Verilog) Matching Force Statement Not Found

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" is released but not forced. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any release statement that has no corresponding force statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module top; reg a, b, c, d; wire e; initial begin assign d = a & b & c; a = 1; b = 0; c = 1; #10; release d; //"d" is released but never been forced, warning release e; //"e" is released but never been forced, warning #10 $finish; end test u_test_0(e, a, b, c); endmodule module test (e,a,b,c); output e; input a,b,c; wire e; and and1(e,a,b,c); endmodule
nLint reports: document.v(12): Warning 26013: signal "d" is released but not forced. (Language Construct) document.v(13): Warning 26013: signal "e" is released but not forced. (Language Construct)
26015 (Verilog) Too Many Bits in Memory

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: total bits in "%s" should be less than %d. Configurable Parameter Rule group: Language Construct; Argument type: integer; Argument description: specify the maximum bits number of memory; Default value: "8096" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the memory bits length exceeds the 'length' bits. Some companies or some tools, like cycle simulator, may have this limitation. If no limitation, just disable it. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test(c,a,b); reg [7:0] mem[0:4096]; //warning here, memory length bits too large input [1:0] a,b; output [1:0] c; reg [1:0] c; always @( a or b ) c = {a[1], b[0]}; endmodule
nLint reports following if the argument value is ("8096"): document.v(2): Warning 26015: total bits in "mem" should be less than 8096. (Language Construct)
27001 (VHDL) Keywords Not Kept in the Same Line

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: keywords "%s" and "%s" should be kept in the same line. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the keywords are not kept together. The following groups of keywords are recommended to be written in one line: "package body", "generic map", "port map", "end entity", "end architecture", "end configuration", "end procedure", "end function", "end package", "end package body", "end component", "end if", "end case", "end for", "end loop", "end block", "end process", "end generate", "end record", "end units" Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 library ieee; use ieee.std_logic_1164.all; entity rom is port ( addr : in std_logic_vector(5 downto 0); dout : out std_logic_vector(7 downto 0); addr_error : out std_logic); end rom; architecture arch of rom is begin end arch; library ieee; use ieee.std_logic_1164.all; use work.all; entity top_ety is port ( n_dout10 : in std_logic_vector(5 downto 0); n_dout3 : out std_logic_vector(7 downto 0) ); end top_ety; architecture arch of top_ety is component rom is port ( addr : in std_logic_vector(5 downto 0); dout : out std_logic_vector(7 downto 0); addr_error : out std_logic); end component; begin i_rom: rom port map ( -- warning here, "port map" should be kept together addr => n_dout10, dout => n_dout3, addr_error => open ); end arch;
nLint reports: document.vhd(35): Warning 27001: keywords "port" and "map" should be kept in the same line. (Coding Style)
27003 (Verilog) Event Control or Delay Statement Not Found in All Branches 27003 (VHDL) WAIT Statement Not Found in All Branches
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: event control statement or delay is lost in some possible branches of always, it may cause simulation time hangs. (VHDL) <filename>(<line no.>): <severity> <rule no.>: WAIT statement is lost in some possible branches of process, it may cause simulation time hangs. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether all the branches( complete ) have a control under event control statement or delay. (VHDL) This rule checks whether all the branches( complete ) have a control under WAIT statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (sel,a,b,s); input sel, a, b; output s; reg s; always begin if ( sel == 0 ) begin s <= a; @( sel or a ); end else //warning here, there is no event control //statement in this branch s <= b; end endmodule
nLint reports: document.v(6): Warning 27003: event control statement or delay is lost in some possible branches of always, it may cause simulation time hangs. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is signal S : Bit; begin BadProcess_Lbl : process begin if S = '0' then
10 11 12 13 14 15 16
S <= '1'; wait for 10 ns; end if; -- Note : if S = '1' then process loops forever, -and time does not advance. end process BadProcess_Lbl; end arch;
nLint reports: document.vhd(7): Warning 27003: WAIT statement is lost in some possible branches of process, it may cause simulation time hangs. (Simulation)
27007 (VHDL) Keyword Case

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: keyword "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the keywords are all in lower (or upper) case. Example
(VHDL) -------------------example : document.vhd------------1 2 entity top_ety is END top_ety; --warning here: the keyword "END" should be in the lower case
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(2): Warning 27007: keyword "END" should be named in CASE_LOWER case. (Naming Convention)
27015 Unconventional File Extension

Message <filename>(<line no.>): <severity> <rule no.>: file extension "%s" should be named in "%s". Configurable Parameter Rule group: Naming Convention; Argument type: string; Argument description: The argument specify regular expression (for clarification, see Regular Expression Help in the end of Rule documentation); specify the preferred file extension names; use semicolon to separate multiple extension names; Default value: "v" for Verilog, "vhd" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the preferred file extension is used or not. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 //design project has three files // system.v (right) // cpu.verilog (wrong should be named as cpu.v) // alu.Veri (wrong should be named as alu.v)
(VHDL) -------------------example : document.vhd------------1 2 3 4 --design project has three files -- system.vhd (right) -- cpu.vhdl (wrong should be named as cpu.vhd) -- alu.Vhd (wrong should be named as alu.vhd)
27027 (VHDL) Pre-defined Identifier Redefined

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: identifier "%s" is predefined in the standard packages and should not be redefined. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there are any names have been defined in the pre-defined packages, such as standard; ieee or synopsys which are re-defined in the design. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is signal integer : bit; --warning on "integer" end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27027: identifier "integer" is predefined in the standard packages and should not be redefined. (Coding Style)
27028 User Reserved Words Redefined

Message <filename>(<line no.>): <severity> <rule no.>: identifier "%s" is a user reserved word and should not be redefined. Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: using regular expression (for clarification, see Regular Expression Help in the end of Rule documentation) to specify a string of reserved identifier(s), different regular expressions are separated by semicolon; Default value: "" for Verilog, "" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are user-reserved names which are redefined. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 //in rs file, regular expression is specified "GND[a-z]*; VSS[0-9]* module m1; wire VSS10; //warning here wire GND,GNDa; //warning here endmodule
nLint reports following if the argument value is ("GND[a-z]*; VSS[0-9]*"): document.v(3): Warning 27028: identifier "VSS10" is a user reserved word and should not be redefined. (Coding Style) document.v(4): Warning 27028: identifier "GNDa" is a user reserved word and should not be redefined. (Coding Style) document.v(4): Warning 27028: identifier "GND" is a user reserved word and should not be redefined. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture arch of top_ety is signal inte : bit; --warning here begin end arch;
nLint reports following if the argument value is ("inte"): document.vhd(5): Warning 27028: identifier "inte" is a user reserved word and should not be redefined. (Coding Style)
27029 (VHDL) Missing Entity Name in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: entity name "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any entity declaration having no entity name specified in the END statement Example
(VHDL) -------------------example : document.vhd------------1 2 entity top_ety is end; --warning here, the entity name "top_ety" should be specified here.
nLint reports: document.vhd(2): Warning 27029: entity name "top_ety" should be specified in the END statement. (Coding Style)
27031 (VHDL) Missing Architecture Name in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: architecture name "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any architecture declaration having no architecture name specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture arch of top_ety is begin end ; --warning here, the architecture name "arch" --should be specified here
nLint reports: document.vhd(6): Warning 27031: architecture name "arch" should be specified in the END statement. (Coding Style)
27033 (VHDL) Missing Configuration Name in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: configuration name "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any configuration declaration having no configuration name specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is begin end arch; configuration CONF_test of top_ety is for arch end for; end; --warning here, the configuration name "CONF_test" -- should be specified here!
nLint reports: document.vhd(11): Warning 27033: configuration name "CONF_test" should be specified in the END statement. (Coding Style)
27035 (VHDL) Missing Package Declaration Name in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: package name "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any package declaration having no package name specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 package PKG is end; --warning here, the package name "PKG" should be specified here entity top_ety is end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27035: package name "PKG" should be specified in the END statement. (Coding Style)
27037 (VHDL) Missing Package Name in the END Statement of Package Body
Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: package body name "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any package body having no package name specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 package PKG is end PKG; package body PKG is end; --warning here: the package body "PKG" should be specified here! entity top_ety is end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(5): Warning 27037: package body name "PKG" should be specified in the END statement. (Coding Style)
27039 (VHDL) Missing Sub-program Name in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: sub-program name "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any sub-program body having no sub-program name specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 entity top_ety is procedure Proc1 is begin end procedure; --warning here : the procedure name "Proc1" --should be specified here end entity top_ety;
nLint reports: document.vhd(4): Warning 27039: sub-program name "Proc1" should be specified in the END statement. (Coding Style)
27041 (VHDL) Missing Block Label in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: block label "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any block body having no block label specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is begin B1: block is begin end block; --warning here: the block label "B1" --should be specified here end arch;
nLint reports: document.vhd(8): Warning 27041: block label "B1" should be specified in the END statement. (Coding Style)
27043 (VHDL) Missing Process Label in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: process label "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any process body having no process label specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety is begin p1: process is begin wait; end process; --warning here: the process label "p1" --should be specified here end arch;
nLint reports: document.vhd(9): Warning 27043: process label "p1" should be specified in the END statement. (Coding Style)
27044 (VHDL) Missing Generate Statement Label in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: generate statement label "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any generate statement having no generate statement label specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is begin g1: for i in 1 to 100 generate end generate; --warning here: the generate label "g1" --should be specified here! end arch;
nLint reports: document.vhd(7): Warning 27044: generate statement label "g1" should be specified in the END statement. (Coding Style)
27045 (VHDL) Missing If Statement Label in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: if statement label "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any if statements having no if statement label specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end top_ety; architecture arch of top_ety is signal s : integer; begin p1 : process is begin l1: if s>0 then end if; --warning here: the if statement label "l1" --should be specified here wait; end process p1; end arch;
nLint reports: document.vhd(10): Warning 27045: if statement label "l1" should be specified in the END statement. (Coding Style)
27047 (VHDL) Missing Case Statement Label in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: case statement label "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any case statement having no case statement label specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is end top_ety; architecture arch of top_ety is signal s : bit; begin p1: process is begin l1 : case (s) is when '0' => s <= '1'; when others => s <= '0'; end case; --warning here : the case statement label "l1" --should be specified here. wait; end process p1; end arch;
nLint reports: document.vhd(12): Warning 27047: case statement label "l1" should be specified in the END statement. (Coding Style)
27049 (VHDL) Missing Loop Statement Label in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: loop statement label "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any loop statement having no loop statement label specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end top_ety; architecture arch of top_ety is signal s : bit; begin p1: process is begin l1 : for i in 1 to 100 loop end loop; --warning here: the loop statement "l1" --should be specified here. wait; end process p1; end arch;
nLint reports: document.vhd(10): Warning 27049: loop statement label "l1" should be specified in the END statement. (Coding Style)
27051 (VHDL) Missing Component Name in the END Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: component name "%s" should be specified in the END statement. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any component declaration having no component name specified in the END statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is component Com_T is end component; --warning here: the component name "com_T" --should be specified here begin end arch;
nLint reports: document.vhd(6): Warning 27051: component name "Com_T" should be specified in the END statement. (Coding Style)
27055 Too Many Lines in a Source File

Message <filename>(<line no.>): <severity> <rule no.>: the lines of a source file should not exceed %d lines. Configurable Parameter Rule group: Coding Style; Argument type: integer; Argument description: specify the maximum number of lines in a file; Default value: "1000" for Verilog, "1000" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are too many lines in one source file. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (q, clk, rst, d); input clk, rst; input d; output q; reg q; always @(posedge clk or negedge rst) if (~rst) q <= 1; else q <= d; endmodule //warning if the number of lines exceed the number of argument
nLint reports following if the argument value is ("10"): document.v(15): Warning 27055: the lines of a source file should not exceed 10 lines. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 library ieee; use ieee.std_logic_1164.all; entity top_ety is port ( Clk : in std_logic; Rst : in std_logic; Din : in std_logic; Qout : out std_logic ); end top_ety; architecture arch of top_ety is begin process (Rst, Clk) begin if (Rst = '1') then Qout <= '0'; elsif (Clk'event and Clk = '1') then Qout <= Din; end if; end process;
21 22 23
end arch; --warning if the number of lines exceed the number of argument
nLint reports following if the argument value is ("10" ): document.vhd(23): Warning 27055: the lines of a source file should not exceed 10 lines. (Coding Style)
27063 (VHDL) Name Case of Number Literal

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the number literal "%s" should use %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_UPPER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether any literals violate the specified letter case. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end; architecture arch of top_ety is constant c1 : real := 1.0e8; --warning here constant c2 : real := 2.0E5; -- no warning here begin end;
nLint reports following if the argument value is ("CASE_UPPER"): document.vhd(5): Warning 27063: the number literal "1.0e8" should use CASE_UPPER case. (Naming Convention)
27069 (VHDL) User-defined Logic Type and its Subtype Not Recommended
Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: type declaration "%s" should be removed. Use pre-defined standard logic type instead. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether type declarations are re-definition of pre-defined standard logic type. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is end; architecture arch of top_ety is type mystd_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); begin end;
nLint reports: document.vhd(6): Warning 27069: type declaration "mystd_ulogic" should be removed. Use pre-defined standard logic type instead. (Coding Style)
27071 (VHDL) Bit or Bit_vector Type Not Recommended

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: bit or bit_vector type should not be used object "%s". Use std_ulogic instead. Configurable Parameter Rule group: Simulation, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether bit or bit_vector is used. Example
(VHDL) -------------------example : document.vhd------------1 entity top_ety is 2 port (pin : in bit; --warning here 3 pout : out bit_vector( 3 downto 0 ) --warning here 4 ); 5 signal s1 : bit; --warning here, use std_ulogic instead. 6 end entity top_ety; 7 8 architecture arch of top_ety is 9 signal s2 : bit_vector(1 downto 0); --warning here, use std_ulogic instead. 10 begin 11 end architecture arch;
nLint reports: document.vhd(2): Warning 27071: bit or bit_vector type should "pin". Use std_ulogic instead. (Simulation,Coding Style) document.vhd(3): Warning 27071: bit or bit_vector type should "pout". Use std_ulogic instead. (Simulation,Coding Style) document.vhd(5): Warning 27071: bit or bit_vector type should "s1". Use std_ulogic instead. (Simulation,Coding Style) document.vhd(9): Warning 27071: bit or bit_vector type should "s2". Use std_ulogic instead. (Simulation,Coding Style)
not be used object not be used object not be used object not be used object
27077 (VHDL) Enumeration Literal Used in Range Specification

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: enumeration literal used in range "%s". Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is enumeration literal in range specification. Use attribute 'low or 'high instead. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is type color is ( black, white, red, green, blue ); type color_active is array ( black to blue ) of boolean; --warning on "black" and "blue". Use attribute --on color instead as following --type color_active is array ( color'low to color'high ) of boolean; end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(3): Warning 27077: enumeration literal used in range "black to blue". (Coding Style)
27081 (VHDL) 'std_ulogic_vector' Not Recommended

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: std_ulogic_vector on object "%s" should be replaced with SIGNED or UNSIGNED type. Configurable Parameter Rule group: Synthesis, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether std_ulogic_vector is used. Use SIGNED or UNSIGNED type instead. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; entity top_ety is port (p : in std_ulogic_vector( 7 downto 0)); --warning here end top_ety; architecture arch of top_ety is signal s1 : std_ulogic_vector( 7 downto 0); --warning here -- Use signed or unsigned instead of std_ulogic_vector signal s2 : unsigned(1 to 10); signal s3 : signed(1 to 10); begin end arch;
nLint reports: document.vhd(6): Warning 27081: std_ulogic_vector on object "p" should be replaced with SIGNED or UNSIGNED type. (Synthesis,Coding Style) document.vhd(10): Warning 27081: std_ulogic_vector on object "s1" should be replaced with SIGNED or UNSIGNED type. (Synthesis,Coding Style)
27083 (VHDL) Resolved/Unresolved Type Not Recommended

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the object "%s" should be declared as %s type. Configurable Parameter Rule group: Synthesis, Coding Style; Argument type: (RESOLVED, UNRESOLVED); Argument description: select RESOLVED to specify that resolved type should be used; select UNRESOLVED to specify that unresolved type should be used; Default value: "RESOLVED" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether any resolved(unresolved) type is used in object declaration. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port (p : in std_ulogic); --warning here: using std_logic instead --of std_ulogic. end top_ety; architecture arch of top_ety is signal s : std_ulogic; --warning here: using std_logic instead --of std_ulogic. begin end arch;
nLint reports following if the argument value is ("RESOLVED"): document.vhd(5): Warning 27083: the object "p" should be declared as RESOLVED type. (Synthesis,Coding Style) document.vhd(10): Warning 27083: the object "s" should be declared as RESOLVED type. (Synthesis,Coding Style)
27085 (VHDL) Constrained Range Used for Array Type

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: type "%s" is %s array type. Please use unconstrained range definition in type declarations, and constrained range definition in subtype declarations. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any constrained range in array type declaration. Use unconstrained range in array type declarations, and constrained range in subtype declarations. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is type array1 is array (8 downto 1) of bit; --warning here, do not use --the constrained array begin end arch;
nLint reports: document.vhd(5): Warning 27085: type "array1" is constrained array type. Please use unconstrained range definition in type declarations, and constrained range definition in subtype declarations. (Coding Style)
27093 (VHDL) NEXT Statement Used in Loop

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: Should not use NEXT statement in a loop statement(at line %d). Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether any NEXT statement is used in a loop statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is begin p1 : process is begin for i in 1 to 10 loop next; -- warning here, next statement is not good end loop; end process p1; end arch;
nLint reports: document.vhd(9): Warning 27093: Should not use NEXT statement in a loop statement(at line 8). (Coding Style)
27095 (VHDL) EXIT Statement Used in Loop

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: Should not use EXIT statement in a loop statement(at line %d). Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether any EXIT statements are used in a loop statement. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is begin p1 : process is begin for i in 1 to 10 loop exit ; --warning here, next statement is not good end loop; end process p1; end arch;
nLint reports: document.vhd(9): Warning 27095: Should not use EXIT statement in a loop statement(at line 8). (Coding Style)
27099 (VHDL) Composite Record Used as Trigger

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the whole record object "%s" is used in the sensitivity list. Use elements instead. Configurable Parameter Rule group: Simulation, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any trigger on a whole composite record. This will decrease the simulator performance. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 package mmm is type my_record is record a : bit; b: integer; end record; end mmm; use work.mmm.all; entity top_ety is port ( s : in my_record; s1 : out my_record ); end top_ety; architecture arch of top_ety is begin p1 : process (s) --warning on "s" begin s1 <= s; end process p1; end arch;
nLint reports: document.vhd(18): Warning 27099: the whole record object "s" is used in the sensitivity list. Use elements instead. (Simulation,Coding Style)
27101 (VHDL) Function Returning Dynamically Allocated Memory may Lead to Memory Leak
Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: function returning access type may lead to memory leaks. Configurable Parameter Rule group: Simulation, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any access object returned by a function, which may lead to memory leak. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end top_ety; architecture arch of top_ety is type my_access is access integer; function func1 return my_access is --warning here, the function return type "my_access" is an --access type variable v: my_access; begin return new integer; end function func1; begin end arch;
nLint reports: document.vhd(6): Warning 27101: function returning access type may lead to memory leaks. (Simulation,Coding Style)
27105 (VHDL) Attribute Leads to Bad Simulation Performance

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: use of attribute "%s" will degrade the simulation performance. Configurable Parameter Rule group: Simulation, Coding Style; Argument type: string; Argument description: specify a string of forbidden ATTRIBUTE(s), separated by comma; Default value: "DELAYED,STABLE,QUIET,TRANSACTION" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there are any pre-specified attributes, which will degrade the simulation performance. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is signal s : bit; begin p1 : process is variable v : boolean; begin v:= s'stable; --warning here end process; end arch;
nLint reports following if the argument value is ("DELAYED,STABLE,QUIET,TRANSACTION"): document.vhd(10): Warning 27105: use of attribute "stable" will degrade the simulation performance. (Simulation,Coding Style)
27107 (VHDL) WAIT Statement Not the First Statement

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: WAIT statement should be used as the first statement in a process that has no sensitivity list. Configurable Parameter Rule group: Coding Style, Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any WAIT statement used as not the first statement in a process that has no sensitivity list. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is signal s : bit; begin p1 : process begin s<='0'; wait on s; --warning here, wait statement should be the first --statement in a process without sensitivity list end process; end arch;
nLint reports: document.vhd(7): Warning 27107: WAIT statement should be used as the first statement in a process that has no sensitivity list. (Synthesis,Coding Style)
27109 (VHDL) Non-event Attribute on Sensitive Signal

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: attribute "%s" should not be used on sensitive signal "%s" in a wait statement (only event attribute is allowed). Configurable Parameter Rule group: Simulation, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is attribute, other than event, used on sensitive signal in wait statement, which is difficult to maintain, and may degrade the simulation performance. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is signal s1,s2 : bit; begin p1 : process begin wait on s1, s2'TRANSACTION; --waring here, non-event --attribute in the wait statement end process p1; end arch;
nLint reports: document.vhd(9): Warning 27109: attribute "TRANSACTION" should not be used on sensitive signal "s2" in a wait statement (only event attribute is allowed). (Simulation,Coding Style)
27111 (VHDL) Should Rising_Edge or Falling_Edge Function

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: should use rising_edge() or falling_edge() function. Configurable Parameter Rule group: Simulation, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any edge-trigger on std_(u)logic signals that does not use rising_edge() or falling_edge() function. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 library ieee; use ieee.std_logic_1164.all; entity top_ety is end top_ety; architecture arch of top_ety is signal s : std_logic; begin p1 : process (s) begin if (s'event and s='1') then --warning here, use rising_edge(s) instead end if; end process p1; end arch;
nLint reports: document.vhd(12): Warning 27111: should use rising_edge() or falling_edge() function. (Simulation,Coding Style)
27115 (VHDL) Integer Type Used

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: integer's subtype with range constraint on object "%s" should be used. Configurable Parameter Rule group: Simulation, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether any integer type is used on object, which will degrade the performance of simulation. Using subtype of integer with range constraint is recommended. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is port ( s : in integer; --warning here, please do not use integer type --directly use its subtype with value --range instead o : out integer --warning here ); end top_ety; architecture arch of top_ety is begin o <= s; end arch;
nLint reports: document.vhd(3): Warning 27115: integer's subtype with range constraint on object "s" should be used. (Simulation,Coding Style) document.vhd(6): Warning 27115: integer's subtype with range constraint on object "o" should be used. (Simulation,Coding Style)
27119 (VHDL) BUFFER Port Used

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: "%s" declared as BUFFER. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any port declared as BUFFER. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is port (s: buffer bit); --warning here, buffer port should be avoided end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27119: "s" declared as BUFFER. (Coding Style)
27122 (Verilog) Variable is Conditionally Assigned in the Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable "%s" is conditionally assigned in the block. Configurable Parameter Rule group: Synthesis; Argument type: (CHECK_IN_SEQ, IGNORE_IN_SEQ); Argument description: select CHECK_IN_SEQ to check in sequential block; select IGNORE_IN_SEQ to ignore checking in sequential block Default value: "IGNORE_IN_SEQ" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any variable is conditionally assigned in the block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 module fsm_test (Clock, Reset, ThreeOnly, StartFSM1); parameter ST_A=0,ST_B=1,ST_C=2,ST_D=3; input Clock, Reset,ThreeOnly,StartFSM1; reg [1:0] CurrStateFSM1, NextStateFSM1; //warning on NextStateFSM1 always @(StartFSM1 or ThreeOnly or CurrStateFSM1) begin: FSM1_COMB //****************************************** // Force NextStateFSM1 to get default value //****************************************** case (CurrStateFSM1) ST_A : if (StartFSM1) NextStateFSM1 = ST_B; else NextStateFSM1 = ST_A; ST_B : NextStateFSM1 = ST_C; ST_C : if (ThreeOnly) NextStateFSM1 = ST_A; else NextStateFSM1 = ST_D; /*ST_D : NextStateFSM1 = ST_A; */ //default : NextStateFSM1 = ST_A; endcase end always @(posedge Clock) begin: FSM1_SEQ if (Reset) CurrStateFSM1 = ST_A; else CurrStateFSM1 = NextStateFSM1; end endmodule
nLint reports following if the argument value is ("IGNORE_IN_SEQ"): document.v(6): Warning 27122: variable "NextStateFSM1" is conditionally assigned in the block. (Synthesis)
27123 (Verilog) Temporary Variable Used in Nonblocking Assignment 27123 (VHDL) Internal Signal Used Resulting in Bad Performance
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: "%s" is used like a temporary variable; by non-blocking assignment, it will reduce one more storage element. (VHDL) <filename>(<line no.>): <severity> <rule no.>: internal signal "%s" should be declared as a variable for performance. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any temporary variable used as LHS of nonblocking assignment. If not, blocking assignment is suggested to use for alternative. (VHDL) Check to see if there is any signal used in just one process. If not, variable is suggested to use for alternative. It will degrade simulation performance. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (clk, y, a, b, c, d); output y; input a, b, c, d; input clk; reg y, tmp1, tmp2; always begin tmp1 tmp2 y <= @(posedge clk) <= a & b; <= c & d; tmp1 | tmp2;
end endmodule
nLint reports: document.v(5): Warning 27123: "tmp1" is blocking assignment, it will reduce one (Simulation,Synthesis) document.v(5): Warning 27123: "tmp2" is blocking assignment, it will reduce one (Simulation,Synthesis)
used like a temporary variable; by nonmore storage element. used like a temporary variable; by nonmore storage element.
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is port (a : in integer; b : in integer; result : out integer); end top_ety; architecture arch of top_ety is
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
signal c: integer:=0; begin p1 : process (a,b) --signal "c" is used as internal signal of this process, --which can be replaced with variable to enhance simulation --performance and will result in unexpected synthesis result begin c <= a - b; if ( a > b ) then result <= c; else result <= -c; end if; end process; end arch;
nLint reports: document.vhd(8): Warning 27123: internal signal "c" should be declared as a variable for performance. (Simulation,Synthesis)
27124 (VHDL) Initialized Variable Used as a Constant

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: variable "%s" with initial value should be declared as constant since it is never assigned elsewhere. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any variable which has initial value but has never been assigned elsewhere. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 package AAA_pkg is subtype bv8 is bit_vector(7 downto 0); end AAA_pkg; library IEEE; use IEEE.std_logic_1164.all, WORK.AAA_pkg.all; entity top_ety is port (clk : in bit; data : in bv8; count : out bv8); end top_ety; architecture arch of top_ety is begin p1 : process variable t1: bv8 := "00000000"; variable t2: bv8; begin t2 := t1; --warning here count <= t2; end process; end arch;
nLint reports: document.vhd(17): Warning 27124: variable "t1" with initial value should be declared as constant since it is never assigned elsewhere. (Coding Style)
27125 Un-initialized Variable Referenced in an Edgetriggered Block

Message <filename>(<line no.>): <severity> <rule no.>: variable "%s" is not fully initialized before being referenced. Configurable Parameter Rule group: Simulation; Argument type: (CHECK_ORDER, CHECK_REF_ONLY); Argument description: If the argument is set to CHECK_ORDER, the rule checks the order of variable assignments and references within an edge-triggered block. The rule is violated if no variable assignments occur prior to a variable reference. If the argument is set to CHECK_REF_ONLY, the rule ignores the order of variable assignments and references within an edge-triggered block. The rule is violated if there are no assignments to a referred variable; Default value: "CHECK_REF_ONLY" for Verilog, "CHECK_REF_ONLY" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any variables whose values are not initialized before being referenced in an edge-triggered block. Non-initialized variables induce unknowns in simulation. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (clk, data, count); input clk,data; output count; reg count; reg t; //initial // t = 1; //if remove the comment of initial block, //warning 27125 on "t" is gone always @( posedge clk )begin count = t & data; //variable "t" is referenced un-initialized end endmodule
nLint reports following if the argument value is ("CHECK_REF_ONLY"): document.v(13): Warning 27125: variable "t" is not fully initialized before being referenced. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is port ( clk : in bit; data : in bit; count : out bit ); end top_ety; architecture arch of top_ety is begin process ( clk ) variable t : bit; --variable t : bit := '1'; --if change the declaration to comment,
13 14 15 16 17 18 19
--warning 27125 on "t" is gone begin if ( clk'event and clk = '1' ) then count <= t and data; --variable "t" is referenced un-initialized end if; end process; end arch;
nLint reports following if the argument value is ("CHECK_REF_ONLY"): document.vhd(16): Warning 27125: variable "t" is not fully initialized before being referenced. (Simulation)
27126 Unassigned Variable Referenced in an Edgetriggered Block

Message <filename>(<line no.>): <severity> <rule no.>: variable "%s" is not fully assigned before being referenced. Configurable Parameter Rule group: Synthesis; Argument type: (CHECK_ORDER, CHECK_REF_ONLY); Argument description: If the argument is set to CHECK_ORDER, the rule checks the order of variable assignments and references within an edge-triggered block. The rule is violated if no variable assignments occur prior to a variable reference. If the argument is set to CHECK_REF_ONLY, the rule ignores the order of variable assignments and references within an edge-triggered block. The rule is violated if there are no assignments to a referred variable; Default value: "CHECK_REF_ONLY" for Verilog, "CHECK_REF_ONLY" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any variables whose values are not fully assigned before being referenced in an edge-triggered block. A variable is not fully assigned when the variable is not assigned in all conditional branches or not all the bits of the variable are assigned. Note that initializations in non-synthesizable source code are not regarded as an assignment in this rule. Example
(Verilog) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 //1. only reference module test (clk, data, count); input clk,data; output count; reg count; reg t; initial t = 1'b1; //Even "t" is initialized here, it is ignored //Because initial block is ignored by synthesizer. always @( posedge clk )begin count = t & data; //Here "t" has not been initialized before //reference. After synthesis, "t" is directly linked //to '0', which cause mis-match between //pre-synthesis status and post-synthesis. end endmodule
nLint reports following if the argument value is ("CHECK_REF_ONLY"): document1.v(14): Warning 27126: variable "t" is not fully assigned before being referenced. (Synthesis) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 //2. not fully assign before referenced module test (rst, clk, data, count); input rst,clk,data; output count; reg count; reg t;
8 9 10 11 12 13 14 15 16
always @( posedge clk )begin if ( rst ) t = 0; count = t & data; //Here "t" has not been assigned fully //before referenced. After synthesis, an //additional storage for "t" will be inferred end endmodule
nLint reports following if the argument value is ("CHECK_TEMPVAR"): document2.v(12): Warning 27126: variable "t" is not fully assigned before being referenced. (Synthesis) ///////////////example : document3.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 //3. assign after referenced module test (data, count, clk); input clk; input data; output count; reg count; reg t; always @( posedge clk ) begin count = t & data; t = 1; //Here "t" is assigned after referenced. After synthesis, //a redundant storage inferred for "t". But it is not //reported as violation since user might need to keep it. end endmodule
nLint reports following if the argument value is ("CHECK_TEMPVAR"): document3.v(11): Warning 27126: variable "t" is not fully assigned before being referenced. (Synthesis) ///////////////example : document4.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 //4. not fully assign before referenced module test (rst, clk, data, count); input rst,clk; input [1:0] data; output [1:0] count; reg [1:0] count; reg [1:0] t; always @( posedge clk )begin if ( rst ) t[0] = 0; else t[0] = 1; count = t & data; //Here "t" has not been assigned fully //before referenced. After synthesis, an //additional storage for "t" will be inferred end endmodule
nLint reports following if the argument value is ("CHECK_REF_ONLY"): document4.v(15): Warning 27126: variable "t[1]" is not fully assigned before being referenced. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 --1. only reference entity top_ety is port (CLK : in bit; D : in bit;
6 Q : out bit ); 7 end; 8 9 architecture arch of top_ety is 10 begin 11 process (CLK) 12 variable t : bit := '1'; --synthesis ignores 13 begin 14 if (CLK'event and CLK = '1') then 15 Q <= t and D; --Here "t" has not been initialized before 16 --reference. After synthesis, "t" is directly linked 17 --to '0', which cause mismatch between 18 --pre-synthesis status and post-synthesis. 19 end if; 20 end process; 21 end; 22 23 --2. not fully assign before referenced 24 25 entity top_ety is 26 port ( clk : in bit; 27 rst : in bit; 28 D : in bit; 29 Q : out bit ); 30 end; 31 32 architecture arch of top_ety is 33 begin 34 process ( clk ) 35 variable t: bit; 36 begin 37 if ( clk'event and clk = '1' ) then 38 if ( rst = '1' ) then 39 t := '0'; 40 end if; 41 Q <= t and D; --Here "t" has not been assigned fully 42 --before referenced. After synthesis, an 43 --additional storage for "t" will be inferred 44 end if; 45 end process; 46 end; 47 48 --3. assign after referenced 49 50 entity top_ety is 51 port ( CLK : in bit; 52 D : in bit; 53 Q : out bit ); 54 end; 55 56 architecture arch of top_ety is 57 begin 58 process (CLK) 59 variable t : bit := '1'; --synthesis ignore 60 begin 61 if (CLK'event and CLK = '1') then 62 Q <= t and D; 63 t := '1'; 64 end if; --Here "t" is assigned after referenced. After synthesis, 65 --a redundant storage inferred for "t". But it is not 66 --reported as violation since user might need to keep it. 67 end process; 68 end; -------------------example : document1.vhd------------1 2 3 4 5 6 7 8 9 10 11 --1. only reference entity top_ety is port (CLK : in bit; D : in bit; Q : out bit ); end top_ety; architecture arch of top_ety is begin process (CLK)
12 13 14 15 16 17 18 19 20 21 22
variable t : bit := '1'; --synthesis ignores begin if (CLK'event and CLK = '1') then Q <= t and D; --Here "t" has not been initialized before --reference. After synthesis, "t" is directly linked --to '0', which cause mismatch between --pre-synthesis status and post-synthesis. end if; end process; end arch;
nLint reports following if the argument value is ("CHECK_REF_ONLY"): document1.vhd(15): Warning 27126: variable "t" is not fully assigned before being referenced. (Synthesis) -------------------example : document2.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 --2. not fully assign before referenced entity top_ety is port ( clk : in bit; rst : in bit; D : in bit; Q : out bit); end top_ety; architecture arch of top_ety is begin process ( clk ) variable t: bit; begin if ( clk'event and clk = '1' ) then if ( rst = '1' ) then t := '0'; end if; Q <= t and D; --Here "t" has not been assigned fully --before referenced. After synthesis, an --additional storage for "t" will be inferred end if; end process; end arch;
nLint reports following if the argument value is ("CHECK_TEMPVAR"): document2.vhd(19): Warning 27126: variable "t" is not fully assigned before being referenced. (Synthesis) -------------------example : document3.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 --3. assign after referenced entity top_ety is port ( CLK : in bit; D : in bit; Q : out bit ); end top_ety; architecture arch of top_ety is begin process (CLK) variable t : bit := '1'; --synthesis ignore begin if (CLK'event and CLK = '1') then Q <= t and D; t := '1'; end if; --Here "t" is assigned after referenced. After synthesis, --a redundant storage inferred for "t". But it is not --reported as violation since user might need to keep it. end process; end arch;
nLint reports following if the argument value is ("CHECK_TEMPVAR"): document3.vhd(15): Warning 27126: variable "t" is not fully assigned before being referenced. (Synthesis) -------------------example : document4.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 --4. not fully assign before referenced entity top_ety is port ( clk : in bit; rst : in bit; D : in bit_vector(1 downto 0); Q : out bit_vector(1 downto 0)); end top_ety; architecture arch of top_ety is begin process ( clk ) variable t: bit_vector(1 downto 0); begin if ( clk'event and clk = '1' ) then if ( rst = '1' ) then t(0) := '0'; else t(0) := '1'; end if; Q <= t and D; --Here "t" has not been assigned fully --before referenced. After synthesis, an --additional storage for "t" will be inferred end if; end process; end arch;
nLint reports following if the argument value is ("CHECK_REF_ONLY"): document4.vhd(21): Warning 27126: variable "t(1)" is not fully assigned before being referenced. (Synthesis)
27127 Un-initialized Variable Referenced in Combinational Process

Message <filename>(<line no.>): <severity> <rule no.>: variable "%s" should be initialized (fully) before referenced in combinational process. Configurable Parameter Rule group: Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any un-initialized variable which is referenced in a combinational process. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (data, count); input data; output count; reg count; reg t; //initial // t = 1; //if remove the comment of initial block, violation will disappear. always @( data ) begin count = t && data; //Here "t" is referenced un-initialized end endmodule
nLint reports: document.v(12): Warning 27127: variable "t" should be initialized (fully) before referenced in combinational process. (Simulation)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is port ( data : in bit; count : out bit ); end top_ety; architecture rtl of top_ety is begin process ( data ) variable t : bit; --variable t : bit := '1'; --if replace the declaration with the comment line, --warning 27127 on "t" is gone begin count <= t and data; --Here "t" is referenced un-initialized end process; end rtl;
nLint reports: document.vhd(14): Warning 27127: variable "t" should be initialized (fully) before referenced in combinational process. (Simulation)
27128 Variable Not Fully Assigned before Referenced in Combinational Process

Message <filename>(<line no.>): <severity> <rule no.>: variable "%s" should be assigned (fully) before being referenced in a combinational process, otherwise it will lead to additional storage or mismatch between pre-synthesis and post-synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any variables are referenced before being assigned in a combinational process, which will result in mismatch between pre-synthesis and post-synthesis. There is an exception that this rule does not care if a variable is referenced in a continuous assignment without being assigned in any other combinational processes. 27676, 27125, 27126 and 27127 are similar rules. The following description clarifies the differences between them: 1) Differences between rule 27676 and 27128 27676 only checks the same always block which may be combinational or sequential, while 27128 checks all combinational processes except continuous assignment in a module. 27676 requires that both the assignment and reference exist in the same always block, while 27128 does not. 27128 reports violations when a variable is conditionally assigned and then unconditionally referenced in one always block, but 27676 does not. 2) Differences between rule 27125, 27126, 27127 and 27128 Both 27127 and 27128 check combinational processes. They are nearly the same except: 27127 is a simulation rule, which is used to prevent mismatch between pre-simulation and post-simulation; therefore, it will check initial blocks and continuous assignments; and 27128 is a synthesis rule, which is used to prevent mismatch between pre-synthesis and post-synthesis; therefore, it will ignore initial blocks and variables being referenced in continuous assignments. Rule 27125 and 27126 are also similar rules. They both check read before write in sequential processes. 27125 is a simulation rule which checks initial blocks and 27126 is a synthesis rule which does not check initial blocks. 3) Why rules 27125 to 27128 are not limited to checking within a single process. The reason is to prevent false warnings. A variable being assigned in one process and referenced in another is acceptable, but if these rules are limited to checking within a single process, they will be falsely fired. Use the following case as an example: although "q1" is referenced but not assigned in the sequential process from line 10 to 11, neither 27125 nor 27126 should fire it. 1 module FF (q2, d, clk, rst); 2 output q2; 3 input d, clk, rst; 4 reg q2, q1;
5 6 always @(posedge clk) 7 if (!rst) q1 <= 1'b0; 8 else q1 <= d; 9 10 always @(posedge clk) 11 q2 <= q1; // No warning on q1 12 endmodule Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 //1. only reference module input output reg reg top_27128_1( data, count ); data; count; count; t;
initial t = 1'b1; //Even "t" is initialized here, it is ignored. //Because initial block is ignored by synthesizer. always @( data ) begin count = t & data; //Here "t" has not been assigned before referenced. //After synthesis, it is directly linked to '0', //which cause mismatch between pre-synthesis and //post-synthesis end endmodule //2. not fully assign before referenced module input output reg reg top_27128_2( data, count ); data; count; count; t;
always @( data )begin if ( data ) t = 1; count = t; //Here "t" has not been assigned fully before referenced. //After synthesis, an additional latch will be inferred. end endmodule //3. assign after referenced module input output reg reg top_27128_3( data, count ); data; count; count; t;
always @( data )begin count = t; t = data; //There is no difference in the result of synthesis if //change the two assignment sequence. So there is mismatch //between pre-synthesis and post-synthesis. end endmodule///////////////example : document1.v//////////// //1. only reference module test (data, count); input data; output count; reg count; reg t; initial t = 1'b1; //Even "t" is initialized here, it is ignored. //Because initial block is ignored by synthesizer.
11 12 13 14 15 16 17 18
always @( data ) begin count = t & data; //Here "t" has not been assigned before referenced. //After synthesis, it is directly linked to '0', //which cause mismatch between pre-synthesis and //post-synthesis end endmodule
nLint reports: document1.v(13): Warning 27128: variable "t" should be assigned (fully) before being referenced in a combinational process, otherwise it will lead to additional storage or mismatch between pre-synthesis and post-synthesis. (Synthesis) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 //2. not fully assign before referenced module test (data, count); input data; output count; reg count; reg t; always @( data )begin if ( data ) t = 1; count = t; //Here "t" has not been assigned fully before referenced. //After synthesis, an additional latch will be inferred. end endmodule
nLint reports: document2.v(12): Warning 27128: variable "t" should be assigned (fully) before being referenced in a combinational process, otherwise it will lead to additional storage or mismatch between pre-synthesis and post-synthesis. (Synthesis) ///////////////example : document3.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 //3. assign after reference module test (data, count); input data; output count; reg count; reg t; always @( data )begin count = t; t = data; //There is no difference in the result of synthesis if //change the two assignment sequence. So there is mismatch //between pre-synthesis and post-synthesis. end endmodule
nLint reports: document3.v(10): Warning 27128: variable "t" should be assigned (fully) before being referenced in a combinational process, otherwise it will lead to additional storage or mismatch between pre-synthesis and post-synthesis. (Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 --1. only reference entity top_ety is port (D : in bit; Q : out bit ); end; architecture arch of top_ety is
9 begin 10 process ( D ) 11 variable t : bit := '1'; --synthesis ignores 12 begin 13 Q <= t and D; --Here "t" has not been assigned before referenced. 14 --After synthesis, it is directly linked to '0', 15 --which cause mismatch between pre-synthesis and 16 --post-synthesis 17 end process; 18 end; 19 20 --2. not fully assign before referenced 21 22 entity top_ety is 23 port ( D : in bit; 24 Q : out bit ); 25 end; 26 27 architecture arch of top_ety is 28 begin 29 process ( D ) 30 variable t: bit; 31 begin 32 if ( D = '1' ) then 33 t := '1'; 34 end if; 35 Q <= t; --Here "t" has not been assigned fully 36 --before referenced. After synthesis, 37 --an additional latch will be inferred. 38 end process; 39 end; 40 41 --3. assign after referenced 42 43 entity top_ety is 44 port ( D : in bit; 45 Q : out bit ); 46 end; 47 48 architecture arch of top_ety is 49 begin 50 process ( D ) 51 variable t : bit := '1'; --synthesis ignores 52 begin 53 Q <= t and D; 54 t := '1'; --There is no difference in the result of synthesis if 55 --change the two assignment sequence. So there is mismatch 56 --between pre-synthesis and post-synthesis. 57 end process; 58 end; -------------------example : document1.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 --1. only reference entity top_ety is port (D : in bit; Q : out bit ); end; architecture arch of top_ety is begin process ( D ) variable t : bit := '1'; --synthesis ignores begin Q <= t and D; --Here "t" has not been assigned before referenced. --After synthesis, it is directly linked to '0', --which cause mismatch between pre-synthesis and --post-synthesis end process; end;
nLint reports: document1.vhd(13): Warning 27128: variable "t" should be assigned (fully) before being referenced in a combinational process, otherwise it will lead to additional
storage or mismatch between pre-synthesis and post-synthesis. (Synthesis) -------------------example : document2.vhd------------1 --2. not fully assign before reference 2 3 entity top_ety is 4 port ( D : in bit; 5 Q : out bit ); 6 end; 7 8 architecture arch of top_ety is 9 begin 10 process ( D ) 11 variable t: bit; 12 begin 13 if ( D = '1' ) then 14 t := '1'; 15 end if; 16 Q <= t; --Here "t" has not been assigned fully 17 --before referenced. After synthesis, 18 --an additional latch will be inferred. 19 end process; 20 end; 21
nLint reports: document2.vhd(16): Warning 27128: variable "t" should be assigned (fully) before being referenced in a combinational process, otherwise it will lead to additional storage or mismatch between pre-synthesis and post-synthesis. (Synthesis) -------------------example : document3.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 --3. assign after referenced entity top_ety is port ( D : in bit; Q : out bit ); end; architecture arch of top_ety is begin process ( D ) variable t : bit := '1'; --synthesis ignores begin Q <= t and D; t := '1'; --There is no difference in the result of synthesis if --change the two assignment sequence. So there is mismatch --between pre-synthesis and post-synthesis. end process; end;
nLint reports: document3.vhd(13): Warning 27128: variable "t" should be assigned (fully) before being referenced in a combinational process, otherwise it will lead to additional storage or mismatch between pre-synthesis and post-synthesis. (Synthesis)
27130 (Verilog) Variable Updated Twice in Same Time Point

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable "%s" is assigned in another assignment (line %d) in same time point. Configurable Parameter Rule group: Coding Style; Argument type: (BLOCKING, NONBLOCKING) (CHECK_INITASS, IGNORE_INITASS); Argument description: This is a multiple select argument. Select BLOCKING to check blocking assignment. Select NONBLOCKING to check non-blocking assignment. select CHECK_INITASS to check all assignments including initial assignment; select IGNORE_INITASS not to check initial assignment; Default value: "NONBLOCKING","CHECK_INITASS" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any variable is assigned in two assignments at the same time point. Example
(Verilog) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 //Ex1 module block( clk, a, b); input clk, b; output a; reg a; always @(posedge clk) begin a <= 1; if (b) a <= 0; end endmodule //Warning if select NONBLOCKING. //In above example, if 'b' is true, the 'a' will be updated different //values in the same time point. The result may be un-determined //according to LRM, however most industry simulators will take the //later value assigned, '0' in this example.
nLint reports following if the argument value is ("NONBLOCKING"): document1.v(7): Warning 27130: variable "a" is assigned in another assignment (line 9) in same time point. (Coding Style) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 //Ex2 module block( clk, a, b); input clk, b; output a; reg a; always @(posedge clk) begin a = 1; if (b) a = 0; //Warning if select BLOCKING. //If 'b' is true, the 'a' will be assigned again in the same //time point. The result is determined. end endmodule
nLint reports following if the argument value is ("BLOCKING"): document2.v(7): Warning 27130: variable "a" is assigned in another assignment (line 9) in same time point. (Coding Style)
27131 (Verilog) Assignment is Redundant

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable "%s" assigned here is completely overwrited by following assignments. Configurable Parameter Rule group: Coding Style; Argument type: (BLOCKING, NONBLOCKING); Argument description: This is a multiple select argument. Select BLOCKING to check blocking assignment. Select NONBLOCKING to check non-blocking assignment; Default value: "NONBLOCKING" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any variable is assigned in redundant statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 module block1( clk, a, b); input clk, b; output a; reg a; always @(posedge clk) begin a <= b; a <= ~b; end endmodule //Warning if select NONBLOCKING. Assignment "a <= b" is redundant here. //In above example, 'a' is updated different values in the same //time point. The result may be un-determined according to LRM, //however most industry simulators will take the later value assigned, //'~b' in this example. module block2( clk, a, b, c ); input clk, b, c; output a; reg a; always @(posedge clk) begin a = 0; if (c) a = b; else a = ~b; end endmodule //Warning if select BLOCKING. Assignment "a = 0" is redundant here //In above example, 'a' is complete overwrited by assignments in //if construct.
nLint reports following if the argument value is ("BLOCKING NONBLOCKING"): document.v(7): Warning 27131: variable "a" assigned here is completely overwrited by following assignments. (Coding Style) document.v(24): Warning 27131: variable "a" assigned here is completely overwrited by following assignments. (Coding Style)
27143 (VHDL) BLOCK Statement Used

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: BLOCK statement should not be used. Configurable Parameter Rule group: HDL Translation, Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any BLOCK statement used. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is begin b1: block is --warning here, block statement should not be used! begin end block b1; end arch;
nLint reports: document.vhd(6): Warning 27143: BLOCK statement should not be used. (HDL Translation,Coding Style)
27144 (VHDL) GENERATE Statement Used

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: GENERATE statement should not be used. Configurable Parameter Rule group: Coding Style, HDL Translation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any GENERATE statement used. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is begin g1: for i in 1 to 100 generate begin end generate g1; end arch;
--warning here
nLint reports: document.vhd(6): Warning 27144: GENERATE statement should not be used. (HDL Translation,Coding Style)
27155 (VHDL) Port Name with Underscore in Top Entity

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: underscore should not be used in port identifier "%s" of top entity. Configurable Parameter Rule group: VITAL Compliant; Argument type: none; Default severity : Level2 (Warning) Description (VHDL) This rule checks whether there is any port named with underscore in top entity, which will not compatible to VITAL support. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is port (clk_s : in bit); --warning here, underscore found in the --port declaration end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27155: underscore should not be used in port identifier "clk_s" of top entity. (VITAL Compliant)
27159 (VHDL) Range Constraint on Port in Top Entity

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: range constraint should not be specified on port "%s" in top entity. Configurable Parameter Rule group: VITAL Compliant; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any port declaration with range constraint in top entity, which is incompatible to VITAL support. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is port (s : in bit_vector(7 downto 0)); --warning here, the port --"s" is constrained. end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27159: range constraint should not be specified on port "s" in top entity. (VITAL Compliant)
27163 (VHDL) Non-std_logic_1164 Type Used on Port in Top Entity

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: type "%s" is not the expected type and should not be used on port "%s" in top entity. Configurable Parameter Rule group: VITAL Compliant; Argument type: string; Argument description: fill the types preferred into the string, separated with comma; if nothing specified in the string, all types in standard, textio, numeric_bit, numeric_std, std_logic_arith, std_logic_misc, std_logic_signed, std_logic_unsigned, vital_primitives, std_logic_textio, vital_timing, std_logic_1164 are available; otherwise, only the types specified in the string are available; Default value: "" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any type other than types in std_logic_1164 used in port declaration in top entity, which is in compatible to VITAL support. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 package pkg is type my_color is (BLUE, GREEN, YELLOW, RED); end pkg; use work.pkg.all; entity top_ety is port (clk : in bit; q : out my_color -- warning on "my_color" ); end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is (""): document.vhd(8): Warning 27163: type "my_color" is not the expected type and should not be used on port "q" in top entity. (VITAL Compliant)
27181 (VHDL) Use Signal Instead of Variable in Process

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: Use signal instead of variable for "%s" in process of synthesizable code. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether any variable assignment is used in process. In synthesizable code, use signal assignment instead to avoid mismatch between pre-synthesis and post-synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port ( data : in bit; count : out bit ); end top_ety; architecture rtl of top_ety is begin process ( data ) variable t : bit; begin count <= t; t := data; end process; end rtl;
nLint reports: document.vhd(9): Warning 27181: Use signal instead of variable for "t" in process of synthesizable code. (Synthesis)
27201 (VHDL) ENTITY Name Length

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of ENTITY name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argument for the length of ENTITY name; Default value: "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the length of the ENTITY name is in the specified range. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 1 2 3 4 5 6 entity TOP_01234567890123456 is --warning on "TOP_01234567890123456" end TOP_01234567890123456; entity T is --warning on "T" end T;-------------------example : document1.vhd------------entity TOP_01234567890123456 is --warning on "TOP_01234567890123456" end TOP_01234567890123456; architecture arch of TOP_01234567890123456 is begin end arch;
nLint reports following if the argument value is ("3","16"): document1.vhd(1): Warning 27201: the length of ENTITY name "TOP_01234567890123456" is unconventional and should be in the range from 3 to 16. (Naming Convention) -------------------example : document2.vhd------------1 2 3 4 5 6 entity T is end T; --warning on "T"
architecture arch of T is begin end arch;
nLint reports following if the argument value is ("3","16"): document2.vhd(1): Warning 27201: the length of ENTITY name "T" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27203 (VHDL) ENTITY Name Case

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: ENTITY "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the ENTITY names are all in lower (or upper) case. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 entity TOP is --warning on "TOP" end TOP; architecture arch of TOP is begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(1): Warning 27203: ENTITY "TOP" should be named in CASE_LOWER case. (Naming Convention)
27205 (VHDL) ENTITY Name Prefix or Suffix

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: clock ENTITY name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_ety" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the ENTITY name has a recommended prefix or suffix. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 entity TEST is --warning on "TEST", using "TEST_ety" end TEST; architecture arch of TEST is begin end arch;
nLint reports following if the argument value is ("SUFFIX","_ety"): document.vhd(1): Warning 27205: clock ENTITY name "TEST" does not match to regular expression ".*_ety". (Naming Convention)
27209 (Verilog) MODULE Name Length 27209 (VHDL) ARCHITECTURE Name Length
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of module name "%s" is unconventional and should be in the range from %d to %d. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of ARCHITECTURE name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argument for the number of characters of ARCHITECTURE name; Default value: "3","16" for Verilog, "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the length of the module name is in the specified range. (VHDL) This rule checks whether the length of the ARCHITECTURE name is in the specified range. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test_top_0123456789012; //warning on "test_top_0123456789012" endmodule
nLint reports following if the argument value is ("3","16"): document.v(1): Warning 27209: the length of module name "test_top_0123456789012" is unconventional and should be in the range from 3 to 16. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture TEST_TOP_01234567890123 of top_ety is --warning on "TEST_TOP_01234567890123" begin end TEST_TOP_01234567890123;
nLint reports following if the argument value is ("3","16"): document.vhd(4): Warning 27209: the length of ARCHITECTURE name "test_top_01234567890123" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27211 (Verilog) MODULE Name Case 27211 (VHDL) ARCHITECTURE Name Case
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: module "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: ARCHITECTURE "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the module names are all in lower (or upper) case. (VHDL) This rule checks whether the ARCHITECTURE names are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 module TEST_TOP; //warning on "TEST_TOP" endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(1): Warning 27211: module "TEST_TOP" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 entity top_ety is end top_ety; architecture TEST_TOP of top_ety is --warning on "TEST_TOP" begin end TEST_TOP;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(4): Warning 27211: ARCHITECTURE "TEST_TOP" should be named in CASE_LOWER case. (Naming Convention)
27213 (Verilog) MODULE Name Prefix or Suffix 27213 (VHDL) ARCHITECTURE Name Prefix or Suffix
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: module name "%s" does not match to regular expression "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: ARCHITECTURE name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_module" for Verilog, "SUFFIX","_arch" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the module names has a recommended prefix or suffix. (VHDL) This rule checks whether the ARCHITECTURE name has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module TEST_TOP; //warning on "TEST_TOP", using //"TOP_module" like endmodule
nLint reports following if the argument value is ("SUFFIX","_module"): document.v(1): Warning 27213: module name "TEST_TOP" does not match to regular expression ".*_module". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture TEST_TOP of top_ety is --warning on "TEST_TOP", using --"TOP_arch" like begin end TEST_TOP;
nLint reports following if the argument value is ("SUFFIX","_arch"): document.vhd(4): Warning 27213: ARCHITECTURE name "test_top" does not match to regular expression ".*_arch". (Naming Convention)
27217 (VHDL) PACKAGE Name Length

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of PACKAGE name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of PACKAGE name; Default value: "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the length of the PACKAGE name is in the specified range. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 package ARITH_0123456789012345 is --warning on "ARITH_0123456789012345" subtype st is integer range 0 to 1; end ARITH_0123456789012345; use work.ARITH_0123456789012345.all; entity top_ety is end top_ety; architecture arch of top_ety is signal s : st; begin end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(1): Warning 27217: the length of PACKAGE name "ARITH_0123456789012345" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27219 (VHDL) PACKAGE Name Case

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: PACKAGE "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the PACKAGE names are all in lower (or upper) case. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 package MATH is end MATH; --warning on "MATH"
use work.MATH.all; entity top_ety is end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(1): Warning 27219: PACKAGE "MATH" should be named in CASE_LOWER case. (Naming Convention)
27221 (VHDL) PACKAGE Name Prefix or Suffix

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: PACKAGE name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_pkg" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the PACKAGE name has a recommended prefix or suffix. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 package MATH is --warning on "MATH", using "MATH_pkg" instead subtype st is integer range 0 to 1; end MATH; use work.MATH.all; entity top_ety is end top_ety; architecture arch of top_ety is signal s : st; begin end arch;
nLint reports following if the argument value is ("SUFFIX","_pkg"): document.vhd(1): Warning 27221: PACKAGE name "MATH" does not match to regular expression ".*_pkg". (Naming Convention)
27225 (VHDL) CONFIGURATION Name Length

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of CONFIGURATION name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of CONFIGURATION name; Default value: "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the length of the CONFIGURATION name is in the specified range. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity test is end test; architecture arch of test is begin end arch; configuration TOP_CONF_0123456789012 of test is --warning on "TOP_CONF_0123456789012" use work.all; for arch end for; end TOP_CONF_0123456789012;
nLint reports following if the argument value is ("3","16"): document.vhd(8): Warning 27225: the length of CONFIGURATION name "TOP_CONF_0123456789012" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27227 (VHDL) CONFIGURATION Name Case

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: CONFIGURATION "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the CONFIGURATION names are all in lower (or upper) case. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is begin end arch; configuration TOP_CONF of top_ety is --warning on "TOP_CONF" use work.all; for arch end for; end TOP_CONF;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(8): Warning 27227: CONFIGURATION "TOP_CONF" should be named in CASE_LOWER case. (Naming Convention)
27229 (VHDL) CONFIGURATION Name Prefix or Suffix

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: CONFIGURATION name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_cfg" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the CONFIGURATION name has a recommended prefix or suffix. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is begin end arch; configuration TOP_CONF of top_ety is --warning on "TOP_CONF" --using "TOP_cfg" like use work.all; for arch end for; end TOP_CONF;
nLint reports following if the argument value is ("SUFFIX","_cfg"): document.vhd(8): Warning 27229: CONFIGURATION name "TOP_CONF" does not match to regular expression ".*_cfg". (Naming Convention)
27233 INSTANCE Name Length

Message <filename>(<line no.>): <severity> <rule no.>: the length of instance name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the range of characters number of instance name; Default value: "3","16" for Verilog, "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the length of the instance name is in the specified range. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module top; wire a, b; EA u_EA_012345678901234 (a, b); //warning on "u_EA_012345678901234" endmodule module EA (a, b); input a; output b; endmodule
nLint reports following if the argument value is ("3","16"): document.v(4): Warning 27233: the length of instance name "u_EA_012345678901234" is unconventional and should be in the range from 3 to 16. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 library IEEE; use IEEE.std_logic_1164.all; entity EA generic port (d q end EA; is (n: integer := 8); : in bit_vector(n-1 downto 0); : out bit_vector(n-1 downto 0));
architecture arch of EA is begin end arch; library IEEE; use IEEE.std_logic_1164.all; use work.all; entity top_ety is end top_ety; architecture TOP_arch of top_ety is constant c: integer := 4; signal d1 : bit_vector(c-1 downto 0); signal q1 : bit_vector(c-1 downto 0);
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
signal d2 : bit_vector(2*c-1 downto 0); signal q2 : bit_vector(2*c-1 downto 0); component EA is generic (n: integer := 8); port (d : in bit_vector(n-1 downto 0); q : out bit_vector(n-1 downto 0)); end component EA; begin u_EA_012345678901234: component EA --warning on "u_EA_012345678901234" generic map (n=>c) port map (d=>d1, q=>q1); end TOP_arch;
nLint reports following if the argument value is ("3","16"): document.vhd(35): Warning 27233: the length of instance name "u_EA_012345678901234" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27235 INSTANCE Name Case

Message <filename>(<line no.>): <severity> <rule no.>: instance "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the instance names are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module top; wire a, b; EA U_EA (a, b); //warning on "U_EA" endmodule module EA (a, b); input a; output b; endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(3): Warning 27235: instance "U_EA" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 library IEEE; use IEEE.std_logic_1164.all; entity EA generic port (d q end EA; is (n: integer := 8); : in bit_vector(n-1 downto 0); : out bit_vector(n-1 downto 0));
architecture arch of EA is begin end arch; library IEEE; use IEEE.std_logic_1164.all; use work.all; entity top_ety is end top_ety; architecture TOP_arch of top_ety is constant c: integer := 4; signal d1 : bit_vector(c-1 downto 0); signal q1 : bit_vector(c-1 downto 0);
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
signal d2 : bit_vector(2*c-1 downto 0); signal q2 : bit_vector(2*c-1 downto 0); component EA is generic (n: integer := 8); port (d : in bit_vector(n-1 downto 0); q : out bit_vector(n-1 downto 0)); end component EA; begin U_EA: component EA --warning on "U_EA" generic map (n=>c) port map(d=>d1, q=>q1); end TOP_arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(35): Warning 27235: instance "U_EA" should be named in CASE_LOWER case. (Naming Convention)
27241 (VHDL) COMPONENT Name Length

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of COMPONENT name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of COMPONENT name; Default value: "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the length of the COMPONENT name is in the specified range. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 library IEEE; use IEEE.std_logic_1164.all; entity EA_012345678901234 is generic (n: integer := 8); port (d : in bit_vector(n-1 downto 0); q : out bit_vector(n-1 downto 0)); end EA_012345678901234; architecture arch of EA_012345678901234 is begin end arch; library IEEE; use IEEE.std_logic_1164.all; use work.all; entity top_ety is end top_ety; architecture TOP_arch of top_ety is constant c: integer := 4; signal d1 : bit_vector(c-1 downto 0); signal q1 : bit_vector(c-1 downto 0); signal d2 : bit_vector(2*c-1 downto 0); signal q2 : bit_vector(2*c-1 downto 0); component EA_012345678901234 is --warning on "EA_012345678901234" generic (n: integer := 8); port (d : in bit_vector(n-1 downto 0); q : out bit_vector(n-1 downto 0)); end component EA_012345678901234; begin U_EA: component EA_012345678901234 generic map (n=>c) port map (d=>d1, q=>q1); end TOP_arch;
nLint reports following if the argument value is ("3","16"): document.vhd(29): Warning 27241: the length of COMPONENT name "EA_012345678901234" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27245 (VHDL) COMPONENT Name Prefix or Suffix

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: COMPONENT name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","com_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the COMPONENT name has a recommended prefix or suffix. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is end top_ety; architecture arch of top_ety is constant c: integer := 4; signal d1 : bit_vector(c-1 downto 0); signal q1 : bit_vector(c-1 downto 0); signal d2 : bit_vector(2*c-1 downto 0); signal q2 : bit_vector(2*c-1 downto 0); component EA is --warning on "EA", using "com_EA" like generic (n: integer := 8); port (d : in bit_vector(n-1 downto 0); q : out bit_vector(n-1 downto 0)); end component EA; begin U_EA: component EA generic map (n=>c) port map (d=>d1, q=>q1); end arch;
nLint reports following if the argument value is ("PREFIX","com_"): document.vhd(15): Warning 27245: COMPONENT name "EA" does not match to regular expression "com_.*". (Naming Convention)
27249 PROCESS Name Length

Message <filename>(<line no.>): <severity> <rule no.>: the length of PROCESS name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of PROCESS name; Default value: "3","16" for Verilog, "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the length of the process name is in the specified range. Process here means initial, always (always_comb, always_ff and always_latch are inclusive) and generate (genfor, gen-if and gen-case are inclusive) statements. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (s, o); input s; output o; reg o; always @( s ) begin : P_0123456789012345 //warning on "P_0123456789012345" o = s; end endmodule
nLint reports following if the argument value is ("3","16"): document.v(6): Warning 27249: the length of PROCESS name "P_0123456789012345" is unconventional and should be in the range from 3 to 16. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is signal s : bit; signal o : bit; begin P_0123456789012345 : process ( s ) --warning on "P_0123456789012345" begin o <= s; end process; end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(8): Warning 27249: the length of PROCESS name "p_0123456789012345" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27251 PROCESS Name Case

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: process "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: PROCESS "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the process names are all in lower or upper case. Process here means initial, always (always_comb, always_ff and always_latch are inclusive) and generate (gen-for, gen-if and gen-case are inclusive) statements. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (s, o); input s; output o; reg o; always @( s ) begin : P1 //warning on "P1" o = s; end endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(6): Warning 27251: process "P1" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is signal s : bit; signal o : bit; begin P1 : process ( s ) --warning on "P1" begin o <= s; end process; end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(8): Warning 27251: PROCESS "P1" should be named in CASE_LOWER case. (Naming Convention)
27257 (VHDL) CONSTANT Name Length

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of CONSTANT name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of CONSTANT name; Default value: "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the length of the CONSTANT name is in the specified range. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is constant C_0123456789012345 : bit := '0'; --warning on "C_0123456789012345" begin end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(5): Warning 27257: the length of CONSTANT name "C_0123456789012345" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27259 (VHDL) CONSTANT Name Case

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: CONSTANT "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the CONSTANT names are all in lower (or upper) case. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture arch of top_ety is constant C1 : bit := '0'; --warning on "C1" begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(5): Warning 27259: CONSTANT "C1" should be named in CASE_LOWER case. (Naming Convention)
27261 (VHDL) CONSTANT Name Prefix or Suffix

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: CONSTANT name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","c_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the CONSTANT name has a recommended prefix or suffix. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is constant Length : integer := 16; --warning on "Length", using "c_Length" like begin end arch;
nLint reports following if the argument value is ("PREFIX","c_"): document.vhd(5): Warning 27261: CONSTANT name "Length" does not match to regular expression "c_.*". (Naming Convention)
27265 TYPE Name Length

Message <filename>(<line no.>): <severity> <rule no.>: the length of TYPE name "%s" is not in the range of %d to %d characters. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: Specify minimum and maximum number of characters of TYPE name in the first and second argument respectively; Default value: "3","16" for Verilog, "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the length of TYPE name is within the specified range. The rule can be used to restrict the naming convention of the length of TYPE name definition. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 //In this example, two arguments of rule 27265 is set to 3 and 16 module test(input r, output q); typedef logic LL; //warning reg r1; int this_is_a_long_int_variable; typedef struct { reg short; reg a_long_name_as_a_field; } a_very_long_name_as_typedef_name; //Warning enum {valid, tr, fs} this_is_a_long_declaration; endmodule
nLint reports following if the argument value is document.v(4): Warning 27265: the length of TYPE 3 to 16 characters. (Naming Convention) document.v(7): Warning 27265: the length of TYPE "a_very_long_name_as_typedef_name" is not in the (Naming Convention)
("3","16"): name "LL" is not in the range of name range of 3 to 16 characters.
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is type Color_01234567890123 is (black, white, red, green); --warning on "Color_01234567890123" end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(2): Warning 27265: the length of TYPE name "Color_01234567890123" is not in the range of 3 to 16 characters. (Naming Convention)
27267 Case of TYPE Name

Message <filename>(<line no.>): <severity> <rule no.>: TYPE "%s" is not in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the TYPE names are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 module topmodule; typedef int intP; intP a, b; endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.sv(3): Warning 27267: TYPE "intP" is not in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is type Color is (black, white, red, green); --warning on "Color" end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(2): Warning 27267: TYPE "Color" is not in CASE_LOWER case. (Naming Convention)
27269 Prefix or Suffix of TYPE Name

Message <filename>(<line no.>): <severity> <rule no.>: TYPE name "%s" does not match specified string "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_typ" for Verilog, "SUFFIX","_typ" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the specified TYPE (PREFIX, SUFFIX, SUB_STRING) names match a recommended prefix, suffix or sub-string respectively. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 module topmodule; typedef int intP; intP a, b; endmodule
nLint reports following if the argument value is ("SUFFIX","_typ"): document.sv(3): Warning 27269: TYPE name "intP" does not match specified string ".*_typ". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is type Color is (black, white, red, green); --warning on "Color", using "Color_typ" like end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("SUFFIX","_typ"): document.vhd(2): Warning 27269: TYPE name "Color" does not match specified string ".*_typ". (Naming Convention)
27273 (Verilog) PARAMETER Name Length 27273 (VHDL) GENERIC Name Length
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of parameter name "%s" is unconventional and should be in the range from %d to %d. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of GENERIC name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of GENERIC name; Default value: "3","16" for Verilog, "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the length of the parameter name is in the specified range (VHDL) This rule checks whether the length of the GENERIC name is in the specified range Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 module test; parameter par_012345678901234 = 5; //warning on "par_012345678901234" endmodule
nLint reports following if the argument value is ("3","16"): document.v(2): Warning 27273: the length of parameter name "par_012345678901234" is unconventional and should be in the range from 3 to 16. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is generic ( G_Size_0123456789012 : integer := 16 --warning on "G_Size_0123456789012" ); end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(3): Warning 27273: the length of GENERIC name "G_Size_0123456789012" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27277 (Verilog) PARAMETER Name Prefix or Suffix 27277 (VHDL) GENERIC Name Prefix or Suffix
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: parameterl name "%s" does not match to regular expression "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: GENERIC name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","p_" for Verilog, "PREFIX","g_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the parameter name has a recommended prefix or suffix. (VHDL) This rule checks whether the GENERIC name has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (clock, reset, control, y); input clock, reset, control; output [2:0] y; reg [2:0] y; parameter st0 = 0; //warning on st0, p_st0 is recommended reg [1:0] current, next; endmodule
nLint reports following if the argument value is ("PREFIX","p_"): document.v(6): Warning 27277: parameterl name "st0" does not match to regular expression "p_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is generic (n: integer := 10; --warning on 'n', 'g_n' is recommended M: bit :='0' --warning on 'M', 'g_M' is recommended ); begin end entity top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("PREFIX","g_"):
document.vhd(2): Warning 27277: GENERIC name "n" does not match to regular expression "g_.*". (Naming Convention) document.vhd(4): Warning 27277: GENERIC name "M" does not match to regular expression "g_.*". (Naming Convention)
27285 SIGNAL Name Prefix or Suffix

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal name "%s" does not match to regular expression "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: SIGNAL name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","s_" for Verilog, "PREFIX","s_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the signal name has a recommended prefix or suffix. (VHDL) This rule checks whether the SIGNAL name has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test ; reg checked; //warning on "checked", using "s_checked" like endmodule
nLint reports following if the argument value is ("PREFIX","s_"): document.v(2): Warning 27285: signal name "checked" does not match to regular expression "s_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is signal checked : boolean; --warning on "checked", --using "s_checked" like end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("PREFIX","s_"): document.vhd(2): Warning 27285: SIGNAL name "checked" does not match to regular expression "s_.*". (Naming Convention)
27287 (Verilog) VARIBLE Name

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable name "%s" does not match regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: string; Argument description: The argument specify regular expression (for clarification, see Regular Expression Help in the end of Rule documentation); Default value: "var_.*" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the variable name matches the regular expression specified by users. The type name and the field of struct or union will not be checked in this rule. And this rule only works for System Verilog. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 interface I1; logic l; endinterface module test(input r, output q); logic var_a [7:0]; logic b [7:0]; typedef struct { logic l1; int i1; } STU; STU su; struct { bit f1; logic f2; STU su; } stvar678901234567; typedef union { shortreal l1; int i1; } UN; UN un; enum {s1=1, s2, s3 } dv ; always_comb begin logic t; for (int i=0; i<8; i++) b[i] = var_a[i]; end function my (input in, output out); logic t ; endfunction endmodule
nLint reports following if the document.sv(2): Warning 27287: "var_.*". (Naming Convention) document.sv(4): Warning 27287: "var_.*". (Naming Convention) document.sv(4): Warning 27287: "var_.*". (Naming Convention) document.sv(6): Warning 27287: "var_.*". (Naming Convention)
argument value is ("var_.*"): variable name "l" does not match regular expression variable name "q" does not match regular expression variable name "r" does not match regular expression variable name "b" does not match regular expression
document.sv(11): Warning 27287: variable name "su" does not match regular expression "var_.*". (Naming Convention) document.sv(15): Warning 27287: variable name "stvar678901234567" does not match regular expression "var_.*". (Naming Convention) document.sv(20): Warning 27287: variable name "un" does not match regular expression "var_.*". (Naming Convention) document.sv(21): Warning 27287: variable name "dv" does not match regular expression "var_.*". (Naming Convention) document.sv(23): Warning 27287: variable name "t" does not match regular expression "var_.*". (Naming Convention) document.sv(24): Warning 27287: variable name "i" does not match regular expression "var_.*". (Naming Convention) document.sv(27): Warning 27287: variable name "out" does not match regular expression "var_.*". (Naming Convention) document.sv(27): Warning 27287: variable name "in" does not match regular expression "var_.*". (Naming Convention) document.sv(28): Warning 27287: variable name "t" does not match regular expression "var_.*". (Naming Convention)
27288 (Verilog) VARIABLE Name Length

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of variable name "%s" should be in the range of "%d" to "%d" characters. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: Arguments specify minimum and maximum number of characters of Variable name; Default value: "3","16" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the length of variable name in the range specified by users. The type name and the field of struct or union will not be checked in this rule. And this rule only works for System Verilog Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 interface I1; logic l; endinterface module test(input r, output q); logic var_a [7:0]; logic b [7:0]; typedef struct { logic l1; int i1; } STU; STU su; struct { bit f1; logic f2; STU su; } stvar678901234567; typedef union { shortreal l1; int i1; } UN; UN un; enum {s1=1, s2, s3 } dv ; always_comb begin logic t; for (int i=0; i<8; i++) b[i] = var_a[i]; end function myf (input in, output out); logic t ; endfunction endmodule
nLint reports following if the argument value is ("3","16"): document.sv(2): Warning 27288: the length of variable name "l" range of "3" to "16" characters. (Naming Convention) document.sv(4): Warning 27288: the length of variable name "q" range of "3" to "16" characters. (Naming Convention) document.sv(4): Warning 27288: the length of variable name "r" range of "3" to "16" characters. (Naming Convention) document.sv(6): Warning 27288: the length of variable name "b" range of "3" to "16" characters. (Naming Convention)
should be in the should be in the should be in the should be in the
document.sv(11): Warning 27288: the length of variable name "su" should be in the range of "3" to "16" characters. (Naming Convention) document.sv(15): Warning 27288: the length of variable name "stvar678901234567" should be in the range of "3" to "16" characters. (Naming Convention) document.sv(20): Warning 27288: the length of variable name "un" should be in the range of "3" to "16" characters. (Naming Convention) document.sv(21): Warning 27288: the length of variable name "dv" should be in the range of "3" to "16" characters. (Naming Convention) document.sv(23): Warning 27288: the length of variable name "t" should be in the range of "3" to "16" characters. (Naming Convention) document.sv(24): Warning 27288: the length of variable name "i" should be in the range of "3" to "16" characters. (Naming Convention) document.sv(27): Warning 27288: the length of variable name "in" should be in the range of "3" to "16" characters. (Naming Convention) document.sv(28): Warning 27288: the length of variable name "t" should be in the range of "3" to "16" characters. (Naming Convention)
27289 (Verilog) FIELD Name

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: field name "%s" does not match regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: string; Argument description: The argument specify regular expression (for clarification, see Regular Expression Help in the end of Rule documentation); Default value: ".*_fld" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the field name in struct or union matches the regular expression specified by users. And this rule only works for System Verilog. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 interface simple; typedef struct { logic l1; int i1_fld; } STU; STU su; endinterface module test(input r, logic b [7:0]; genvar gi; typedef struct { logic l1; int i1; } STU; STU su; typedef union { shortreal l1_fld; int i1; } UN; UN un; endmodule
output q);
nLint reports following if the argument value is (".*_fld"): document.sv(3): Warning 27289: field name "l1" does not match regular expression ".*_fld". (Naming Convention) document.sv(12): Warning 27289: field name "l1" does not match regular expression ".*_fld". (Naming Convention) document.sv(13): Warning 27289: field name "i1" does not match regular expression ".*_fld". (Naming Convention) document.sv(18): Warning 27289: field name "i1" does not match regular expression ".*_fld". (Naming Convention)
27290 (Verilog) FIELD Name Length

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of field name "%s" should range between "%d" and "%d" characters. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: Arguments specify minimum and maximum number of characters of field name; Default value: "3","16" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the length of field name in struct, union or enum is in the specified range. This rule only works for SystemVerilog. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 interface simple; typedef struct { logic l1; int i1; } STU; STU su; endinterface module test(input r, logic b [7:0]; genvar gi; typedef struct { logic l1; int i1; } STU; STU su; typedef union { shortreal s1; int i1; } UN; UN un; endmodule
output q);
nLint reports following if the argument value is ("3","16"): document.sv(3): Warning 27290: the length of field name "l1" should range between "3" and "16" characters. (Naming Convention) document.sv(4): Warning 27290: the length of field name "i1" should range between "3" and "16" characters. (Naming Convention) document.sv(12): Warning 27290: the length of field name "l1" should range between "3" and "16" characters. (Naming Convention) document.sv(13): Warning 27290: the length of field name "i1" should range between "3" and "16" characters. (Naming Convention) document.sv(17): Warning 27290: the length of field name "s1" should range between "3" and "16" characters. (Naming Convention) document.sv(18): Warning 27290: the length of field name "i1" should range between "3" and "16" characters. (Naming Convention)
27293 VARIABLE Name Prefix or Suffix

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable name "%s" does not match to regular expression "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: VARIABLE name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","v_" for Verilog, "PREFIX","v_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the variable name has a recommended prefix or suffix. (VHDL) This rule checks whether the VARIABLE name has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 module test; integer Length; //warning on "Length", using "var_Length" like endmodule
nLint reports following if the argument value is ("PREFIX","v_"): document.v(2): Warning 27293: variable name "Length" does not match to regular expression "v_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety is begin process variable Length : integer := 16; --warning on "Length", using "var_Length" like begin end process; end arch;
nLint reports following if the argument value is ("PREFIX","v_"): document.vhd(7): Warning 27293: VARIABLE name "Length" does not match to regular expression "v_.*". (Naming Convention)
27297 FUNCTION Name Length

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of function name "%s" is unconventional and should be in the range from %d to %d. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of FUNCTION name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of function name; Default value: "3","16" for Verilog, "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the length of the function name is in the specified range. (VHDL) This rule checks whether the length of the FUNCTION name is in the specified range. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module test; function [12:0] mu; //warning on "mu" input [12:0] a; input [15:0] b; begin: serialMult reg [5:0] mcnd,mpy; mpy = b[5:0]; mcnd = a[5:0]; mu=0; repeat(6) begin if(mpy[0]) mu = mu + {mcnd,6'b000000}; mu = mu >> 1; mpy = mpy >> 1; end end endfunction endmodule
nLint reports following if the argument value is ("3","16"): document.v(3): Warning 27297: the length of function name "mu" is unconventional and should be in the range from 3 to 16. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is function func_add_0123456789 --warning on "func_add_0123456789" ( a : integer; b : integer ) return integer is begin end func_add_0123456789; begin
10
end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(5): Warning 27297: the length of FUNCTION name "func_add_0123456789" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27299 FUNCTION Name Case

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: function "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: FUNCTION "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the function names are all in lower (or upper) case. (VHDL) This rule checks whether the FUNCTION names are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test; function Func_add; //warning on "Func_add" input a; input b; begin end endfunction endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(2): Warning 27299: function "Func_add" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is function Func_add --warning on "Func_add" ( a : integer; b : integer ) return integer is begin end Func_add; begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(5): Warning 27299: FUNCTION "Func_add" should be named in CASE_LOWER case. (Naming Convention)
27301 FUNCTION Name Prefix or Suffix

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: function name "%s" does not match to regular expression "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: FUNCTION name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","f_" for Verilog, "PREFIX","f_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the function name has a recommended prefix or suffix. (VHDL) This rule checks whether the FUNCTION name has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test; function add; //warning on "add", using "f_add" like input a; input b; begin end endfunction endmodule
nLint reports following if the argument value is ("PREFIX","f_"): document.v(2): Warning 27301: function name "add" does not match to regular expression "f_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is function add --warning on "add", using "f_add" like ( a : integer; b : integer ) return integer is begin end add; begin end arch;
nLint reports following if the argument value is ("PREFIX","f_"): document.vhd(5): Warning 27301: FUNCTION name "add" does not match to regular expression "f_.*". (Naming Convention)
27305 (Verilog) TASK Name Length 27305 (VHDL) PROCEDURE Name Length
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the length of task name "%s" is unconventional and should be in the range from %d to %d. (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of PROCEDURE name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of PROCEDURE name; Default value: "3","16" for Verilog, "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the length of the task name is in the specified range. (VHDL) This rule checks whether the length of the PROCEDURE name is in the specified range. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; task Check_0123456789012; //warning on "Check_0123456789012" begin end endtask endmodule
nLint reports following if the argument value is ("3","16"): document.v(2): Warning 27305: the length of task name "Check_0123456789012" is unconventional and should be in the range from 3 to 16. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety is procedure Check_0123456789012 --warning on "Check_0123456789012" ( a : in integer; b : in integer ) is begin end Check_0123456789012; begin end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(5): Warning 27305: the length of PROCEDURE name "Check_0123456789012" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27307 (Verilog) TASK Name Case 27307 (VHDL) PROCEDURE Name Case
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: task "%s" should be named in %s case. (VHDL) <filename>(<line no.>): <severity> <rule no.>: PROCEDURE "%s" should be named in %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for Verilog, "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the task names are all in lower (or upper) case. (VHDL) This rule checks whether the PROCEDURE names are all in lower (or upper) case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; task Check; //warning on "Check" begin end endtask endmodule
nLint reports following if the argument value is ("CASE_LOWER"): document.v(2): Warning 27307: task "Check" should be named in CASE_LOWER case. (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is procedure Check --warning on "Check" ( a : in integer; b : in integer ) is begin end Check; begin end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(5): Warning 27307: PROCEDURE "Check" should be named in CASE_LOWER case. (Naming Convention)
27309 (Verilog) TASK Name Prefix or Suffix 27309 (VHDL) PROCEDURE Name Prefix or Suffix
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: task name "%s" does not match to regular expression "%s". (VHDL) <filename>(<line no.>): <severity> <rule no.>: PROCEDURE name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","p_" for Verilog, "PREFIX","p_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the task name has a recommended prefix or suffix. (VHDL) This rule checks whether the PROCEDURE name has a recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; task Check; //warning on "Check", using "p_Check" like begin end endtask endmodule
nLint reports following if the argument value is ("PREFIX","p_"): document.v(2): Warning 27309: task name "Check" does not match to regular expression "p_.*". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is procedure Check --warning on "Check", using "p_Check" like ( a : in integer; b : in integer ) is begin end Check; begin end arch;
nLint reports following if the argument value is ("PREFIX","p_"): document.vhd(5): Warning 27309: PROCEDURE name "Check" does not match to regular expression "p_.*". (Naming Convention)
27313 (VHDL) BLOCK Name Length

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of BLOCK name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of BLOCK name; Default value: "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the length of the BLOCK name is in the specified range. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port (s1: in bit; s2: out bit; s3: inout bit; s4: buffer bit); end top_ety; architecture arch of top_ety is begin b_01234567890123456: block --warning on "b_01234567890123456" signal s : bit; begin end block b_01234567890123456; end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(10): Warning 27313: the length of BLOCK name "b_01234567890123456" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27315 (VHDL) BLOCK Name Case

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: BLOCK "%s" should be named with %s case. Configurable Parameter Rule group: Naming Convention; Argument type: (CASE_UPPER, CASE_LOWER); Argument description: If the argument is set to CASE_UPPER, the rule checks whether the string is in upper case. If the argument is set to CASE_LOWER, the rule checks whether the string is in lower case. Default value: "CASE_LOWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the BLOCK names are all in lower (or upper) case. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port (s1: in bit; s2: out bit; s3: inout bit; s4: buffer bit); end top_ety; architecture arch of top_ety is begin BL: block --warning on "BL" signal s : bit; begin end block BL; end arch;
nLint reports following if the argument value is ("CASE_LOWER"): document.vhd(10): Warning 27315: BLOCK "BL" should be named with CASE_LOWER case. (Naming Convention)
27317 (VHDL) BLOCK Name Prefix or Suffix

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: BLOCK name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","blk_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the BLOCK name has a recommended prefix or suffix. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end top_ety; architecture arch of top_ety is begin ladd: block is --warning on "ladd", using "blk_add" like signal s : bit; begin end block ladd; blk_b2: block is --no warning here begin end block blk_b2; end arch;
nLint reports following if the argument value is ("PREFIX","blk_"): document.vhd(6): Warning 27317: BLOCK name "ladd" does not match to regular expression "blk_.*". (Naming Convention)
27321 (VHDL) ATTRIBUTE Name Length

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the length of ATTRIBUTE name "%s" is unconventional and should be in the range from %d to %d. Configurable Parameter Rule group: Naming Convention; Argument type: integer, integer; Argument description: specify the least number by the first argument and the most number by the second argumentfor the number of characters of ATTRIBUTE name; Default value: "3","16" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the length of the ATTRIBUTE name is in the specified range. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is port (s1: in bit; s2: out bit; s3: inout bit; s4: buffer bit); type Byte is range 0 to 255; attribute attr_string_01234567890 : string; --warning on "attr_string_01234567890" attribute attr_string_01234567890 of top_ety : entity is "abc"; end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("3","16"): document.vhd(8): Warning 27321: the length of ATTRIBUTE name "attr_string_01234567890" is unconventional and should be in the range from 3 to 16. (Naming Convention)
27325 (VHDL) ATTRIBUTE Name Prefix or Suffix

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: ATTRIBUTE name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "PREFIX","attr_" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether the ATTRIBUTE name has a recommended prefix or suffix. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is port (s1: in bit; s2: out bit; s3: inout bit; s4: buffer bit); type Byte is range 0 to 255; attribute ex_name : string; --warning on "ex_name", using "attr_ex_name" attribute ex_name of top_ety : entity is "abc"; end top_ety; architecture arch of top_ety is begin end arch;
nLint reports following if the argument value is ("PREFIX","attr_"): document.vhd(8): Warning 27325: ATTRIBUTE name "ex_name" does not match to regular expression "attr_.*". (Naming Convention)
27327 (VHDL) Mixed Sequential and Combinational Logic in a PROCESS

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: mixed sequential and combinational logic infered in a process. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether mixed sequential and combinational logic infered in a process. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 entity top_ety is end top_ety; architecture rtl of top_ety is signal ERSTN,ECLK,pipe1,pipe2,pipe3,pipe1_ack,pipe2_ack,elack : bit; begin process(ECLK, pipe1, pipe2, pipe1_ack, pipe2_ack) --warning here begin if ( pipe1 = '1') then pipe1_ack <= elack; else pipe1_ack <= '0'; end if; if ( pipe2 = '1') then pipe2_ack <= elack; else pipe2_ack <= '0'; end if; if ( ERSTN = '0' ) then pipe2 <= '0'; pipe3 <= '0'; elsif ( ECLK'event and ECLK = '1' ) then if ( pipe1_ack = '1' ) then pipe2 <= pipe1; end if; if ( pipe2_ack = '1' ) then pipe3 <= pipe2; end if; end if; end process; end rtl;
nLint reports: document.vhd(8): Warning 27327: mixed sequential and combinational logic infered in a process. (Design Style)
27328 (Verilog) Combinational Logic Found in Sequential Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: combinational expression or statement not allowed in sequential block. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any combinational expression or statement mixed in sequential block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (clock, reset, a, b, c, d, in1, in2, out); input clock; input reset; input a, b, c, d, in1, in2; output out; reg out; always @(posedge clock) begin if ( ( a & b )== 0 ) // warning here out = 0; else if ( c & d ) // warning here out = 1; else out = ( in1 & in2 ); // warning here end endmodule
nLint reports: document.v(9): Warning 27328: combinational expression or statement not allowed in sequential block. (Design Style) document.v(11): Warning 27328: combinational expression or statement not allowed in sequential block. (Design Style) document.v(14): Warning 27328: combinational expression or statement not allowed in sequential block. (Design Style)
27329 (Verilog) Unrecommended Continuous Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: there is directly continuous assignment on net "%s", which is unrecommended. Configurable Parameter Rule group: Design Style; Argument type: (NET_DECL, CONTINUOUS); Argument description: select NET_DECL to specify that only net declaration assignment will be checked; select CONTINUOUS to specify that all continuous assignment including that in net declaration will be checked; Default value: "NET_DECL" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is direct and unrecommended continuous assignment. For continuous assignment in net declaration, it is a direction assignment of a net. In RTL code, it will induce a buffer that designer may not expect after synthesis; in gate level, such code will cause trouble for APR tool. For general continuous assignment, it can always be replaced with equivalent always block statements, since the assignment generally simulates slower than always block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test; wire b; wire a = b; //warning here endmodule module test_nowarning; wire b; wire a; assign a = b; //no warning here endmodule
nLint reports following if the argument value is ("NET_DECL"): document.v(3): Warning 27329: there is directly continuous assignment on net "a", which is unrecommended. (Design Style)
27331 (VHDL) Constrained Return Expression in Unconstrained Return Type Function

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: there is constrained return expression "%s" in unconstrained return type function. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) Constrained return expression does not match unconstrained return type. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is end top_ety; architecture rtl of top_ety is function make_mask (length : bit_vector(1 downto 0)) return bit_vector is begin case length is when "00" => return "000"; --warning here when "01" => return "001"; when "10" => return "010"; when "11" => return "100"; end case; end make_mask; begin end rtl;
nLint reports: document.vhd(8): Warning 27331: there is constrained return expression ""000"" in unconstrained return type function. (Design Style) document.vhd(9): Warning 27331: there is constrained return expression ""001"" in unconstrained return type function. (Design Style) document.vhd(10): Warning 27331: there is constrained return expression ""010"" in unconstrained return type function. (Design Style) document.vhd(11): Warning 27331: there is constrained return expression ""100"" in unconstrained return type function. (Design Style)
27333 (Verilog) Variables Declared in Automatic Tasks Used with Incorrect Constructs
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable "%s" should not be assigned or referenced in automatic task "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) Variables declared in automatic tasks are de-allocated at the end of the task invocation, so they should not be used with constructs that would refer to them after that point. For example, variables declared in automatic tasks should not be used when the assigned values are used in nonblocking assignments or procedural continuous assignments, referenced by procedural continuous assignments or procedural force statements, referenced in intra-assignment event controls of nonblocking assignments, or traced with system tasks such as $monitor and $dumpvars. Example
(Verilog) ///////////////example : document.v2k//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module test; task automatic ALU; input clock; input [1:0] ctrl; input [12:0] a; input [12:0] b; output [12:0] y; begin case (ctrl) 2'b00: y <= a + b; //warning on y 2'b01: y <= @ ( posedge clock ) a - b; //warning on y, clock 2'b10: force y = a + b; //warning a, b 2'b11: assign y = a + b; //warning on a, b, y endcase $monitor($time,,,"a=%d,b=%d,y=%d",a,b,y); //warning a, b, y end endtask endmodule
nLint reports: document.v2k(12): Warning 27333: variable "y" should not in automatic task "ALU". (Language Construct) document.v2k(14): Warning 27333: variable "y" should not in automatic task "ALU". (Language Construct) document.v2k(14): Warning 27333: variable "clock" should referenced in automatic task "ALU". (Language Construct) document.v2k(16): Warning 27333: variable "a" should not in automatic task "ALU". (Language Construct) document.v2k(16): Warning 27333: variable "b" should not in automatic task "ALU". (Language Construct) document.v2k(18): Warning 27333: variable "y" should not in automatic task "ALU". (Language Construct) document.v2k(18): Warning 27333: variable "a" should not in automatic task "ALU". (Language Construct) document.v2k(18): Warning 27333: variable "b" should not
be assigned or referenced be assigned or referenced not be assigned or be assigned or referenced be assigned or referenced be assigned or referenced be assigned or referenced be assigned or referenced
in automatic task document.v2k(20): in automatic task document.v2k(20): in automatic task document.v2k(20): in automatic task
"ALU". (Language Construct) Warning 27333: variable "a" should not be assigned or referenced "ALU". (Language Construct) Warning 27333: variable "b" should not be assigned or referenced "ALU". (Language Construct) Warning 27333: variable "y" should not be assigned or referenced "ALU". (Language Construct)
27335 Synopsys Directives 'translate_off'/'translate_on' Used

Message <filename>(<line no.>): <severity> <rule no.>: statement/expression used in translate_off/translate_on may cause mismatch between pre-synthesis and post-synthesis. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description Statement/expression in directive translate_off/translate_on may cause mismatch between presynthesis and post-synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module test (a,b,c,SADDR,E21_REG_BPP,y,SOFFSET); input a,b,c; input [03:00] SADDR; input [01:00] E21_REG_BPP; output y; output [03:00] SOFFSET; reg [03:00] SOFFSET; assign y = // synopsys translate_off a | b | // synopsys translate_on c; always @(E21_REG_BPP) case (E21_REG_BPP[01:00]) 2'b00 : SOFFSET[03:00] <= SADDR[03:00]; 2'b01 : SOFFSET[03:00] <= {SADDR[02:00], 1'b0}; 2'b11 : SOFFSET[03:00] <= {SADDR[01:00], 2'b0}; //synopsys translate_off default : SOFFSET[03:00] <= 0; //synopsys translate_on endcase endmodule
nLint reports: document.v(11): Warning 27335: statement/expression used in translate_off/translate_on may cause mismatch between pre-synthesis and postsynthesis. (Simulation,Synthesis) document.v(21): Warning 27335: statement/expression used in translate_off/translate_on may cause mismatch between pre-synthesis and postsynthesis. (Simulation,Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is port (a,b,c: in bit; SADDR: in bit_vector(3 downto 0); y : out bit; SOFFSET: out bit_vector(3 downto 0)); end top_ety;
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
architecture arch of top_ety is signal E21_REG_BPP : bit_vector(1 downto 0); begin y <= --synopsys translate_off a or b or --synopsys translate_on c; process(E21_REG_BPP) begin case E21_REG_BPP(1 downto 0) is when "00" => SOFFSET <= SADDR; when "01" => SOFFSET <= SADDR(2 downto 0) & '0'; when "11" => SOFFSET <= SADDR(1 downto 0) & "00"; --synopsys translate_off when others => SOFFSET <= "0000"; --synopsys translate_on end case; end process; end arch;
nLint reports: document.vhd(13): Warning 27335: statement/expression translate_off/translate_on may cause mismatch between synthesis. (Simulation,Synthesis) document.vhd(23): Warning 27335: statement/expression translate_off/translate_on may cause mismatch between synthesis. (Simulation,Synthesis)
used in pre-synthesis and postused in pre-synthesis and post-
27337 (Verilog) Synopsys Directives 'full_case' Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: case statement with both full_case directive and default clause may cause mismatch between pre-synthesis and post-synthesis. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: ( CHECK_FULL_CASE, CHECK_UNI_PRI, CHECK_BOTH); Argument description: select CHECK_FULL_CASE to check Synopsys pragma full_case. select CHECK_UNI_PRI to check unique and priority; select CHECK_BOTH to check both; Default value: "CHECK_FULL_CASE" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) Case statement with both full_case directive and default clause may cause mismatch between pre-synthesis and post-synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (sel,b); input [1:0] sel; output [1:0] b; reg [1:0] b; always @(sel) case(sel) //synopsys full_case , warning here 2'b00: b = 2'b01; 2'b01: b = 2'b10; default: b = 2'b11; endcase endmodule
nLint reports following if the argument value is ("CHECK_FULL_CASE"): document.v(7): Warning 27337: case statement with both full_case directive and default clause may cause mismatch between pre-synthesis and post-synthesis. (Simulation,Synthesis) ///////////////example : document1.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module test(input bit sel1, sel2, sel3); int a, b, c; always_comb case (sel1) //synopsys full_case 1'b1: a = 0; default: a = 1; endcase always_comb unique case (sel2) 1'b1: b = 0; default: b = 1; endcase
//warning here if CHECK_UNI_PRI is specified
always_comb priority case (sel3) //warning here if CHECK_UNI_PRI is specified 1'b1: c = 0; default: c = 1; endcase endmodule
nLint reports following if the argument value is ( CHECK_UNI_PRI): document1.sv(12): Warning 27337: case statement with both full_case directive and default clause may cause mismatch between pre-synthesis and post-synthesis. (Simulation,Synthesis) document1.sv(18): Warning 27337: case statement with both full_case directive and default clause may cause mismatch between pre-synthesis and post-synthesis. (Simulation,Synthesis)
27338 (Verilog) Mixed Signed and Unsigned Operands Not Recommended

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signed operand "%s" should not be mixed with unsigned operand "%s". Configurable Parameter Rule group: Coding Style; Argument type: (IGNORE_SIGNED_POSITIVE_CONST, CHECK_ALL); Argument description: select CHECK_ALL to specify that all signed operands mixed with unsigned operands are not permitted; select IGNORE_SIGNED_POSITIVE_CONST to specify that unsigned operands mixed with signed positive constant does not violate this rule; Default value: "IGNORE_SIGNED_POSITIVE_CONST" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any signed operands are mixed with unsigned operands in an operation expression. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test; logic logic logic logic integer logic always v1 = v2 = v3 = end endmodule [7:0] v1, v2, v3; a, b; c;
signed
en; i; [31:0] j; begin a * b; a + c; en? i : j;
//OK //Warning on 'a' and 'c' //Warning on 'i' and 'j'
nLint reports following if the argument value is ("IGNORE_SIGNED_POSITIVE_CONST"): document.sv(14): Warning 27338: signed operand "c" should not be mixed with unsigned operand "a". (Coding Style) document.sv(15): Warning 27338: signed operand "i" should not be mixed with unsigned operand "j". (Coding Style) ///////////////example : document2.sv//////////// 1 module test; 2 parameter reg signed [7:0] A = 3; 3 4 logic [3:0] b, c1, c2, c3; 5 6 always begin 7 c1 = b - A; //No warning if select "IGNORE_SIGNED_POSITIVE_CONST" 8 c2 = b * 3; //No warning if select "IGNORE_SIGNED_POSITIVE_CONST" 9 c3 = b / 3'sb011; //No warning if select "IGNORE_SIGNED_POSITIVE_CONST"
10 11
end endmodule
nLint reports following if the argument value is ( IGNORE_SIGNED_POSITIVE_CONST): ///////////////example : document3.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 module test; parameter reg signed [7:0] A = 3; logic [3:0] b, c1, c2, c3; always begin c1 = b - A; c2 = b * 3; c3 = b / 3'sb011; end endmodule
//Warning if select "CHECK_ALL" //Warning if select "CHECK_ALL" //Warning if select "CHECK_ALL"
nLint reports following if the argument value is ( CHECK_ALL): document3.sv(7): Warning 27338: signed operand "A" should not be mixed with unsigned operand "b". (Coding Style) document3.sv(8): Warning 27338: signed operand "3" should not be mixed with unsigned operand "b". (Coding Style) document3.sv(9): Warning 27338: signed operand "3'sb011" should not be mixed with unsigned operand "b". (Coding Style)
27339 (Verilog) Sign/Unsigned Conversion in Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s to %s assignment occurs. Configurable Parameter Rule group: Coding Style; Argument type: (IGNORE_SIGNED_POSITIVE_CONST, CHECK_ALL); Argument description: select CHECK_ALL to specify that all conversions between signed and unsigned expressions are not permitted; select IGNORE_SIGNED_POSITIVE_CONST to specify that the conversion of signed positive constant to unsigned variable does not violate this rule; Default value: "CHECK_ALL" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any signed/unsigned conversion in assignment. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; wire [7:0] regA; reg signed [7:0] regS; always @( regA ) regS = regA; //warning here endmodule
nLint reports following if the argument value is ("CHECK_ALL"): document.v(6): Warning 27339: unsigned to signed assignment occurs. (Coding Style) ///////////////example : document2.v2k//////////// 1 module test(sig1, sig2, sig3); 2 input [2:0] sig1, sig2, sig3; 3 wire [2:0] sig1, sig2, sig3; 4 5 assign sig1 = 3'sb011; //no warning if select argument "IGNORE_SIGNED_POSITIVE_CONST" 6 assign sig2 = 3; //no warning if select argument "IGNORE_SIGNED_POSITIVE_CONST" 7 assign sig3 = -3; //warning anyway 8 endmodule
nLint reports following if the argument value is ( IGNORE_SIGNED_POSITIVE_CONST): document2.v2k(7): Warning 27339: signed to unsigned assignment occurs. (Coding Style) ///////////////example : document3.v2k//////////// 1 2 3 4 5 6 7 8 module test(sig1, sig2, sig3); input [2:0] sig1, sig2, sig3; wire [2:0] sig1, sig2, sig3; assign sig1 = 3'sb011; assign sig2 = 3; assign sig3 = -3; endmodule //warning if select argument "CHECK_ALL" //warning if select argument "CHECK_ALL" //warning anyway
nLint reports following if the argument value is ( CHECK_ALL):
document3.v2k(5): Warning 27339: signed to unsigned assignment occurs. (Coding Style) document3.v2k(6): Warning 27339: signed to unsigned assignment occurs. (Coding Style) document3.v2k(7): Warning 27339: signed to unsigned assignment occurs. (Coding Style)
27341 (VHDL) Place Entity, Architecture and Configuration into the Same File
Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: %s "%s" is detected in different file of entity "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any architecture or configuration declared in different files of entity declaration. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 --a.vhd entity test is --warning here end entity test; --b.vhd architecture arch of test is begin end architecture arch;
27343 (Verilog) Integer Type Used on Port Instance

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: integer type should not be used on port instance "%s". Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any integer type used on port instance. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (a,c); input a; output c; integer d; wire c,e; assign e = a & c; submod sub(.a(a),.b(d),.c(c)); endmodule module submod (a,b,c); input [31:0] a,b; output [31:0]c; wire [31:0] c; assign c = a | b; endmodule //warning here
nLint reports: document.v(8): Warning 27343: integer type should not be used on port instance "d". (Design Style)
27345 (Verilog) Size Constant should be Specified for Integer

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: a size constant should be specified for integer "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) A size constant should be specified for integer constant. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test (a,b,c,d); input [1:0] a,b; output [1:0] c; output [2:0] d; reg [1:0] c; reg [2:0] d; always @ ( a ) if (a) c = 1; //warning here, c= 2'b01 desired else c = a; always @ ( b ) d = b + 3; //warning here, d = b + 2'b11 desired endmodule
nLint reports: document.v(10): Warning 27345: a size constant should be specified for integer "1". (Language Construct) document.v(15): Warning 27345: a size constant should be specified for integer "3". (Language Construct)
27347 Nested Synopsys Translate_on or Translate_off Directive Found

Message <filename>(<line no.>): <severity> <rule no.>: nested synopsys translate_on or translate_off directive couldn't be used. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any nested synopsys translate_on or translate_off directive. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module ALUB; //synopsys translate_off //synopsys translate_off //warning here //synopsys translate_on //synopsys translate_on //warning here endmodule
nLint reports: document.v(3): Warning 27347: nested synopsys translate_on or translate_off directive couldn't be used. (Coding Style) document.v(5): Warning 27347: nested synopsys translate_on or translate_off directive couldn't be used. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is begin --synopsys translate_off --synopsys translate_off --warning here --synopsys translate_on --synopsys translate_on --warning here end arch;
nLint reports: document.vhd(7): Warning 27347: nested synopsys translate_on or translate_off directive couldn't be used. (Coding Style) document.vhd(9): Warning 27347: nested synopsys translate_on or translate_off directive couldn't be used. (Coding Style)
27349 (Verilog) No Comment Added after End Statement

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: a comment should be added after %s statement. Configurable Parameter Rule group: Coding Style; Argument type: (END,ENDCASE,ENDCONFIG,ENDFUNCTION,ENDGENERATE,ENDMODULE,ENDPRIM ITIVE,ENDSPECIFY,ENDTABLE,ENDTASK); Argument description: It is a multiple select argument. Select any of them to specify to check the comment following the keyword must be provided. Default value: "END" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any comment added after end statement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module test (sel,a,b,c); input a,b,sel; output c; reg c; always @ (a or b or sel) begin case(sel) 1'b0: c = a & b; 1'b1: c = a | b; default: c = 1'b0; endcase //no warning here, warning if "ENDCASE" is in argument end //no warning here, warning if there is no this comment endmodule //no warning here, warning if "ENDMODULE" is in argument //Default: Checking if there is any comment after "END" statement. //Argument should be set if the violation is expected.
nLint reports following if the argument value is ("END"):
27351 Operator Not Allowed

Message <filename>(<line no.>): <severity> <rule no.>: operator "%s" should not be used. Configurable Parameter Rule group: Coding Style; Argument type: (UNARY_PLUS, BINARY_PLUS, UNARY_MINUS, BINARY_MINUS, MULTIPLY, DIVIDE, MOD, POWER, CHECK_PARAMETER); Argument description: UNARY_PLUS means unary operator +, eg. +3, BINARY_PLUS means binary operator +, eg. 3+3, UNARY_MINUS means unary operator -, eg. -3, BINARY_MINUS means binary operator -, eg. 3-3, MULTIPLY means *, DIVIDE means /, MOD means % or mod, POWER means **, CHECK_PARAMETER means check the rule in parameter or not Default value: "UNARY_PLUS, UNARY_MINUS, MULTIPLY, DIVIDE, MOD, POWER" for Verilog, "UNARY_PLUS, UNARY_MINUS, MULTIPLY, DIVIDE, MOD, POWER" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any operators specified in the argument list are used. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test; integer a, b; integer out1; assign out1 = a * b ; //warning here assign out1 = a / b ; //warning here endmodule
nLint reports following if the argument value is ("UNARY_PLUS, UNARY_MINUS, MULTIPLY, DIVIDE, MOD, POWER"): document.v(5): Warning 27351: operator "*" should not be used. (Coding Style) document.v(6): Warning 27351: operator "/" should not be used. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety is signal x, z, mi : integer ; begin process begin x <= z * mi; --warning here end process; end arch;
nLint reports following if the argument value is ("UNARY_PLUS, UNARY_MINUS, MULTIPLY, DIVIDE, MOD, POWER"): document.vhd(9): Warning 27351: operator "*" should not be used. (Coding Style)
27353 (Verilog) No Escape Name Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: escape name "%s" should not be used. Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: The argument is a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). If the escape name satisfying the regular expression, the violation will not be reported. If the argument is empty, all the escape names will be reported; Default value: "" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any escape name. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 // vlog_val="\.*.*" if the escape name has "*", then don't report. module test; reg \cpu[0] ; //warning here reg *22 ; //no warning because has "*" endmodule
nLint reports following if the argument value is ("\.*.*"): document.v(3): Warning 27353: escape name "\cpu[0] " should not be used. (Coding Style)
27355 (Verilog) Conflict of Hierarchy Interconnection

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s signal "%s" is connected to %s port "%s". Configurable Parameter Rule group: Block Interconnect; Argument type: (INPUT_SIGNAL_TO_OUTPUT_PORT, OUTPUT_SIGNAL_TO_INPUT_PORT); Argument description: Select INPUT_SIGNAL_TO_OUTPUT_PORT to check whether an input signal is connected to an output port. Select OUTPUT_SIGNAL_TO_INPUT_PORT to check whether an output signal is connected an input port; Default value: "INPUT_SIGNAL_TO_OUTPUT_PORT" for Verilog; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there are any connection conflicts between input/output signals of the module and ports of instantiated instances. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test(ina,inb,out); input ina,inb; output out; wire out; endmodule module top(INA,INB,OUT); input INA,INB; output OUT; test u_test(.out(INA),.inb(OUT),.ina(INB)); //warning on input INA is connected to output port .out //warning on output OUT is connected to input port .inb endmodule
nLint reports following if the argument value is ("INPUT_SIGNAL_TO_OUTPUT_PORT, OUTPUT_SIGNAL_TO_INPUT_PORT"): document.v(10): Warning 27355: output signal "OUT" is connected to input port "inb". (Coding Style) document.v(10): Warning 27355: input signal "INA" is connected to output port "out". (Coding Style)
27356 (Verilog) Block Assembly Error in the Same Hierarchy Level

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: wire "%s" connects to %s port "%s" and %s port "%s" without %s. Configurable Parameter Rule group: Block Interconnect; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any input-to-input connections without drivers or there are any output-to-output connections. Example
(Verilog) ///////////////example : document1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 //sample case for checking input module test; wire a, b, c; and u1 (c, a, b); test1 u2 (a); test2 u3 (c); endmodule module test1(a); //warning here input a; wire a; endmodule module test2(a); input a; wire a; endmodule
nLint reports: document1.v(10): Warning 27356: wire "test.a" connects to input port "test.u2.a" and input port "test.u3.a" without any drivers. (Block Interconnect) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 //sample case for checking output module test(c); input c; wire a,b,c; test1 u1 (a); test2 u2 (b); and u3 (a, b, c); endmodule module test1(a); //warning here output a; wire a; endmodule module test2(a); output a; wire a; endmodule
nLint reports: document2.v(11): Warning 27356: wire "test.a" connects to output port "test.u1.a" and output port "test.u2.a" without any loads. (Block Interconnect)
27357 (Verilog) Module Defined More than Once

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: module "%s" should not be redefined. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any module is redefined in source files and library files. Please note: 1. Since the checking scope of this rule includes all the library cells, you don't need to set "lint_cell_lib" option; 2. If you use "-y" to specify the library cell, this rule will only check the file name in the corresponding directory and it will not parse any file, because for "-y", the file name should be the same as the module name; 3. When checking this rule, you should not use "-r All +r 27357" style, but use "-rs <rs file>" style instead. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 //file "1.f" -v a.v b.v //file "a.v" module A; //warning here endmodule module A; endmodule //file "b.v" module B; A aa (); endmodule
nLint reports: a.v(1): Warning 27357: module "A" should not be redefined. (Coding Style)
27359 (Verilog) Unused Macro

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: macro "%s" is defined but not used. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any macro is unused. If a macro is defined in a module, nLint will report violation if it is never referenced before the end of the module. If a macro is defined outside a module, nLint will report violation if and only if it is never referenced in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 `define TWO 2 `define THREE 3 module test(sel,a,c); input [1:0] a ; input [2:0] sel; output [1:0] c; reg [1:0] c; `define FOUR 4 `define FIVE 5 always begin case (sel) `TWO: c=a; `FOUR: c=~a; default: c=2'b00; endcase end endmodule
nLint reports: document.v(2): Warning 27359: macro "THREE" is defined but not used. (Design Style) document.v(11): Warning 27359: macro "FIVE" is defined but not used. (Design Style)
27361 No Falling Active Clock Used

Message <filename>(<line no.>): <severity> <rule no.>: falling active clock "%s" should not be used. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any falling active clock used. (VHDL) Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module dffn( clk, d, q ); input clk, d; output q; reg q; always @( negedge clk ) //warning here q <= d; endmodule module test( clock, d, q ); input clock; input [3:0] d; output [3:0] q; wire clkn; assign clkn = ~clock; dffn i_dffn_1( clkn, d[0], q[0] ); dffn i_dffn_2( clock, d[1], q[1] ); endmodule
nLint reports: document.v(5): Warning 27361: falling active clock "clk" should not be used. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all; entity top_ety is port ( Clock : in std_logic; A1, A2 : in bit; Y1, Y2 : out bit); end top_ety; architecture RTL of top_ety is begin process(Clock, A2) begin if falling_edge ( Clock ) then Y2 <= A2; end if; end process; end RTL;
--warning here
nLint reports: document.vhd(14): Warning 27361: falling active clock "Clock" should not be used.
(Design Style)
27363 (Verilog) 'for' Loop Detected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: for-loop is detected. Configurable Parameter Rule group: Coding Style; Argument type: (CHECK_GENERATEFOR, IGNORE_GENERATEFOR); Argument description: select CHECK_GENERATEFOR to check generate for-loop statements; select IGNORE_GENERATEFOR to ignore generate for-loop statements; Default value: "IGNORE_GENERATEFOR" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checkes whether a for-loop is used in design when the argument is set as CHECK_GENERATEFOR. This rule will not check the for-loop with a generate statement when the argument is set as IGNORE_GEREATEFOR. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (clk, d, q); input clk; input [7:0] d; output [7:0] q; reg [7:0] q; integer i; always @( posedge clk ) for ( i=0; i<8; i=i+1 ) //warning here q[7-i] <= d[i]; endmodule // SSHqa03600.v
nLint reports following if the argument value is ("IGNORE_GENERATEFOR"): document.v(8): Warning 27363: for-loop is detected. (Coding Style)
27365 (Verilog) Casex or Casez Detected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: no %s statement allowed. Configurable Parameter Rule group: Coding Style; Argument type: (CASEX, CASEZ); Argument description: select CASEX to specify that casex statement is not allowed; select CASEZ to specify that casez statement is not allowed; Default value: "CASEX" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any casex or casez statement used. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test (out0,in1,in2,in3,sel); input [1:0] in1,in2,in3,sel; output [1:0] out0; reg [1:0] out0; always @( in1 or in2 or sel) begin casex(sel) //warning here 2'b00: out0 = in1; 2'b01: out0 = in2; 2'b10: out0 = in3; default: out0 = in1; endcase end endmodule // SSHqa03598.v
nLint reports following if the argument value is ("CASEX"): document.v(7): Warning 27365: no casex statement allowed. (Coding Style)
27367 (Verilog) Conditional Assignment Detected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: no conditional assignment allowed, using if-then-else instead. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any conditional assignment used, it generally simulates slower than if-then-else. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 module test (out0,in1,in2,sel); input sel; input [1:0] in1,in2; output [1:0] out0; reg [1:0] out0; always @( in1 or in2 or sel) out0 = sel ? in1 : in2; //warning here endmodule
nLint reports: document.v(8): Warning 27367: no conditional assignment allowed, using if-thenelse instead. (Coding Style)
27369 Integer Type Object Detected

Message <filename>(<line no.>): <severity> <rule no.>: integer type object "%s" should not be used. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any integer type object used. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test; parameter n=8; //no warning, not an integer integer a; //warning here function func1; input f1; integer f2; //warning here func1=0; endfunction endmodule
nLint reports: document.v(3): Warning 27369: integer type object "a" should not be used. (Design Style) document.v(7): Warning 27369: integer type object "f2" should not be used. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 entity top_ety is generic (n: integer :=10); --warning here end top_ety; architecture arch of top_ety is type BYTE_LENGTH is range 0 to 255; signal a: integer; signal b: BYTE_LENGTH; signal clk: bit; --warning here --warning here
function func1 return integer is variable f1: integer; --warning here begin return 0; end; begin process (clk) variable c: BYTE_LENGTH; --warning here begin end process; end arch;
nLint reports: document.vhd(2): Warning 27369: integer type object "n" should not be used. (Design Style) document.vhd(8): Warning 27369: integer type object "a" should not be used.
(Design Style) document.vhd(9): Warning 27369: integer type object "b" should not be used. (Design Style) document.vhd(13): Warning 27369: integer type object "f1" should not be used. (Design Style) document.vhd(19): Warning 27369: integer type object "c" should not be used. (Design Style)
27371 Synopsys Synthesis Directive Detected

Message <filename>(<line no.>): <severity> <rule no.>: synopsys synthesis directive "%s" should not be used. Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: any valid synopsys directives can be specified in the string argument separated by comma; any directive specified will be checked; Default value: "parallel_case,full_case" for Verilog, "parallel_case,full_case" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any synopsys synthesis directive used. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 module test; // synopsys parallel_case // warning here // synopsys full_case // warning here endmodule
nLint reports following if the argument value is ("parallel_case,full_case"): document.v(2): Warning 27371: synopsys synthesis directive "// synopsys parallel_case" should not be used. (Coding Style) document.v(4): Warning 27371: synopsys synthesis directive "// synopsys full_case" should not be used. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 entity top_ety is end top_ety; architecture arch of top_ety is -- synopsys parallel_case -- warning here -- synopsys full_case -- warning here begin end arch;
nLint reports following if the argument value is ("parallel_case,full_case"): document.vhd(5): Warning 27371: synopsys synthesis directive "-- synopsys parallel_case" should not be used. (Coding Style) document.vhd(7): Warning 27371: synopsys synthesis directive "-- synopsys full_case" should not be used. (Coding Style)
27373 Next State Name Prefix or Suffix

Message <filename>(<line no.>): <severity> <rule no.>: next register name "%s" does not match to regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: (PREFIX, SUFFIX, SUB_STRING, REGEXPR), string; Argument description: Set the first argument as PREFIX, SUFFIX or SUB_STRING to check prefix, suffix or sub-string of a name respectively, and set REGEXPR to check whether a name matches a regular expression (for clarification, see Regular Expression Help in the end of Rule documentation). Specify a string or a regular expression in the second argument for the name to check as specified in the first argument. Default value: "SUFFIX","_ns" for Verilog, "SUFFIX","_ns" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the next state register names have recommended prefix or suffix. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 module fsm(out, in, clock, reset); output out; input in, clock, reset; reg out; reg [1:0] current, next; always @(in or current) begin out = ~current[1] & current[0]; next = 0; if (current == 0) if (in) next = 1; if (current == 1) if (in) next = 3; if (current == 3) if (in) next = 3; else next = 1; end always @(posedge clock or negedge reset) begin if (~reset) current <= 0; else current <= next; //warning here on "next" //good style if using "_ns" //as suffix of current state //register "next" end endmodule
nLint reports following if the argument value is ("SUFFIX","_ns"): document.v(27): Warning 27373: next register name "next" does not match to regular expression ".*_ns". (Naming Convention)
(VHDL)
-------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 entity top_ety is port ( reset : in bit; clock : in bit; in1 : in bit; s: out integer ); end entity top_ety; architecture arch of top_ety is type state_T is (a,b); signal current : state_T :=a; signal next1 : state_T; begin p1: process (current,in1) is begin if (current=a) then if (in1='1') then next1<=b; end if; end if; if (current=b) then if (in1='1') then next1<=a; end if; end if; end process p1; p2: process (clock,reset) is begin if (reset='1') then current<=a; elsif (clock='1') then current<=next1; --warning here on "next1" --good style if using '_ns' --as suffix of current --state register "next1" end if; end process p2; end architecture arch;
nLint reports following if the argument value is ("SUFFIX","_ns"): document.vhd(34): Warning 27373: next register name "next1" does not match to regular expression ".*_ns". (Naming Convention)
27375 IDENTIFIER Name

Message <filename>(<line no.>): <severity> <rule no.>: identifier name "%s" does not follow the regular expression "%s". Configurable Parameter Rule group: Naming Convention; Argument type: string; Argument description: specify regular expression and can be separated by comma; Default value: ".*" for Verilog, ".*" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any identifier name does not follow the argument requirement. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 //set argument with "a.*,.*b" module abc; //begin with 'a', ok reg cba; //warning integer cab; //end with 'b', ok endmodule
nLint reports following if the argument value is ("a.*;.*b"): document.v(3): Warning 27375: identifier name "cba" does not follow the regular expression "a.*;.*b". (Naming Convention)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 --set argument with "a.*,.*b" entity top_ety is end top_ety;
--warning
architecture abc of top_ety is --begin with 'a', ok signal cab : bit; --end with 'b', ok begin end abc;
nLint reports following if the argument value is ("a.*;.*b"): document.vhd(2): Warning 27375: identifier name "top_ety" does not follow the regular expression "a.*;.*b". (Naming Convention)
27377 (Verilog) Empty Module 27377 (VHDL) Empty Architecture

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: module "%s" is empty. (VHDL) <filename>(<line no.>): <severity> <rule no.>: architecture "%s" is empty. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) Description (Verilog) This rule checks whether there are any empty modules. (VHDL) This rule checks whether there are any empty architecture. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 module test(a); input a; wire a; reg b; endmodule //warning
nLint reports: document.v(1): Warning 27377: module "test" is empty. (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is port ( clk : in bit); end top_ety; architecture arch of top_ety is signal s : bit; begin process (clk) begin end process; end arch; -- no warning
nLint reports:
27379 (Verilog) Unsigned Vector Compared with a Negative Value

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: unsigned vector "%s" should not be compared with a negative value "%s". Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any unsigned vector compared with a negative value. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (out0,in1,in2,sel); input sel; input [1:0] in1,in2; output [1:0] out0; reg [1:0] out0; always @( in1 or in2 or sel) if ( sel == 1'b1 ) out0 = (in1 > -2'd1); //warning here else out0 = in2; endmodule
nLint reports: document.v(9): Warning 27379: unsigned vector "in1" should not be compared with a negative value " - 2'd1". (Coding Style)
27381 Scan Enable Driven by Combinational Logic

Message <filename>(<line no.>): <severity> <rule no.>: scan enable signal should not be driven by combinational logic (scan enable: "%s" (%s(%d)); combinational logic output: "%s"). Configurable Parameter Rule group: DFT; Argument type: (CHECK_TIE_LOW_HIGH, IGNORE_TIE_LOW_HIGH); Argument description: select CHECK_TIE_LOW_HIGH to check tie-high and tie-low cells; select IGNORE_TIE_LOW_HIGH to ignore checking tie-high and tie-low cells; Default value: "IGNORE_TIE_LOW_HIGH" for Verilog, "IGNORE_TIE_LOW_HIGH" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any scan enable signal is driven by combinational logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test (D,CP,TI,TE,Q,QN,a,b); input D,CP,TI,TE,a,b; output Q,QN; FD1S u1 (.D(D), .CP(CP), .TI(TI), .TE(TE), .Q(Q), .QN(QN)); and u2 (TE, a, b); endmodule
nLint reports following if the argument value is ("IGNORE_TIE_LOW_HIGH"): document.v(6): Warning 27381: scan enable signal should not be driven by combinational logic (scan enable: "TE" (document.v(5)); combinational logic output: "TE"). (DFT)
(VHDL) -------------------example : document.vhd------------1 entity top_ety is 2 port (D1 : in bit; 3 CP1 : in bit; 4 TI1 : in bit; 5 a : in bit; 6 Q1 : out bit; 7 QN1 : out bit); 8 end top_ety; 9 10 architecture arch of top_ety is 11 component FD1S is 12 port( D : in bit; 13 CP: in bit; 14 TI: in bit; 15 TE: in bit; 16 Q : out bit; 17 QN: out bit); 18 end component FD1S; 19 20 signal TE1 : bit; 21 begin 22 u1: component FD1S port map (D=>D1, CP=>CP1, TI=>TI1, TE=>TE1, Q=>Q1, QN=>QN1); 23
24 25 26 27 28
p1: process(CP1,a) is begin TE1 <= CP1 and a; --warning here end process p1; end arch;
nLint reports following if the argument value is ("IGNORE_TIE_LOW_HIGH"): document.vhd(26): Warning 27381: scan enable signal should not be driven by combinational logic (scan enable: "TE1" (document.vhd(22)); combinational logic output: "TE1"). (DFT)
27383 Scan Enable Driven by Sequential Logic

Message <filename>(<line no.>): <severity> <rule no.>: scan enable signal should not be driven by sequential logic (scan enable: "%s" (%s(%d)); sequential logic output: "%s"). Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any scan enable signal is driven by sequential logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 module test (D,CP,TI,c,Q,QN); input D,CP,TI; output Q,QN; output [3:0] c; reg [3:0] c; FD1S u1 (.D(D), .CP(CP), .TI(TI), .TE(c[3]), .Q(Q), .QN(QN)); always @(posedge CP) c <= c + 1; endmodule
nLint reports: document.v(10): Warning 27383: scan enable signal should not be driven by sequential logic (scan enable: "c[3]" (document.v(7)); sequential logic output: "c[3]"). (DFT)
(VHDL) -------------------example : document.vhd------------1 entity top_ety is 2 port (D1 : in bit; 3 CP1 : in bit; 4 TI1 : in bit; 5 a : in bit; 6 Q1 : out bit; 7 QN1 : out bit); 8 end top_ety; 9 10 architecture arch of top_ety is 11 component FD1S is 12 port( D : in bit; 13 CP: in bit; 14 TI: in bit; 15 TE: in bit; 16 Q : out bit; 17 QN: out bit); 18 end component FD1S; 19 20 signal TE1 : bit; 21 begin 22 u1: component FD1S port map (D=>D1, CP=>CP1, TI=>TI1, TE=>TE1, Q=>Q1, QN=>QN1); 23 24 p1: process(CP1,a) is 25 begin 26 if (CP1'event and CP1='1') then
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TE1 <= a; --warning here end if; end process p1; end arch;
nLint reports: document.vhd(27): Warning 27383: scan enable signal should not be driven by sequential logic (scan enable: "TE1" (document.vhd(22)); sequential logic output: "TE1"). (DFT)
27385 Scan Enable Signal Used as Data Input

Message <filename>(<line no.>): <severity> <rule no.>: scan enable signal should not be used as data (scan enable: "%s" (%s(%d)); data: "%s"). Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any scan enable signal is used as datum. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module test (D,CP,TI,TE,Q,QN,y); input D,CP,TI,TE; output Q,QN,y; reg y; FD1S u1 (.D(D), .CP(CP), .TI(TI), .TE(TE), .Q(Q), .QN(QN)); always @(posedge CP) y = TE; endmodule
nLint reports: document.v(9): Warning 27385: scan enable signal should not be used as data (scan enable: "TE" (document.v(6)); data: "TE"). (DFT)
(VHDL) -------------------example : document.vhd------------1 entity top_ety is 2 port (D1 : in bit; 3 CP1 : in bit; 4 TI1 : in bit; 5 TE1 : in bit; 6 rst : in bit; 7 Q1 : out bit; 8 QN1 : out bit; 9 y : out bit); 10 end top_ety; 11 12 architecture arch of top_ety is 13 component FD1S is 14 port( D : in bit; 15 CP: in bit; 16 TI: in bit; 17 TE: in bit; 18 Q : out bit; 19 QN: out bit); 20 end component FD1S; 21 22 begin 23 u1: component FD1S port map (D=>D1, CP=>CP1, TI=>TI1, TE=>TE1, Q=>Q1, QN=>QN1); 24 25 p1: process (rst) is 26 begin 27 if (rst='1') then 28 y <= TE1; --warning here
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else y <= '0'; end if; end process p1; end arch;
nLint reports: document.vhd(28): Warning 27385: scan enable signal should not be used as data (scan enable: "TE1" (document.vhd(23)); data: "TE1"). (DFT)
27387 Scan Enable Feeds into Primary Output

Message <filename>(<line no.>): <severity> <rule no.>: scan enable signal feeds into primary output (scan enable: "%s" (%s(%d)); output signal: "%s"). Configurable Parameter Rule group: DFT; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any scan enable signal feeds into primary output. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test (D,CP,TI,TE,Q,QN,y); input D,CP,TI,TE; output Q,QN,y; FD1S u1 (.D(D), .CP(CP), .TI(TI), .TE(TE), .Q(Q), .QN(QN)); assign y = TE; endmodule
nLint reports: document.v(1): Warning 27387: scan enable signal feeds into primary output (scan enable: "TE" (document.v(5)); output signal: "y"). (DFT)
(VHDL) -------------------example : document.vhd------------1 entity top_ety is 2 port (D1 : in bit; 3 CP1 : in bit; 4 TI1 : in bit; 5 TE1 : in bit; 6 rst : in bit; 7 Q1 : out bit; 8 QN1 : out bit; 9 y : out bit); -- warning here 10 end top_ety; 11 12 architecture arch of top_ety is 13 component FD1S is 14 port( D : in bit; 15 CP: in bit; 16 TI: in bit; 17 TE: in bit; 18 Q : out bit; 19 QN: out bit); 20 end component FD1S; 21 22 begin 23 u1: component FD1S port map (D=>D1, CP=>CP1, TI=>TI1, TE=>TE1, Q=>Q1, QN=>QN1); 24 25 p1: process (rst) is 26 begin 27 y <= TE1; 28 end process p1; 29 end arch;
nLint reports: document.vhd(9): Warning 27387: scan enable signal feeds into primary output (scan enable: "TE1" (document.vhd(23)); output signal: "y"). (DFT)
27389 (Verilog) Timescale Missing

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: timescale missing on module "%s". Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any module missing timescale declaration. Example
(Verilog) ///////////////example : document.v//////////// 1 2 module test; endmodule
nLint reports: document.v(1): Warning 27389: timescale missing on module "test". (Coding Style)
27391 (Verilog) 'reg' Declaration Detected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: 'reg' declaration is detected, use %s instead. Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: The argument allows you to specify the types, such as logic, which can be used to replace the 'reg' declarations; Default value: "logic" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any 'reg' declarations in the design. Replacement type can be configured in the rule argument. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 module test; reg a; //warning here wire b; logic c; bit d; integer e; endmodule
nLint reports following if the argument value is ("logic"): document.sv(2): Warning 27391: 'reg' declaration is detected, use logic instead. (Coding Style)
27393 (Verilog) Wire Declaration Detected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: 'wire' declaration is detected, use %s instead. Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: The argument allows you to specify the types, such as logic, which can be used to replace the 'wire' declarations; Default value: "logic" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any 'wire' declarations in the design. The replacement type can be configured in the rule argument. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 module test; reg a; wire b; //warning here logic c; bit d; integer e; endmodule
nLint reports following if the argument value is ("logic"): document.sv(3): Warning 27393: 'wire' declaration is detected, use logic instead. (Coding Style)
27394 (Verilog) 'tri' Declaration Detected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: 'tri' declaration is detected, use %s instead. Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: The argument allows you to specify the types, such as logic, which can be used to replace the 'tri' declarations; Default value: "logic" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any 'tri' declarations in the design. The replacement type can be configured in the rule argument. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 module test; reg a; tri b; //warning here logic c; bit d; integer e; endmodule
nLint reports following if the argument value is ("logic"): document.v(3): Warning 27394: 'tri' declaration is detected, use logic instead. (Coding Style)
27395 (Verilog) No Direct Usage of Specified Data Types

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: type "%s" should not be used directly, use "%s" instead. Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: The argument allows you to configure the types that can be directly used and the types that cannot be directly used. List the data types, separated by comma, in the argument. The first one is the data type that should be used, and the others are the data types that should not be used directly; Default value: "my_bit,bit,logic;" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any prohibited data types are being used directly. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 module test; typedef bit my_bit; //assumed that "my_bit" is the global type to be used typedef bit another_bit; //warning bit a; //warning logic b; //warning endmodule
nLint reports following if the argument value is ("my_bit,bit,logic;"): document.sv(3): Warning 27395: type "another_bit" should not be used directly, use "my_bit" instead. (Coding Style) document.sv(4): Warning 27395: type "bit" should not be used directly, use "my_bit" instead. (Coding Style) document.sv(5): Warning 27395: type "logic" should not be used directly, use "my_bit" instead. (Coding Style)
27397 (Verilog) `define Used to Define Constants

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: 'define is not allowed for defining constants. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any `define text macros used to define constants. The 'parameter' construct is recommended for defining constants. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 module test; `define WIDTH 128 //warning here `define SIZE WIDTH*2 //warning here `define AA bb endmodule
nLint reports: document.sv(2): Warning 27397: 'define is not allowed for defining constants. (Coding Style) document.sv(3): Warning 27397: 'define is not allowed for defining constants. (Coding Style)
27399 Comment on Synchronous Set or Reset

Message <filename>(<line no.>): <severity> <rule no.>: synchronous set or reset "%s" inferred without comment "%s". Configurable Parameter Rule group: Coding Style; Argument type: string; Argument description: the comment string; Default value: "//sync" for Verilog, "--sync" for VHDL; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the synchronous set or reset inferred with comment. If there is a comment, "sync" should appear in the comment string. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module smp(out,ck,res,set,d); input ck,res,set,d; output out; reg out;
parameter D1 = 1;
always @(posedge ck) if ( res==1'b0 ) //warning out <= 1'b0; else if ( set==1'b0 ) //warning out <= 1'b1; else out <= #D1 d; endmodule
nLint reports following if the argument value is ("//sync"): document.v(12): Warning 27399: synchronous set or reset "res" inferred without comment "//sync". (Coding Style) document.v(14): Warning 27399: synchronous set or reset "set" inferred without comment "//sync". (Coding Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 library IEEE; use IEEE.std_logic_1164.all; entity top_ety is port (reset : in std_logic; set : in std_logic; clk : in std_logic; d : in std_logic; q : out std_logic ); end entity top_ety; architecture arch of top_ety is
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begin p1: process (clk) is begin if ( rising_edge(clk) ) then if (reset='1') then --warning q<='0'; elsif (set='1') then --warning q<='1'; else q<=d; end if; end if; end process p1; end architecture arch;
nLint reports following if the argument value is ("--sync"): document.vhd(18): Warning 27399: synchronous set or reset "reset" inferred without comment "--sync". (Coding Style) document.vhd(20): Warning 27399: synchronous set or reset "set" inferred without comment "--sync". (Coding Style)
27401 Mix Combinational Logic with Sequential Logic

Message <filename>(<line no.>): <severity> <rule no.>: sequential logic "%s" should not be mixed with combinational logic in the same always block. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any mixed combinational logic with sequential logic in the same always block. This rule is checked accroding to inference result. The engine will check the latch or register inferred device and trace its data port backward. If there is any functional logic found in the same always block, warning is reported. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module smp(out,ck,res,sel); input ck,res; input[1:0] sel; output[3:0] out; reg[3:0] out;
parameter D1 = 1; always @(negedge ck or negedge res) if ( res==1'b0 ) out <= 4'b0000; else begin case(sel) 2'b00 : out <= #D1 4'b0001; //warning here 2'b01 : out <= #D1 4'b0010; 2'b10 : out <= #D1 4'b0100; 2'b11 : out <= #D1 4'b1000; default : out <= #D1 4'bxxxx; endcase end endmodule
nLint reports: document.v(16): Warning 27401: sequential logic "out" should not be mixed with combinational logic in the same always block. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end; architecture arch of top_ety is signal clk : bit; signal in1 : bit; signal in2 : bit; signal out1 : bit; signal set : bit; begin process(clk, in1, in2, set) begin
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if (set = '1') then out1 <= '1'; elsif (clk'event and clk = '1') then out1 <= in1 and in2; --warning here end if; end process; end;
nLint reports: document.vhd(16): Warning 27401: sequential logic "out1" should not be mixed with combinational logic in the same always block. (Design Style)
27411 (Verilog) Use Parameters for FSM State Coding

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: use symbolic parameter instead of "%s" for FSM state encoding. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) The symbolic parameters aid users understand what the encoding state stands for. It enhances the readability. This also eases retargeting to different state machine implementations, e.g., changing from a binary-coding style to 1-hot style. Limitation for a "state" in FSM coding: If user write "number state" in all the places, 27411 will be reported for that. But if user has written "parameter state" in any place, 27411 will not be reported. Example
(Verilog) ///////////////example : document.v//////////// 1 module inival; 2 reg clock,reset,control; 3 wire [2:0] y; 4 5 initial 6 begin 7 $monitor($time,,,"control=%d,reset=%d,clock=%b,y=%b,current =%d,next =%d",control,reset,clock, y,cc.current ,cc.next ); 8 clock = 0; 9 reset=0; 10 control=0; 11 #160 $finish; 12 end 13 always 14 #4 clock=!clock; 15 always begin 16 #4 reset=1; 17 #4 reset=0; 18 #2 control = 1; 19 #200 reset = 1; 20 end 21 block cc (clock,reset,control,y); 22 endmodule 23 24 module block(clock,reset,control,y); 25 input clock,reset,control; 26 output [2:0] y; 27 reg [2:0] y; 28 29 parameter st0 = 0,st1 = 1,st2 = 2,st3 = 3; 30 reg[1:0] current , next ; 31 32 always@(control or current ) //report here 33 begin 34 case (current ) 35 //st0: begin y = 1; next = st1; end 36 0: begin y = 1; next = st1; end //should use parameter "st0" instead 37 st1: begin 38 y = 2; 39 if (control) next = st2; 40 else next = st3;
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end st2: begin y = 3; next = st3; end //st3: begin y = 4; next = st0; end st3: begin y = 4; next = 0; end //default: begin y = 1; next = st0; end default: begin y = 1; next = 0; end endcase end always @(posedge clock or posedge reset) begin if(reset) current = 0; else current = next ; end endmodule
nLint reports: document.v(32): Warning 27411: use symbolic parameter instead of "0" for FSM state encoding. (Coding Style)
27412 (Verilog) Too Many States in a FSM

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the number of states of a FSM should be kept within %d. Configurable Parameter Rule group: Coding Style; Argument type: integer; Argument description: specify the maximum number of states of a FSM; Default value: "40" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the number of states for a recognized FSM are within the specified limit. A vilation will be reported when the number of states exceeds the specified value in argument. Example
(Verilog) ///////////////example : document.v//////////// 1 module FSM (clk, rst_n, enable, y); 2 input clk; 3 input rst_n; 4 input enable; 5 output [1:0] y; 6 7 reg [1:0] rw_cs; // current state 8 reg [1:0] rw_ns; // next state 9 reg [1:0] y; 10 reg control; 11 12 //in rs file, argument be specified 3 13 //so nLint will report 27412 because the number of state in the case exceeds 3. 14 always @ (rw_cs or control) 15 begin 16 rw_ns = rw_cs; 17 case (rw_cs) 18 2'b00: 19 begin 20 y = 2'b00; 21 if (control == 1'b1) 22 rw_ns = 2'b01; 23 else 24 rw_ns = 2'b00; 25 end 26 2'b01: 27 begin 28 y = 2'b01; 29 rw_ns = 2'b10; 30 end 31 2'b10: 32 begin 33 y = 2'b10; 34 rw_ns = 2'b11; 35 end 36 2'b11: 37 begin 38 y = 2'b11; 39 rw_ns= 2'b00; 40 end 41 endcase 42 end 43
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// Logic for generating internal control signal always @ ( posedge clk or negedge rst_n ) begin if (!rst_n) control <= 1'b0; else control <= enable; end always @ (negedge rst_n or posedge clk) // sequential logic begin if (!rst_n) rw_cs <= 2'b00; else rw_cs <= rw_ns; end endmodule
nLint reports following if the argument value is (3): document.v(14): Warning 27412: the number of states of a FSM should be kept within 3. (Coding Style)
27413 Mutiple Clock Source Not Recommended

Message <filename>(<line no.>): <severity> <rule no.>: multiple clock source founded ("%s" line %d, "%s" line %d, ...). Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether the design use only one clock source. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test; wire clk2, clk1, d, set; //2 clk sources reg q; always @(posedge clk2) begin if (set) q <= 1'b1; else q<=d; end always @(posedge clk1) begin if (set) q<= 1'b1; else q<=d; end endmodule
nLint reports: document.v(2): Warning 27413: multiple clock source founded ("test.clk1" line 2, "test.clk2" line 2, ...). (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 entity test is end; architecture arch of test is signal clk : bit; --clk source signal in1 : bit; signal clk1 : bit;--clk source signal out1 : bit; signal out2 : bit; signal set : bit; begin process(clk, in1, set) begin if (set = '1') then out1 <= '1'; elsif (clk'event and clk = '1') then out1 <= in1; end if; end process; process(clk1, in1, set) begin if (set = '1') then out2 <= '1'; elsif (clk1'event and clk1 = '1') then out2 <= in1; end if;
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end process; end;
nLint reports: document.vhd(7): Warning 27413: multiple clock source founded ("test.clk1" line 7, "test.clk" line 5, ...). (Design Style)
27415 (Verilog) Specified Delay should be Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: delay in flip-flop/latch data path is lost or wrong, use delay "%s" instead. Configurable Parameter Rule group: Naming Convention; Argument type: string; Argument description: specify delay name; Default value: "D1" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the delay in flip-flop/latch data path is the specified delay. Example
(Verilog) ///////////////example : document.v//////////// 1 module smp( data_out, ck, res, data_in); 2 input ck, res, data_in; 3 output data_out; 4 reg data_out; 5 parameter D1 = 1; 6 parameter D2 = 2; 7 8 always @(negedge res or posedge ck) 9 if (~res) 10 data_out <= #D2 1'b1; //Warning (The variable "D2" is not the specified delay, use D1 instead.) 11 else 12 data_out <= #D1 data_in; //OK 13 endmodule 14
nLint reports following if the argument value is ("D1"): document.v(10): Warning 27415: delay in flip-flop/latch data path is lost or wrong, use delay "D1" instead. (Naming Convention)
27417 No Glue Logic Allowed in Top Module

Message <filename>(<line no.>): <severity> <rule no.>: glue logic should not be allowed in top module. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any glue logic in top module. Here "glue logic" means gate instance and RTL instance. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module top; wire in1, clock; wire a, b, c, d; reg y; test u1 (in1); and u2 (a, b, c); //warning here, gate inst always @(posedge clock) begin //warning here, rtl inst y <= d; end endmodule module test(in); input in; wire in; endmodule
nLint reports: document.v(8): Warning 27417: glue logic should not be allowed in top module. (Design Style) document.v(10): Warning 27417: glue logic should not be allowed in top module. (Design Style)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity test1 is port( in1 : in bit); end; architecture arch1 of test1 is begin end; library IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all; use work.all; entity top_ety is port ( clock : in std_logic ); end; architecture arch of top_ety is signal a : bit; signal b : bit;
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signal c : bit; signal d : bit; signal y : bit; signal in2 : bit; begin process (a,b) -- warning here begin c <= a and b; end process; process (clock, d) -- warning here begin if rising_edge(clock) then y <= d; end if; end process; u1 : entity test1(arch1) port map (in1=>in2); end;
nLint reports: document.vhd(25): Warning 27417: glue logic should not be allowed in top module. (Design Style) document.vhd(30): Warning 27417: glue logic should not be allowed in top module. (Design Style)
27419 Mutiple Resolved Point Not Recommended

Message <filename>(<line no.>): <severity> <rule no.>: multiple resolved point founded on "%s". Configurable Parameter Rule group: Clock; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether any multiple resolved point is found. This rule will be checked only if clock source tree is extracted. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 //symbol library lsi10k_u module test(clk,clk1,rst,din,dout1,dout2,dout3); input clk,clk1,rst,din; output dout1,dout2,dout3; FD2 u1(.D(clk),.CP(clk1),.CD(rst),.Q(dout1)); FD2 u2(.D(din),.CP(clk),.CD(rst),.Q(dout2)); MUX21H u3(.A(clk),.B(clk1),.S(sel),.Z(y)); //warning here FD2 u4(.D(din),.CP(y),.CD(rst),.Q(dout3)); endmodule
nLint reports: document.v(7): Warning 27419: multiple resolved point founded on
"test.y". (Clock)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 entity test is end entity test; architecture arch of test is signal clk,clk1,clk2,y,y1,y2,data,sel : bit; begin process (clk) begin if (clk'event and clk = '1') then y <= data; end if; end process; process (clk1) begin if (clk1'event and clk1 = '1') then y1 <= data; end if; end process; process (clk2) begin if (clk2'event and clk2 = '1') then y2 <= data; end if; end process; process (sel) begin if (sel = '0') then clk <= clk1; --warning here
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else clk <= clk2; end if; end process; end architecture arch;
nLint reports: document.vhd(31): Warning 27419: multiple resolved point founded on (Clock)
"test.clk".
27421 (Verilog) FSM Stuck in State

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: FSM is stuck in state "%s". Configurable Parameter Rule group: Design Style; Argument type: (CHECK_ALL, IGNORE_UNREACHABLE_STATE); Argument description: Select CHECK_ALL to specify that the rule 27421 will be violated if the FSM is stuck in any states; select IGNORE_UNREACHABLE_STATE to specify that the rule 27421 will not be violated if the FSM is stuck in any unreachable states; Default value: "CHECK_ALL" for Verilog; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any states without an output transition to other states in any FSMs. If command line option "-rtl_fsm" is turned off, this rule will be suppressed. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 module FSM (clk, rst_n, enable); input clk; input rst_n; input enable; parameter [2:0] ST_IN = 3'b000, ST_S1 = 3'b001, ST_S2 = 3'b010, ST_S3 = 3'b011; reg [2:0] rw_cs; reg [2:0] rw_ns; reg control; reg y; always @ (rw_cs or control) begin case (rw_cs) ST_IN: begin if (control == 1'b1) rw_ns = ST_S1; else rw_ns = ST_S3; end ST_S1: begin rw_ns = ST_S2; end ST_S2: begin rw_ns = ST_IN; end ST_S3: begin y = 1; end endcase end always @ (negedge rst_n or posedge clk) begin if (!rst_n) rw_cs <= ST_IN; else rw_cs <= rw_ns; end
45
endmodule
nLint reports following if the argument value is ("CHECK_ALL"): document.v(9): Error 27421: FSM is stuck in state "ST_S3". (Design Style) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 module FSM (clk, rst_n, enable); input clk; input rst_n; input enable; parameter [2:0] ST_IN = 3'b000, ST_S1 = 3'b001, ST_S2 = 3'b010; reg [2:0] rw_cs; reg [2:0] rw_ns; reg control; always @ (rw_cs or control) begin case (rw_cs) ST_IN: rw_ns = ST_S1; ST_S1: rw_ns = ST_IN; default: rw_ns = 3'bxxx; endcase end always @ (negedge rst_n or posedge clk) begin if (!rst_n) rw_cs <= ST_IN; else rw_cs <= rw_ns; end endmodule
nLint reports following if the argument value is ( IGNORE_UNREACHABLE_STATE):
27423 (Verilog) Un-reached State from Initial State of FSM

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: FSM state "%s" cannot be reached from the initial state either directly or indirectly through other states. Configurable Parameter Rule group: Design Style; Argument type: (IGNORE_DEFAULT,CHECK_DEFAULT); Argument description: If the argument is set to CHECK_DEFAULT, the default state, which can not be reached from the initial state, will be checked and reported by this rule. If the argument is set to IGNORE_DEFAULT, the default state will be ignored by this rule; Default value: "IGNORE_DEFAULT" for Verilog; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any states that cannot be reached from the initial state either directly or indirectly through other states. If command line option "-rtl_fsm" is turned off, this rule will be suppressed. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 module FSM (clk, rst_n, enable, y); input clk; input rst_n; input enable; output [1:0] y; parameter [2:0] ST_IN = 3'b000, ST_S1 = 3'b001, ST_S2 = 3'b010, ST_S3 = 3'b011, ST_S4 = 3'b100, ST_S5 = 3'b101; reg [2:0] rw_cs; reg [2:0] rw_ns; reg [1:0] y; reg control; always @ (rw_cs or control) begin case (rw_cs) ST_IN: begin y = 2'b00; if (control == 1'b1) rw_ns = ST_S1; else rw_ns = ST_IN; end ST_S1: begin y = 2'b01; rw_ns = ST_S2; end ST_S2: begin y = 2'b10; rw_ns = ST_S3; end ST_S3: begin
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
y = 2'b11; rw_ns= ST_IN; end ST_S4: begin y = 2'b10; rw_ns= ST_S5; end ST_S5: begin rw_ns = ST_IN; end default: begin y = 2'b00; rw_ns = ST_IN; end endcase end always @ (negedge rst_n or posedge clk) // sequential logic begin if (!rst_n) rw_cs <= ST_IN; else rw_cs <= rw_ns; end endmodule
nLint reports following if the argument value is ("IGNORE_DEFAULT"): document.v(46): Error 27423: FSM state "ST_S4" cannot be reached from the initial state either directly or indirectly through other states. (Coding Style) document.v(50): Error 27423: FSM state "ST_S5" cannot be reached from the initial state either directly or indirectly through other states. (Coding Style)
27425 (Verilog) FSM without Initial State

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: FSM without an initial state is detected. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any FSMs without an initial state. If a FSM hasn't the capability to reset its state a const value, this rule will be violated. If command line option "rtl_fsm" is turned off, this rule will be suppressed. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 module FSM (clk, rst_n, enable); input clk; input rst_n; input enable; parameter [2:0] // symbolic state_vector ST_IN = 3'b000, ST_S1 = 3'b001, ST_S2 = 3'b010, ST_S3 = 3'b011; reg [2:0] rw_cs; // current state reg [2:0] rw_ns; // next state reg control; reg y; always @ (rw_cs or control) // combinational logic begin case (rw_cs) ST_IN: begin if (control == 1'b1) rw_ns = ST_S1; else rw_ns = ST_S3; end ST_S1: begin rw_ns = ST_S2; end ST_S2: begin rw_ns = ST_S3; end ST_S3: begin rw_ns = ST_IN; y = 1; end default: begin rw_ns = ST_IN; end endcase end always @ (posedge clk) // sequential logic begin rw_cs <= rw_ns; end always @ (negedge rst_n or posedge clk) begin if (!rst_n)
50 51 52 53 54
control <= 1'b0; else control <= 1'b1; end endmodule
nLint reports: document.v(14): Error 27425: FSM without an initial state is detected. (Design Style)
27427 (Verilog) Next State In Default Branch

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: next state "%s" is not specified as a constant value in the default branch. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a next state is specified as a constant value in the default branch. If command line option "-rtl_fsm" is disabled, this rule will be suppressed. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 module fsm1( Clock, Reset, ThreeOnly,StartFSM1, En_A, En_B, En_C); parameter ST_A=0,ST_B=1,ST_C=2; // FSM1 input Clock, Reset,ThreeOnly,StartFSM1; output En_A, En_B, En_C; reg En_A, En_B, En_C; reg [1:0] CurrStateFSM1, NextStateFSM1;
always @(StartFSM1 or ThreeOnly or CurrStateFSM1) begin: FSM1_COMB En_A = 0; En_B = 0; En_C = 0; case (CurrStateFSM1) ST_A : NextStateFSM1 = ST_B; ST_B : NextStateFSM1 = ST_C; ST_C : NextStateFSM1 = ST_A; default : NextStateFSM1 = CurrStateFSM1; endcase end always @(posedge Clock) begin: FSM1_SEQ if (Reset) CurrStateFSM1 = ST_A; else CurrStateFSM1 = NextStateFSM1; end endmodule
nLint reports: document.v(20): Warning 27427: next state "NextStateFSM1" is not specified as a constant value in the default branch. (Design Style)
27505 (VHDL) Non-integer Type Generic Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: non-integer type "%s" on generic "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether any non-integer type is used to specify types of generics. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is generic( Width_g : bit := '1' ); --warning on "Width_g" end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27505: non-integer type "bit" on generic "Width_g" is not synthesizable. (Synthesis)
27507 (VHDL) Declaration Here Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: declaration here is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any declaration in some structures (entity, generate statement, configuration) which is not synthesizable. Following list the declaration not synthesizable (or ignored by synthesizer) in entity and configuration: for entity declaration subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | signal_declaration | shared_variable_declaration -- this is checked in 27515 | file_declaration -- this is checked in 27517 | alias_declaration -- this is checked in 27519 | attribute_declaration | attribute_specification | disconnection_specification -this is checked in 27557 | use_clause | group_template_declaration -- this is checked in 27522 | group_declaration -- this is checked in 27521 for configuration declarative part use_clause | attribute_specification | group_declaration -- this is checked in 27521 Warning will be reported at the first declaration of each structure Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is generic( Width : integer ); port( Clk : in bit; Data : in bit; Q : out bit ); constant CI : integer := 1; end top_ety;
--warning here
architecture arch of top_ety is begin Lbl: for I in 1 to 2 generate signal S1 : integer; --warning here begin S1 <= CI; Inst1 : and_gate port map( S1,P2(I),p3 ); end generate Lbl; end arch;
nLint reports: document.vhd(6): Warning 27507: declaration here is not synthesizable. (Synthesis) document.vhd(12): Warning 27507: declaration here is not synthesizable. (Synthesis)
27509 (VHDL) Passive Entity Statement Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: passive entity statement is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any passive entity statement which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is signal monitor : bit := '0'; begin assert NOT (monitor = '1') --warning here report "monitor is 1" severity NOTE; end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(4): Warning 27509: passive entity statement is ignored by synthesis. (Synthesis)
27515 (VHDL) Shared Variable Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: shared variable "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any shared variable which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture arch of top_ety is shared variable Shar_v : bit; --warning on "Shar_v" begin end arch;
nLint reports: document.vhd(5): Warning 27515: shared variable "Shar_v" is not synthesizable. (Synthesis)
27517 (VHDL) File Object Declaration Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: file object declaration "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any file object declaration which is ignored or not supported by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is end top_ety; architecture arch of top_ety is type IntFile_Typ is file of integer; file DataOut_f : IntFile_Typ open Write_Mode is "IntOut.txt" ; --warning on "DataOut_f" begin process variable Int_v : integer := 0; variable fStatus_v : File_Open_Status; begin write( DataOut_f, Int_v); Endfile(DataOut_f); wait; end process; end arch;
nLint reports: document.vhd(6): Warning 27517: file object declaration "DataOut_f" is ignored by synthesis. (Synthesis)
27518 (VHDL) File Operation Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: file operation should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any file type operation which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 entity top_ety is end top_ety; architecture arch of top_ety is type IntFile_Typ is file of integer; file DataOut_f : IntFile_Typ open Write_Mode is "IntOut.txt"; --warning on "open" begin process variable Int_v : integer := 0; variable fStatus_v : File_Open_Status; begin write( DataOut_f, Int_v); Endfile(DataOut_f); wait; end process; end arch;
nLint reports: document.vhd(6): Warning 27518: file operation should not be used because it is not synthesizable. (Synthesis)
27519 (VHDL) Alias Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: alias "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any alias which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is signal Bus_s : bit_vector(31 downto 0) := X"AB_CD_0234"; alias OpCode_s : bit_vector(7 downto 0) is Bus_s( 31 downto 24); --warning on "OpCode_s" begin end arch;
nLint reports: document.vhd(6): Warning 27519: alias "OpCode_s" is ignored by synthesis. (Synthesis)
27521 (VHDL) Group Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: group "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any group which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is group group_of_TOP is (entity); group group_of_test : group_of_TOP (top_ety); --warning here begin end arch;
nLint reports: document.vhd(6): Warning 27521: group "group_of_test" is ignored by synthesis. (Synthesis)
27522 (VHDL) Group Template Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: group template "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any group template which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is group group_of_TOP is (entity); --warning here group group_of_test : group_of_TOP (top_ety); begin end arch;
nLint reports: document.vhd(5): Warning 27522: group template "group_of_TOP" is ignored by synthesis. (Synthesis)
27523 (VHDL) Pure or Impure for Sub-program Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: "%s" specification for sub-program is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is pure or impure specification for subprogram which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 entity top_ety is port(d1 : in bit_vector; d2 : in bit_vector; c1 : in boolean; o : out bit_vector ); end top_ety; architecture arch of top_ety is shared variable c2 : boolean := false; signal c3 : boolean := false; impure function test --warning here (signal a : in bit_vector; signal b : in bit_vector ) return bit_vector is begin if ( c1 ) then --reference outside object return ( a and b ); elsif ( c2 ) then --reference outside object return ( a or b ); elsif ( c3 ) then --reference outside object return a; else return b; end if; end test; begin o <= test( d1, d2 ); end arch;
nLint reports: document.vhd(11): Warning 27523: "impure" specification for sub-program is not synthesizable. (Synthesis)
27524 Synthesis Ignores Initial Value

Message <filename>(<line no.>): <severity> <rule no.>: initial value "%s" assigned to "%s" will be ignored by synthesis process. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description This rule checks whether any initial values are assigned to input argument, signal, variable, or port (signal, variable) statements. Initial values are ignored by synthesis. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 module test; logic a = 1'b1; reg b = 1'b1; logic c; reg d; initial begin c = 1'b1; d = #3 1'b1; end endmodule
//warning //warning
//warning //warning
nLint reports: document.sv(2): Warning 27524: initial value ignored by synthesis process. (Synthesis) document.sv(3): Warning 27524: initial value ignored by synthesis process. (Synthesis) document.sv(7): Warning 27524: initial value ignored by synthesis process. (Synthesis) document.sv(8): Warning 27524: initial value ignored by synthesis process. (Synthesis)
"1'b1" assigned to "a" will be "1'b1" assigned to "b" will be "1'b1" assigned to "c" will be "1'b1" assigned to "d" will be
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 entity top_ety is end top_ety; architecture arch of top_ety is signal Init_s : bit := '1'; --warning here shared variable Init_sv : bit := '1'; --warning here procedure Init_p (constant Init_c : in natural := 10; signal Init_si : out bit := '1'; --warning here variable Init_vi : inout bit := '1' ) --warning here is variable Init_vv : bit := '1'; --warning here begin end Init_p; begin process variable Init_v : bit := '1'; --warning here begin wait; end process; end arch;
nLint reports: document.vhd(5): Warning 27524: initial value "1" assigned to "Init_s" will be ignored by synthesis process. (Synthesis) document.vhd(6): Warning 27524: initial value "1" assigned to "Init_sv" will be ignored by synthesis process. (Synthesis) document.vhd(9): Warning 27524: initial value "1" assigned to "Init_si" will be ignored by synthesis process. (Synthesis) document.vhd(10): Warning 27524: initial value "1" assigned to "Init_vi" will be ignored by synthesis process. (Synthesis) document.vhd(12): Warning 27524: initial value "1" assigned to "Init_vv" will be ignored by synthesis process. (Synthesis) document.vhd(17): Warning 27524: initial value "1" assigned to "Init_v" will be ignored by synthesis process. (Synthesis)
27525 (VHDL) User-defined Attribute Except ENUM_ENCODING Ignored

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: user-defined attribute "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any user-defined attribute (except ENUM_ENCODING) which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is attribute type_a : string; --warning here signal Attr_s : integer; attribute type_a of Attr_s : signal is "int"; --warning here begin end arch;
nLint reports: document.vhd(5): Warning 27525: user-defined attribute "type_a" is ignored by synthesis. (Synthesis) document.vhd(7): Warning 27525: user-defined attribute "type_a" is ignored by synthesis. (Synthesis)
27529 (VHDL) Signature Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: signature "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is signature specification which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is type MVF is ('0', '1', 'x', 'z'); function Sig_f1 (A: in MVF; B: in MVF) return MVF; function Sig_f2 (A: in bit; B: in bit) return bit; attribute Type_A : string; attribute Type_A of Sig_f1 [MVF, MVF return MVF] : function is "MVF"; --warning here begin end arch;
nLint reports: document.vhd(9): Warning 27529: signature "MVF" is not synthesizable. (Synthesis)
27531 (VHDL) Deferred Constant in Package Declaration Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: deferred constant "%s" in package declaration is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is deferred constant in package declaration which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 package Deferred_Pkg is constant MaxCount_c : natural; --warning here type MY_LOGIC is ('0', '1', 'X', 'Z'); end Deferred_Pkg; package body Deferred_Pkg is constant MaxCount_c : natural := 10; end Deferred_Pkg; use work.Deferred_Pkg.all; entity top_ety is end top_ety; architecture arch of top_ety is signal S : MY_LOGIC; begin end arch;
nLint reports: document.vhd(2): Warning 27531: deferred constant "MaxCount_c" in package declaration is not synthesizable. (Synthesis)
27533 (VHDL) Null Range Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: range of "%s" should not be null range (reverse or out of bound) because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level3 (Error) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is null range (reverse or out of bound) which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is signal A : bit_vector(1 downto 0); signal C : bit; signal A0_3_s : bit_vector(0 to 3); signal A3_0_s : bit_vector(3 downto 0); begin C <= A(2); --warning here A3_0_s(0 to 3) <= "0101"; --warning here A3_0_s(A0_3_s'range) <= "0101"; --warning here end arch;
nLint reports: document.vhd(10): Error 27533: range of "A" should not be null range (reverse or out of bound) because it is not synthesizable. (Synthesis) document.vhd(11): Error 27533: range of "A3_0_s" should not be null range (reverse or out of bound) because it is not synthesizable. (Synthesis) document.vhd(12): Error 27533: range of "A3_0_s" should not be null range (reverse or out of bound) because it is not synthesizable. (Synthesis)
27535 (VHDL) Access Type Declaration Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: access type declaration "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any access type declaration which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is type AInt_Typ is access integer; --warning here shared variable AInt1_v, AInt2_v : Aint_Typ; begin end arch;
nLint reports: document.vhd(5): Warning 27535: access type declaration "AInt_Typ" is ignored by synthesis. (Synthesis)
27536 (VHDL) Object of Ignored Type Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: object "%s" of ignored type "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any use of ignored type in NOT-IGNORED construct, which is not synthesizable. The following types will be ignored by synthesis and the object of the type is not-synthesizable. object declared as access type access type object/literal object declared as physical type physical type object/literal object declared as floating type floating type object/literal object declared as file type file type object/literal object declared as alias type alias object/literal user attribute declaration use of user defined attribute Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is type AInt_Typ is access integer; shared variable AInt1_v, AInt2_v : Aint_Typ; --warning here begin end arch;
nLint reports: document.vhd(6): Warning 27536: object "AInt2_v" of ignored type "AInt_Typ" should not be used because it is not synthesizable. (Synthesis) document.vhd(6): Warning 27536: object "AInt1_v" of ignored type "AInt_Typ" should not be used because it is not synthesizable. (Synthesis)
27537 (VHDL) Incomplete Type Declaration

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: type declaration "%s" is incomplete and it is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any incomplete type declaration which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is type Rec_Typ; --warning here type ARecPntr_Typ is access Rec_Typ; type Rec_Typ is record Int_v : integer; IsLabel_v : boolean; end record; begin end arch;
nLint reports: document.vhd(5): Warning 27537: type declaration "Rec_Typ" is incomplete and it is ignored by synthesis. (Synthesis)
27539 (VHDL) Multi-dimensional Array Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: type "%s" is of multi-dimensional array type, which is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks if there are multi-dimensional array type declaration and object of this type which are not synthesizable (only arrays of arrays are supported). Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety is subtype Depth_Typ is integer range 0 to 1024; subtype Width_Typ is integer range 7 downto 0; type Mem_Typ is array(Depth_Typ, Width_Typ) of bit;--warning here subtype Data_Typ is Bit_vector(Width_Typ); type Memory_Typ is array(Depth_Typ) of Data_Typ; begin end arch;
nLint reports: document.vhd(7): Warning 27539: type "Mem_Typ" is of multi-dimensional array type, which is not synthesizable. (Synthesis) document.vhd(9): Warning 27539: type "Memory_Typ" is of multi-dimensional array type, which is not synthesizable. (Synthesis)
27541 (VHDL) Non-integer Type Range Value Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: range "%s" of "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is non-integer bound array type declaration and object of this type which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture arch of top_ety is type tSpec_Typ is array(integer) of bit; --warning here begin end arch;
nLint reports: document.vhd(5): Warning 27541: range "integer" of "tSpec_Typ" is not synthesizable. (Synthesis)
27543 (VHDL) User-defined Resolution Function Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: user-defined resolution function "%s" should not be used in sub-type declaration because it is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is user-defined resolution function in subtype declarations, which is ignored by synthesis and will cause mismatch between pre-synthesis and post-synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 entity top_ety is end top_ety; architecture arch of top_ety is type Bool_Array is array(7 downto 0) of boolean; function fb_Resolve ( DRIVERS : Bool_Array) return boolean is variable Found_True : boolean := false; begin LoopThruAllDrivers: for Idx_i in DRIVERS'range loop if DRIVERS(Idx_i) then Found_True := true; exit LoopThruAllDrivers; end if; end loop LoopThruAllDrivers; return Found_True; end fb_Resolve; subtype Rbool_Typ is fb_Resolve boolean; --warning here begin end arch;
nLint reports: document.vhd(18): Warning 27543: user-defined resolution function "fb_resolve" should not be used in sub-type declaration because it is ignored by synthesis. (Synthesis)
27545 (VHDL) Signal with REGISTER or BUS Kind Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: REGISTER or BUS kind in signal (port) declaration are not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any signal kind specification (REGISTER or BUS) in signal declarations (including "bus" in interface signal declaration) which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 library ieee; use ieee.std_logic_1164.all; entity top_ety is end top_ety; architecture arch of top_ety is signal Reg_s : std_logic register; --warning here signal Bus_s : std_logic_vector(7 downto 0) bus; --warning here begin end arch;
nLint reports: document.vhd(8): Warning 27545: REGISTER or BUS kind in signal (port) declaration are not synthesizable. (Synthesis) document.vhd(9): Warning 27545: REGISTER or BUS kind in signal (port) declaration are not synthesizable. (Synthesis)
27549 (VHDL) Assigning to Global Signal Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: assigning to global signal "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any global signal being assigned in architectures which is not synthesizable. Global signal can only be initialized, but not assigned. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 package PKG is signal global_signal : boolean; end PKG; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; library WORK; use WORK.PKG.all; entity top_ety is port (d1 : in signed; d2 : in signed; c1 : in signed; c2 : in signed; o : out signed ); end top_ety; architecture top_arch of top_ety is component AAA is port (a : in signed; b : in signed; o : out signed ); end component; begin p1 : process( d1, d2, global_signal ) is begin if ( global_signal ) then --global signal referenced o <= d1 + d2; else o <= d1 - d2; end if; end process; u_AAA_1 : AAA port map ( a=>c1, b=>c2, o=>o ); end top_arch; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; library WORK; use WORK.PKG.all;
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
entity AAA is port (a : in signed; b : in signed; o : buffer signed ); end AAA; architecture arch of AAA is begin p2 : process( a, b ) is begin o <= a + b; if ( o > 10 ) then global_signal <= true; --global signal assigned else global_signal <= false; --global signal assigned end if; end process; end arch;
nLint reports: document.vhd(2): Warning 27549: assigning to global signal "global_signal" is not synthesizable. (Synthesis)
27550 (VHDL) Global Signal without Initial Value

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: global signal "%s" should be initialized when it is delcared. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any global signal without an initial value which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 package Global_Pkg is signal gControl_s : bit; --warning on "gControl_s" type My_logic is ('0', '1', 'X'); end Global_Pkg; use work.Global_Pkg.all; entity top_ety is end top_ety; architecture arch of top_ety is signal S : My_logic; begin end arch;
nLint reports: document.vhd(2): Warning 27550: global signal "gControl_s" should be initialized when it is delcared. (Simulation,Synthesis)
27551 (VHDL) Linkage Mode Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: linkage mode on "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any linkage mode in interface declaration which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is port( a : linkage bit; --warning on "a" b : in bit ); end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27551: linkage mode on "a" is not synthesizable. (Synthesis)
27553 (VHDL) Type Conversion in Formal Part of Association List Not Synthesizable
Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: type conversion "%s" in formal part of association list is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any type conversion in formal part of association list which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 package pkg is type A_Typ is range 0 to 10; type B_Typ is range 0 to 10; function GetWidth (NUM: in A_Typ) return integer; procedure Asso_p ( variable Init_v : in A_Typ ); end pkg; package body pkg is function GetWidth (NUM: in A_Typ) return integer is begin return (32); end GetWidth; procedure Asso_p ( Init_v : in A_Typ ) is begin end Asso_p; end pkg; use work.pkg.all; entity Latch is generic(Width : integer); port( A : in A_Typ; B : out B_Typ); end entity; architecture arch of Latch is begin end arch; library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.pkg.all; entity top_ety is end top_ety; architecture arch of top_ety is component Latch is generic(Width : integer); port( A : in A_Typ; B : out B_Typ); end component Latch; signal A : A_Typ := 3; signal B : B_Typ := 7; signal C : unsigned(3 downto 0) := "1001";
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
begin U1: Latch generic map( Width => GetWidth(A) ) --warning here port map( A => A_Typ(B), --warning here A_Typ(B) => A); --warning here process variable VA : A_Typ := 3; variable VB : B_Typ := 7; variable VC : unsigned(3 downto 0) := "1001"; begin --Asso_p( Init_v => unsigned2Int( "1001" ) ); --warning here --Asso_p( Init_v => CONV_INTEGER(VC) ); --warning here Asso_p( Init_v => A_Typ(VB) ); --warning here end process; end arch;
nLint reports: document.vhd(51): Warning 27553: type conversion "A_Typ(B)" in formal part of association list is not synthesizable. (Synthesis)
27557 (VHDL) Disconnect Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: disconnect is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any disconnect which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is signal Guard_S : bit; disconnect Guard_S : bit after 20 ns; begin end arch;
--warning here
nLint reports: document.vhd(6): Warning 27557: disconnect is ignored by synthesis. (Synthesis)
27559 (VHDL) Xnor Operator Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: xnor operator is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any xnor operator which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end top_ety; architecture arch of top_ety is begin process variable Left_v : bit := '1'; variable Right_v : bit := '0'; variable Result_v : bit; begin Result_v := Left_v xnor Right_v; --warning here wait; end process; end arch;
nLint reports: document.vhd(11): Warning 27559: xnor operator is not synthesizable. (Synthesis)
27561 (VHDL) Shift Operator Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: shift operator "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any shift operator (sll, srl, sla, sra, rol, ror) which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is signal S : bit_vector(3 downto 0); begin process variable ShiftVector_v : bit_vector(3 downto 0) := "1011"; begin S <= ShiftVector_v sll 3; --warning on "sll" end process; end arch;
nLint reports: document.vhd(10): Warning 27561: shift operator "(ShiftVector_v sll 3)" is not synthesizable. (Synthesis)
27563 (VHDL) Non-static Operand in Multiplying or Miscellaneous Operation

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: operand "%s" in operation "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any unsuitable operand in multiplying or miscellaneous operation which is not synthesizable. For (/ mod rem) both operands should be static or the right operand should be a static power of 2; for (**) both operands should be static or the left operand should be a static value of 2. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 entity top_ety is port ( Clk : in bit ); end top_ety; architecture arch of top_ety is constant Num1_c : integer := 16; constant Num2_c : integer := 17; begin process( Clk ) variable Num1_v : integer; variable Num2_v : integer; variable Result : integer; begin Result := Num1_v / 2; --warning Result:= 5 / 3; --warning Result := 5 / (2+2); Result := Num1_v mod Num2_c; --warning Result := Num2_c rem Num1_c; Result := 2 ** 7; Result := Num1_c ** Num2_c; --warning end process; end arch;
here here here
here
nLint reports: document.vhd(14): Warning 27563: operand "Num1_v" in operation "(num1_v / 2)" is not synthesizable. (Synthesis) document.vhd(15): Warning 27563: operand "3" in operation "(5 / 3)" is not synthesizable. (Synthesis) document.vhd(17): Warning 27563: operand "Num1_v" in operation "(num1_v mod num2_c)" is not synthesizable. (Synthesis) document.vhd(20): Warning 27563: operand "num1_c" in operation "(num1_c ** num2_c)" is not synthesizable. (Synthesis)
27565 (VHDL) Null for Expression Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: null for expression here is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any literal null used as expression which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 entity top_ety is port ( Clk : in bit ); end top_ety; architecture arch of top_ety is type AInt_Typ is access integer; shared variable AInt_v : Aint_Typ := null; --no warning here ----Initial value ignored begin process (Clk) variable Bint : integer; begin if ( Clk = '1' ) then report "Clock is OK" severity warning; elsif ( Clk = '0' ) then Bint := null; --warning here end if; end process; end arch;
nLint reports: document.vhd(16): Warning 27565: null for expression here is not synthesizable. (Synthesis)
27567 (VHDL) Allocator and Deallocator Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: allocator or deallocator operation "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there are allocator and deallocator operations which are not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is end top_ety; architecture arch of top_ety is type AInt_Typ is access integer; begin process variable AInt1_v, AInt2_v : Aint_Typ; begin Aint1_v := new integer'(5); --warning on "new" Aint2_v := new integer; --warning on "new" Aint2_v.all := Aint1_v.all; Deallocate(Aint1_v); --warning on "Deallocate" end process; end arch;
nLint reports: document.vhd(10): Warning 27567: allocator or deallocator operation "new " is not synthesizable. (Synthesis) document.vhd(11): Warning 27567: allocator or deallocator operation "new " is not synthesizable. (Synthesis) document.vhd(13): Warning 27567: allocator or deallocator operation "deallocate" is not synthesizable. (Synthesis)
27571 (VHDL) Wait on Sensitivity List Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: keyword "on" in wait statement is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any wait on sensitivity list statement which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is port ( Clock: in bit; D : in bit; Q : out bit ); end top_ety; architecture arch of top_ety is begin process begin wait on Clock until Clock = '1'; Q <= D; end process; end arch;
--warning here
nLint reports: document.vhd(11): Warning 27571: keyword "on" in wait statement is not synthesizable. (Synthesis)
27573 (VHDL) Timeout Clause in Wait Statement Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: timeout clause in wait statement is ignored by synthesis. Configurable Parameter Rule group: Synthesis, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any timeout clause in wait statement which is ignored by synthesis and may cause simulation mismatch. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity top_ety is port ( Clk : in bit; D : in bit; Q : out bit ); end top_ety; architecture arch of top_ety is begin process begin -- [wher=IEEE Standard for VHDL RTL Synthesis, -Level 1: Draft 1.4 8.8.1] wait for 10 ns; --warning here if ( Clk'event and Clk = '1' ) then Q <= D; end if; end process; end arch;
nLint reports: document.vhd(13): Warning 27573: timeout clause in wait statement is ignored by synthesis. (Simulation,Synthesis)
27575 (VHDL) Assertion Statement Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: assertion statement is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any assertion statement which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 entity top_ety is end top_ety; architecture arch of top_ety is signal Rst : bit; begin process begin assert Rst = '1' --warning on "assert" report "Async reset detected" severity warning; end process; end arch;
nLint reports: document.vhd(9): Warning 27575: assertion statement is ignored by synthesis. (Synthesis)
27577 (VHDL) Report Statement Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: report statement is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any report statement which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 entity top_ety is port ( Clk : in bit; D : in bit; Q : out bit ); end top_ety; architecture arch of top_ety is begin process( Clk ) begin if ( Clk'event and Clk = '1' ) then Q <= D; else report "Clk is down" severity warning; --warning here end if; end process; end arch;
nLint reports: document.vhd(14): Warning 27577: report statement is not synthesizable. (Synthesis)
27581 (VHDL) Transport Delay in Signal Assignment Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: transport delay in signal assignment is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any transport delay which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is signal Sig : bit; signal ABC_s1 : bit; signal ABC_s2 : bit; signal ABC_s3 : bit; begin ABC_s1 <= transport Sig; --warning on "transport" ABC_s2 <= inertial Sig; ABC_s3 <= reject 10 ns inertial Sig; end arch;
nLint reports: document.vhd(10): Warning 27581: transport delay in signal assignment is ignored by synthesis. (Synthesis)
27585 (VHDL) Multiple Waveform Elements Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: multiple waveform elements are not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is waveform with multiple elements which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 entity top_ety is end top_ety; architecture arch of top_ety is signal Sig : bit; signal ABC_s : bit; begin ABC_s <= Sig after 10 ns, not Sig after 20 ns, Sig after 30 ns; end arch;
--warning on "not Sig"
nLint reports: document.vhd(9): Warning 27585: multiple waveform elements are not synthesizable. (Synthesis)
27587 (VHDL) Unaffected Clause Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: unaffected clause is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any unaffected clause which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 entity top_ety is end top_ety; architecture arch of top_ety is signal ABC_s : bit; begin ABC_s <= unaffected; --warning on "unaffected" end arch;
nLint reports: document.vhd(7): Warning 27587: unaffected clause is not synthesizable. (Synthesis)
27589 (VHDL) After Clause Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: after clause is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any after clause which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is end top_ety; architecture arch of top_ety is signal ABC_s : bit; begin ABC_s <= '1' after 20 ns; --warning on "after" end arch;
nLint reports: document.vhd(7): Warning 27589: after clause is ignored by synthesis. (Synthesis)
27595 (VHDL) POSTPONED Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: POSTPONED is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any POSTPONED which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 entity top_ety is 2 port (Clock : in bit; 3 Data : in bit); 4 end top_ety; 5 6 architecture arch of top_ety is 7 signal ABC1_s : bit; 8 signal ABC2_s : integer; 9 signal Sele_S : bit_vector(1 downto 0); 10 signal S1, S2 : bit; 11 procedure ABC_proc (A: in bit; B: in bit) is 12 begin 13 null; 14 end ABC_proc; 15 begin 16 postponed process( Clock ) --warning on "postponed" 17 begin 18 end process; 19 20 Proc_Lbl: postponed ABC_proc(A=>S1, B=>S2); --warning on "postponed" 21 22 postponed assert (true) report "Wrong" severity warning; --warning on "postponed" 23 24 postponed ABC1_s <= Data when Clock = '1' else --warning on "postponed" 25 not Data when Clock = '0'; 26 27 postponed with Sele_S select --warning on "postponed" 28 ABC2_s <= 0 when "00", 29 1 when "01", 30 2 when "10", 31 3 when "11"; 32 end arch;
nLint reports: document.vhd(16): document.vhd(20): document.vhd(22): document.vhd(24): document.vhd(27):
Warning Warning Warning Warning Warning
27595: 27595: 27595: 27595: 27595:
POSTPONED POSTPONED POSTPONED POSTPONED POSTPONED
is is is is is
not not not not not
synthesizable. synthesizable. synthesizable. synthesizable. synthesizable.
(Synthesis) (Synthesis) (Synthesis) (Synthesis) (Synthesis)
27597 (VHDL) Guarded Expression Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: guarded expression "%s" in block statement is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any guarded expression in block which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is port (Clock: in bit; Cin : in bit; Cout : out bit); end top_ety; architecture arch of top_ety is begin Blk_Lbl: block ( Clock = '1' ) begin Cout <= guarded Cin; end block Blk_Lbl; end arch;
--warning on "Clock = '1'"
nLint reports: document.vhd(9): Warning 27597: guarded expression "(Clock = '1')" in block statement is not synthesizable. (Synthesis)
27598 (VHDL) Explicit Signal GUARD Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: explicit guarded signal "%s" in block statement is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any explicit signal GUARD declaration in block which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 entity top_ety is end top_ety; architecture arch of top_ety is signal IN_1 : bit; signal OUT_1 : bit; begin ALU : block signal GUARD: Boolean := False; -- Warning here. begin OUT_1 <= guarded not IN_1 after 5 ns; P_1: process begin GUARD <= True; wait; end process P_1; end block ALU; end arch;
nLint reports: document.vhd(9): Warning 27598: explicit guarded signal "GUARD" in block statement is not synthesizable. (Synthesis)
27599 (VHDL) Guarded Signal Assignment Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: guarded signal assignment is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any explicit and implicit guarded signal assignment which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is port ( Clock : in bit; Cin : in bit; Cout : out bit); end top_ety; architecture arch of top_ety is begin Blk_Lbl: block (Clock = '1') begin Cout <= guarded Cin; --warning on "guarded" end block Blk_Lbl; end arch;
nLint reports: document.vhd(11): Warning 27599: guarded signal assignment is not synthesizable. (Synthesis)
27601 (VHDL) Block Header Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: block header is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any block header which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 entity top_ety is port (Clock : in bit; S1 : in bit; S2 : in bit ); end top_ety; architecture arch of top_ety is signal A,B : bit; begin Blk_Lbl: block (Clock = '1') --warning on "Blk_Lbl" generic (Width : integer); generic map (Width => 4); port (A,B : in Bit); port map (A=>S1, B=>S2); begin end block Blk_Lbl; end arch;
nLint reports: document.vhd(11): Warning 27601: block header is not synthesizable. (Synthesis)
27605 (VHDL) Binding Specification in Component Instantiation Statement Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: binding specification "%s" in component instantiation statement is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any binding specification in component instantiation statement which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 library IEEE; use IEEE.std_logic_1164.all; entity Reg is port ( Clk : in bit; Data : in bit; D : out bit); end Reg; architecture Reg_RTL of Reg is begin process (Clk) begin if (Clk'event and Clk = '1') then D <= Data; end if; end process; end Reg_RTL; configuration Reg_Conf of Reg is for Reg_RTL end for; end configuration Reg_Conf; use work.all; entity top_ety port( Clk : Data : D : end top_ety;
is in bit; in bit; out bit);
architecture arch of top_ety is component com_Reg is port( Clk : in bit; Data : in bit; D : out bit); end component com_Reg; begin U1: component com_Reg port map( Clk, Data, D); U2: entity Reg(Reg_RTL) port map( Clk, Data, D); --warning on "entity"
46 47 48 49
U3: configuration Reg_Conf port map( Clk, Data, D); end arch;
--warning on "configuration"
nLint reports: document.vhd(43): Warning 27605: binding specification "entity" in component instantiation statement is not synthesizable. (Synthesis) document.vhd(46): Warning 27605: binding specification "configuration" in component instantiation statement is not synthesizable. (Synthesis)
27609 (VHDL) Non-synthesizable Pre-defined Attribute

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: pre-defined attribute "%s" for "%s" or expression in attribute is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there are any unsuitable predefined attributes which are not synthesizable. The following pre-defined attributes are synthesizable: t'base; t'left; t'right; t'high; t'low; t'value(x); t'pos(x); t'val(x); t'succ(x); a'left; a'right; a'high; a'low; a'range; a'reverse_range; a'length; s'stable; s'event t -- type a -- array (two and up dimensions array are not supported, so a'attribute_name(n) is not supported, eg: ABC'length(2) s -- signal The following pre-defined attributes are not synthesizable: t'ascending, t'image, t'pred(x), t'leftof(x), t'rightof(x) a'ascending, a'ascending(n) s'delayer, s'delayer(t), s'quiet, s'transaction, s'active, s'last_event, s'last_active, s'last_value, s'driving, s'driving_value e'simple_name, e'instance_name, e'path_name attribute foreign Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; entity top_ety is port (d : in signed; clk : bit; o : out signed ); end top_ety; architecture arch of top_ety is begin p1 : process( clk ) begin if ( clk'last_value = '0' and clk = '1' ) then --warning on "last_value" o <= d; end if; end process; end arch;
nLint reports: document.vhd(15): Warning 27609: pre-defined attribute "last_value" for "clk" or expression in attribute is not synthesizable. (Synthesis)
27610 (VHDL) Expression in Attribute Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: expression "%s" in attribute "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any expression used in some synthesizable attributes, of which the use of expression is not synthesizable. Although following attributes are allowed: a'left; a'right; a'high; a'low; a'range; a'reverse_range; a'length; s'stable; But the above attributes with an index (position or time point) are not-synthesizable: a'left(n); a'right(n); a'high(n); a'low(n); a'range(n); a'reverse_range(n); a'length(n); s'stable(t); t -- type a -- array (two and up dimensions array are not supported, so a'attribute_name(n) is not supported, eg: ABC'length(2) s -- signal Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 entity top_ety is port ( Clk : in bit ); end top_ety; architecture arch of top_ety is type TwoDim is array( integer range <>, integer range <> ) of bit; type ThreeDim is array( integer range <>, integer range <>, integer range <> ) of bit; signal S1 : TwoDim( 1 to 3, 1 to 3 ); signal S2 : ThreeDim( 1 to 3, 1 to 3, 1 to 3 ); signal S3 : TwoDim( 1 to 3, 1 to 3 ); signal S4 : ThreeDim( 1 to 3, 1 to 3, 1 to 3 ); signal O1 : integer; signal O2 : integer; signal O3 : integer; signal O4 : integer; begin process( Clk ) begin if ( Clk'event and Clk = '1' ) then O1 <= S1'high(2); O2 <= S2'low(3); O3 <= S3'left(2); O4 <= S4'right(3); end if; end process; end arch;
nLint reports: document.vhd(21): Warning 27610: expression "2" in attribute "high" should not be
used because it is not synthesizable. (Synthesis) document.vhd(22): Warning 27610: expression "3" in attribute "low" should not be used because it is not synthesizable. (Synthesis) document.vhd(23): Warning 27610: expression "2" in attribute "left" should not be used because it is not synthesizable. (Synthesis) document.vhd(24): Warning 27610: expression "3" in attribute "right" should not be used because it is not synthesizable. (Synthesis)
27613 (VHDL) Package TEXTIO Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: package "std.textio" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any reference to package TEXTIO which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 library std; use std.textio.all; entity top_ety is end top_ety; architecture arch of top_ety is begin end arch;
--warning on "TEXTIO"
nLint reports: document.vhd(2): Warning 27613: package "std.textio" is not synthesizable. (Synthesis)
27615 (VHDL) Wait Statement in Sub-program Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: wait statement is not synthesizable in sub-program. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any wait statement used in sub-program which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; entity top_ety is port (d1 : in signed; d2 : in signed; o : out signed ); end top_ety; architecture arch of top_ety is procedure test (a : in signed; b : in signed; signal c : out signed ) is begin wait for 10 ns; --warning here c <= a + b; end test; begin l1:test( d1, d2, o ); end arch;
nLint reports: document.vhd(17): Warning 27615: wait statement is not synthesizable in subprogram. (Synthesis)
27617 (VHDL) Use Clause Not Referencing the Entire Package

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: use clause should not reference only a portion of a package. Instead, it should reference the entire package. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any use clause that references only a portion of a package which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 library IEEE; use IEEE.STD_LOGIC_1164.std_ulogic; --warning here entity top_ety is port (d : in std_ulogic; o : out std_ulogic ); end top_ety; architecture arch of top_ety is begin o <= d; end arch;
nLint reports: document.vhd(2): Warning 27617: use clause should not reference only a portion of a package. Instead, it should reference the entire package. (Synthesis)
27619 (VHDL) Physical Type Declaration Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: physical type declaration "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any physical type definition which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 entity top_ety is end top_ety; architecture arch of top_ety is type distance is range -2147483647 to 2147483647 --warning here units nm; um = 1000 nm; mm = 1000 um; m = 1000 mm; km = 1000 m; end units; begin end arch;
nLint reports: document.vhd(5): Warning 27619: physical type declaration "distance" is ignored by synthesis. (Synthesis)
27621 (VHDL) Floating Type Declaration Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: floating type declaration "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any floating type definition which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 entity top_ety is end top_ety; architecture arch of top_ety is type small_float is range -10.0 to 10.0; --warning here begin end arch;
nLint reports: document.vhd(5): Warning 27621: floating type declaration "small_float" is ignored by synthesis. (Synthesis)
27623 (VHDL) File Type Enumeration Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: file type enumeration "%s" is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any pre-defined file type enumeration (FILE_OPEN_KIND, FILE_OPEN_STATUS), which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is end top_ety; architecture arch of top_ety is type IntFile_Typ is file of integer; file DataOut_f : IntFile_Typ open Write_Mode is "IntOut.txt"; begin process variable Int_v : integer := 0; variable fStatus_v : File_Open_Status; --warning here begin write( F => DataOut_f, Value => Int_v); Endfile(DataOut_f); end process; end arch;
nLint reports: document.vhd(10): Warning 27623: file type enumeration "file_open_status" is not synthesizable. (Synthesis)
27625 (VHDL) Severity Level Enumeration Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: severity level enumeration "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any pre-defined severity level enumeration (SEVERITY_LEVEL) used which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 library IEEE; use IEEE.STD_LOGIC_1164.all; entity top_ety is signal monitor : bit := '0'; signal s : severity_level := NOTE; --warning here begin end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(6): Warning 27625: severity level enumeration "severity_level" is ignored by synthesis. (Synthesis)
27627 (VHDL) File Type Declaration Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: file type declaration "%s" is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any file type declaration because it is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 entity top_ety is end top_ety; architecture arch of top_ety is type IntFile_Typ is file of integer; --warning on "IntFile_Typ" file DataOut_f : IntFile_Typ open Write_Mode is "IntOut.txt"; begin process variable Int_v : integer := 0; variable fStatus_v : File_Open_Status; begin write( DataOut_f, Int_v ); Endfile(DataOut_f); wait; end process; end arch;
nLint reports: document.vhd(5): Warning 27627: file type declaration "IntFile_Typ" is ignored by synthesis. (Synthesis)
27629 (VHDL) File in Port Association Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: file "%s" in port association should not be used because the file in interface is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any file name used in port association which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 library IEEE; use IEEE.STD_LOGIC_1164.all; entity top_ety is end top_ety; architecture arch of top_ety is type IntFile_Typ is file of integer; file Out_f : IntFile_Typ open Write_Mode is "IntOut.txt"; function wfile( file DataOut_f : IntFile_Typ ) return boolean is variable Int_v : integer := 0; begin for count_i in 1 to 10 loop Int_v := Int_v + 1; write( F => DataOut_f, Value => Int_v ); end loop; return true; end wfile; begin p1 : process begin wait for 10 ns; wfile( DataOut_f => Out_f ); --warning here end process; end arch;
nLint reports: document.vhd(15): Warning 27629: file be used because the file in interface document.vhd(24): Warning 27629: file used because the file in interface is
"DataOut_f" in port association should not is not synthesizable. (Synthesis) "Out_f" in port association should not be not synthesizable. (Synthesis)
27631 (VHDL) VHDL-93 Only Syntax Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: "%s" should not be used because it is VHDL-93 only and is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any VHDL-93 only syntax which may not be supported by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 entity Reg_com is port( Clk : in bit; Data : in bit; D : out bit); end entity Reg_com; --warning on "entity" architecture arch of Reg_com is begin process (Clk) begin if (Clk'event and Clk = '1') then D <= Data; end if; end process; end architecture arch; --warning on "architecture" library IEEE; use IEEE.STD_Logic_1164.all; use IEEE.Numeric_STD.all; use work.all; entity top_ety is port (Clock: in bit; Rst : in bit; Data : in bit; D : out bit; Q : out bit ); end top_ety; architecture arch signal ABC_s : signal ABC_s2 : signal SI : signal CS : shared variable of top_ety is bit; bit; integer; bit_vector(1 downto 0); SV : integer;
component Reg_com is --warning on "is" port( Clk : in bit; Data : in bit; D : out bit); end component Reg_com; --warning on "component" function ABC_F( A: bit; B: bit ) return bit is begin Ret_Lbl: return B; --warning on "Ret_Lbl" end function ABC_F; --warning on "function"
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98
procedure Bit2Int(A: in bit; B: out integer) is begin if A = '1' then B := 1; else B := 0; end if; end procedure Bit2Int; --warning on "procedure" begin Blk_Lbl: block is --warning on "Blk_Lbl" begin end block Blk_Lbl; process( Clock ) is --warning here begin end process; Pro_Lbl: Process(Clock) variable ABC_v : bit; variable B : integer; begin If_Lbl: if Clock'event and Clock = '1' then --warning on "If_Lbl" SAssign_Lbl: ABC_s <= '1'; --warning on "SAssign_Lbl" VAssign_Lbl: ABC_v := '1'; --warning on "VAssign_Lbl" else Null_Lbl: null; --warning on "Null_Lbl" end if; -- end if If_Lbl; Ass_Lbl: assert Rst = '1' --warning on "Ass_Lbl" report "Async reset detected" severity warning; Rep_Lbl: report "Hold time checked error" --warning on "Rep_Lbl" severity warning; Proc_Lbl: Bit2Int(ABC_s, B); --warning on "Proc_Lbl" Case_Lbl: case CS is when "00" => null; when "01" => null; when "10" => null; when "11" => null; end case Case_Lbl; --warning on "Case_Lbl"
Loop_Lbl: for index_v in 0 to 5 loop Next_Lbl: next Loop_Lbl when index_v = 3; --warning on "Next_Lbl"(only Next_Lbl is unsupport) Exit_Lbl: exit Loop_Lbl when index_v = 4; --warning on "Exit_Lbl"(only Exit_Lbl is unsupport) SI <= SI + index_v; end loop Loop_Lbl; end process Pro_Lbl; Conc_Proc_Lbl: Bit2Int( ABC_s, SV ); --warning on "Conc_Proc_Lbl"
Cond_Assign_Lbl: ABC_s2 <= Data when Clock = '1' else --warning here on "Cond_Assign_Lbl" not Data when Clock = '0'; Sele_Assign_Lbl: with CS select --warning here on "Sele_Assign_Lbl" SI <= 0 when "00", 1 when "01", 2 when "10", 3 when "11"; Lbl: for I in 1 to 2 generate signal S2 : integer; begin --warning on "begin" S2 <= SI; end generate Lbl; U1: Reg_com port map( Clock, Data, D); U2: component Reg_com --warning on "component"
98 98 98
port map( Clock, Data, D); end arch;
nLint reports: document.vhd(5): Warning 27631: "entity" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(15): Warning 27631: "architecture" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(38): Warning 27631: "is" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(42): Warning 27631: "Reg_com" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(46): Warning 27631: "Ret_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(47): Warning 27631: "function" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(56): Warning 27631: "procedure" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(59): Warning 27631: "is" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(63): Warning 27631: "is" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(71): Warning 27631: "If_Lbl" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(72): Warning 27631: "SAssign_Lbl" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(73): Warning 27631: "VAssign_Lbl" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(75): Warning 27631: "Null_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(78): Warning 27631: "Ass_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(80): Warning 27631: "Rep_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(83): Warning 27631: "Proc_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(85): Warning 27631: "Case_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(93): Warning 27631: "Next_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(95): Warning 27631: "Exit_Lbl" should not be used because it is VHDL93 only and is not synthesizable. (Synthesis) document.vhd(102): Warning 27631: "Conc_Proc_Lbl" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(104): Warning 27631: "Cond_Assign_Lbl" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(108): Warning 27631: "Sele_Assign_Lbl" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(116): Warning 27631: "begin" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis) document.vhd(123): Warning 27631: "component" should not be used because it is VHDL-93 only and is not synthesizable. (Synthesis)
27633 (VHDL) Configuration Specification Ignored by Synthesis

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: configuration specification is ignored by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any configuration specification which is ignored by synthesis. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; entity AAA is port (a : in signed; b : in signed; o : out signed ); end AAA; architecture TEST_AAA of AAA is begin p2 : process( a, b ) is begin o <= a + b; end process; end TEST_AAA; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; library WORK; use WORK.all; entity top_ety is port (c1 : in signed; c2 : in signed; o : out signed ); end top_ety; architecture arch of top_ety is component COM_AAA is port (a : in signed; b : in signed; o : out signed ); end component; for u_AAA_1 : COM_AAA --warning here use entity AAA(TEST_AAA); begin u_AAA_1 : COM_AAA port map ( a=>c1, b=>c2, o=>o ); end arch;
nLint reports: document.vhd(38): Warning 27633: configuration specification is ignored by synthesis. (Synthesis)
27635 (VHDL) Index Name on Unconstrained Object Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: using an index name "%s" of an unconstrained out parameter "%s" in a procedure shall not be supported. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any index name of an unconstrained out parameter in a procedure. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 entity top_ety is end top_ety; architecture arch of top_ety is procedure SetZero( signal Data_s : out bit_vector ) is begin Data_s(0) <= '1'; --warning here for i in Data_s'range loop Data_s(i) <= '0'; end loop; end SetZero; begin end arch;
nLint reports: document.vhd(8): Warning 27635: using an index name "0" of an unconstrained out parameter "Data_s" in a procedure shall not be supported. (Synthesis)
27639 (VHDL) Explicit Inertial Delay Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: explicit inertial delay in signal assignment should not used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any inertial delay (reject, inertial) specified in signal assignment which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 entity top_ety is end top_ety; architecture arch of top_ety is signal Sig : bit; signal ABC_s1 : bit; signal ABC_s2 : bit; signal ABC_s3 : bit; begin ABC_s1 <= transport Sig; ABC_s2 <= inertial Sig; --warning on "inertial" ABC_s3 <= reject 10 ns inertial Sig; --warning on "inertial" end arch;
nLint reports: document.vhd(11): Warning 27639: explicit inertial delay in signal assignment should not used because it is not synthesizable. (Synthesis) document.vhd(12): Warning 27639: explicit inertial delay in signal assignment should not used because it is not synthesizable. (Synthesis)
27641 (VHDL) Meta-logic Value in Case Choice

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: meta-logic value "%s" in case choice should not be used because it is interpreted as never-occur by synthesis. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any meta-logic value used in case choice which is interpreted as never-occur by synthesis tool. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 library IEEE; use IEEE.STD_LOGIC_1164.all; entity top_ety is subtype my_vec is std_ulogic_vector(1 downto 0); end top_ety; architecture arch of top_ety is signal c_s : my_vec; signal n_s : my_vec; begin p1 : process( c_s ) begin case c_s is when "X0" => --warning here n_s <= "01"; when "0Z" => --warning here n_s <= "10"; when others => n_s <= "00"; end case; end process; end arch;
nLint reports: document.vhd(15): Warning 27641: meta-logic value ""X0"" in case choice should not be used because it is interpreted as never-occur by synthesis. (Synthesis) document.vhd(17): Warning 27641: meta-logic value ""0Z"" in case choice should not be used because it is interpreted as never-occur by synthesis. (Synthesis)
27643 (VHDL) Edge Specification in Concurrent Signal Assignment Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: edge specification in concurrent signal assignment not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any edge specification in concurrent signal assignment which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 library IEEE; use IEEE.STD_LOGIC_1164.all; entity top_ety is end top_ety; architecture arch of top_ety is subtype my_vec is std_ulogic_vector(1 downto 0); signal c_s : my_vec; signal n_s : my_vec; signal clk : bit; signal rst : bit; begin n_s <= "00" when rst = '1' else c_s when clk'event and clk = '1' --warning here else "XX"; end arch;
nLint reports: document.vhd(15): Warning 27643: edge specification in concurrent signal assignment not synthesizable. (Synthesis)
27645 (VHDL) Same Signal Assigned and Referenced in Waveforms Not Synthesizable
Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: same signal "%s" assigned and referenced in waveforms should not be used in concurrent assignment because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any same signal assigned and referenced in waveforms of concurrent signal assignment at the same time, which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 library IEEE; use IEEE.STD_LOGIC_1164.all; entity top_ety is end top_ety; architecture arch of top_ety is subtype my_vec is std_ulogic_vector(1 downto 0); signal c_s : my_vec; signal n_s : my_vec; signal rst : bit; begin n_s <= "00" when rst = '1' else not n_s when rst = '0' else --warning here "XX"; end arch;
nLint reports: document.vhd(14): Warning 27645: same signal "n_s" assigned and referenced in waveforms should not be used in concurrent assignment because it is not synthesizable. (Synthesis)
27649 (VHDL) Generate Parameter Specification Not Static

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: generate scheme "%s" can not be statically evaluated which is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any generate scheme that cannot be statically evaluated (for example it is not static expression or not in the form "identifier in range"). It is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; entity AAA is port (a : in signed; b : in signed; o : out signed ); end AAA; architecture TEST_AAA of AAA is begin p2 : process( a, b ) begin o <= a + b; end process; end TEST_AAA; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; library WORK; use WORK.all; entity top_ety is subtype my_signed is signed(3 downto 0); signal c1 : my_signed; signal c2 : my_signed; signal n : my_signed; signal o : signed(15 downto 0); end top_ety; architecture arch of top_ety is component AAA port (a : in my_signed; b : in my_signed; o : out my_signed ); end component; begin G : if n=1 generate --warning here u_AAA_1 : AAA port map ( a=>c1, b=>c2, o=>o(3 downto 0 ) );
44 45
end generate; end arch;
nLint reports: document.vhd(41): Warning 27649: generate scheme "(n = 1)" can not be statically evaluated which is not synthesizable. (Synthesis)
27651 (VHDL) Extended Identifier Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: extended identifier "%s" should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any extended identifier used which is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 library IEEE; use IEEE.STD_LOGIC_1164.all; entity top_ety is signal 123 _$%: std_logic; --warning here end top_ety; architecture 7(*&)of top_ety is --warning here begin end 7(*&) --warning here
nLint reports: document.vhd(5): Warning 27651: extended identifier "123 _$% should not be used because it is not synthesizable. (Synthesis) document.vhd(8): Warning 27651: extended identifier "7(*&) should not be used because it is not synthesizable. (Synthesis) document.vhd(10): Warning 27651: extended identifier "7(*&) should not be used because it is not synthesizable. (Synthesis)
27653 (VHDL) Clock Signal Type Not BIT or STD_ULOGIC

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: clock signal "%s" should be of BIT or STD_ULOGIC data type. Otherwise it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any clock signal whose type is not of BIT or STD_ULOGIC data type. Otherwise it is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library ieee; use ieee.std_logic_1164.all; entity top_ety is end top_ety; architecture arch of top_ety is signal clk : integer range 0 to 1; signal d : integer; signal q : integer; begin p1 : process( clk ) begin if( clk'event and clk = 1 ) then --warning here q <= d; end if; end process; end arch;
nLint reports: document.vhd(14): Warning 27653: clock signal "clk" should be of BIT or STD_ULOGIC data type. Otherwise it is not synthesizable. (Synthesis)
27655 (VHDL) Else Branch Following Edge Condition Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: the else branch following an edge condition branch should not be used because it is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any edge condition branch with else branch because the coding style is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 entity top_ety is end top_ety; architecture arch of top_ety is signal clk : bit; signal rst : bit; signal set : bit; signal d : integer; signal q : integer; begin p1 : process( clk, rst, set ) begin if ( rst = '1' ) then q <= 0; elsif( clk'event and clk = '1' ) then q <= d; elsif ( set = '1' ) then --warning here q <= 1; end if; end process; end arch;
nLint reports: document.vhd(15): Warning 27655: the else branch following an edge condition branch should not be used because it is not synthesizable. (Synthesis)
27657 (VHDL) Statements Outside of Edge-sensitive If Statement Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: statements outside of an edge-sensitive ifstatement not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any statement placed outside of edge-sensitive ifstatement because the coding style is not synthesizable. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 entity top_ety is port( clk : in bit; rst : in bit; set : in bit; d : in bit; q : out bit ); end top_ety; architecture arch of top_ety is begin p1 : process( clk, rst ) begin if ( set = '1' ) then q <= '1'; --warning here end if; if ( rst = '1' ) then q <= '0'; elsif( clk'event and clk = '1' ) then q <= d; end if; end process; end arch;
nLint reports: document.vhd(14): Warning 27657: statements outside of an edge-sensitive ifstatement not synthesizable. (Synthesis)
27661 Asynchronous Reference in Edge-sensitive Logic

Message <filename>(<line no.>): <severity> <rule no.>: signal "%s" is being read asynchronously. It may cause simulation-synthesis mismatch. Configurable Parameter Rule group: Synthesis, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there is any signal being read asynchronously in an edge-sensitive logic. It may cause simulation-synthesis mismatches. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test (a, b, clk, reset, chk); output a; input b, clk, reset, chk; reg a; always @(posedge clk or posedge reset or posedge chk) if (reset) a <= 0; else if (chk) a <= b; //warning here else a <= a; endmodule
nLint reports: document.v(9): Warning 27661: signal "b" is being read asynchronously. It may cause simulation-synthesis mismatch. (Simulation,Synthesis)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 entity top_ety is end; architecture arch of top_ety is signal clk : bit; signal chk : bit; signal rst : bit; signal a : bit; signal b : bit; begin process( clk, chk, rst ) begin if ( rst = '0' ) then a <= '0'; elsif ( chk = '0' ) then a <= b; --warning here elsif ( clk'event and clk = '1' ) then a <= a; end if; end process; end;
nLint reports: document.vhd(16): Warning 27661: signal "b" is being read asynchronously. It may cause simulation-synthesis mismatch. (Simulation,Synthesis)
27662 (Verilog) Dual Set or Reset Detected

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" has already been set or reset at line %d. Configurable Parameter Rule group: Synthesis, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any dual asynchronous sets or resets exist in edgesensitive logic to avoid potential simulation-synthesis mismatches. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test (clock, ctrl1, ctrl2, q, d); input clock, ctrl1, ctrl2; input d; output q; reg q; always @( posedge clock or negedge ctrl1 or negedge ctrl2 ) if ( !ctrl1 ) q <= #1 1'b0; //ctrl1 is treated as reset else if ( !ctrl2 ) q <= #1 1'b0; //ctrl2 is treated as reset, warning here else q <= d; endmodule
nLint reports: document.v(11): Warning 27662: signal "q" has already been set or reset at line 9. (Simulation,Synthesis)
27663 (VHDL) Unconstrained Port Not Synthesizable

Message (VHDL) <filename>(<line no.>): <severity> <rule no.>: unconstrained port "%s" declaration shall not be supported. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (VHDL) This rule checks whether there is any unconstrained port declaration in entity. Example
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 entity top_ety is port (a : in bit_vector; --warning q2 : out bit_vector ); --warning end top_ety; architecture arch of top_ety is begin end arch;
nLint reports: document.vhd(2): Warning 27663: unconstrained port "a" declaration shall not be supported. (Synthesis) document.vhd(3): Warning 27663: unconstrained port "q2" declaration shall not be supported. (Synthesis)
27664 (Verilog) Large Multiplier Inferred

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: do not infer large multiplier by the operand "%s" whose bit-width is larger than %d. Configurable Parameter Rule group: Synthesis; Argument type: integer; Argument description: specify the maximum number of bit-width for inferred multipliers; Default value: "16" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the bit width of inferred multipliers at RTL level is within the specified limit. A violation will be reported when the bit width exceeds the specified argument value. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module smp(IN1, IN2, OUT1, OUT2); input [16:0] IN1; input [15:0] IN2; output [16:0] OUT1; output [15:0] OUT2; reg [16:0] OUT1; reg [15:0] OUT2; always @(IN1 or IN2) if(IN1 < IN2) OUT1 = IN1 * 2; //warning here if width argument is set to 16 else OUT1 = IN1 / 2; always @(IN1 or IN2) if(IN2 > IN1) OUT2 = IN2 * 4; //no warning here else OUT2 = IN2 / 4; endmodule
nLint reports following if the argument value is ("16"): document.v(13): Warning 27664: do not infer large multiplier by the operand "IN1" whose bit-width is larger than 16. (Synthesis)
27665 (Verilog) Bit Width Mismatch in Logical Operation

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: width of operand "%s"(%d) does not match that of operand "%s"(%d) in logical operation. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the signal bit width for logical operations are equivalent. A violation will be reported if the bit-width mismatches on the left/right side of the logical operator. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 module smp(A,B,C); input A; input[1:0] B; output C; assign C = ( A && B ) ? 1'b1 : 1'b0; endmodule //warning on (A && B) here
27666 (Verilog) Complex Repeating Statements is Not Allowed

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: do not use for statements for other than simple repeating statements (that do not generate priorities). Configurable Parameter Rule group: SC.Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is any complex repeating statements used in for loop. Example
(Verilog) ///////////////example : document_1.v//////////// 1 module smp(INA,F); 2 3 input[7:0] INA; 4 output F; 5 6 reg F; 7 8 integer I; 9 10 always @(INA) begin : loop 11 F = INA[0] ^ INA[1]; 12 for (I = 2; I <= 7; I = I + 1) 13 F = F ^ INA[I]; 14 end 15 16 endmodule 17 ///////////////example : document_2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module smp(INA,F); input[7:0] output reg F; reg A; integer I; always F = for A F end end endmodule @(INA) begin : loop INA[0] ^ INA[1]; (I = 2; I <= 7; I = I + 1) begin = F ^ INA[I]; = A; INA; F;
27667 (Verilog) Condition Signal Assigned to 'x' in Default Branch

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the signal "%s" is assigned to x in default clause of conditional expression (line %d). Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the signal in a condition expression is assigned to 'x' in the default branch of a case statement. A violation will be reported if a signal assigned to 'x' in the default clause of a case statement is referenced in any condition expression- including if and assign condition expression. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 module smp(zo,fout,sel,res,ck,fin); input[1:0] sel; input res, ck, fin; output[3:0] zo; output fout; reg [3:0] zo; reg fout; parameter D1=1; always@( sel ) case(sel) 2'b00: zo = 4'b0001; 2'b01: zo = 4'b0010; 2'b10: zo = 4'b0100; default: zo = 4'bxxxx; endcase always@( negedge res or posedge ck ) if( ~res ) fout <= #D1 1'b0; else if(zo==4'b0100) fout <= #D1 1'b1; else fout <= #D1 fin;
endmodule
27668 (Verilog) Arithmetic/Relational Operations Sharing with Large Operand Not Allowed
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: either arithmetic or relational operation "%s" whose operand is larger than %d bits is the same as expression in line %d. Configurable Parameter Rule group: Synthesis; Argument type: integer; Argument description: specify the maximum bit width number ; Default value: "8" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rules check whether either the arithmetic operator (+, -, *) or relational operator (<, >, =) are shared with a large bit-width operand. A violation will be reported if the operator is shared and if the bit-width of the operand exceeds the specified argument. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module smp(IN1, IN2, OUT1, OUT2); input [16:0] IN1; input [16:0] IN2; output [16:0] OUT1; output [16:0] OUT2; reg [16:0] OUT1; reg [16:0] OUT2; always @(IN1 or IN2) if(IN1 < IN2) OUT1 = IN1 * 2; else OUT1 = IN1 / 2; always @(IN1 or IN2) if(IN2 > IN1) OUT2 = IN2 * 4; else OUT2 = IN2 / 4; endmodule
27669 (Verilog) Timing Path Limited in Two Sub Blocks

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: timing path from "%s" to "%s" should be kept in two sub-blocks in basic block "%s". Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) A timing path is defined from an output of a flip-flop to an input of another flip-flop. If there are combinational logic in the timing path, all of them should be put into no more than two sub-blocks. Please note that checking is only within sub-blocks which are instantiated by a basic block. A block is a module instantiated by the top module which instates the linting. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 module sub (a, clk, q); input a, clk; output q; wire a, clk, b, q; reg q_temp; assign b = !a; always @(posedge clk) q_temp = b; assign q = !q_temp; endmodule module basic(clk, q); input clk; output q; wire clk, clk1, a, q1, q2, q; wire q1_temp, q2_temp; assign q1_temp = !q1; assign q2_temp = !q2; sub s1(a, clk, q1); sub s2(q1_temp, clk1, q2); sub s3(q2_temp, clk, q); endmodule module top(); wire a, clk; basic i1(clk, a); endmodule
nLint reports: document.v(8): Warning 27669: timing path from "top.i1.s2.sub:Always2#Always0:8:9:Reg" to "top.i1.s3.sub:Always2#Always0:8:9:Reg" should be kept in two sub-blocks in basic block "basic". (Synthesis) document.v(8): Warning 27669: timing path from "top.i1.s1.sub:Always2#Always0:8:9:Reg" to "top.i1.s2.sub:Always2#Always0:8:9:Reg" should be kept in two sub-blocks in basic block "basic". (Synthesis)
27670 (Verilog) Always Block Contains Multiple Resets

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: multiple asynchronous resets are specified in the same always construct. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there is only one reset in an always block. A violation is reported if the number of resets exceeds one in an always block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module smp(RES1,RES2,CK,FIN,FOUT); input output RES1,RES2,CK,FIN; FOUT;
reg FOUT; parameter D1 = 1; always@(negedge RES1 or negedge RES2 or posedge CK) if(~RES1 || ~RES2) FOUT <= #D1 1'b0; else FOUT <= #D1 FIN; endmodule
27671 (Verilog) Critical Path in Multiple Blocks

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the number of sub-blocks in the critical path from "%s" to "%s" is %d (should not exceed %d) in basic block "%s". Configurable Parameter Rule group: Synthesis; Argument type: integer; Argument description: specify the maximum number of sub-blocks; Default value: "3" for Verilog; Default severity : Level3 (Error) This rule is turned OFF by default; Description (Verilog) This rule checks whether a critical path crosses more than a specified number of subblocks. Please note that checking is only within sub-blocks which are instantiated by a basic block. A block is a module instantiated by the top module which instates the linting. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 module smp(tout1, tin1, tclk); output tout1; input tin1, tclk; wire ttmp1; MB1 X1(.mout1(ttmp1), .min1(tin1), .mclk(tclk)); MB2 X2(.mout1(tout1), .min1(ttmp1), .mclk(tclk)); endmodule
module MB1 (mout1, min1, mclk); output mout1; input min1, mclk; wire mtmp1, mtmp2, mtmp3, mtmp4; M1 M2 M2 M1 X11 X12 X14 X13 (.out1(mtmp1), (.out1(mtmp2), (.out1(mtmp3), (.out1(mtmp4), .in1(min1), .clk(mclk)); .in1(mtmp1), .in2(mtmp1)); .in1(mtmp2), .in2(mtmp2)); .in1(mtmp3), .clk(mclk));
assign mout1 = ~mtmp4; endmodule
module MB2 (mout1, min1, mclk); output mout1; input min1, mclk; wire mtmp1, mtmp2; M1 X21 (.out1(mtmp1), .in1(min1), .clk(mclk)); M1 X22 (.out1(mtmp2), .in1(mtmp1), .clk(mclk)); assign mout1 = ~mtmp2; endmodule
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
module M1 (out1, in1, clk); output out1; input in1, clk; wire int1; reg int2; assign int1 = ~in1; always @ (posedge clk) begin int2 <= int1; end assign out1 = ~int2; endmodule
module M2 (out1, in1, in2); output out1; input in1, in2; assign out1 = in1 & in2; endmodule
nLint reports following if the argument value is ("3"): document.v(56): Error 27671: the number of sub-blocks in the critical path from "smp.X1.X11.M1:Always2#Always0:56:59:Reg" to "smp.X1.X13.M1:Always2#Always0:56:59:Reg" is 4 (should not exceed 3) in basic block "MB1". (Synthesis)
27672 (Verilog) Large Bit Width of Reduction Operand

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the bit width of reduction operand "%s" is larger than %d. Configurable Parameter Rule group: Simulation; Argument type: integer; Argument description: specify the maximum bit width for the reduction operand; Default value: "32" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the bit width of reduction operands is within the specified limit. A violation will be reported when the bit-width exceeds the specified argument value. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module test; reg [39:0] a; wire b; assign b = &a; endmodule
nLint reports following if the argument value is ("32"): document.v(6): Warning 27672: the bit width of reduction operand "a" is larger than 32. (Simulation)
27673 (Verilog) Signal Written and Read in Same Always Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" is written and read in the same always block. Configurable Parameter Rule group: Simulation; Argument type: ( CHECK_TEMPVAR, IGNORE_TEMPVAR); Argument description: CHECK_TEMPVAR includes temporary variable, which is fully assigned before referenced in the checking; IGNORE_TEMPVAR ignores temporary variable in the checking; Default value: "IGNORE_TEMPVAR" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a signal is written and read in the same level sensitive always block. Example
(Verilog) ///////////////example : document_1.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test( AIN, BIN, CIN, QOUT ); input AIN, BIN, CIN; output QOUT; reg QOUT; reg tmp; always @( AIN or BIN or CIN) begin tmp <= AIN & BIN; if ( tmp == CIN ) QOUT <= 1'b0; else QOUT <= 1'b1; end endmodule
nLint reports following if the argument value is ("IGNORE_TEMPVAR"): document_1.v(7): Warning 27673: signal "tmp" is written and read in the same always block. (Simulation) ///////////////example : document_2.v//////////// 1 2 3 4 5 6 7 8 rule 9 10 11 12 13 14 module test( AIN, BIN, CIN, QOUT ); input AIN, BIN, CIN; output QOUT; reg QOUT; reg tmp; always @( AIN or BIN or CIN) begin tmp = AIN & BIN; //If choose IGNORE_TEMPVAR, tmp will not violate this if ( tmp == CIN ) QOUT <= 1'b0; else QOUT <= 1'b1; end endmodule
nLint reports following if the argument value is ("IGNORE_TEMPVAR"):
27674 (Verilog) Reduce Selectors with Same Contents

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: conditional expression has the same content "%s" as conditional expression in line %d. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the same content appears in different conditional expressions of an if statement. This will introduce redundant logics and may degrade the performance when the if statement is deep. The recommendation is to extract the identical content first and then re-construct the if statement based on new expressions. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module test( A, B, C, Y ); input A, B, C; output [2:0] Y; reg [2:0] Y; always @ (A or B or C) if ( A==1'b0 && B==1'b0 && C==1'b0 ) Y = 3'b010; else if ( A==1'b0 && B==1'b0 && C==1'b1 Y = 3'b101; else if ( A==1'b0 && B==1'b1 && C==1'b0 Y = 3'b100; else if ( A==1'b0 && B==1'b1 && C==1'b1 Y = 3'b000; else if ( A==1'b1 && B==1'b0 && C==1'b0 Y = 3'b001; else if ( A==1'b1 && B==1'b0 && C==1'b1 Y = 3'b110; else if ( A==1'b1 && B==1'b1 && C==1'b0 Y = 3'b111; else Y = 3'b011; endmodule
) ) ) ) ) )
27675 (Verilog) Simple Signal Names for Array Index

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: index name "%s" should be simple signal name. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any expressions used as an array index. Example
(Verilog) ///////////////example : document.v2k//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module smp(A,C,D,DOUT1,DOUT2,DOUT3,DOUT4,DOUT5,DOUT6); input [3:0] A; input [1:0] C,D; output DOUT1,DOUT2; output [1:0] DOUT3, DOUT4, DOUT5,DOUT6; assign assign assign assign assign assign DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 = = = = = = A[C+1]; A[C]; A[C+:2]; A[C:C+1]; A[C+D:C+D+1]; A[(C+D)+:2]; //warning here //no warning //no warning //no warning //warning here //warning here
endmodule
27676 (Verilog) Signal Read before Written in Same Always Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: signal "%s" is read before being written in the same always block. Configurable Parameter Rule group: Simulation, Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a signal is read and then written in the same always block. If a signal is read before being written in the same combinational always block, it will cause a simulation/synthesis mismatch. Please note that this rule does not check sequential always blocks, because whether a signal is read first or written first does not cause a simulation/synthesis mismatch in a sequential always block. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module test(); reg A, IN, clk; reg foo, foo1, foo2, sig1, sig2; reg out, out1, out2; always @ (A or IN) begin if ( A ) foo <= IN; out <= foo; end //OK: "foo" is assigned before being referenced
always_ff @ (posedge clk) begin if ( foo1 == 1'b1 ) sig1 <= 1'b0; foo1 <= 1'b0; end //OK: 27676 need not check sequential always blocks
always_comb begin sig2 = foo2; foo2 = 0; //Warning: "foo2" is referenced before being assigned end endmodule
nLint reports: document.sv(21): Warning 27676: signal "foo2" is read before being written in the same always block. (Simulation,Synthesis)
27801 (Verilog) 'iff' Construct Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: 'iff' construct is not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any 'iff' constructs, which are not synthesizable, used in the design. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 module latch (output logic [31:0] y, input [31:0] a, input enable); always @(a iff enable == 1) y = a; endmodule
nLint reports: document.sv(2): Warning 27801: 'iff' construct is not synthesizable. (Synthesis)
27803 (Verilog) Statement Labels Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: statement labels are not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether statement labels, which are not synthesizable, are used in the design. The synthesis is no longer a problem with the code of statement label from DC version V2003.12-SP1-DWF_0403, Mar 11, 2004. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 module dff_with_imm_assert(input DATA, CLK, RESET, output reg Q); always_ff @(posedge CLK) if (~RESET) dff_reset: Q <= 1'b0; else Q <= DATA; endmodule
nLint reports: document.sv(4): Warning 27803: statement labels are not synthesizable. (Synthesis)
27805 (Verilog) Task in 'always_comb' Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: task is used in 'always_comb' block. Configurable Parameter Rule group: Synthesis, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether tasks are used inside always_comb blocks. To avoid simulation and synthesis mismatch, void functions are recommended to be used inside always_comb instead of tasks. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 module comb1(input logic a, b ,c, output logic [1:0] y); task ort1; input a; y[0] = a | b | c; endtask always_comb ort1(a); //warning here endmodule
nLint reports: document.sv(8): Warning 27805: task is used in 'always_comb' block. (Simulation,Synthesis)
27807 (Verilog) Non-void Function Not Declared as Automatic

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: non-void function is not declared as automatic. Configurable Parameter Rule group: Coding Style; Argument type: ( CHECK_NOT_FULL_RET, IGNORE_NOT_FULL_RET); Argument description: If the argument is set to CHECK_NOT_FULL_RET, the rule checks functions whose return variable is not fully assigned in each conditional branch. If the argument is set to IGNORE_NOT_FULL_RET, the rule ignores the checking for functions whose return variable is not fully assigned in each conditional branch; Default value: "IGNORE_NOT_FULL_RET" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any non-void functions not declared as automatic. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 module latch1b (output reg y, input d, en); always @* y = lat(d, en); function lat (input d, en); //warning here if (en) lat = d; endfunction endmodule
nLint reports following if the argument value is ("IGNORE_NOT_FULL_RET"): document.sv(6): Warning 27807: non-void function is not declared as automatic. (Coding Style)
27813 (Verilog) Constructs in $root Not Synthesizable

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: Constructs in $root are not synthesizable. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any logics described in $root. They are not supported in synthesis. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 logic v1, v2, v3, v4, v5; wire w1; reg r1; const logic v10 = 0; int i1; typedef int intp; intp i2; struct{ logic a1; }s1; typedef struct{ logic a2; }type_s; type_s s2; //warning here //warning here //warning here //warning here //warning here
//warning here
//warning here
enum { a, b, c} enumRoot; //warning here typedef enum {R, Y, G} Light; Light light1; //warning here assign v5 = v4; //warning here
module test (input logic in, output logic out); logic aa; always_comb out = in; endmodule test mytestinst (v4, v5); and myGateInst(v3, v1, v2); //warning here //warning here
interface Intf; logic d1; logic d2; modport P1 (input d1, output d2); modport P2 (input d2, output d1); endinterface Intf myInterface(); //warning here
nLint reports: document.sv(1): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(1): Warning 27813: Constructs in $root are not synthesizable. (Synthesis)
document.sv(1): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(1): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(1): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(2): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(3): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(7): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(9): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(13): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(18): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(20): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(22): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(24): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(31): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(33): Warning 27813: Constructs in $root are not synthesizable. (Synthesis) document.sv(42): Warning 27813: Constructs in $root are not synthesizable. (Synthesis)
27815 (Verilog) Incremented/Decremented Variables Used More than Once in the Same Expression
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: incremented/decremented variable "%s" is operatedused more than once in the same expression. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the same variable using increment (++) or decrement (--) operators appears more than once in the same expression. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 module test; int foo; int number; initial begin foo = 0; number = foo + foo ++ ; //warning here end endmodule
nLint reports: document.sv(7): Warning 27815: incremented/decremented variable "foo" is operatedused more than once in the same expression. (Coding Style)
27817 (Verilog) 'always_ff' Not Used for Sequential Blocks

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: 'always_ff' is not used to model sequential blocks. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any sequential blocks modelled by an always block. The recommended construct is 'always_ff'. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module test; logic clk; logic a,b,c,d,d1; logic q, q1,sel; always @* begin //no violation because it is inferred as combination logic a = b & c; end always @( posedge clk ) begin //report warning q1 <= d1; end always @* begin //no warning, since it is inferred as a latch; if ( sel ) q <= d; end endmodule
nLint reports: document.sv(11): Warning 27817: 'always_ff' is not used to model sequential blocks. (Coding Style)
27819 (Verilog) Use 'always_comb' to Model Combinational Behavior

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: use always_comb to model combinational behavior. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether always @* is used to model combinational logic; always_comb is the recommended alternative. Example
(Verilog) ///////////////example : document.sv//////////// 1 module test; 2 3 logic a, b, c; 4 logic clk; 5 logic sel; 6 logic q, q1, d, d1; 7 8 always @* begin //always_comb preferred; 9 a = b & c; 10 end 11 12 always_ff @( posedge clk ) begin //no warning, since it is inferred as a flip-flop 13 q <= d; 14 end 15 16 always_latch //no warning, since it is inferred as a latch; 17 if ( sel ) 18 q1 <= d1; 19 20 endmodule 21
nLint reports: document.sv(8): Warning 27819: use always_comb to model combinational behavior. (Coding Style)
27821 (Verilog) Incomplete Assignment in 'always_comb'

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: variable "%s" is not completely assigned in always_comb block. Configurable Parameter Rule group: Synthesis, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the left-hand side variables in always_comb block are assigned in every condition branch. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 typedef struct { logic a; logic b; } st; module test( input logic en ); st tmp; always_comb begin //warning on tmp.b here tmp.a = 0; //tmp.a is fully assigned if (en == 1 ) tmp.b = 0; //tmp.b is not assigned in all branches end endmodule
nLint reports: document.sv(9): Warning 27821: variable "tmp.b" is not completely assigned in always_comb block. (Simulation,Synthesis)
27823 (Verilog) Event Control Construct in 'always_comb'

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: event construct @ is found in always_comb procedure. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the event control construct @, is used in always_comb procedure. Always_comb procedure represents combinational logics hence it should not contain any timing event. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module test(clk,data1,data2,y1,y2); input clk,data1,data2; output y1,y2; reg y1,y2; always_comb begin y1 = data1; @(y1) y2 = data2; end endmodule
//warning here
nLint reports: document.sv(8): Warning 27823: event construct @ is found in always_comb procedure. (Synthesis)
27825 (Verilog) Repeated Common Subexpression Not Allowed in 'for' Loop

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: common sub-expression is detected within for/generate loop statement. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether any common sub-expressions are repeated generate or for-loop statements. Example
(Verilog) ///////////////example : document.sv//////////// 1 module test(A1,B1,C1,D1,A2,B2,C2,D2); 2 input [31:0] B1,B2,C1,C2,D1,D2; 3 output [31:0] A1,A2; 4 reg [31:0] A1; 5 wire [31:0] A2; 6 integer i; 7 8 always @(B1,C1,D1) begin 9 for (i=0; i<32; i=i+1) 10 A1[i] = B1[i] & (|(C1 & D1)); //warning on repeated common subexpression within loop 11 end 12 13 genvar g; 14 generate 15 for (g=0; g<32; g=g+1) begin: a2 16 assign A2[g] = B2[g] & (|(C2 & D2)); //warning on repeated common subexpression with in generate loop 17 end 18 endgenerate 19 20 endmodule
nLint reports: document.sv(10): Warning 27825: common sub-expression is detected within for/generate loop statement. (Synthesis) document.sv(16): Warning 27825: common sub-expression is detected within for/generate loop statement. (Synthesis)
27827 (Verilog) Declaration of Variable with Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: assignment is used in declaration of variable "%s". Configurable Parameter Rule group: Design Style; Argument type: (NET,VARIABLE,ALL); Argument description: NET means to check Verilog net type only; VARIABLE means to check types other than net; ALL means to check all types. Default value: "ALL" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the value assignment is used in variable declaration. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 module test; wire a; wire b = 1'b1; wire c = a; logic d = 1'b1; endmodule
nLint reports following document.sv(3): Warning (Design Style) document.sv(4): Warning (Design Style) document.sv(5): Warning (Design Style)
if the argument value is ("ALL"): 27827: assignment is used in declaration of variable "b". 27827: assignment is used in declaration of variable "c". 27827: assignment is used in declaration of variable "d".
27829 (Verilog) Unintended Logic Inferred

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %s logic inferred on signal "%s" in %s block. Configurable Parameter Rule group: Synthesis; Argument type: (CHECK_ALWAYS_LATCH, CHECK_ALWAYS_FF, CHECK_ALWAYS_COMB); Argument description: If CHECK_ALWAYS_LATCH is specified, the always_latch block will be checked, if CHECK_ALWAYS_FF is specified, the always_ff block will be checked, if CHECK_ALWAYS_COMB is specified,the always_comb block will be checked. The argument is multiple selected type, so CHECK_ALWAYS_LATCH,CHECK_ALWAYS_FF and CHECK_ALWAYS_COMB can be specified at the same time; Default value: "CHECK_ALWAYS_LATCH, CHECK_ALWAYS_FF,CHECK_ALWAYS_COMB" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any unintended logic inferred. The non-latch logic is inferred in the always_latch block, or the non-ff logic is inferred in the always_ff block, or the non-comb logic is inferred in the always_comb block. Example
(Verilog) ///////////////example : document.sv//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 module m1(input clk, input a, d, e, output c, q, q2, f1, f2); always_latch begin logic b; b = ~a; //no warning, b is only used within this block if (clk) begin //no warning, this is a latch. c = b; end f1 = e & c; //warning, non-latch logic inferred end always_ff @(posedge clk) q = d; //no warning, register inferred always_ff begin logic b; b = ~d; if(clk) q2 = d; end
//no warning, b is only used within this block //warning, non-ff logic inferred
always_comb begin logic b; if (clk) //warning, non-comb logic inferred c = ~a; if (clk) //no warning, b is only used within this block b= a; f2 = e & c; //no warning, comb logic inferred end endmodule
nLint reports following if the argument value is ("CHECK_ALWAYS_LATCH, CHECK_ALWAYS_FF,CHECK_ALWAYS_COMB"):
document.sv(8): Warning 27829: non-latch logic inferred on signal "f1" in always_latch block. (Synthesis) document.sv(17): Warning 27829: non-ff logic inferred on signal "q2" in always_ff block. (Synthesis) document.sv(23): Warning 27829: non-comb logic inferred on signal "c" in always_comb block. (Synthesis)
28009 End Point Not Generated from a Single Clock Source

Message <filename>(<line no.>): <severity> <rule no.>: %s "%s" comes from more than one clock source. Configurable Parameter Rule group: Clock; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are any end points generated from more than one clock source tree. This rule will be checked only if clock source tree is extracted. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module test (clk1, clk2, clk3, d1, d2, q); input clk1, clk2, clk3, d1, d2; output q; wire clk1, clk2, clk3, d1, d2, temp; reg q1, q, q2; always @(posedge clk1) q1 = d1; always @(posedge clk2) q2 = d2; assign temp = q1 & q2; always @(negedge clk3) q = temp; endmodule
nLint reports: document.v(16): Warning 28009: the input of register "q" comes from more than one clock source. (Clock)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 library ieee; use ieee.std_logic_1164.all; entity top_ety is port (clk1, clk2, clk3, d1, d2 : in std_logic; q : out std_logic); end top_ety; architecture arch of top_ety is signal temp : std_logic; signal q1, q2 : std_logic; begin Process(clk1) begin if (clk1'event and clk1 = '1' ) then q1 <= d1; end if; end Process;
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Process(clk2) begin if (clk2'event and clk2 = '1' ) then q2 <= d2; end if; end Process; temp <= q1 and q2; Process(clk3) begin if (clk3'event and clk3 = '0' ) then q <= temp; end if; end Process; end arch;
nLint reports: document.vhd(32): Warning 28009: the input of register "q" comes from more than one clock source. (Clock)
28011 Inputs of a Tri-state Bus Not Generated from a Single Clock Source
Message <filename>(<line no.>): <severity> <rule no.>: the inputs of the tri-state bus "%s" are not generated from a single clock source. Configurable Parameter Rule group: Clock; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether all the inputs of a tri-state bus are generated from a single clock source. This rule will be checked only if a clock source tree is extracted. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test (clk1, clk2, en1, en2, d1, d2, q); input clk1, clk2, en1, en2, d1, d2; output q; wire clk1, clk2, d1, d2, q, en1, en2; reg q1, q2; always @(posedge q1 = d1; always @(posedge q2 = d2; assign q = en1 ? assign q = en2 ? endmodule clk1) clk2) q1 : 'bZ; q2 : 'bZ;
nLint reports: document.v(4): Warning 28011: the inputs of the tri-state bus "q" are not generated from a single clock source. (Clock)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library ieee; use ieee.std_logic_1164.all; entity top_ety is port (clk1, clk2, en1, en2, d1, d2 : in std_logic; q : out std_logic); end top_ety; architecture arch of top_ety is signal q1, q2 : std_logic; begin Process (clk1) begin if (clk1'event and clk1 = '1') then q1 <= d1; end if; end Process; Process (clk2) begin if (clk2'event and clk2 = '1') then q2 <= d2;
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end if; end Process; Process begin wait; if (en1 = '1') then q <= q1; else q <= 'Z'; end if; end Process; Process begin wait; if (en2 = '1') then q <= q2; else q <= 'Z'; end if; end Process; end arch;
nLint reports: document.vhd(6): Warning 28011: the inputs of the tri-state bus "q" are not generated from a single clock source. (Clock)
28015 Tri-state Buffer in a Clock Path

Message <filename>(<line no.>): <severity> <rule no.>: tri-state buffer "%s" exists in a clock path from "%s" to "%s". Configurable Parameter Rule group: Clock; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description This rule checks whether there are tri-state buffers in a clock path. This rule will be checked only if clock source tree is extracted. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module test (clk, en, d, q); input clk, en, d; output q; wire clk1, clk, d, en; reg q; always @(posedge clk1) q = d; assign clk1 = en ? clk : 'bZ; endmodule //specify options in command line : -ex_clk -clk_source "test.clk" //to set test.clk as clock source
nLint reports: document.v(10): Warning 28015: tri-state buffer "test:Always0#SigOp0:10:10:TriState" exists in a clock path from "test.clk" to "test.clk1". (Clock)
(VHDL) -------------------example : document.vhd------------1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library ieee; use ieee.std_logic_1164.all; entity top_ety is port (clk, en, d : in std_logic; q : out std_logic); end top_ety; architecture arch of top_ety is signal clk1 : std_logic; begin Process (clk1) begin if (clk1'event and clk1 = '1' ) then q <= d; end if; end Process; Process (clk) begin if (en = '1') then clk1 <= clk;
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else clk1 <= 'Z'; end if; end Process; end arch; --specify comamnd line option : -ex_clk -clk_source "top_ety.clk" --to set "top_ety.clk" as clock source
nLint reports: document.vhd(19): Warning 28015: tri-state buffer "top_ety(arch):Process1#line__19:19:26:TriState" exists in a clock path from "top_ety.clk" to "top_ety.clk1". (Clock)
28101 (Verilog) Both Set and Reset Found for a Flipflop/Latch

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: set ("%s") and reset ("%s" (%d)) are specified for the same flip-flop/latch. Configurable Parameter Rule group: hidden.Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a flip-flop/latch has both set and reset. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 module test(clk,set,reset, enable,D,Q1,Q2,Q3); input clk,set,reset, enable; input D; output Q1,Q2,Q3; reg Q1,Q2,Q3; always @(posedge clk or negedge reset or posedge set) begin if (set) Q1 <=1'b1; else if (!reset) //violation here Q1 <= 1'b0; else Q1 <= D; end always @(posedge clk) begin if (set) Q2 <= 1'b1; else if(!reset) Q2 <= 1'b0; //violation here else Q2 <= D; end always @(enable or set or reset begin if (!reset) Q3 = 1'b0; else if (set) Q3 = 1'b1; //violation here else if (enable) Q3 = D; end endmodule or D)
nLint reports: document.v(9): Warning 28101: set ("set") and reset ("reset" (11)) are specified for the same flip-flop/latch. (Synthesis) document.v(19): Warning 28101: set ("set") and reset ("reset" (21)) are specified for the same flip-flop/latch. (Synthesis) document.v(31): Warning 28101: set ("set") and reset ("reset" (29)) are specified for the same flip-flop/latch. (Synthesis)
29001 (Verilog) User Defined Primitive should be Named in Lower Case

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: user defined primitive should be named in lower case. Configurable Parameter Rule group: IPQ, Design, Guidelines., Naming Convention; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Check to see if user defined primitive are all named in lower case. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module test(); wire carryOut, carryIn, aIn, bIn; Carry u1( carryOut, carryIn, aIn, bIn ); endmodule primitive Carry(carryOut,carryIn,aIn,bIn);//Warning here output carryOut; input carryIn, aIn,bIn; table // carryIn aIn bIn carryOut 0 0 0 : 0; 0 0 1 : 0; 0 1 0 : 0; 0 1 1 : 1; 1 0 0 : 0; 1 0 1 : 1; 1 1 0 : 1; 1 1 1 : 1; endtable endprimitive
nLint reports: document.v(9): Warning 29001: user defined primitive should be named in lower case (Naming Convention)
29002 (Verilog) Instance Name Related to Module Name

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: Instance name must be related to module name and indexed by an integer if multiple instantiated. Configurable Parameter Rule group: Naming Convention; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Instance names must be related to the module name and indexed by an integer if multiple instantiated. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module adderx(ss); input [1:0] ss; parameter check = 1; endmodule module test_adder; wire [1:0] in1; adderx adderx adderx adderx adderx adderx_1(in1); //OK adderx_2(in1);//OK test_1_adderx(in1);//OK. testadder(in1);//Waring,instname does not relate to module name. adderx_last(in1);//Warning,instname does not have an index.
endmodule
nLint reports: document.v(14): Warning 29002: instance name "testadder" must be related to module name and indexed by an integer if multiple instantiated (Naming Convention) document.v(15): Warning 29002: instance name "adderx_last" must be related to module name and indexed by an integer if multiple instantiated (Naming Convention)
29003 (Verilog) Bus Direction Consist on Port Binding

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: bus direction of "%s" is not consistent with "%s". Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Bus direction should keep consistancy between port instance and port on module binding. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 //module decl: module m1(a,b,c); input [0:7] a; input [7:0] b; output [7:0] c; endmodule module m2(.a({a0,a1}),b,c); input [0:3] a0; input [3:0] a1; input [7:0] b; output [7:0] c; endmodule //module instantiation: module top(); wire [7:0] A; wire [7:0] B; wire [3:0] C1; wire [0:3] C2; wire [0:1] C3; wire [1:0] C4; m1 u1_m1(.a(A), //inconsistant,report warning on A vs a //since it is the case "normal portinst" + "normal port" .b(B), .c({C1,C2})); //inconsistant ,report warning on C2 vs c //it is "simple concat portinst" + "normal port" m1 u2_m1(.a(A),//inconsistant,report warning on A vs a .b(B), .c({C1,{C3,C4}}));//inconsistant ,report warning on C3 vs c //it is "complex concat portinst"+"normal port" m2 u_m2(.a(A),//inconsistant,report warning on A vs a0 //it is "normal portinst"+"concat port" .b(B), .c({C1,C2}));//inconsistant ,report warning on C2 vs c endmodule
nLint reports: document.v(22): (Coding Style) document.v(25): (Coding Style) document.v(28): (Coding Style) document.v(30): (Coding Style)
Warning 29003: bus direction of "A" is not consistent with "a" Warning 29003: bus direction of "C2" is not consistent with "c" Warning 29003: bus direction of "A" is not consistent with "a" Warning 29003: bus direction of "C3" is not consistent with "c"
document.v(33): Warning 29003: bus direction of "A" is not consistent with "a0" (Coding Style) document.v(36): Warning 29003: bus direction of "C2" is not consistent with "c" (Coding Style) ///////////////example : document_limit1.v//////////// 1 // will report violation on impending(floating) bus , though it is not expected. 2 // ( by the way:the floating bus can be introduced by a concat port or concat portinst) 3 4 module test(a); 5 input[0:7] a; 6 endmodule 7 8 module top (); 9 wire [0:3] B; 10 wire [0:3] C; 11 wire [3:0] D; 12 test i_test({D,B,C});//D will improperly reported. 13 //the conections are: 14 //B[0:3]<==>a[0:3] C[0:3]<==>a[4:7], D is floating. 15 16 endmodule
nLint reports: document_limit1.v(12): Warning 29003: bus direction of "D" is not consistent with "a" (Coding Style) ///////////////example : document_limit2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 //do not lint special cases in which both portinst and port are concated. //e.g. module test(.a({in1,in2})); input [0:3] in1; input [3:0] in2; endmodule module top (); wire [0:3] B; wire [3:0] C; test i_test({C,B});//will not check the portinst, //since both port and portinst are concated, //though C[3:0]<==>in1[0:3], B[0:3]<==>in2[3:0] //which break the the rule. endmodule
nLint reports: ///////////////example : document_notreport.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 //module decl: module m1(a,b,c); input [0:7] a; input [7:0] b; output [7:0] c; endmodule module m2(a,b,c); input a; input [7:0] b; output [5:5]c; endmodule //module instantiation: module top(); wire [7:0] A; wire [7:0] B; wire [3:0] C1; wire [0:3] C2; m1 u1_m1(.a(A[0]),//not report on single bit selection belong to portinst .b(B), .c({C1,C2[1]}));//not report on single bit selection in a concat belong
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
//to portinst. m1 u2_m1(.a(A[0]),//not report on single bits selection belong to portinst .b(B), .c({C1,{C2[0],C2[1],C2[2],C2[3]}}));//not report on single bits selection //in a simple concat/complex concat. //though it can be merged into C2[0:3] m2 u_m2(.a(A),//not report on a single bit port. .b(B), .c({C1,C2}));//not report on a single bit port.
m1 u3_m1(.a(A&B), //not report when introduce a rtl inst. (A&B). .b(B), .c({C1,~C2})); //not report when introduce a rtl inst (~C2). endmodule
nLint reports:
29004 (Verilog) Module Name Follow Predefined Pattern

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: module "%s" (of instance "%s") is named in the predefined pattern "%s". Configurable Parameter Rule group: Naming Convention; Argument type: string; Argument description: specify the pattern for checking; Default value: ".*GTECH.*" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) report warning if a module (not top) is named in a predefined pattern,reporting location is at the instance of the module. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module mGTECH1(i, o); input i; output o; endmodule module test; mGTECH1 inst_1 (i, o); //warning with the pattern .*GTECH.* endmodule
nLint reports following if the argument value is ( ".*GTECH.*"): document.v(7): Warning 29004: module "mGTECH1" (of instance "inst_1") is named in the predefined pattern ".*GTECH.*" (Naming Convention)
29005 (Verilog) Too Many Levels of Nested If

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the nested level of if statement (%d levels) detected exceeding %d levels. Configurable Parameter Rule group: Coding Style; Argument type: integer; Argument description: specify the maximum number of levels allowed for nested if statements; Default value: "3" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) This rule checks whether the level number of nested if statements exceeds the predefined maximum number of levels. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 is 3 17 18 19 20 21 22 module top(a,b,c,d,e,f,g,h,o); input a,b,c,d,e,f,g,h; output o; reg o; always @(a or b or c or d or e or f or g or h) begin if (a) //level 1 begin if (b & c) //level 2 o = d; else o = e; end else if (f) //level 3 o = g; else if (h) //level 4; warning here if maximum nested level allowed o = 1'b1; else o = 1'b0; end endmodule
nLint reports following if the argument value is ( 3): document.v(16): Warning 29005: the nested level of if statement (4 levels) detected exceeding 3 levels (Coding Style)
29006 (Verilog) Too Many Levels of Nested Case

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: the nested level of case statement (%d levels) detected exceeding %d levels. Configurable Parameter Rule group: Coding Style; Argument type: integer; Argument description: specify maximum number of levels nested allowed for case statement; Default value: "2" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Check to see there is any case statement nested exceeding pre-defined maximum number of levels Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module test(opcode,opcode2,opcode3,not_reset,clk); input [2:0] opcode; input [2:0] opcode2; input [2:0] opcode3; input not_reset,clk; wire [2:0] opcode; wire [2:0] opcode2; always @(posedge clk) case (opcode) //level= 1 3'h6 : case (opcode2)//level =2 3'h2: if(not_reset)$stop; 3'h1: case(opcode3)//level=3, warning here 3'h3:if(not_reset)$stop; default: begin $display("bad opcode3"); end endcase default: begin $display("bad opcode2"); end endcase default : begin $display("bad opcode"); $stop; end endcase endmodule
nLint reports following if the argument value is ( 2): document.v(12): Warning 29006: the nested level of case statement (3 levels) detected exceeding 2 levels (Coding Style)
29100 (Verilog) Preserve Port Order

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : IO declaration %s is not in order with its port declaration. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning when the index of a IO declaration is different to its index in module declaration. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module Decoder(HRESETn, HADDR, HSEL_1, HSEL_2, HSEL_3, HSEL_4 ); input HRESETn; //system reset input [31:0] HADDR; //AHB address bus output HSEL_1; output HSEL_2; output HSEL_4; output HSEL_3; endmodule //Select //Select //Select //Select AHB AHB AHB AHB Slave1 Slave2 Slave4 Slave3
nLint reports: document.v(13): Warning 29100: IO declaration "HSEL_4" is not in order with its port declaration. (Coding Style) document.v(14): Warning 29100: IO declaration "HSEL_3" is not in order with its port declaration. (Coding Style)
29101 (Verilog) Declaration of All Internal Nets should Follow the Port I/O Declaration at the Top of the Module
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : the declaration of all internal nets should follow the port I/O declaration at the top of the module. Configurable Parameter Rule group: IPQ Design Guidelines.Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning when net declaration occurs at two or more sections in a module, function, task, or when there are other statement between net declaration and IO declaration. Here, net declaration does not includes the net declaration in always block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module test(i, o); wire w; //warning: not following the port declaration reg r; input i; //port declaration output o; endmodule module test1(i, o); input i; output o; reg r; parameter p = 8; wire w; //warning: not in one section. endmodule
nLint reports: document.v(2): Information 29101: the declaration of all internal nets should follow the port I/O declaration at the top of the module (Coding Style) document.v(13): Information 29101: the declaration of all internal nets should follow the port I/O declaration at the top of the module (Coding Style) document.v(13): Information 29101: internal signal "w" should be declared in one section (Coding Style)
29102 (Verilog) Need Comment before Functional Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : No comment is found before the functional block. Configurable Parameter Rule group: IPQ Design Guidelines.Coding Style; Argument type: (always, assign, function, task); Argument description: Multiple arguments can be selected; Default value: "always,assign,function,task" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning when no comment is found before always, assign, function or task statements. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 //always module testalways(a, b, c); input a, b; output c; reg c; always @(a or b) //warning c = a & b; endmodule //continuous assign module testassign(a, b, c); input a, b; output c; assign c = a & b; //warning endmodule //function module testfunction; function [8*8:1] op2str; //warning input [2:0] op; case (op) 0 : op2str = "halt "; 1 : op2str = "skz "; 2 : op2str = "add "; 3 : op2str = "and "; 4 : op2str = "xor "; 5 : op2str = "load "; 6 : op2str = "store "; 7 : op2str = "jump "; default : op2str = "????????"; endcase endfunction endmodule //task module testtask; reg inc_pc, load_acc, load_pc, wr, rd, load_ir, halt; task instruction_fetch_setup; //waring begin inc_pc=0; load_acc=0; load_pc=0; wr=0; rd=0; load_ir=0; halt=0; end
42 43
endtask endmodule
nLint reports following if the argument value is ("always,assign,function,task"): document.v(6): Information 29102: no comment is found before always (Comments) document.v(14): Information 29102: no comment is found before assign (Comments) document.v(19): Information 29102: no comment is found before function (Comments) document.v(38): Information 29102: no comment is found before task (Comments)
29103 (Verilog) Use One Line Comment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : don't use multi-line comment from line "%d" to "%d". Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning when multi-line comment is found Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 //module begin *****OK******* /*Module ******warning here******** **sub */ module sub(clk, i, o);/*sub module*/ //*******warning here******* input clk, i; output o; endmodule
nLint reports: document.v(2): Information 29103: don't use multi-line comment from line "2" to "4" (Comments) document.v(5): Information 29103: don't use multi-line comment from line "5" to "5" (Comments)
29104 (Verilog) Comment on Cell Instantiation

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : no comment before the cell instance. Configurable Parameter Rule group: IPQ Design Guidelines.Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning if no comment is found before a cell instance. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 //Cell instance include primitive cell, symbol cell and lib cell. //1. Primitive cell; Udp, gate //Example: udpcell.v module test_udp_cell; wire a,b,c; and and_l(a,b,c); //warning endmodule // 2. Symbol cell; //Example: macro.map: // CELL macro MACRO // I INPUT L D // O OUTPUT R COM // macro.v: // module test; // macro i_macro(.I(I), .O(O)); //warning // endmodule // 3. lib cell //Example: libcell.v module test_lib_cell; IVAA i_iv(.Z(Z), .A(A)); //warning endmodule `celldefine //or -v -y module IVAA (Z,A); output Z; input A; assign Z=~A; endmodule èndcelldefine
nLint reports: document.v(6): Warning 29104: no comment is found before the cell instantiation (Comments) document.v(21): Warning 29104: no comment is found before the cell instantiation (Comments)
29105 (Verilog) Comment Synthesis Directives

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: :no comment on this synthesis directive. Configurable Parameter Rule group: IPQ Design Guidelines.Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning if no comment is found before a synthesis directive. A synthesis directive is a comment which have a string 'synopsys' after the comment symbol '//' or '/*'. Only blank space is allowed between the comment symbol and the synthesis directive keyword 'synopsys'. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module test( data, sel, out ); input [2:0] data; input [1:0] sel; output out; reg out; always @( data or sel ) begin case ( sel ) //synopsys full_case //warning 2'b10 : out = data[0]; 2'b11 : out = data[1]; 2'b01 : out = data[2]; endcase end endmodule //two examples of comment without warning //xxxx synopsis full_case (not a syntehsis directive) //comment //synopsis full_case
(synthesis directive with comment)
nLint reports: document.v(9): Information 29105: no comment on this synthesis directive (Comments)
29106 (Verilog) Check File Header Format

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : Cannot find %s. Configurable Parameter Rule group: IPQ Design Guidelines.Coding Style; Argument type: FILENAME_ARG; Argument description: A file header file can be imported here. The default file is an example; Default value: "file_header.tmpl" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Use a file header template file to match every file header. About file header, see CustomizeFileHeader.htm. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 //+FHDR-------------------------------------------------------------// (C) Copyright Company, Industrial technology Research Institute (ITRI) // All Right Reserved //------------------------------------------------------------------// FILE NAME: document.v // AUTHOR: xxx // CONTACT INFORMATION: [email protected] //------------------------------------------------------------------// RELEASE VERSION: V1.0 // VERSION DESCRIPTION: for test Lint Tool //------------------------------------------------------------------// RELEASE DATE: 05-31-2004 //------------------------------------------------------------------// PURPOSE: Short description of functionality //------------------------------------------------------------------// PARAMETERS: none //------------------------------------------------------------------// REUSE ISSUES: test // Reset Strategy: test // Clock Strategy: test // Critical Timing: test // Test Feature: test // Asynchronous Interface: test // Scan Methodology: test //-FHDR-------------------------------------------------------------module input input output assign FH1to3 (a, b, c); [7 : 0] a; [0: 15] b; [7 : 0] c; c = a | b;
endmodule
nLint reports following if the argument value is ("file_header.tmpl"):
29107 (Verilog) Comment Compiler Directives

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : no comment behind the compiler directive. Configurable Parameter Rule group: IPQ Design Guidelines.Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning if no comment is found behind the compiler directive Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 ìnclude "lib.v" //*****warning upper line****** ìfdef FOR_SIMULATION //abc *****OK***** `define SIMULATION 1 //*****warning upper line****** èlse /*cba*/ //*****Upper line OK***** `define SIMULATION 0 //xyz *****OK***** èndif // *****warning upper line******
nLint reports: document.v(1): Information 29107: no comment behind the ìnclude (Comments) document.v(4): Information 29107: no comment behind the `define (Comments) document.v(9): Information 29107: no comment behind the èndif (Comments) ///////////////example : lib.v//////////// 1 2 module lib; endmodule
29108 (Verilog) Usage of Specific Keyword(s) Not Allowed

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : specific keyword %s is not allowed in design. Configurable Parameter Rule group: Design Style; Argument type: (always, and, assign, automatic, begin, buf, bufif0, bufif1, case, casex, casez, cell, cmos, config, deassign, default, defparam, design, disable, edge, else, end, endcase, endconfig, endfunction, endgenerate, endmodule, endprimitive, endspecify, endtable, endtask, event, for, force, forever, fork, function, generate, genvar, highz0, highz1, if, ifnone, incdir, include, initial, inout, input, instance, integer, join, large, liblist, library, localparam, macromodule, medium, module, nand, negedge, nmos, nor, noshowcancelled, not, notif0, notif1, or, output, parameter, pmos, posedge, primitive, pull0, pull1, pulldown, pullup, pulsestyle_onevent, pulsestyle_ondetect, rcmos, real, realtime, reg, release, repeat, rnmos, rpmos, rtran, rtranif0, rtranif1, scalared, showcancelled, signed, small, specify, specparam, strong0, strong1, supply0, supply1, table, task, time, tran, tranif0, tranif1, tri, tri0, tri1, triand, trior, trireg, unsigned, use, vectored, wait, wand, weak0, weak1, while, wire, wor, xnor, xor); Argument description: Multiple arguments can be selected. All keywords defined in Verilog language are included in this set; Default value: "always,assign,initial,specify,function,task" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) The rule checks whether there are any language keywords used in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 //use default argument value module test_adder(out3,in1,in2); input [1:0] in1,in2; output [1:0] out3; wire[3:1] out; assign out = out3[0]; and test_and(out3[0],in1[0],in2); function show; input [3:1] show_input1; show = show_input1; endfunction time local_time; initial begin local_time = $time; end endmodule //report warning
//report warning
//report warning
nLint reports following if the argument value is ("always,assign,initial,specify,function,task"): document.v(6): Warning 29108: specific keyword "assign" is not allowed in design (Design Style) document.v(10): Warning 29108: specific keyword "function" is not allowed in design (Design Style)
document.v(16): Warning 29108: specific keyword "initial" is not allowed in design (Design Style)
29109 (Verilog) Macro Naming Convention

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : macro name must be of upper case. Configurable Parameter Rule group: IPQ, Design, Guidelines., Naming Convention; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning if macro name in compiler directive `define, ùndef or ìfdef is of lower case Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 `define add(a,b) a + b `define NAND(delay) nand #(delay) ìfdef DEFed `define Def1 0 èlse `define Def2 0 èndif ùndef DEFed module test; endmodule //warning //OK //warning //warning //warning //warning
nLint reports: document.v(1): document.v(3): document.v(4): document.v(6): document.v(8):
Warning Warning Warning Warning Warning
29109: 29109: 29109: 29109: 29109:
macro macro macro macro macro
name name name name name
must must must must must
be be be be be
of of of of of
upper upper upper upper upper
case case case case case
(Naming (Naming (Naming (Naming (Naming
Convention) Convention) Convention) Convention) Convention)
29110 (Verilog) Signals Names of an Identical Signal should Remain the Same throughout the Design Hierarchy.
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : Port instance name "%s" is different to port name "%s". Configurable Parameter Rule group: IPQ, Design, Guidelines., Design Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning if the name of port instance is different to the name of the port it connected to. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 module block1( rst_n, clk, addr, wr_data ); input rst_n; // Top module reset signal input clk; // Top module clock signal input [15:0] addr; // Top module address bus output [31:0] wr_data; // Top module write data bus endmodule module block2( reset_n, sysclk, address, WR_data ); input reset_n; // Top module reset signal input sysclk; // Top module clock signal input [15:0] address; // Top module address bus output [31:0] WR_data; // Top module write data bus endmodule module top( rst_n, clk, addr, wr_data ); input rst_n; // Top module reset signal input clk; // Top module clock signal input [15:0] addr; // Top module address bus output [31:0] wr_data; // Top module write data bus block1 u_blockOk ( .clk (clk), .addr (addr), .wr_data(wr_data) ); .rst_n (rst_n),
block2 u_blockError ( .reset_n .sysclk (clk),
(rst_n),
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.address .WR_data );
(addr), (wr_data)
block2 u_blockExplict (rst_n, clk, addr, wr_data ); endmodule
nLint reports: document.v(41): Warning 29110: port name "reset_n" (Naming Convention) document.v(42): Warning 29110: port "sysclk" (Naming Convention) document.v(43): Warning 29110: port "address" (Naming Convention) document.v(44): Warning 29110: port name "WR_data" (Naming Convention) document.v(47): Warning 29110: port name "reset_n" (Naming Convention) document.v(48): Warning 29110: port "sysclk" (Naming Convention) document.v(49): Warning 29110: port "address" (Naming Convention) document.v(50): Warning 29110: port name "WR_data" (Naming Convention)
instance name "rst_n" is different to port instance name "clk" is different to port name instance name "addr" is different to port name instance name "wr_data" is different to port instance name "rst_n" is different to port instance name "clk" is different to port name instance name "addr" is different to port name instance name "wr_data" is different to port
29111 (Verilog) Check Construct Header Format

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : Cannot find %s. Configurable Parameter Rule group: IPQ Design Guidelines.Coding Style; Argument type: FILENAME_ARG; Argument description: A construct header file can be imported here. The default file is an example; Default value: "construct_header.tmpl" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Use a construct header template file to match every construct header. About construct header, see CustomizeConstructHeader.htm. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 //+FHDR-------------------------------------------------------------// (C) Copyright Company // All Right Reserved //------------------------------------------------------------------// FILE NAME: // AUTHOR: // CONTACT INFORMATION: //------------------------------------------------------------------// RELEASE VERSION: V1.0 // VERSION DESCRIPTION: //------------------------------------------------------------------// RELEASE DATE: MM-DD-YYYY //------------------------------------------------------------------// PURPOSE: Short description of functionality //------------------------------------------------------------------// PARAMETERS: // PARAMETER NAME RANGE DESCRIPTION DEFAULT VALUE // e.g. DATA_WIDTH [31:0] width of the data 32 // OTHER REUSE ISSUES // RESET STRATEGY : // CLOCK STRATEGY : // CRITICAL TIMING : // TEST FEATER : // ASYNCHRONOUS I/F : // SCAN METHDOLOGY : //-FHDR-------------------------------------------------------------module FH5to7 (CLK, D1, Q1); input CLK; input D1; output Q1; reg Q1; always @ (posedge CLK or D1) begin Q1 <= D1; end //+CHDR-------------------------------------------------------------// CONSTRUCT NAME & RETURN VALUES: // Mux(A,B,SEL,Y0) //------------------------------------------------------------------// TYPE: task //------------------------------------------------------------------// PURPOSE: for Lint Tool Testing
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//------------------------------------------------------------------// PARAMETERS: none //------------------------------------------------------------------// OTHERS: leave blank if N/A //-CHDR-------------------------------------------------------------task Mux; input A; input B; input SEL; output Y0; begin assign Y0 = SEL ? A : B; end endtask endmodule
nLint reports following if the argument value is ("construct_header.tmpl"):
29112 (Verilog) Use Simple Expression for Asynchronous Set or Reset

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : don't use complex expression in the condition expression for asynchronous set or reset. Configurable Parameter Rule group: Synthesis; Argument type: (BitNegOp, EqOp, NotEqOp, NotOp); Argument description: Multiple arguments can be selected. Only the selected operations are allowed for the asynchronous set or reset clause in always blocks. A violation will be reported if any other operations are found. Following are examples for the arguments: BitNegOp, EqOp, NotEqOp, and NotOp respectively: If (~reset) If (reset == 0) If (reset != 0 ) If (!reset); Default value: "BitNegOp, EqOp, NotEqOp" for Verilog; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) The rule checks whether there are any prohibited operations used for asynchronous set or reset expressions in if-statements. Simple expressions, such as "if (reset)" and "if (~reset)", are suggested. The user can remove some restrictions by arguments. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 module test2(d1, clk, R, d, q, d2); input d1, d2, clk, R, d; output q; reg q; always @( posedge clk or posedge R) begin if (R & d1!=d2) //not a simple condition q = 0; else q = d; end endmodule module test3(d1, clk, R, d, q, d2); input d1, d2, clk, R, d; output q; reg q; always @( posedge clk or posedge R) begin if ( &R ) //not a simple condition q = 0; else q = d; end endmodule module test4(clk, reset, d, q); input clk, reset, d; output q; reg q; always @ (posedge clk or negedge reset)
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begin if (reset) q = 0; else q = d; end endmodule module test5(clk, reset, set, d, q); input clk, reset, set, d; output q; reg q; always @ (posedge clk or posedge reset) begin if (reset&set) //not a simple condition q = 0; else q = d; end endmodule
nLint reports following if the argument value is ("BitNegOp, EqOp, NotEqOp"): document.v(7): Warning 29112: don't use complex expression in the condition expression for asynchronous set or reset (Synthesis) document.v(21): Warning 29112: don't use complex expression in the condition expression for asynchronous set or reset (Synthesis) document.v(51): Warning 29112: don't use complex expression in the condition expression for asynchronous set or reset (Synthesis)
29113 (Verilog) If Statement Describing Asynchronous Set/Reset should be the Most Beginning Statement in a Always Block
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): if statement describing asynchronous set/reset should be put before any other logic statement in always block. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning if a if-statement describing asynchronous set or reset is not in the beginning of always block. For an "if" statement describing asynchronous set or reset, the ifcondition should a simple expression like 'if (res)' 'if(~res)' 'if (res == 0)' and 'if(res != 0)'). And the if-statement should be put in the beginning of the always block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 module test(d1, clk, R, d, q, d2); input d1, clk, R, d; output q, d2; reg q, d2; always @( posedge clk or posedge R) begin d2 = d1; if (R) //not the first statement q = 0; else q = d; end endmodule
nLint reports: document.v(8): Warning 29113: if statement describing asynchronous set/reset should be put before any other logic statement in always block (Synthesis)
29114 (Verilog) A Signal is Connected to Both Input and Output Ports of an Instance
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : Signal %s should not connect both input and output port of the instance. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) For a module instance, compare each output signal in its high-connection expression with each input signal. If there is a signal connected to both input and output port of the instance, report warning Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module test1( a, b, c ); input a, b; output c; assign c = a & b; endmodule module test2( .A(a), .B(b), .C(c) ); input a, b; output c; test1 u1( c, b, c ); //here signal connected to output "c" goes into //input "a" of test1 again. //or something like following test1 u2( c&a, b, c);
endmodule
nLint reports: document.v(13): Warning 29114: Signal "c" should not connect both input and output port of the instance (Design Style) document.v(17): Warning 29114: Signal "c" should not connect both input and output port of the instance (Design Style)
29115 (Verilog) Clock cannot be Explicitly Read in Always Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : clock should not be explicitly read in the always block. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) If every signal in sensitivity list is read or written in always block, report warning on the always block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 fine. 8 9 10 11 12 module test(d1, clk, R, d, q1, q2, d2); input d1, d2, clk, R, d; output q1, q2; reg q1, q2; always @( posedge clk ) begin //warning in this always block if ( clk == 1'b1 ) //clock is explicitly read, however the logic seems q1 <= d1 & d2; end endmodule
nLint reports: document.v(6): Warning 29115: clock should not be explicitly read in the always block (Synthesis)
29116 (Verilog) Signal Assigned by Independent Statements in a Sequential Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): The signal "%s" is assigned by independent statements in a sequential block. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) If the same signal is assigned by independent statements in a sequential block, warning will be reported on the signal. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 module test (rst,clk,en); input rst; input clk; input en; wire rst; wire clk; reg flag1; always@(posedge clk or negedge rst) begin // 1st if if(!rst) begin flag1 <= 1'b0; end // end of 1st if // 2nd if if (en==1'b1) begin flag1 <= 1'b1; end // end of 2nd if assign flag1 = 0'b0; end // end of always endmodule
nLint reports: document.v(13): Warning 29116: The signal "flag1" is assigned by independent statements in a sequential block. (Synthesis)
29118 (Verilog) Do Not Use Integer Variable in Port Expression

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: : integer variable %s is used at port expression. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) Report warning if an integer variable used in port expression Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module ABC(P,P1,P2,P3,P4); input [31:0] P1,P2,P; input [3:0] P3; output P4; endmodule
module test ; integer k; reg [31:0] a; wire [31:0] b; ABC u( .P(k), //not allowed .P1( 1 ), //allowed .P2( k & a ), //not allowed .P3( a[3:0] ), //allowed .P4( b[k] ) //not to check this ); endmodule
nLint reports: document.v(15): Warning 29118: integer variable "k" is used at port expression (Synthesis) document.v(17): Warning 29118: integer variable "k" is used at port expression (Synthesis)
29201 (Verilog) Mismatched Synopsys 'translate_on'/'translate_off' Comments

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): mismatched %s is found. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) The rule checks whether there are any mismatched synopsys translate_on or translate_off comments in the design. All translate_off and translate_on pairs are expected to be within a module or within a file. Any dangling or nested comments in a file or a module may cause unexpected synthesis results or syntax error in synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
//synopsys translate_on //synopsys translate_off macromodule up_counter( clk, reset, count, carry ); parameter WIDTH = 4; input clk, reset; output [WIDTH-1:0] count; output carry; reg [WIDTH-1:0] count; reg carry; reg [1:0] c; //synopsys translate_off always @( posedge clk ) begin if ( reset ) begin count <= 0; carry <= 0; c <= 0; end else begin : ADD reg [WIDTH-1:0] tmp; tmp = count + 1; count <= tmp; if ( count != 0 && tmp == 0 ) carry <= 1; else carry <= 0; end end endmodule
nLint reports: document.v(2): Warning 29201: mismatched translate_on is found (Synthesis) document.v(4): Warning 29201: mismatched translate_off is found (Synthesis) document.v(15): Warning 29201: mismatched translate_off is found (Synthesis)
29204 (Verilog) Instance Name Required for Module

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): instance name for module "%s" is missed. Configurable Parameter Rule group: vl., Naming Convention; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) The rule checks whether there is an instance without a name in the design. Name for a module instance is expected. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
module top (clk, reset, d, q); input clk, reset, d; output q; ffd1 (clk, reset, d, q); ffd2 (clk, reset, d, q); endmodule module ffd1 (clk, reset, d, q); input clk, reset, d; output q; reg q; always @(posedge clk or posedge reset) if (reset == 1'b1) q <= 1'b0; else q <= d; endmodule `celldefine module ffd2 (clk, reset, d, q); input clk, reset, d; output q; reg q; always @(posedge clk or posedge reset) if (reset == 1'b1) q <= 1'b0; else q <= ~d; endmodule èndcelldefine //Warning
nLint reports: document.v(6): Information 29204: instance name for module "ffd1" is missed (Naming Convention) document.v(7): Information 29204: instance name for module "ffd2" is missed (Naming Convention)
29206 (Verilog) Real Value Compared in Case Item

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): real expression "%s" is used in case item. Configurable Parameter Rule group: vl.Coding Style; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) The rule checks whether there are real comparisons in case item expressions. Real comparisons are typically not used in case items. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
`define AA 1.1 module test; reg a,b; real c; parameter k=1.0; initial begin a=ÀA; c=1.2; case (a) a 1 ÀA k 1.1,c default endcase case (b) ÀA+1 k+1.0 c+1 ÀA+((c+1)+(k+0.11)) default endcase end endmodule
: : : : : :
b=0; b=0; b=1; b=1; b=1; b=0;
: : : : :
a=1; a=1; a=1; a=1; a=0;
nLint reports: document.v(15): Warning 29206: real Style) document.v(16): Warning 29206: real Style) document.v(17): Warning 29206: real (Coding Style) document.v(22): Warning 29206: real (Coding Style) document.v(23): Warning 29206: real (Coding Style) document.v(24): Warning 29206: real (Coding Style) document.v(25): Warning 29206: real used in case item (Coding Style)
expression "1.1" is used in case item (Coding expression "k" is used in case item (Coding expression "1.1 , c" is used in case item expression "(1.1 + 1)" is used in case item expression "(k + 1.0)" is used in case item expression "(c + 1)" is used in case item expression "(1.1 + ((c + 1) + (k + 0.11)))" is
29211 (Verilog) Procedural Continuous Assignment Used in Task/Function

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): procedural continuous assignment is used in task/function "%s". Configurable Parameter Rule group: vl.Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) The rule checks whether there are any procedural continuous assignment in tasks and functions. Procedural continuous assignment should not be used in any tasks and functions. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module top(clk,f); input clk; output f; function top; input x; if (!x) assign top=1'b1; else deassign top; endfunction reg f; always @clk f=top(1'b1); endmodule
nLint reports: document.v(8): Warning 29211: procedural continuous assignment is used in task/function "top" (Synthesis)
29212 (Verilog) Procedural Continuous Deassign Used in Task/Function

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): procedural continuous deassign is used in task/function "%s". Configurable Parameter Rule group: vl.Synthesis; Argument type: none; Default severity : Level2 (Warning) Can be suppressed by Synopsys compiler directive "synopsys translate_off"; This rule is turned OFF by default; Description (Verilog) The rule checks whether any deassign statements in tasks and functions. Deassign statements should not be used in any tasks and functions. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module top(clk,f); input clk; output f; function top; input x; if (!x) assign top=1'b1; else deassign top; endfunction reg f; always @clk f=top(1'b1); endmodule
nLint reports: document.v(10): Warning 29212: procedural continuous deassign is used in task/function "top" (Synthesis)
29801 (Verilog) Nested Text Macro

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Nested text macros "%s" is found. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any nested text macros defined in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 `define macro1 1 `define macro2 `macro1 module smp(A,B,Y,Z); input output A,B; Y,Z;
assign Z = ( A == `macro1 ) ? 1'b1 : 1'b0; assign Y = ( B == `macro2 ) ? 1'b0 : 1'b1; endmodule
nLint reports: document.v(2): Error 29801: Nested text macros "macro2" is found. (SC)
29802 (Verilog) Constant Value Assigned to Case Default Clause

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Constant value "%s" is assigned to default case clause. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a constant value is assigned to the case default clause. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module smp(zo,sel); input[1:0] sel; output[3:0] zo; function[3:0] test; input [1:0] sel; case(sel) 2'b00: test = 4'b0001; 2'b01: test = 4'b0010; 2'b10: test = 4'b0100; default: test = 4'b0000; endcase endfunction assign zo = test(sel); endmodule
nLint reports: document.v(12): Warning 29802: Constant value "0000" is assigned to case default clause (SC)
29803 (Verilog) Filp-flop Reset Logic in 'for' Loop

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): the reset logic should be separate from the for loop logic. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the reset logic is separte from the for loop logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 module smp (out1, in1, clk, reset); output [3:0] out1; input [3:0] in1; input clk, reset; reg [3:0] out1; integer i; always @ (posedge clk or negedge reset) for (i = 0; i < 4; i = i + 1) if ( !reset ) out1[i] = 1'b0; else out1[i] = in1[i]; endmodule
nLint reports: document.v(11): Error 29803: the reset logic should be separate from the for loop logic. (SC)
29804 (Verilog) Number Not execced threshold value

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): the number of line in always construct should not be up to threshold value. Configurable Parameter Rule group: Coding Style; Argument type: integer; Argument description: specify the maximum line number of an always block; Default value: "200" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) the number of line in always construct should not be up to threshold value Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module smp(dout,ck,res,din); input ck,res,din; output dout; reg douti; parameter D1 = 1; always @(posedge ck or negedge res) begin if ( ~res ) douti <= #D1 1'b0; else douti <= #D1 din;
end
//Warning: the number of line in //always construct should not be //up to threshold value endmodule
nLint reports following if the argument value is ("200"): document.v(9): Warning 29804: the number of line in always construct should not be up to "10" from line "9" to line "20" (Coding Style)
29805 (Verilog) Use Case for Cases without 'Don't Care' Values
Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l):use case instead of casex or casez for cases without don't care values in the case items. Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether casex or casez is used for cases without don't care values in the case items. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module smp(zo,sel); input[1:0] sel; output[3:0] zo; reg [3:0] zo;
always@( sel ) casex(sel) 2'b00: zo 2'b01: zo 2'b10: zo 2'b11: zo default: zo endcase endmodule
= = = = =
4'b0001; 4'b0010; 4'b0100; 4'b1000; 4'b0000;
nLint reports: document.v(9): Error 29805: use case instead of casex or casez for cases without don't care values in the case items. (SC) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module smp2(zo,sel); input[1:0] sel; output[3:0] zo; reg [3:0] zo;
always@( sel ) casez(sel) 2'b00: zo 2'b01: zo 2'b10: zo 2'b11: zo default: zo endcase endmodule
= = = = =
4'b0001; 4'b0010; 4'b0100; 4'b1000; 4'b0000;
nLint reports: document2.v(9): Error 29805: use case instead of casex or casez for cases without don't care values in the case items. (SC)
29806 (Verilog) Negative Value Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): do not assign signal with negative value "%s". Configurable Parameter Rule group: Language Construct; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any negative values used in assignments. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module smp(A,B,C,G,H,Z); input A,B,C,G,H; output Z; reg Z; always@( A or B or C or G or H ) case ({G,H}) 2'b00 : Z <= A; 2'b01 : Z <= B; 2'b10 : Z <= C; 2'b11 : Z <= -1; default : Z <= 1'bx; endcase endmodule
nLint reports: document.v(12): Error 29806: do not assign signal with negative value "-1" (SC)
29807 (Verilog) Fractional Delay Value

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Fractional delay value "%s" is found. Configurable Parameter Rule group: Language Construct, Simulation; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any fractional delay values used in the design. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module smp1(res,ck,fin,fout); input res,ck,fin; output fout; reg fout; parameter D1=-1.5; always@( negedge res or posedge ck ) if(~res) fout <= #D1 1'b0; //Error: do not use fractional delay value else fout <= #D1 fin; //Error: do not use fractional delay value endmodule
nLint reports: document.v(11): Error 29807: Fractional delay value "-1.500000" is found (SC) document.v(13): Error 29807: Fractional delay value "-1.500000" is found (SC)
29808 (Verilog) Fixed Value of Case Selection Expression

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): the value of case selection expression is fixed. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether case selection expression is a fixed value. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module smp(zo,sel); input[3:0] sel; output[3:0] zo; reg [3:0] zo;
always@( sel ) case(1'b1) sel[0]: sel[1]: sel[2]: sel[3]: default: endcase endmodule
zo zo zo zo zo
= = = = =
4'b0001; 4'b0010; 4'b0100; 4'b1000; 4'b0000;
nLint reports: document.v(9): Error 29808: the value of case selection expression is fixed. (SC)
29809 (Verilog) Negative Value Assigned to an Integer

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): A negative value is assigned to an integer. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any negative values assigned to integers. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module smp(INA,F); input[7:0] output reg F; integer I; always I = for F end endmodule @(INA) begin : loop -1; (I = 0; I <= 7; I = I + 1) = INA[I]; INA; F;
nLint reports: document.v(11): Error 29809: A negative value is assigned to an integer. (SC)
29810 (Verilog) Non-blocking Statement in Function

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): non-blocking assignment is used inside a function. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are non-blocking statements used inside a function. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module smp(A,B,C,D,G,H,ZF); input A,B,C,D,G,H; output ZF; function ZFC; input A,B,C,D,G,H; begin case ({G,H}) 2'b00 : ZFC <= 2'b01 : ZFC <= 2'b10 : ZFC <= 2'b11 : ZFC <= default : ZFC <= endcase end endfunction
A; B; C; D; 1'bx;
assign ZF = ZFC ( A,B,C,D,G,H ); endmodule
nLint reports: document.v(10): (SC) document.v(11): (SC) document.v(12): (SC) document.v(13): (SC) document.v(14): (SC)
Error 29810: non-blocking assignment is used inside a function. Error 29810: non-blocking assignment is used inside a function. Error 29810: non-blocking assignment is used inside a function. Error 29810: non-blocking assignment is used inside a function. Error 29810: non-blocking assignment is used inside a function.
29811 (Verilog) Parameter Base Not Specified Explicitly

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Specify base explicitly for parameter "%s". Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) The rule checks whether the parameter base is specified explicitly. If parameter values are more than 2 digits (e.g. 10), it is recommended to specify parameter base 'h, 'd, 'b, or 'o explicitly to prevent confusion. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module smp(CK,FIN,FOUT); parameter W = 16; input CK; input[W-1:0] output[W-1:0]
FIN; FOUT;
reg[W-1:0] FOUT; parameter D1 = 1; always@( posedge CK ) FOUT <= #D1 FIN; endmodule
nLint reports: document.v(3): Error 29811: Specify base explicitly for parameter "W" (SC)
29812 (Verilog) Specify Constant Bit Width Explicitly

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Specify bit width explicitly when assigning a constant of 5 bits or more. Configurable Parameter Rule group: Coding Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) The rule checks whether there are any constants greater than or equal to 5-bits whose bit widths are not specified explicitly. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module smp(A,B,C); input[6:0] A,B; output[6:0] C; reg[6:0] C; always@(A or B or C) case( A ) 7'd0 : C = B; 7'd1 : C = 'b000_0010; 7'd2 : C = 'b000_0100; 7'd3 : C = 'b000_1000; 7'd4 : C = 'b001_0000; default : C = 'b111_1111; endcase endmodule
nLint reports: document.v(11): Error constant of 5 bits or document.v(12): Error constant of 5 bits or document.v(13): Error constant of 5 bits or document.v(14): Error constant of 5 bits or document.v(15): Error constant of 5 bits or
29812: Specify more. (SC) 29812: Specify more. (SC) 29812: Specify more. (SC) 29812: Specify more. (SC) 29812: Specify more. (SC)
bit width explicitly when assigning a bit width explicitly when assigning a bit width explicitly when assigning a bit width explicitly when assigning a bit width explicitly when assigning a
29813 (Verilog) Logical/Arithmetic/BitWise Operation in Case Selection Expression

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Logical, arithmetic or bitwise operation is in the case selection expression. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any logical, arithmetic or bitwise operation used in the case selection expression. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module smp(zo,sel1,sel2); input[1:0] sel1,sel2; output[3:0] zo; reg [3:0] zo;
always@( sel1 or sel2 ) case(sel1&sel2) 2'b00: zo = 4'b0001; 2'b01: zo = 4'b0010; 2'b10: zo = 4'b0100; 2'b11: zo = 4'b1000; default: zo = 4'b0000; endcase endmodule
nLint reports: document.v(9): Warning 29813: Logical, arithmetic or bitwise operation is in the case selection expression. (SC)
29814 (Verilog) One Statement in a Single Always Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): more than one statement (if/case/while/for/forever/repeat) is described in a single always block. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule check whether there is more than one statement (if/case/while/for/forever/repeat) within a single always block. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module smp(A,B,C,D,S,W); input output reg W; always@( A or B or C or D or S ) begin if( A ) begin W = B; end case( S ) 1'b0 : W = C; 1'b1 : W = D; endcase end endmodule A,B,C,D,S; W;
nLint reports: document.v(9): Warning 29814: more than one statement (if/case/while/for/forever/repeat) is described in a single always block. (SC)
29815 (Verilog) Logical Operators Used in Single-bit Operations

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): bit-wise operators should be used instead of logical operators "%s" in single-bit operations. Configurable Parameter Rule group: Design Style; Argument type: (CHECK_CONDEXPR, IGNORE_CONDEXPR); Argument description: select CHECK_CONDEXPR to check this rule and select IGNORE_CONDEXPR to ignore checking this rule; Default value: "CHECK_CONDEXPR" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether single-bit operations use bit-wise operations. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 module smp(out, in1, in2, in3); output out; input in1, in2, in3; assign out = !(in1 & in2 | in3); endmodule
nLint reports following if the argument value is ("CHECK_CONDEXPR"): document.v(6): Warning 29815: bit-wise operators should be used instead of logical operators "NotOp" in single-bit operations. (SC) ///////////////example : document2.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 module t(clk,A,B,c); input clk; input A,B; output c; reg c; always @(posedge clk) begin if ( (A==1) && (B==1) ) c = 0; assign c = (A==1) && (B==1); end endmodule
nLint reports following if the argument value is ("CHECK_CONDEXPR"): document2.v(8): Warning 29815: bit-wise operators should be used instead of logical operators "LogAndOp" in single-bit operations. (Design Style) document2.v(10): Warning 29815: bit-wise operators should be used instead of logical operators "LogAndOp" in single-bit operations. (Design Style) ///////////////example : document3.v//////////// 1 2 3 4 5 6 module t(clk,A,B,c); input clk; input A,B; output c; reg c;
7 8 9 10 11 12
always @(posedge clk) begin if ( (A==1) && (B==1) ) c = 0; assign c = (A==1) && (B==1); end endmodule
nLint reports following if the argument value is ( IGNORE_CONDEXPR): document3.v(10): Warning 29815: bit-wise operators should be used instead of logical operators "LogAndOp" in single-bit operations. (Design Style)
29816 (Verilog) Describe Combinational Logic with Functions and an Assignment

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): use function and assignment constructs rather than an always construct to describe combinational logic. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether combinational logic is implemented by function and assignment constructs. Since functions cannot be used in sequential logic, it reduces the mistakes of using always blocks that can describe both sequential and combinational logic. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 module smp(A,B,C,D,E,F,G,H,WA,Y,ZA,ZF); input A,B,C,D,E,F,G,H; output WA,Y,ZA,ZF; reg WA,ZA;
always@(A or B) if( A ) WA = 1'b0; else WA = B; assign Y = ( C ) ? D : F; always@(A or B or C or D or G or H) case ({G,H}) 2'b00 : ZA = A; 2'b01 : ZA = B; 2'b10 : ZA = C; 2'b11 : ZA = D; default : ZA = 1'bx; endcase function ZFC; input A,B,C,D,G,H; begin case ({G,H}) 2'b00 : ZFC = 2'b01 : ZFC = 2'b10 : ZFC = 2'b11 : ZFC = default : ZFC = endcase end endfunction
A; B; C; D; 1'bx;
assign ZF = ZFC ( A,B,C,D,G,H ); endmodule
nLint reports: document.v(8): Warning 29816: use function and assignment constructs rather than an always construct to describe combinational logic. (SC)
document.v(16): Warning 29816: use function and assignment constructs rather than an always construct to describe combinational logic. (SC)
29817 (Verilog) Function Called in an Always Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): function "%s" is called in an always block. Configurable Parameter Rule group: Design Style; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any functions called in an always block Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module smp(CK,A,B,C,D,G,H,ZF); input input output reg CK; A,B,C,D,G,H; ZF; ZF;
function ZFC; input A,B,C,D,G,H; begin case ({G,H}) 2'b00 : ZFC = 2'b01 : ZFC = 2'b10 : ZFC = 2'b11 : ZFC = default : ZFC = endcase end endfunction
A; B; C; D; 1'bx;
always@( posedge CK ) ZF <= ZFC ( A,B,C,D,G,H ); endmodule
nLint reports: document.v(22): Error 29817: function "ZFC" is called in an always block. (SC)
29818 (Verilog) 'set_dont_touch' Used

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): set_dont_touch directive is used. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any set_dont_touch directives specified in the source code. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 module smp(out1, out2, in, clk); output out1, out2; input in, clk; //synopsys set_dont_touch FF1 FF1 myFF1(.Din(in), .Clk(clk), .Q(out1), .QB(out2)); endmodule
`celldefine module FF1(Din, Clk, Q, QB); input Din, Clk; output Q, QB; reg Q, QB; always @(posedge Clk) begin Q = Din; QB = ~Din; end endmodule èndcelldefine
nLint reports: document.v(6): Error 29818: set_dont_touch directive is used. (SC)
29819 (Verilog) Arithmetic Operations in 'for' Loop

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Arithmetic operation is performed on non for loop variables. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) The rule checks whether there are any arithmetic operations performed on non for loop variables. The operations induce logic as many times as the for loop iterates and will consume a larger area after synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module smp(INA,F); input[7:0] output reg F; integer I; always @(INA) begin : loop for (I = 0; I <= 7; I = I + 1) F = INA[I] + 1'b1; end endmodule INA; F;
nLint reports: document.v(12): Error 29819: Arithmetic operation is performed on non for loop variables. (SC)
29820 (Verilog) Logical or Relational Operations in 'for' Loop

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Logical or relational operation is performed on non for loop variables. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether there are any logical or relational operations performed on one for loop variables. The operations induce logic as many times as the for loop iterates and will consume a larger area after synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module smp(INA,INB,F); input[7:0] output reg F; integer I; always @(INA or INB) begin : loop for (I = 0; I <= 7; I = I + 1) F = INA[I]ÎNB[I]; end endmodule INA,INB; F;
nLint reports: document.v(12): Error 29820: Logical or relational operation is performed on non for loop variables (SC)
29821 (Verilog) Instance/Module Name Matches Library Cell Name

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): Instance/module name "%s" uses the same name as an ASIC library cell name. Configurable Parameter Rule group: Synthesis; Argument type: FILENAME_ARG; Argument description: Specify a file name in the argument. The file should contain a list of library cell names to be checked in this rule; Default value: "m190c_list.txt" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether a module or an instance name is the same as a library cell name. The library cells to be checked are listed in the file as specified in the argument. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module smp(RES,CK,FIN,FOUT); input input input output RES; CK; FIN; FOUT;
reg fo; parameter D1 = 1; always@( negedge RES or posedge CK ) if(~RES) fo <= #D1 1'b1; else fo <= #D1 FIN; JANIV IJANIV ( .bout(FOUT), .bin(fo) ); endmodule module JANIV (bin,bout); input bin; output bout; assign bout = bin; endmodule
nLint reports following if the argument value is ("m190c_list.txt"): document.v(21): Error 29821: Instance/module name "JANIV" uses the same name as an ASIC library cell name (SC)
29822 (Verilog) Library Cell Instantiated

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): library cell "%s" is instantiated. Configurable Parameter Rule group: Synthesis; Argument type: FILENAME_ARG; Argument description: Specify a file name in the argument. The file should contain a list of library cell names to be checked in this rule; Default value: "m190c_list.txt" for Verilog; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) The rule checks whether any library cells instantiated in the design. The library cells to be checked are listed in the file as specified in the argument. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module smp(dout,ck,res,din); input ck,res,din; output dout; reg douti; parameter D1 = 1; always @(posedge ck or negedge res) if ( ~res ) douti <= #D1 1'b0; else douti <= #D1 din; JANIV OBUF (.A(douti), .Z(dout)); endmodule `celldefine module JANIV(A, Z); input A; output Z; assign Z = A; endmodule èndcelldefine
nLint reports following if the argument value is ("m190c_list.txt"): document.v(15): Error 29822: library cell "JANIV" is instantiated (SC)
29823 (Verilog) Flip-flop Initialized in Initial Block

Message (Verilog) <filename>(<line no.>): <severity> <rule no.>: %f(%l): The initial value of flip-flop "%s" is specified in an initial block. Configurable Parameter Rule group: Synthesis; Argument type: none; Default severity : Level2 (Warning) This rule is turned OFF by default; Description (Verilog) This rule checks whether the initial value of a flip-flop is specified in an initial block. Since initial blocks are ignored by synthesis tools, the initial value is not set after synthesis. Example
(Verilog) ///////////////example : document.v//////////// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module smp(in1, out1, clk); input in1, clk; output out1; reg out1; initial begin out1 = 1'b0; end always @(posedge clk) out1 <= in1; endmodule
nLint reports: document.v(10): Error 29823: The initial value of flip_flop "out1" is specified in an initial block (SC)
Customize a file header

Rule 29106 imports a file by argument and check the file header of design based on the content of the file. The following explanation will assist you in customizing a file header for nLint rule 29106.
File header format

Here is a simple example for file header format.
CommentFormat = "FILE_HEADER File Name: $FileName RELEASE HISTORY: VERSION DATE AUTHOR DESCRIPTION $foreach { $Version $Date $Author $AnyString }+ $Separator PARAMETER: PARAM NAME: RANGE: DESCRIPTION: DEFAULT: UNITS $foreach $ParamSet { $ParamSet.Object.Name : $ParamSet.Object.Range: $AnyString: $AnyString } $Separator Instaniations: $foreach $InstanceSet { $InstanceSet.Object.Name } END_HEADER ";
The words put in the quotation mark (' ') which is at right side of the equal sign is the description of file header format. Every line represents a comment line in the design. Comment format for matching comment in design is case sensitive. Some parts of description are different because of file differences. Below is Variable, RegExp and Set used to describe the transformable comment.
Refer a Variable When a variable is referred, it must take a '$' as the header. If only the variable '$FileName' is provided, it represents the current file name. Refer a RegExp When a regexp is referred, it must take a '$' as the header. Some regexp are provided as references. See the table below for examples.
Name AnyString Separator Version Author Date Yes_No EmailAddress RegExp .* ----* [0-9]+\.[0-9]+ [a-zA-Z][a-zA-Z_]* (20|19)[0-9][0-9]-[0-1][0-9]-[0-3][0-9] (Y|N) [a-zA-Z].*@.*
Refer a Set
When a set is referred, it must take a '$' as the header. A period ( . ) can be used to connect the property of a set, such as $Set.Object.Type. Set name without property, such as '$set', is not allowed. Some sets are provided as references. See the table below for examples.
Set name ParamSet
Description Collect all parameters in the file
Property of set Type, Name, File, LineNo, BeginLine, EndLine, Range, ConstType, Value, IsSigned, IsLocalParam, Size
InstanceSet
Collect all Type, Name, File, LineNo, BeginLine, EndLine, module instances IsArray, Size, DefFile, DefLineNo, DefBeginNo, in the file DefEndLine, IsCellInstance, DefNetType, TimePrecision, TimeUnit
PortSet
Collect all ports in the file
Type, Name, File, LineNo, BeginLine, EndLine, PortIndex, Direction, IsConnByName, IsExplicitName, IsVector, IsScalar, Size
These sets can be used in the following syntax.
ifEmpty(ifNotEmpty)...else Users can control their comment format flexibly by the keyword pair, 'ifEmpty' and 'else', 'ifNotEmpty' and 'else'. 'ifEmpty' or 'ifNotEmpty' must have a set as its parameter. For 'ifEmpty', if the set is null, the first branch is valid for check engine; otherwise, the second branch (else) is valid for check engine. For 'ifNotEmpty', it is contrary to 'ifEmpty'. The first and second branch may be null; if a null branch is used, no match will be done by check engine. When used in the grid, 'ifNotEmpty' and 'else' must take a '$' as a header. Brace should be used to enclose the content of the two branches. 'else' can not appear alone. Example
$ifNotEmpty $InstanceSet{ There are instances in the file. } $else { No instance in the module. }
'ifNotEmpty' can be used alone and the second branch is regarded as a null branch.
$ifNotEmpty $InstanceSet{ There are instances in the file. }
The first branch is null
$ifNotEmpty $InstanceSet{ } $else { No instance in the file. }
Foreach When user wants to repeat certain lines or patterns, or gets a full list of something in Verilog design file, the keyword, Foreach, can be used.
When used in the grid, 'foreach' must take a '$' as a header. A brace is used to enclose the repeated pattern. The nesting is allowed for the keyword. If no set is in the repeated pattern, a symbol for prompting the repeated times should be specified after the right brace. '+' means plus times beginning from one and '*' means minus time beginning from zero. If a set is referred in the repeated pattern, it must be the only one and be writen out after 'foreach'. The size of the set is the times of repeat. The default traverse mode for a set in the repeated pattern is not listed in order. All elements in a set can be listed randomly in comment. An option '-order' can be invoked after 'foreach'. Elements must be listed according to the order added to the set.
Example
VERSION, DATE, AUTHOR, DESCRIPTION is RegExp. a. Repeat line (one and more times)(no set) $foreach { $VERSION : $DATE : $ AUTHOR: $DESCRIPTION }+ b. Repeat words (one and more times) Instantiations: $foreach $InstanceSet { $InstanceSet.Object.Name } c. Repeat line (zero and more) $foreach $InstanceSet { Instantiations: $InstanceSet.Object.Name } d. Repeat line (zero and more)(-order) $foreach $InstanceSet -order { Instantiations: $InstanceSet.Object.Name }
Special Functional Symbol

Char $, {, }, \, + and " are special functional symbol. If you use any of it at the beginning of a word, you can prefix the char with a '\'. For example, '\$ModuleName' is a general string, not a variable.
Customize a construct header

Rule 29111 imports a file by argument and check the construct header in design based on the content of the construct. The following explanation will assist you in customizing a construct header for nLint rule 29111.
Construct header format

Here is a simple example for construct header format.
CommentFormat = "\+CHDR CONSTRUCT NAME & RETURN VALUES: $ConstructName ( $foreach $IOSet -order { $IOSet.Object.Name } ) TYPE: $ConstructType $Separator PURPOSE: $AnyString $Separator PARAMETER: PARAM NAME: RANGE: DESCRIPTION: DEFAULT VALUE $foreach $ParamSet { $ParamSet.Object.Name : $ParamSet.Object.Range : $AnyString : $ParamSet.Object.Value } $Separator OTHERS: $AnyString -CHDR ";
The words put in the quotation mark (' ') which is at right side of the equal sign is the description of construct header format. Every line represents a comment line in the design. Comment format for matching comment in design is case sensitive. Some parts of description are different because of file differences. Below is Variable, RegExp and Set used to describe the transformable comment.
Refer a Variable When a variable is referred, it must take a '$' as the header. Variable '$ConstructName' and $ConstructType' represents the current construct name and type (task, function, user-definedprimitive). Refer a RegExp When a regexp is referred, it must take a '$' as the header. Some regexp are provided as references. See the table below for examples
Name AnyString Separator CommaOrnon RegExp .* ----* ,?
Refer a set When a set is referred, it must take a '$' as the header. A period ( . ) can be used to connect the property of a set, such as $Set.Object.Type. Set name without property, such as '$set', is not allowed. Some sets are provided as references. See the table below for examples.
Set name ParamSet Description Collect all parameters in the file Collect all module instances in the file Property of set Type, Name, File, LineNo, BeginLine, EndLine, Range, ConstType, Value, IsSigned, IsLocalParam, Size Type, Name, File, LineNo, BeginLine, EndLine, Size, DefFile, Direction, IsVector, IsScalar
IOSet
These sets can be used in the following syntax. ifEmpty(ifNotEmpty)...else Users can control their comment format flexibly by the keyword pair, 'ifEmpty' and 'else, 'ifNotEmpty' and 'else'. 'ifEmpty' or 'ifNotEmpty' must have a set as its parameter. For 'ifEmpty', if the set is null, the first branch is valid for check engine; otherwise, the second branch (else) is valid for check engine. For 'ifNotEmpty', it is contrary to 'ifEmpty'. The first and second branch may be null; if a null branch is used, no any match is done by check engine. When used in the grid, 'ifNotEmpty' and 'else' must take a '$' as a header. Brace should be used to enclose the content of the two branches. 'else' can not appear alone.
Example
$ifNotEmpty $ParamSet{ There are parameter(s) in the construct. } $else { No parameter in the construct. }
'ifNotEmpty' can be used alone and the second branch is regarded as a null branch.
$ifNotEmpty $ParamSet{ There are parameter(s) in the construct. }
The first branch is null
$ifNotEmpty $ParamSet{ } $else { No parameter in the construct. }
Foreach When user wants to repeat certain lines or patterns, or gets a full list of something in Verilog design file, the keyword, Foreach, can be used.
When used in the grid, 'foreach' must take a '$' as a header. A brace is used to enclose the repeated pattern. The nesting is allowed for the keyword. If no set is in the repeated pattern, a symbol for prompting the repeated times should be specified after the right brace. '+' means plus times beginning from one and '*' means minus time beginning from zero. If a set is referred in the repeated pattern, it must be the only one and be writen out after 'foreach'. The size of the set is the times of repeat. The default traverse mode for a set in the repeated pattern is not listed in order. All elements in a set can be listed randomly in comment. An option '-order' can be invoked after 'foreach'. Elements must be listed according to the order added to the set.
Example
VERSION, DATE, AUTHOR, DESCRIPTION is RegExp. a. Repeat line (one and more times)(no set) $foreach { $VERSION : $DATE : $ AUTHOR: $DESCRIPTION }+ b. Repeat words (one and more times) Parameters: $foreach $ParamSet{ $ParamSet.Object.Name } c. Repeat line (zero and more) $foreach $ParamSet { Parameters: $ParamSet.Object.Name } d. Repeat line (zero and more)(-order) $foreach $ParamSet -order { Parameters: $ParamSet.Object.Name }
Special Functional Symbol

Char $, {, }, \, + and " are special functional symbol. If you use any of it at the beginning of a word, you can prefix the char with a '\'. For example, '\$ModuleName' is a general string, not a variable.
Header File
Overview
Since a header file can be included in lots of files, nLint only enables the first check point for every rule to avoid redundant warnings; other check points are disabled to get the best performance. There is a risk that nLint will lose some messages when a rule is violated from the second check point but was not violated at the first check point.
Solution
Considering most users' cases: only parameter and macro definitions are written in a header file. The solution focuses on parameter and macro definitions. In nLint, some rules are context-sensitive, e.g. rule 22061 (Unused Object) and 27359 (Unused Macro), while some rules are not context-sensitive, e.g. 21041 (parameter case). Context-sensitive rules may check parameter or macro definitions many times, but other rules only need to check once. nLint uses the following guidelines when encountering header files: For rule 22061and 27359, nLint enables all check points for the header file no matter how many times it is included by other files. For the other rules, nLint only checks the header file once when it is first parsed and filters all messages from the second time it is parsed.
Usage Notes
If a header file is included outside a module declaration, all parameters declared in this header file are global. If a parameter declared in the header file is not used in anywhere in the design, nLint will report it.
Example
line 1: ìnclude "eg.vh" line 2: module test(); line 3: ... line 40 endmodule
All parameters declared in header file eg.vh are effective throughout the whole design.
If a header file is included in a module declaration, all parameters declared in this header file are local to the module. If a parameter declared in the header file is not used in within the module, nLint will report it.
Example
line 1: module test(); line 2: ìnclude "eg.vh" line 3: ... line 40 endmdoule
All parameters declared in header file eg.vh are effective locally within module test. If a parameter declared in eg.vh is not used in the module test, a violation will be reported.
Example
Example1
--param.h-line 1 parameter PARAMA = 1'b0; line 2 parameter PARAMB = 1'b1; --test1.v-line 1 module test1; line 2 ìnclude "param.h" line 3 logic [PARAMA : 0] a; line 4 endmodule
--test2.v line 1 module test2; line 2 ìnclude "param.h"
line 3 endmodule
The header file param.h is included in both module test1 and test2. All parameters declared in param.h are locally effective in test1 or test2. In test1, PARAMA is used, but PARAMB is not used, so nLint reports: param.h(2): Warning 22061: object "PARAMB" is declared but not used. (Design Style) In test2, neither PARAMA or PARAMB are used, so nLint reports: param.h(1): Warning 22061: object "PARAMA" is declared but not used. (Design Style)param.h(2): Warning 22061: object "PARAMB" is declared but not used. (Design Style) Example2
--param.h-line 1 parameter PARAMA = 1'b0; line 2 parameter PARAMB = 1'b1;
--test1.v-line 1 module test1; line 2 logic [PARAMA : 0] a; line 3 endmodule
--test2.v line 1 ìnclude "param.h" line 2 module test2; line 3 endmodule
The header file param.h is included in test2.v outside the module declaration, so all parameters declared in param.h are effective globally. Since PARAMA is used in test1.v, while PARAMB is never used through the whole design,nLint reports: param.h(2): Warning 22061: object "PARAMB" is declared but not used. (Design Style)
Regular Expression Help

Regular Expressions
[1] [2] [3] char . \ matches itself, unless it is a special character (metachar): . \ [ ] * + ? ^ $ | { } ( ) matches any character. matches the character following it, except when followed a digit 1 to 9 or a left or right angle bracket. (see [7], [8] and [9]) It is used as an escape character for all other meta-characters, and itself. When used in a set ([4]), it is treated as an ordinary character. matches one of the characters in the set. If the first character in the set is "^", it matches a character NOT in the set. A shorthand S-E is used to specify a set of characters S upto E, inclusive. The special characters "]" and "-" have no special meaning if they appear as the first chars in the set. examples: match: [a-z] any lowercase alpha [^]-] any char except ] and [Â-Z] any char except uppercase alpha [a-zA-Z] any alpha any regular expression form [1] to [4], followed by closure char (*) matches zero or more matches of that form. same as [5], except it matches one or more. same as [5], except it matches zero or one. a regular expression in the form [1] to [10], enclosed as (form) matches what form matches. The enclosure creates a set of tags, used for [8] and for pattern match/substution. The tagged forms are numbered starting from 1. a \ followed by a digit 1 to 9 matches whatever a previously tagged regular expression ([7]) matched. a regular expression starting with a \< construct and/or ending with a \> construct, restricts the pattern matching to the beginning of a word, and/or the end of a word. A word is defined to be a character beginning and/or ending with the characters A-Z a-z 0-9 and _. It must also be preceded and/or followed by any character outside those mentioned. a composite regular expression xy where x and y are in the form [1] to [10] matches the longest match of x followed by a match for y. a regular expression starting with a ^ character and/or ending with a $ character, restricts the pattern matching to the beginning of the line, or the end of line. [anchors] Elsewhere in the pattern, ^ and $ are treated as ordinary characters. or two conditions together. For example (him|her) matches the "him" and matches "her" but does not match "them."
[4]
[set]
[5]
[6]
[6.1] ? [7] ()
[8]
\digit
[9]
\<\>
[10]
[11] ^ $
[12] |
[13] {i}{i,j} {i,}{,j}
match a specific number of instances or instances within a range of the preceding character. {i,} {,j} For example, the expression A[0-9]{3} will match "A" followed by exactly 3 digits. That is, it will match A123 but not A1234. The expression [0-9]{4,6} any sequence of 4, 5, or 6 digits. The expression A[0-9]{1,} match "A" followed by at least 1 digit. {,j} means {1,j}, A[0-9]{,3} match "A" followed by at most 3 digits, at least 1 digit
Examples
pattern: matches: pattern: matches: pattern: matches: pattern: matches: pattern: matches: pattern: matches: pattern: matches: pattern: matches: foo*.* fo foo fooo foobar fobar foxx ... fo[ob]a[rz] fobar fooar fobaz fo foo\\+ foo\ foo\\ foo\\\ ... (foo)[1-3]\1 (same as foo[1-3]foo) foo1foo foo2foo foo3foo (fo.*)_\1 foo_foo fo_fo fob_fob foobar_foobar ... foo(1|9) foo1 foo9 foo[0-9]{3} foo123 foo111 foo379 ... foo[0-9]{1,3} foo1 foo12 foo123 foo87 ...

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How to Reach SpringSoft, Inc.

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21013 Clock Name Prefix or Suffix

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21014 Latch Name Prefix or Suffix

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21015 Reset Name Prefix or Suffix

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21017 Set Name Prefix or Suffix

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end if; end process p1; end architecture arch;

nLint Rule Category 45

21019 Current State Name Prefix or Suffix

(VHDL) -------------------example : document.vhd-------------

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nLint Rule Category 47

21020 Active Low Signal Name Prefix or Suffix

nLint reports following if the argument value is ("SUFFIX","_n"):